Applied fixes to NormMatts r1150 fixes - V-Rally 3 working again
Re-added nasm.props to vs2008 build folder + changes to nasm.rules for spaces in paths. git-svn-id: https://svn.code.sf.net/p/vbam/code/trunk@1161 a31d4220-a93d-0410-bf67-fe4944624d44
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@ -0,0 +1,26 @@
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<?xml version="1.0" encoding="utf-8"?>
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<Project xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
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<PropertyGroup
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Condition="'$(NASMBeforeTargets)' == '' and '$(NASMAfterTargets)' == '' and '$(ConfigurationType)' != 'Makefile'">
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<NASMBeforeTargets>Midl</NASMBeforeTargets>
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<NASMAfterTargets>CustomBuild</NASMAfterTargets>
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</PropertyGroup>
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<PropertyGroup>
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<NASMDependsOn
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Condition="'$(ConfigurationType)' != 'Makefile'">_SelectedFiles;$(NASMDependsOn)</NASMDependsOn>
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</PropertyGroup>
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<ItemDefinitionGroup>
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<NASM>
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<TreatWarningsAsErrors>False</TreatWarningsAsErrors>
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<DisableOrphanLabelsWarning>False</DisableOrphanLabelsWarning>
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<GenerateDebugInfo>False</GenerateDebugInfo>
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<ObjectFileName>$(IntDir)%(Filename).obj</ObjectFileName>
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<Optimization>0</Optimization>
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<ObjectFileFormat>8</ObjectFileFormat>
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<ErrorReportingFormat>1</ErrorReportingFormat>
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<CommandLineTemplate>"$(SolutionDir)..\..\..\dependencies\nasm.exe" [AllOptions] [AdditionalOptions] -- [inputs]</CommandLineTemplate>
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<Outputs>%(ObjectFileName)</Outputs>
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<ExecutionDescription>Assembling...</ExecutionDescription>
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</NASM>
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</ItemDefinitionGroup>
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</Project>
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@ -7,11 +7,10 @@
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<CustomBuildRule
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Name="NASM"
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DisplayName="Netwide Assembler"
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CommandLine="$(SolutionDir)..\..\..\dependencies\nasm.exe [AllOptions] [AdditionalOptions] -- [inputs]"
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CommandLine=""$(SolutionDir)..\..\..\dependencies\nasm.exe" [AllOptions] [AdditionalOptions] -- [inputs]"
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Outputs="[$ObjectFileName]"
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FileExtensions="*.asm"
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ExecutionDescription="Assembling..."
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>
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ExecutionDescription="Assembling..." >
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<Properties>
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<StringProperty
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Name="ObjectFileName"
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@ -753,27 +753,31 @@ static void count(u32 opcode, int cond_res)
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// OP Rd,Rb,Rm LSL Rs
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#ifndef VALUE_LSL_REG_C
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#define VALUE_LSL_REG_C \
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unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
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if (LIKELY(shift)) { \
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if (shift == 32) { \
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value = 0; \
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C_OUT = (reg[opcode & 0x0F].I & 1 ? true : false);\
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} else if (LIKELY(shift < 32)) { \
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u32 v = reg[opcode & 0x0F].I; \
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C_OUT = (v >> (32 - shift)) & 1 ? true : false;\
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value = v << shift; \
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} else { \
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value = 0; \
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C_OUT = false; \
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} \
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} else { \
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value = reg[opcode & 0x0F].I; \
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u32 shift = reg[(opcode >> 8)&15].B.B0; \
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u32 rm = reg[opcode & 0x0F].I; \
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if((opcode & 0x0F) == 15) { \
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rm += 4; \
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} \
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if (LIKELY(shift)) { \
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if (shift == 32) { \
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value = 0; \
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C_OUT = (rm & 1 ? true : false); \
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} else if (LIKELY(shift < 32)) { \
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u32 v = rm; \
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C_OUT = (v >> (32 - shift)) & 1 ? true : false; \
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value = v << shift; \
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} else { \
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value = 0; \
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C_OUT = false; \
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} \
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} else { \
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value = rm; \
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}
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#endif
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// OP Rd,Rb,Rm LSR #
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#ifndef VALUE_LSR_IMM_C
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#define VALUE_LSR_IMM_C \
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unsigned int shift = (opcode >> 7) & 0x1F; \
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u32 shift = (opcode >> 7) & 0x1F; \
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if (LIKELY(shift)) { \
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u32 v = reg[opcode & 0x0F].I; \
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C_OUT = (v >> (shift - 1)) & 1 ? true : false; \
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@ -787,12 +791,16 @@ static void count(u32 opcode, int cond_res)
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#ifndef VALUE_LSR_REG_C
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#define VALUE_LSR_REG_C \
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unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
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u32 rm = reg[opcode & 0x0F].I; \
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if((opcode & 0x0F) == 15) { \
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rm += 4; \
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} \
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if (LIKELY(shift)) { \
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if (shift == 32) { \
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value = 0; \
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C_OUT = (reg[opcode & 0x0F].I & 0x80000000 ? true : false);\
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C_OUT = (rm & 0x80000000 ? true : false);\
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} else if (LIKELY(shift < 32)) { \
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u32 v = reg[opcode & 0x0F].I; \
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u32 v = rm; \
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C_OUT = (v >> (shift - 1)) & 1 ? true : false;\
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value = v >> shift; \
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} else { \
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@ -800,7 +808,7 @@ static void count(u32 opcode, int cond_res)
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C_OUT = false; \
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} \
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} else { \
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value = reg[opcode & 0x0F].I; \
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value = rm; \
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}
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#endif
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// OP Rd,Rb,Rm ASR #
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@ -826,13 +834,17 @@ static void count(u32 opcode, int cond_res)
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#ifndef VALUE_ASR_REG_C
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#define VALUE_ASR_REG_C \
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unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
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u32 rm = reg[opcode & 0x0F].I; \
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if((opcode & 0x0F) == 15) { \
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rm += 4; \
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} \
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if (LIKELY(shift < 32)) { \
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if (LIKELY(shift)) { \
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s32 v = reg[opcode & 0x0F].I; \
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s32 v = rm; \
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C_OUT = (v >> (int)(shift - 1)) & 1 ? true : false;\
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value = v >> (int)shift; \
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} else { \
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value = reg[opcode & 0x0F].I; \
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value = rm; \
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} \
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} else { \
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if (reg[opcode & 0x0F].I & 0x80000000) { \
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@ -864,17 +876,20 @@ static void count(u32 opcode, int cond_res)
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#ifndef VALUE_ROR_REG_C
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#define VALUE_ROR_REG_C \
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unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
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u32 rm = reg[opcode & 0x0F].I; \
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if((opcode & 0x0F) == 15) { \
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rm += 4; \
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} \
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if (LIKELY(shift & 0x1F)) { \
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u32 v = reg[opcode & 0x0F].I; \
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u32 v = rm; \
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C_OUT = (v >> (shift - 1)) & 1 ? true : false; \
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value = ((v << (32 - shift)) | \
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(v >> shift)); \
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} else { \
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value = reg[opcode & 0x0F].I; \
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value = rm; \
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if (shift) \
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C_OUT = (value & 0x80000000 ? true : false);\
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}
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#endif
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}#endif
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// OP Rd,Rb,# ROR #
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#ifndef VALUE_IMM_C
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#define VALUE_IMM_C \
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