From 26c8c61b88ec702b1c5eb967db19d14af7e0cbd9 Mon Sep 17 00:00:00 2001 From: retro-wertz Date: Tue, 5 Jun 2018 18:43:32 +0800 Subject: [PATCH] Fix some formatting alignments in arm/thumb opcodes --- src/gba/GBA-arm.cpp | 154 +-- src/gba/GBA-thumb.cpp | 2425 +++++++++++++++++++++-------------------- 2 files changed, 1290 insertions(+), 1289 deletions(-) diff --git a/src/gba/GBA-arm.cpp b/src/gba/GBA-arm.cpp index cee81cd5..5cd1f098 100644 --- a/src/gba/GBA-arm.cpp +++ b/src/gba/GBA-arm.cpp @@ -593,10 +593,10 @@ static void count(uint32_t opcode, int cond_res) EMIT2(cmp, KONST(0x3C), esi) \ EMIT1(je, LABELREF(8, f)) \ OP SETCOND \ - EMIT1(jmp, LABELREF(9, f)) \ - LABEL(8) \ - OP \ - LABEL(9) + EMIT1(jmp, LABELREF(9, f)) \ + LABEL(8) \ + OP \ + LABEL(9) #define OP_AND \ EMIT2(and, eax, edx) \ @@ -692,19 +692,19 @@ static void count(uint32_t opcode, int cond_res) #define ROR_IMM_MSR \ __asm { \ __asm mov ecx, shift \ - __asm ror value, cl \ + __asm ror value, cl \ } #define ROR_OFFSET \ __asm { \ __asm mov ecx, shift \ - __asm ror offset, cl \ + __asm ror offset, cl \ } #define RRX_OFFSET \ __asm { \ __asm bt dword ptr C_FLAG, 0 \ - __asm rcr offset, 1 \ + __asm rcr offset, 1 \ } #endif // !__GNUC__ @@ -714,19 +714,19 @@ static void count(uint32_t opcode, int cond_res) // C core -#define C_SETCOND_LOGICAL \ +#define C_SETCOND_LOGICAL \ N_FLAG = ((int32_t)res < 0) ? true : false; \ - Z_FLAG = (res == 0) ? true : false; \ + Z_FLAG = (res == 0) ? true : false; \ C_FLAG = C_OUT; -#define C_SETCOND_ADD \ - N_FLAG = ((int32_t)res < 0) ? true : false; \ - Z_FLAG = (res == 0) ? true : false; \ - V_FLAG = ((NEG(lhs) & NEG(rhs) & POS(res)) | (POS(lhs) & POS(rhs) & NEG(res))) ? true : false; \ +#define C_SETCOND_ADD \ + N_FLAG = ((int32_t)res < 0) ? true : false; \ + Z_FLAG = (res == 0) ? true : false; \ + V_FLAG = ((NEG(lhs) & NEG(rhs) & POS(res)) | (POS(lhs) & POS(rhs) & NEG(res))) ? true : false; \ C_FLAG = ((NEG(lhs) & NEG(rhs)) | (NEG(lhs) & POS(res)) | (NEG(rhs) & POS(res))) ? true : false; -#define C_SETCOND_SUB \ - N_FLAG = ((int32_t)res < 0) ? true : false; \ - Z_FLAG = (res == 0) ? true : false; \ - V_FLAG = ((NEG(lhs) & POS(rhs) & POS(res)) | (POS(lhs) & NEG(rhs) & NEG(res))) ? true : false; \ +#define C_SETCOND_SUB \ + N_FLAG = ((int32_t)res < 0) ? true : false; \ + Z_FLAG = (res == 0) ? true : false; \ + V_FLAG = ((NEG(lhs) & POS(rhs) & POS(res)) | (POS(lhs) & NEG(rhs) & NEG(res))) ? true : false; \ C_FLAG = ((NEG(lhs) & POS(rhs)) | (NEG(lhs) & POS(res)) | (POS(rhs) & POS(res))) ? true : false; #define maybe_unused(var) (void) var @@ -744,7 +744,7 @@ static void count(uint32_t opcode, int cond_res) if (LIKELY(!shift)) { /* LSL #0 most common? */ \ value = reg[opcode & 0x0F].I; \ } else { \ - uint32_t v = reg[opcode & 0x0F].I; \ + uint32_t v = reg[opcode & 0x0F].I; \ C_OUT = (v >> (32 - shift)) & 1 ? true : false; \ value = v << shift; \ } @@ -752,8 +752,8 @@ static void count(uint32_t opcode, int cond_res) // OP Rd,Rb,Rm LSL Rs #ifndef VALUE_LSL_REG_C #define VALUE_LSL_REG_C \ - uint32_t shift = reg[(opcode >> 8) & 15].B.B0; \ - uint32_t rm = reg[opcode & 0x0F].I; \ + uint32_t shift = reg[(opcode >> 8) & 15].B.B0; \ + uint32_t rm = reg[opcode & 0x0F].I; \ if ((opcode & 0x0F) == 15) { \ rm += 4; \ } \ @@ -762,7 +762,7 @@ static void count(uint32_t opcode, int cond_res) value = 0; \ C_OUT = (rm & 1 ? true : false); \ } else if (LIKELY(shift < 32)) { \ - uint32_t v = rm; \ + uint32_t v = rm; \ C_OUT = (v >> (32 - shift)) & 1 ? true : false; \ value = v << shift; \ } else { \ @@ -776,9 +776,9 @@ static void count(uint32_t opcode, int cond_res) // OP Rd,Rb,Rm LSR # #ifndef VALUE_LSR_IMM_C #define VALUE_LSR_IMM_C \ - uint32_t shift = (opcode >> 7) & 0x1F; \ + uint32_t shift = (opcode >> 7) & 0x1F; \ if (LIKELY(shift)) { \ - uint32_t v = reg[opcode & 0x0F].I; \ + uint32_t v = reg[opcode & 0x0F].I; \ C_OUT = (v >> (shift - 1)) & 1 ? true : false; \ value = v >> shift; \ } else { \ @@ -790,7 +790,7 @@ static void count(uint32_t opcode, int cond_res) #ifndef VALUE_LSR_REG_C #define VALUE_LSR_REG_C \ unsigned int shift = reg[(opcode >> 8) & 15].B.B0; \ - uint32_t rm = reg[opcode & 0x0F].I; \ + uint32_t rm = reg[opcode & 0x0F].I; \ if ((opcode & 0x0F) == 15) { \ rm += 4; \ } \ @@ -799,7 +799,7 @@ static void count(uint32_t opcode, int cond_res) value = 0; \ C_OUT = (rm & 0x80000000 ? true : false); \ } else if (LIKELY(shift < 32)) { \ - uint32_t v = rm; \ + uint32_t v = rm; \ C_OUT = (v >> (shift - 1)) & 1 ? true : false; \ value = v >> shift; \ } else { \ @@ -816,7 +816,7 @@ static void count(uint32_t opcode, int cond_res) unsigned int shift = (opcode >> 7) & 0x1F; \ if (LIKELY(shift)) { \ /* VC++ BUG: uint32_t v; (int32_t)v>>n is optimized to shr! */ \ - int32_t v = reg[opcode & 0x0F].I; \ + int32_t v = reg[opcode & 0x0F].I; \ C_OUT = (v >> (int)(shift - 1)) & 1 ? true : false; \ value = v >> (int)shift; \ } else { \ @@ -833,13 +833,13 @@ static void count(uint32_t opcode, int cond_res) #ifndef VALUE_ASR_REG_C #define VALUE_ASR_REG_C \ unsigned int shift = reg[(opcode >> 8) & 15].B.B0; \ - uint32_t rm = reg[opcode & 0x0F].I; \ + uint32_t rm = reg[opcode & 0x0F].I; \ if ((opcode & 0x0F) == 15) { \ rm += 4; \ } \ if (LIKELY(shift < 32)) { \ if (LIKELY(shift)) { \ - int32_t v = rm; \ + int32_t v = rm; \ C_OUT = (v >> (int)(shift - 1)) & 1 ? true : false; \ value = v >> (int)shift; \ } else { \ @@ -860,11 +860,11 @@ static void count(uint32_t opcode, int cond_res) #define VALUE_ROR_IMM_C \ unsigned int shift = (opcode >> 7) & 0x1F; \ if (LIKELY(shift)) { \ - uint32_t v = reg[opcode & 0x0F].I; \ + uint32_t v = reg[opcode & 0x0F].I; \ C_OUT = (v >> (shift - 1)) & 1 ? true : false; \ value = ((v << (32 - shift)) | (v >> shift)); \ } else { \ - uint32_t v = reg[opcode & 0x0F].I; \ + uint32_t v = reg[opcode & 0x0F].I; \ C_OUT = (v & 1) ? true : false; \ value = ((v >> 1) | (C_FLAG << 31)); \ } @@ -873,12 +873,12 @@ static void count(uint32_t opcode, int cond_res) #ifndef VALUE_ROR_REG_C #define VALUE_ROR_REG_C \ unsigned int shift = reg[(opcode >> 8) & 15].B.B0; \ - uint32_t rm = reg[opcode & 0x0F].I; \ + uint32_t rm = reg[opcode & 0x0F].I; \ if ((opcode & 0x0F) == 15) { \ rm += 4; \ } \ if (LIKELY(shift & 0x1F)) { \ - uint32_t v = rm; \ + uint32_t v = rm; \ C_OUT = (v >> (shift - 1)) & 1 ? true : false; \ value = ((v << (32 - shift)) | (v >> shift)); \ } else { \ @@ -892,7 +892,7 @@ static void count(uint32_t opcode, int cond_res) #define VALUE_IMM_C \ int shift = (opcode & 0xF00) >> 7; \ if (UNLIKELY(shift)) { \ - uint32_t v = opcode & 0xFF; \ + uint32_t v = opcode & 0xFF; \ C_OUT = (v >> (shift - 1)) & 1 ? true : false; \ value = ((v << (32 - shift)) | (v >> shift)); \ } else { \ @@ -938,7 +938,7 @@ static void count(uint32_t opcode, int cond_res) SETCOND \ } #ifndef OP_AND -#define OP_AND \ +#define OP_AND \ uint32_t res = reg[(opcode >> 16) & 15].I & value; \ reg[dest].I = res; #endif @@ -946,7 +946,7 @@ static void count(uint32_t opcode, int cond_res) #define OP_ANDS OP_AND C_CHECK_PC(C_SETCOND_LOGICAL) #endif #ifndef OP_EOR -#define OP_EOR \ +#define OP_EOR \ uint32_t res = reg[(opcode >> 16) & 15].I ^ value; \ reg[dest].I = res; #endif @@ -954,7 +954,7 @@ static void count(uint32_t opcode, int cond_res) #define OP_EORS OP_EOR C_CHECK_PC(C_SETCOND_LOGICAL) #endif #ifndef OP_SUB -#define OP_SUB \ +#define OP_SUB \ uint32_t lhs = reg[(opcode >> 16) & 15].I; \ uint32_t rhs = value; \ uint32_t res = lhs - rhs; \ @@ -964,7 +964,7 @@ static void count(uint32_t opcode, int cond_res) #define OP_SUBS OP_SUB C_CHECK_PC(C_SETCOND_SUB) #endif #ifndef OP_RSB -#define OP_RSB \ +#define OP_RSB \ uint32_t lhs = value; \ uint32_t rhs = reg[(opcode >> 16) & 15].I; \ uint32_t res = lhs - rhs; \ @@ -974,7 +974,7 @@ static void count(uint32_t opcode, int cond_res) #define OP_RSBS OP_RSB C_CHECK_PC(C_SETCOND_SUB) #endif #ifndef OP_ADD -#define OP_ADD \ +#define OP_ADD \ uint32_t lhs = reg[(opcode >> 16) & 15].I; \ uint32_t rhs = value; \ uint32_t res = lhs + rhs; \ @@ -984,19 +984,19 @@ static void count(uint32_t opcode, int cond_res) #define OP_ADDS OP_ADD C_CHECK_PC(C_SETCOND_ADD) #endif #ifndef OP_ADC -#define OP_ADC \ - uint32_t lhs = reg[(opcode >> 16) & 15].I; \ - uint32_t rhs = value; \ - uint32_t res = lhs + rhs + (uint32_t)C_FLAG; \ +#define OP_ADC \ + uint32_t lhs = reg[(opcode >> 16) & 15].I; \ + uint32_t rhs = value; \ + uint32_t res = lhs + rhs + (uint32_t)C_FLAG; \ reg[dest].I = res; #endif #ifndef OP_ADCS #define OP_ADCS OP_ADC C_CHECK_PC(C_SETCOND_ADD) #endif #ifndef OP_SBC -#define OP_SBC \ - uint32_t lhs = reg[(opcode >> 16) & 15].I; \ - uint32_t rhs = value; \ +#define OP_SBC \ + uint32_t lhs = reg[(opcode >> 16) & 15].I; \ + uint32_t rhs = value; \ uint32_t res = lhs - rhs - !((uint32_t)C_FLAG); \ reg[dest].I = res; #endif @@ -1004,9 +1004,9 @@ static void count(uint32_t opcode, int cond_res) #define OP_SBCS OP_SBC C_CHECK_PC(C_SETCOND_SUB) #endif #ifndef OP_RSC -#define OP_RSC \ - uint32_t lhs = value; \ - uint32_t rhs = reg[(opcode >> 16) & 15].I; \ +#define OP_RSC \ + uint32_t lhs = value; \ + uint32_t rhs = reg[(opcode >> 16) & 15].I; \ uint32_t res = lhs - rhs - !((uint32_t)C_FLAG); \ reg[dest].I = res; #endif @@ -1014,31 +1014,31 @@ static void count(uint32_t opcode, int cond_res) #define OP_RSCS OP_RSC C_CHECK_PC(C_SETCOND_SUB) #endif #ifndef OP_TST -#define OP_TST \ +#define OP_TST \ uint32_t res = reg[(opcode >> 16) & 0x0F].I & value; \ C_SETCOND_LOGICAL; #endif #ifndef OP_TEQ -#define OP_TEQ \ +#define OP_TEQ \ uint32_t res = reg[(opcode >> 16) & 0x0F].I ^ value; \ C_SETCOND_LOGICAL; #endif #ifndef OP_CMP -#define OP_CMP \ +#define OP_CMP \ uint32_t lhs = reg[(opcode >> 16) & 15].I; \ uint32_t rhs = value; \ uint32_t res = lhs - rhs; \ C_SETCOND_SUB; #endif #ifndef OP_CMN -#define OP_CMN \ +#define OP_CMN \ uint32_t lhs = reg[(opcode >> 16) & 15].I; \ uint32_t rhs = value; \ uint32_t res = lhs + rhs; \ C_SETCOND_ADD; #endif #ifndef OP_ORR -#define OP_ORR \ +#define OP_ORR \ uint32_t res = reg[(opcode >> 16) & 0x0F].I | value; \ reg[dest].I = res; #endif @@ -1046,7 +1046,7 @@ static void count(uint32_t opcode, int cond_res) #define OP_ORRS OP_ORR C_CHECK_PC(C_SETCOND_LOGICAL) #endif #ifndef OP_MOV -#define OP_MOV \ +#define OP_MOV \ uint32_t res = value; \ reg[dest].I = res; #endif @@ -1054,7 +1054,7 @@ static void count(uint32_t opcode, int cond_res) #define OP_MOVS OP_MOV C_CHECK_PC(C_SETCOND_LOGICAL) #endif #ifndef OP_BIC -#define OP_BIC \ +#define OP_BIC \ uint32_t res = reg[(opcode >> 16) & 0x0F].I & (~value); \ reg[dest].I = res; #endif @@ -1062,7 +1062,7 @@ static void count(uint32_t opcode, int cond_res) #define OP_BICS OP_BIC C_CHECK_PC(C_SETCOND_LOGICAL) #endif #ifndef OP_MVN -#define OP_MVN \ +#define OP_MVN \ uint32_t res = ~value; \ reg[dest].I = res; #endif @@ -1074,7 +1074,7 @@ static void count(uint32_t opcode, int cond_res) #define SETCOND_NONE /*nothing*/ #endif #ifndef SETCOND_MUL -#define SETCOND_MUL \ +#define SETCOND_MUL \ N_FLAG = ((int32_t)reg[dest].I < 0) ? true : false; \ Z_FLAG = reg[dest].I ? false : true; #endif @@ -1089,7 +1089,7 @@ static void count(uint32_t opcode, int cond_res) #endif #ifndef ROR_IMM_MSR -#define ROR_IMM_MSR \ +#define ROR_IMM_MSR \ uint32_t v = opcode & 0xff; \ value = ((v << (32 - shift)) | (v >> shift)); #endif @@ -1137,7 +1137,7 @@ static void count(uint32_t opcode, int cond_res) #define MODECHANGE_NO /*nothing*/ #define MODECHANGE_YES CPUSwitchMode(reg[17].I & 0x1f, false); -#define DEFINE_ALU_INSN_C(CODE1, CODE2, OP, MODECHANGE) \ +#define DEFINE_ALU_INSN_C(CODE1, CODE2, OP, MODECHANGE) \ static INSN_REGPARM void arm##CODE1##0(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSL_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); } \ static INSN_REGPARM void arm##CODE1##1(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSL_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); } \ static INSN_REGPARM void arm##CODE1##2(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); } \ @@ -1147,7 +1147,7 @@ static void count(uint32_t opcode, int cond_res) static INSN_REGPARM void arm##CODE1##6(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_ROR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); } \ static INSN_REGPARM void arm##CODE1##7(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_ROR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); } \ static INSN_REGPARM void arm##CODE2##0(uint32_t opcode) { ALU_INSN(ALU_INIT_C, VALUE_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); } -#define DEFINE_ALU_INSN_NC(CODE1, CODE2, OP, MODECHANGE) \ +#define DEFINE_ALU_INSN_NC(CODE1, CODE2, OP, MODECHANGE) \ static INSN_REGPARM void arm##CODE1##0(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSL_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); } \ static INSN_REGPARM void arm##CODE1##1(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSL_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); } \ static INSN_REGPARM void arm##CODE1##2(uint32_t opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); } \ @@ -1237,12 +1237,12 @@ DEFINE_ALU_INSN_C(1F, 3F, MVNS, YES) // CYCLES: base cycle count (1, 2, or 3) #define MUL_INSN(OP, SETCOND, CYCLES) \ int mult = (opcode & 0x0F); \ - uint32_t rs = reg[(opcode >> 8) & 0x0F].I; \ + uint32_t rs = reg[(opcode >> 8) & 0x0F].I; \ int acc = (opcode >> 12) & 0x0F; /* or destLo */ \ int dest = (opcode >> 16) & 0x0F; /* or destHi */ \ OP; \ SETCOND; \ - if ((int32_t)rs < 0) \ + if ((int32_t)rs < 0) \ rs = ~rs; \ if ((rs & 0xFFFFFF00) == 0) \ clockTicks += 0; \ @@ -1268,13 +1268,13 @@ typedef int64_t s32; #define OP_MULL(SIGN) \ SIGN##64 res = (SIGN##64)(SIGN##32)reg[mult].I \ * (SIGN##64)(SIGN##32)rs; \ - reg[acc].I = (uint32_t)res; \ + reg[acc].I = (uint32_t)res; \ reg[dest].I = (uint32_t)(res >> 32); #define OP_MLAL(SIGN) \ SIGN##64 res = ((SIGN##64)reg[dest].I << 32 | reg[acc].I) \ + ((SIGN##64)(SIGN##32)reg[mult].I \ * (SIGN##64)(SIGN##32)rs); \ - reg[acc].I = (uint32_t)res; \ + reg[acc].I = (uint32_t)res; \ reg[dest].I = (uint32_t)(res >> 32); #define OP_UMULL OP_MULL(u) #define OP_UMLAL OP_MLAL(u) @@ -1508,22 +1508,22 @@ static INSN_REGPARM void arm121(uint32_t opcode) #define OFFSET_LSR \ int shift = (opcode >> 7) & 31; \ int offset = shift ? reg[opcode & 15].I >> shift : 0; -#define OFFSET_ASR \ - int shift = (opcode >> 7) & 31; \ - int offset; \ - if (shift) \ +#define OFFSET_ASR \ + int shift = (opcode >> 7) & 31; \ + int offset; \ + if (shift) \ offset = (int)((int32_t)reg[opcode & 15].I >> shift); \ - else if (reg[opcode & 15].I & 0x80000000) \ - offset = 0xFFFFFFFF; \ - else \ + else if (reg[opcode & 15].I & 0x80000000) \ + offset = 0xFFFFFFFF; \ + else \ offset = 0; -#define OFFSET_ROR \ - int shift = (opcode >> 7) & 31; \ +#define OFFSET_ROR \ + int shift = (opcode >> 7) & 31; \ uint32_t offset = reg[opcode & 15].I; \ - if (shift) { \ - ROR_OFFSET; \ - } else { \ - RRX_OFFSET; \ + if (shift) { \ + ROR_OFFSET; \ + } else { \ + RRX_OFFSET; \ } #define ADDRESS_POST (reg[base].I) diff --git a/src/gba/GBA-thumb.cpp b/src/gba/GBA-thumb.cpp index 1aeb4c8c..1b1844fb 100644 --- a/src/gba/GBA-thumb.cpp +++ b/src/gba/GBA-thumb.cpp @@ -572,9 +572,9 @@ static INSN_REGPARM void thumbBreakpoint(uint32_t opcode) #ifndef ADD_RD_RS_RN #define ADD_RD_RS_RN(N) \ { \ - uint32_t lhs = reg[source].I; \ - uint32_t rhs = reg[N].I; \ - uint32_t res = lhs + rhs; \ + uint32_t lhs = reg[source].I; \ + uint32_t rhs = reg[N].I; \ + uint32_t res = lhs + rhs; \ reg[dest].I = res; \ Z_FLAG = (res == 0) ? true : false; \ N_FLAG = NEG(res) ? true : false; \ @@ -585,9 +585,9 @@ static INSN_REGPARM void thumbBreakpoint(uint32_t opcode) #ifndef ADD_RD_RS_O3 #define ADD_RD_RS_O3(N) \ { \ - uint32_t lhs = reg[source].I; \ - uint32_t rhs = N; \ - uint32_t res = lhs + rhs; \ + uint32_t lhs = reg[source].I; \ + uint32_t rhs = N; \ + uint32_t res = lhs + rhs; \ reg[dest].I = res; \ Z_FLAG = (res == 0) ? true : false; \ N_FLAG = NEG(res) ? true : false; \ @@ -601,9 +601,9 @@ static INSN_REGPARM void thumbBreakpoint(uint32_t opcode) #ifndef ADD_RN_O8 #define ADD_RN_O8(d) \ { \ - uint32_t lhs = reg[(d)].I; \ - uint32_t rhs = (opcode & 255); \ - uint32_t res = lhs + rhs; \ + uint32_t lhs = reg[(d)].I; \ + uint32_t rhs = (opcode & 255); \ + uint32_t res = lhs + rhs; \ reg[(d)].I = res; \ Z_FLAG = (res == 0) ? true : false; \ N_FLAG = NEG(res) ? true : false; \ @@ -614,9 +614,9 @@ static INSN_REGPARM void thumbBreakpoint(uint32_t opcode) #ifndef CMN_RD_RS #define CMN_RD_RS \ { \ - uint32_t lhs = reg[dest].I; \ - uint32_t rhs = value; \ - uint32_t res = lhs + rhs; \ + uint32_t lhs = reg[dest].I; \ + uint32_t rhs = value; \ + uint32_t res = lhs + rhs; \ Z_FLAG = (res == 0) ? true : false; \ N_FLAG = NEG(res) ? true : false; \ ADDCARRY(lhs, rhs, res); \ @@ -624,24 +624,24 @@ static INSN_REGPARM void thumbBreakpoint(uint32_t opcode) } #endif #ifndef ADC_RD_RS -#define ADC_RD_RS \ - { \ - uint32_t lhs = reg[dest].I; \ - uint32_t rhs = value; \ - uint32_t res = lhs + rhs + (uint32_t)C_FLAG; \ - reg[dest].I = res; \ - Z_FLAG = (res == 0) ? true : false; \ - N_FLAG = NEG(res) ? true : false; \ - ADDCARRY(lhs, rhs, res); \ - ADDOVERFLOW(lhs, rhs, res); \ +#define ADC_RD_RS \ + { \ + uint32_t lhs = reg[dest].I; \ + uint32_t rhs = value; \ + uint32_t res = lhs + rhs + (uint32_t)C_FLAG; \ + reg[dest].I = res; \ + Z_FLAG = (res == 0) ? true : false; \ + N_FLAG = NEG(res) ? true : false; \ + ADDCARRY(lhs, rhs, res); \ + ADDOVERFLOW(lhs, rhs, res); \ } #endif #ifndef SUB_RD_RS_RN #define SUB_RD_RS_RN(N) \ { \ - uint32_t lhs = reg[source].I; \ - uint32_t rhs = reg[N].I; \ - uint32_t res = lhs - rhs; \ + uint32_t lhs = reg[source].I; \ + uint32_t rhs = reg[N].I; \ + uint32_t res = lhs - rhs; \ reg[dest].I = res; \ Z_FLAG = (res == 0) ? true : false; \ N_FLAG = NEG(res) ? true : false; \ @@ -652,9 +652,9 @@ static INSN_REGPARM void thumbBreakpoint(uint32_t opcode) #ifndef SUB_RD_RS_O3 #define SUB_RD_RS_O3(N) \ { \ - uint32_t lhs = reg[source].I; \ - uint32_t rhs = N; \ - uint32_t res = lhs - rhs; \ + uint32_t lhs = reg[source].I; \ + uint32_t rhs = N; \ + uint32_t res = lhs - rhs; \ reg[dest].I = res; \ Z_FLAG = (res == 0) ? true : false; \ N_FLAG = NEG(res) ? true : false; \ @@ -668,9 +668,9 @@ static INSN_REGPARM void thumbBreakpoint(uint32_t opcode) #ifndef SUB_RN_O8 #define SUB_RN_O8(d) \ { \ - uint32_t lhs = reg[(d)].I; \ - uint32_t rhs = (opcode & 255); \ - uint32_t res = lhs - rhs; \ + uint32_t lhs = reg[(d)].I; \ + uint32_t rhs = (opcode & 255); \ + uint32_t res = lhs - rhs; \ reg[(d)].I = res; \ Z_FLAG = (res == 0) ? true : false; \ N_FLAG = NEG(res) ? true : false; \ @@ -689,9 +689,9 @@ static INSN_REGPARM void thumbBreakpoint(uint32_t opcode) #ifndef CMP_RN_O8 #define CMP_RN_O8(d) \ { \ - uint32_t lhs = reg[(d)].I; \ - uint32_t rhs = (opcode & 255); \ - uint32_t res = lhs - rhs; \ + uint32_t lhs = reg[(d)].I; \ + uint32_t rhs = (opcode & 255); \ + uint32_t res = lhs - rhs; \ Z_FLAG = (res == 0) ? true : false; \ N_FLAG = NEG(res) ? true : false; \ SUBCARRY(lhs, rhs, res); \ @@ -699,16 +699,16 @@ static INSN_REGPARM void thumbBreakpoint(uint32_t opcode) } #endif #ifndef SBC_RD_RS -#define SBC_RD_RS \ - { \ - uint32_t lhs = reg[dest].I; \ - uint32_t rhs = value; \ +#define SBC_RD_RS \ + { \ + uint32_t lhs = reg[dest].I; \ + uint32_t rhs = value; \ uint32_t res = lhs - rhs - !((uint32_t)C_FLAG); \ - reg[dest].I = res; \ - Z_FLAG = (res == 0) ? true : false; \ - N_FLAG = NEG(res) ? true : false; \ - SUBCARRY(lhs, rhs, res); \ - SUBOVERFLOW(lhs, rhs, res); \ + reg[dest].I = res; \ + Z_FLAG = (res == 0) ? true : false; \ + N_FLAG = NEG(res) ? true : false; \ + SUBCARRY(lhs, rhs, res); \ + SUBOVERFLOW(lhs, rhs, res); \ } #endif #ifndef LSL_RD_RM_I5 @@ -740,15 +740,15 @@ static INSN_REGPARM void thumbBreakpoint(uint32_t opcode) } #endif #ifndef ASR_RD_RM_I5 -#define ASR_RD_RM_I5 \ - { \ +#define ASR_RD_RM_I5 \ + { \ C_FLAG = ((int32_t)reg[source].I >> (int)(shift - 1)) & 1 ? true : false; \ value = (int32_t)reg[source].I >> (int)shift; \ } #endif #ifndef ASR_RD_RS -#define ASR_RD_RS \ - { \ +#define ASR_RD_RS \ + { \ C_FLAG = ((int32_t)reg[dest].I >> (int)(value - 1)) & 1 ? true : false; \ value = (int32_t)reg[dest].I >> (int)value; \ } @@ -763,9 +763,9 @@ static INSN_REGPARM void thumbBreakpoint(uint32_t opcode) #ifndef NEG_RD_RS #define NEG_RD_RS \ { \ - uint32_t lhs = reg[source].I; \ - uint32_t rhs = 0; \ - uint32_t res = rhs - lhs; \ + uint32_t lhs = reg[source].I; \ + uint32_t rhs = 0; \ + uint32_t res = rhs - lhs; \ reg[dest].I = res; \ Z_FLAG = (res == 0) ? true : false; \ N_FLAG = NEG(res) ? true : false; \ @@ -776,9 +776,9 @@ static INSN_REGPARM void thumbBreakpoint(uint32_t opcode) #ifndef CMP_RD_RS #define CMP_RD_RS \ { \ - uint32_t lhs = reg[dest].I; \ - uint32_t rhs = value; \ - uint32_t res = lhs - rhs; \ + uint32_t lhs = reg[dest].I; \ + uint32_t rhs = value; \ + uint32_t res = lhs - rhs; \ Z_FLAG = (res == 0) ? true : false; \ N_FLAG = NEG(res) ? true : false; \ SUBCARRY(lhs, rhs, res); \ @@ -789,7 +789,7 @@ static INSN_REGPARM void thumbBreakpoint(uint32_t opcode) #define IMM5_INSN(OP, N) \ int dest = opcode & 0x07; \ int source = (opcode >> 3) & 0x07; \ - uint32_t value; \ + uint32_t value; \ OP(N); \ reg[dest].I = value; \ N_FLAG = (value & 0x80000000 ? true : false); \ @@ -797,7 +797,7 @@ static INSN_REGPARM void thumbBreakpoint(uint32_t opcode) #define IMM5_INSN_0(OP) \ int dest = opcode & 0x07; \ int source = (opcode >> 3) & 0x07; \ - uint32_t value; \ + uint32_t value; \ OP; \ reg[dest].I = value; \ N_FLAG = (value & 0x80000000 ? true : false); \ @@ -832,9 +832,9 @@ static INSN_REGPARM void thumbBreakpoint(uint32_t opcode) OP(N); #endif - // Shift instructions ///////////////////////////////////////////////////// +// Shift instructions ///////////////////////////////////////////////////// -#define DEFINE_IMM5_INSN(OP, BASE) \ +#define DEFINE_IMM5_INSN(OP, BASE) \ static INSN_REGPARM void thumb##BASE##_00(uint32_t opcode) { IMM5_INSN_0(OP##_0); } \ static INSN_REGPARM void thumb##BASE##_01(uint32_t opcode) { IMM5_INSN(OP, 1); } \ static INSN_REGPARM void thumb##BASE##_02(uint32_t opcode) { IMM5_INSN(OP, 2); } \ @@ -868,16 +868,16 @@ static INSN_REGPARM void thumbBreakpoint(uint32_t opcode) static INSN_REGPARM void thumb##BASE##_1E(uint32_t opcode) { IMM5_INSN(OP, 30); } \ static INSN_REGPARM void thumb##BASE##_1F(uint32_t opcode) { IMM5_INSN(OP, 31); } - // LSL Rd, Rm, #Imm 5 - DEFINE_IMM5_INSN(IMM5_LSL, 00) - // LSR Rd, Rm, #Imm 5 - DEFINE_IMM5_INSN(IMM5_LSR, 08) - // ASR Rd, Rm, #Imm 5 - DEFINE_IMM5_INSN(IMM5_ASR, 10) +// LSL Rd, Rm, #Imm 5 +DEFINE_IMM5_INSN(IMM5_LSL, 00) +// LSR Rd, Rm, #Imm 5 +DEFINE_IMM5_INSN(IMM5_LSR, 08) +// ASR Rd, Rm, #Imm 5 +DEFINE_IMM5_INSN(IMM5_ASR, 10) - // 3-argument ADD/SUB ///////////////////////////////////////////////////// +// 3-argument ADD/SUB ///////////////////////////////////////////////////// -#define DEFINE_REG3_INSN(OP, BASE) \ +#define DEFINE_REG3_INSN(OP, BASE) \ static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP, 0); } \ static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP, 1); } \ static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP, 2); } \ @@ -887,7 +887,7 @@ static INSN_REGPARM void thumbBreakpoint(uint32_t opcode) static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP, 6); } \ static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP, 7); } -#define DEFINE_IMM3_INSN(OP, BASE) \ +#define DEFINE_IMM3_INSN(OP, BASE) \ static INSN_REGPARM void thumb##BASE##_0(uint32_t opcode) { THREEARG_INSN(OP##_0, 0); } \ static INSN_REGPARM void thumb##BASE##_1(uint32_t opcode) { THREEARG_INSN(OP, 1); } \ static INSN_REGPARM void thumb##BASE##_2(uint32_t opcode) { THREEARG_INSN(OP, 2); } \ @@ -897,625 +897,624 @@ static INSN_REGPARM void thumbBreakpoint(uint32_t opcode) static INSN_REGPARM void thumb##BASE##_6(uint32_t opcode) { THREEARG_INSN(OP, 6); } \ static INSN_REGPARM void thumb##BASE##_7(uint32_t opcode) { THREEARG_INSN(OP, 7); } - // ADD Rd, Rs, Rn - DEFINE_REG3_INSN(ADD_RD_RS_RN, 18) - // SUB Rd, Rs, Rn - DEFINE_REG3_INSN(SUB_RD_RS_RN, 1A) - // ADD Rd, Rs, #Offset3 - DEFINE_IMM3_INSN(ADD_RD_RS_O3, 1C) - // SUB Rd, Rs, #Offset3 - DEFINE_IMM3_INSN(SUB_RD_RS_O3, 1E) +// ADD Rd, Rs, Rn +DEFINE_REG3_INSN(ADD_RD_RS_RN, 18) +// SUB Rd, Rs, Rn +DEFINE_REG3_INSN(SUB_RD_RS_RN, 1A) +// ADD Rd, Rs, #Offset3 +DEFINE_IMM3_INSN(ADD_RD_RS_O3, 1C) +// SUB Rd, Rs, #Offset3 +DEFINE_IMM3_INSN(SUB_RD_RS_O3, 1E) - // MOV/CMP/ADD/SUB immediate ////////////////////////////////////////////// +// MOV/CMP/ADD/SUB immediate ////////////////////////////////////////////// - // MOV R0, #Offset8 - static INSN_REGPARM void thumb20(uint32_t opcode) { MOV_RN_O8(0); } - // MOV R1, #Offset8 - static INSN_REGPARM void thumb21(uint32_t opcode) { MOV_RN_O8(1); } - // MOV R2, #Offset8 - static INSN_REGPARM void thumb22(uint32_t opcode) { MOV_RN_O8(2); } - // MOV R3, #Offset8 - static INSN_REGPARM void thumb23(uint32_t opcode) { MOV_RN_O8(3); } - // MOV R4, #Offset8 - static INSN_REGPARM void thumb24(uint32_t opcode) { MOV_RN_O8(4); } - // MOV R5, #Offset8 - static INSN_REGPARM void thumb25(uint32_t opcode) { MOV_RN_O8(5); } - // MOV R6, #Offset8 - static INSN_REGPARM void thumb26(uint32_t opcode) { MOV_RN_O8(6); } - // MOV R7, #Offset8 - static INSN_REGPARM void thumb27(uint32_t opcode) { MOV_RN_O8(7); } +// MOV R0, #Offset8 +static INSN_REGPARM void thumb20(uint32_t opcode) { MOV_RN_O8(0); } +// MOV R1, #Offset8 +static INSN_REGPARM void thumb21(uint32_t opcode) { MOV_RN_O8(1); } +// MOV R2, #Offset8 +static INSN_REGPARM void thumb22(uint32_t opcode) { MOV_RN_O8(2); } +// MOV R3, #Offset8 +static INSN_REGPARM void thumb23(uint32_t opcode) { MOV_RN_O8(3); } +// MOV R4, #Offset8 +static INSN_REGPARM void thumb24(uint32_t opcode) { MOV_RN_O8(4); } +// MOV R5, #Offset8 +static INSN_REGPARM void thumb25(uint32_t opcode) { MOV_RN_O8(5); } +// MOV R6, #Offset8 +static INSN_REGPARM void thumb26(uint32_t opcode) { MOV_RN_O8(6); } +// MOV R7, #Offset8 +static INSN_REGPARM void thumb27(uint32_t opcode) { MOV_RN_O8(7); } - // CMP R0, #Offset8 - static INSN_REGPARM void thumb28(uint32_t opcode) { CMP_RN_O8(0); } - // CMP R1, #Offset8 - static INSN_REGPARM void thumb29(uint32_t opcode) { CMP_RN_O8(1); } - // CMP R2, #Offset8 - static INSN_REGPARM void thumb2A(uint32_t opcode) { CMP_RN_O8(2); } - // CMP R3, #Offset8 - static INSN_REGPARM void thumb2B(uint32_t opcode) { CMP_RN_O8(3); } - // CMP R4, #Offset8 - static INSN_REGPARM void thumb2C(uint32_t opcode) { CMP_RN_O8(4); } - // CMP R5, #Offset8 - static INSN_REGPARM void thumb2D(uint32_t opcode) { CMP_RN_O8(5); } - // CMP R6, #Offset8 - static INSN_REGPARM void thumb2E(uint32_t opcode) { CMP_RN_O8(6); } - // CMP R7, #Offset8 - static INSN_REGPARM void thumb2F(uint32_t opcode) { CMP_RN_O8(7); } +// CMP R0, #Offset8 +static INSN_REGPARM void thumb28(uint32_t opcode) { CMP_RN_O8(0); } +// CMP R1, #Offset8 +static INSN_REGPARM void thumb29(uint32_t opcode) { CMP_RN_O8(1); } +// CMP R2, #Offset8 +static INSN_REGPARM void thumb2A(uint32_t opcode) { CMP_RN_O8(2); } +// CMP R3, #Offset8 +static INSN_REGPARM void thumb2B(uint32_t opcode) { CMP_RN_O8(3); } +// CMP R4, #Offset8 +static INSN_REGPARM void thumb2C(uint32_t opcode) { CMP_RN_O8(4); } +// CMP R5, #Offset8 +static INSN_REGPARM void thumb2D(uint32_t opcode) { CMP_RN_O8(5); } +// CMP R6, #Offset8 +static INSN_REGPARM void thumb2E(uint32_t opcode) { CMP_RN_O8(6); } +// CMP R7, #Offset8 +static INSN_REGPARM void thumb2F(uint32_t opcode) { CMP_RN_O8(7); } - // ADD R0,#Offset8 - static INSN_REGPARM void thumb30(uint32_t opcode) { ADD_RN_O8(0); } - // ADD R1,#Offset8 - static INSN_REGPARM void thumb31(uint32_t opcode) { ADD_RN_O8(1); } - // ADD R2,#Offset8 - static INSN_REGPARM void thumb32(uint32_t opcode) { ADD_RN_O8(2); } - // ADD R3,#Offset8 - static INSN_REGPARM void thumb33(uint32_t opcode) { ADD_RN_O8(3); } - // ADD R4,#Offset8 - static INSN_REGPARM void thumb34(uint32_t opcode) { ADD_RN_O8(4); } - // ADD R5,#Offset8 - static INSN_REGPARM void thumb35(uint32_t opcode) { ADD_RN_O8(5); } - // ADD R6,#Offset8 - static INSN_REGPARM void thumb36(uint32_t opcode) { ADD_RN_O8(6); } - // ADD R7,#Offset8 - static INSN_REGPARM void thumb37(uint32_t opcode) { ADD_RN_O8(7); } +// ADD R0,#Offset8 +static INSN_REGPARM void thumb30(uint32_t opcode) { ADD_RN_O8(0); } +// ADD R1,#Offset8 +static INSN_REGPARM void thumb31(uint32_t opcode) { ADD_RN_O8(1); } +// ADD R2,#Offset8 +static INSN_REGPARM void thumb32(uint32_t opcode) { ADD_RN_O8(2); } +// ADD R3,#Offset8 +static INSN_REGPARM void thumb33(uint32_t opcode) { ADD_RN_O8(3); } +// ADD R4,#Offset8 +static INSN_REGPARM void thumb34(uint32_t opcode) { ADD_RN_O8(4); } +// ADD R5,#Offset8 +static INSN_REGPARM void thumb35(uint32_t opcode) { ADD_RN_O8(5); } +// ADD R6,#Offset8 +static INSN_REGPARM void thumb36(uint32_t opcode) { ADD_RN_O8(6); } +// ADD R7,#Offset8 +static INSN_REGPARM void thumb37(uint32_t opcode) { ADD_RN_O8(7); } - // SUB R0,#Offset8 - static INSN_REGPARM void thumb38(uint32_t opcode) { SUB_RN_O8(0); } - // SUB R1,#Offset8 - static INSN_REGPARM void thumb39(uint32_t opcode) { SUB_RN_O8(1); } - // SUB R2,#Offset8 - static INSN_REGPARM void thumb3A(uint32_t opcode) { SUB_RN_O8(2); } - // SUB R3,#Offset8 - static INSN_REGPARM void thumb3B(uint32_t opcode) { SUB_RN_O8(3); } - // SUB R4,#Offset8 - static INSN_REGPARM void thumb3C(uint32_t opcode) { SUB_RN_O8(4); } - // SUB R5,#Offset8 - static INSN_REGPARM void thumb3D(uint32_t opcode) { SUB_RN_O8(5); } - // SUB R6,#Offset8 - static INSN_REGPARM void thumb3E(uint32_t opcode) { SUB_RN_O8(6); } - // SUB R7,#Offset8 - static INSN_REGPARM void thumb3F(uint32_t opcode) { SUB_RN_O8(7); } +// SUB R0,#Offset8 +static INSN_REGPARM void thumb38(uint32_t opcode) { SUB_RN_O8(0); } +// SUB R1,#Offset8 +static INSN_REGPARM void thumb39(uint32_t opcode) { SUB_RN_O8(1); } +// SUB R2,#Offset8 +static INSN_REGPARM void thumb3A(uint32_t opcode) { SUB_RN_O8(2); } +// SUB R3,#Offset8 +static INSN_REGPARM void thumb3B(uint32_t opcode) { SUB_RN_O8(3); } +// SUB R4,#Offset8 +static INSN_REGPARM void thumb3C(uint32_t opcode) { SUB_RN_O8(4); } +// SUB R5,#Offset8 +static INSN_REGPARM void thumb3D(uint32_t opcode) { SUB_RN_O8(5); } +// SUB R6,#Offset8 +static INSN_REGPARM void thumb3E(uint32_t opcode) { SUB_RN_O8(6); } +// SUB R7,#Offset8 +static INSN_REGPARM void thumb3F(uint32_t opcode) { SUB_RN_O8(7); } - // ALU operations ///////////////////////////////////////////////////////// +// ALU operations ///////////////////////////////////////////////////////// - // AND Rd, Rs - static INSN_REGPARM void thumb40_0(uint32_t opcode) - { - int dest = opcode & 7; - reg[dest].I &= reg[(opcode >> 3) & 7].I; - N_FLAG = reg[dest].I & 0x80000000 ? true : false; - Z_FLAG = reg[dest].I ? false : true; - THUMB_CONSOLE_OUTPUT(NULL, reg[2].I); - } +// AND Rd, Rs +static INSN_REGPARM void thumb40_0(uint32_t opcode) +{ + int dest = opcode & 7; + reg[dest].I &= reg[(opcode >> 3) & 7].I; + N_FLAG = reg[dest].I & 0x80000000 ? true : false; + Z_FLAG = reg[dest].I ? false : true; + THUMB_CONSOLE_OUTPUT(NULL, reg[2].I); +} - // EOR Rd, Rs - static INSN_REGPARM void thumb40_1(uint32_t opcode) - { - int dest = opcode & 7; - reg[dest].I ^= reg[(opcode >> 3) & 7].I; - N_FLAG = reg[dest].I & 0x80000000 ? true : false; - Z_FLAG = reg[dest].I ? false : true; - } +// EOR Rd, Rs +static INSN_REGPARM void thumb40_1(uint32_t opcode) +{ + int dest = opcode & 7; + reg[dest].I ^= reg[(opcode >> 3) & 7].I; + N_FLAG = reg[dest].I & 0x80000000 ? true : false; + Z_FLAG = reg[dest].I ? false : true; +} - // LSL Rd, Rs - static INSN_REGPARM void thumb40_2(uint32_t opcode) - { - int dest = opcode & 7; - uint32_t value = reg[(opcode >> 3) & 7].B.B0; - if (value) { - if (value == 32) { - value = 0; - C_FLAG = (reg[dest].I & 1 ? true : false); - } else if (value < 32) { - LSL_RD_RS; - } else { - value = 0; - C_FLAG = false; - } - reg[dest].I = value; - } - N_FLAG = reg[dest].I & 0x80000000 ? true : false; - Z_FLAG = reg[dest].I ? false : true; - clockTicks = codeTicksAccess16(armNextPC) + 2; - } +// LSL Rd, Rs +static INSN_REGPARM void thumb40_2(uint32_t opcode) +{ + int dest = opcode & 7; + uint32_t value = reg[(opcode >> 3) & 7].B.B0; + if (value) { + if (value == 32) { + value = 0; + C_FLAG = (reg[dest].I & 1 ? true : false); + } else if (value < 32) { + LSL_RD_RS; + } else { + value = 0; + C_FLAG = false; + } + reg[dest].I = value; + } + N_FLAG = reg[dest].I & 0x80000000 ? true : false; + Z_FLAG = reg[dest].I ? false : true; + clockTicks = codeTicksAccess16(armNextPC) + 2; +} - // LSR Rd, Rs - static INSN_REGPARM void thumb40_3(uint32_t opcode) - { - int dest = opcode & 7; - uint32_t value = reg[(opcode >> 3) & 7].B.B0; - if (value) { - if (value == 32) { - value = 0; - C_FLAG = (reg[dest].I & 0x80000000 ? true : false); - } else if (value < 32) { - LSR_RD_RS; - } else { - value = 0; - C_FLAG = false; - } - reg[dest].I = value; - } - N_FLAG = reg[dest].I & 0x80000000 ? true : false; - Z_FLAG = reg[dest].I ? false : true; - clockTicks = codeTicksAccess16(armNextPC) + 2; - } +// LSR Rd, Rs +static INSN_REGPARM void thumb40_3(uint32_t opcode) +{ + int dest = opcode & 7; + uint32_t value = reg[(opcode >> 3) & 7].B.B0; + if (value) { + if (value == 32) { + value = 0; + C_FLAG = (reg[dest].I & 0x80000000 ? true : false); + } else if (value < 32) { + LSR_RD_RS; + } else { + value = 0; + C_FLAG = false; + } + reg[dest].I = value; + } + N_FLAG = reg[dest].I & 0x80000000 ? true : false; + Z_FLAG = reg[dest].I ? false : true; + clockTicks = codeTicksAccess16(armNextPC) + 2; +} - // ASR Rd, Rs - static INSN_REGPARM void thumb41_0(uint32_t opcode) - { - int dest = opcode & 7; - uint32_t value = reg[(opcode >> 3) & 7].B.B0; - if (value) { - if (value < 32) { - ASR_RD_RS; - reg[dest].I = value; - } else { - if (reg[dest].I & 0x80000000) { - reg[dest].I = 0xFFFFFFFF; - C_FLAG = true; - } else { - reg[dest].I = 0x00000000; - C_FLAG = false; - } - } - } - N_FLAG = reg[dest].I & 0x80000000 ? true : false; - Z_FLAG = reg[dest].I ? false : true; - clockTicks = codeTicksAccess16(armNextPC) + 2; - } +// ASR Rd, Rs +static INSN_REGPARM void thumb41_0(uint32_t opcode) +{ + int dest = opcode & 7; + uint32_t value = reg[(opcode >> 3) & 7].B.B0; + if (value) { + if (value < 32) { + ASR_RD_RS; + reg[dest].I = value; + } else { + if (reg[dest].I & 0x80000000) { + reg[dest].I = 0xFFFFFFFF; + C_FLAG = true; + } else { + reg[dest].I = 0x00000000; + C_FLAG = false; + } + } + } + N_FLAG = reg[dest].I & 0x80000000 ? true : false; + Z_FLAG = reg[dest].I ? false : true; + clockTicks = codeTicksAccess16(armNextPC) + 2; +} - // ADC Rd, Rs - static INSN_REGPARM void thumb41_1(uint32_t opcode) - { - int dest = opcode & 0x07; - uint32_t value = reg[(opcode >> 3) & 7].I; - ADC_RD_RS; - } +// ADC Rd, Rs +static INSN_REGPARM void thumb41_1(uint32_t opcode) +{ + int dest = opcode & 0x07; + uint32_t value = reg[(opcode >> 3) & 7].I; + ADC_RD_RS; +} - // SBC Rd, Rs - static INSN_REGPARM void thumb41_2(uint32_t opcode) - { - int dest = opcode & 0x07; - uint32_t value = reg[(opcode >> 3) & 7].I; - SBC_RD_RS; - } +// SBC Rd, Rs +static INSN_REGPARM void thumb41_2(uint32_t opcode) +{ + int dest = opcode & 0x07; + uint32_t value = reg[(opcode >> 3) & 7].I; + SBC_RD_RS; +} - // ROR Rd, Rs - static INSN_REGPARM void thumb41_3(uint32_t opcode) - { - int dest = opcode & 7; - uint32_t value = reg[(opcode >> 3) & 7].B.B0; +// ROR Rd, Rs +static INSN_REGPARM void thumb41_3(uint32_t opcode) +{ + int dest = opcode & 7; + uint32_t value = reg[(opcode >> 3) & 7].B.B0; + if (value) { + value = value & 0x1f; + if (value == 0) { + C_FLAG = (reg[dest].I & 0x80000000 ? true : false); + } else { + ROR_RD_RS; + reg[dest].I = value; + } + } + clockTicks = codeTicksAccess16(armNextPC) + 2; + N_FLAG = reg[dest].I & 0x80000000 ? true : false; + Z_FLAG = reg[dest].I ? false : true; +} - if (value) { - value = value & 0x1f; - if (value == 0) { - C_FLAG = (reg[dest].I & 0x80000000 ? true : false); - } else { - ROR_RD_RS; - reg[dest].I = value; - } - } - clockTicks = codeTicksAccess16(armNextPC) + 2; - N_FLAG = reg[dest].I & 0x80000000 ? true : false; - Z_FLAG = reg[dest].I ? false : true; - } +// TST Rd, Rs +static INSN_REGPARM void thumb42_0(uint32_t opcode) +{ + uint32_t value = reg[opcode & 7].I & reg[(opcode >> 3) & 7].I; + N_FLAG = value & 0x80000000 ? true : false; + Z_FLAG = value ? false : true; +} - // TST Rd, Rs - static INSN_REGPARM void thumb42_0(uint32_t opcode) - { - uint32_t value = reg[opcode & 7].I & reg[(opcode >> 3) & 7].I; - N_FLAG = value & 0x80000000 ? true : false; - Z_FLAG = value ? false : true; - } +// NEG Rd, Rs +static INSN_REGPARM void thumb42_1(uint32_t opcode) +{ + int dest = opcode & 7; + int source = (opcode >> 3) & 7; + NEG_RD_RS; +} - // NEG Rd, Rs - static INSN_REGPARM void thumb42_1(uint32_t opcode) - { - int dest = opcode & 7; - int source = (opcode >> 3) & 7; - NEG_RD_RS; - } +// CMP Rd, Rs +static INSN_REGPARM void thumb42_2(uint32_t opcode) +{ + int dest = opcode & 7; + uint32_t value = reg[(opcode >> 3) & 7].I; + CMP_RD_RS; +} - // CMP Rd, Rs - static INSN_REGPARM void thumb42_2(uint32_t opcode) - { - int dest = opcode & 7; - uint32_t value = reg[(opcode >> 3) & 7].I; - CMP_RD_RS; - } +// CMN Rd, Rs +static INSN_REGPARM void thumb42_3(uint32_t opcode) +{ + int dest = opcode & 7; + uint32_t value = reg[(opcode >> 3) & 7].I; + CMN_RD_RS; +} - // CMN Rd, Rs - static INSN_REGPARM void thumb42_3(uint32_t opcode) - { - int dest = opcode & 7; - uint32_t value = reg[(opcode >> 3) & 7].I; - CMN_RD_RS; - } +// ORR Rd, Rs +static INSN_REGPARM void thumb43_0(uint32_t opcode) +{ + int dest = opcode & 7; + reg[dest].I |= reg[(opcode >> 3) & 7].I; + Z_FLAG = reg[dest].I ? false : true; + N_FLAG = reg[dest].I & 0x80000000 ? true : false; +} - // ORR Rd, Rs - static INSN_REGPARM void thumb43_0(uint32_t opcode) - { - int dest = opcode & 7; - reg[dest].I |= reg[(opcode >> 3) & 7].I; - Z_FLAG = reg[dest].I ? false : true; - N_FLAG = reg[dest].I & 0x80000000 ? true : false; - } +// MUL Rd, Rs +static INSN_REGPARM void thumb43_1(uint32_t opcode) +{ + clockTicks = 1; + int dest = opcode & 7; + uint32_t rm = reg[dest].I; + reg[dest].I = reg[(opcode >> 3) & 7].I * rm; + if (((int32_t)rm) < 0) + rm = ~rm; + if ((rm & 0xFFFFFF00) == 0) + clockTicks += 0; + else if ((rm & 0xFFFF0000) == 0) + clockTicks += 1; + else if ((rm & 0xFF000000) == 0) + clockTicks += 2; + else + clockTicks += 3; + busPrefetchCount = (busPrefetchCount << clockTicks) | (0xFF >> (8 - clockTicks)); + clockTicks += codeTicksAccess16(armNextPC) + 1; + Z_FLAG = reg[dest].I ? false : true; + N_FLAG = reg[dest].I & 0x80000000 ? true : false; +} - // MUL Rd, Rs - static INSN_REGPARM void thumb43_1(uint32_t opcode) - { - clockTicks = 1; - int dest = opcode & 7; - uint32_t rm = reg[dest].I; - reg[dest].I = reg[(opcode >> 3) & 7].I * rm; - if (((int32_t)rm) < 0) - rm = ~rm; - if ((rm & 0xFFFFFF00) == 0) - clockTicks += 0; - else if ((rm & 0xFFFF0000) == 0) - clockTicks += 1; - else if ((rm & 0xFF000000) == 0) - clockTicks += 2; - else - clockTicks += 3; - busPrefetchCount = (busPrefetchCount << clockTicks) | (0xFF >> (8 - clockTicks)); - clockTicks += codeTicksAccess16(armNextPC) + 1; - Z_FLAG = reg[dest].I ? false : true; - N_FLAG = reg[dest].I & 0x80000000 ? true : false; - } +// BIC Rd, Rs +static INSN_REGPARM void thumb43_2(uint32_t opcode) +{ + int dest = opcode & 7; + reg[dest].I &= (~reg[(opcode >> 3) & 7].I); + Z_FLAG = reg[dest].I ? false : true; + N_FLAG = reg[dest].I & 0x80000000 ? true : false; +} - // BIC Rd, Rs - static INSN_REGPARM void thumb43_2(uint32_t opcode) - { - int dest = opcode & 7; - reg[dest].I &= (~reg[(opcode >> 3) & 7].I); - Z_FLAG = reg[dest].I ? false : true; - N_FLAG = reg[dest].I & 0x80000000 ? true : false; - } +// MVN Rd, Rs +static INSN_REGPARM void thumb43_3(uint32_t opcode) +{ + int dest = opcode & 7; + reg[dest].I = ~reg[(opcode >> 3) & 7].I; + Z_FLAG = reg[dest].I ? false : true; + N_FLAG = reg[dest].I & 0x80000000 ? true : false; +} - // MVN Rd, Rs - static INSN_REGPARM void thumb43_3(uint32_t opcode) - { - int dest = opcode & 7; - reg[dest].I = ~reg[(opcode >> 3) & 7].I; - Z_FLAG = reg[dest].I ? false : true; - N_FLAG = reg[dest].I & 0x80000000 ? true : false; - } +// High-register instructions and BX ////////////////////////////////////// - // High-register instructions and BX ////////////////////////////////////// +// ADD Rd, Hs +static INSN_REGPARM void thumb44_1(uint32_t opcode) +{ + reg[opcode & 7].I += reg[((opcode >> 3) & 7) + 8].I; +} - // ADD Rd, Hs - static INSN_REGPARM void thumb44_1(uint32_t opcode) - { - reg[opcode & 7].I += reg[((opcode >> 3) & 7) + 8].I; - } +// ADD Hd, Rs +static INSN_REGPARM void thumb44_2(uint32_t opcode) +{ + reg[(opcode & 7) + 8].I += reg[(opcode >> 3) & 7].I; + if ((opcode & 7) == 7) { + reg[15].I &= 0xFFFFFFFE; + armNextPC = reg[15].I; + reg[15].I += 2; + THUMB_PREFETCH; + clockTicks = codeTicksAccessSeq16(armNextPC) * 2 + + codeTicksAccess16(armNextPC) + 3; + } +} - // ADD Hd, Rs - static INSN_REGPARM void thumb44_2(uint32_t opcode) - { - reg[(opcode & 7) + 8].I += reg[(opcode >> 3) & 7].I; - if ((opcode & 7) == 7) { - reg[15].I &= 0xFFFFFFFE; - armNextPC = reg[15].I; - reg[15].I += 2; - THUMB_PREFETCH; - clockTicks = codeTicksAccessSeq16(armNextPC) * 2 - + codeTicksAccess16(armNextPC) + 3; - } - } +// ADD Hd, Hs +static INSN_REGPARM void thumb44_3(uint32_t opcode) +{ + reg[(opcode & 7) + 8].I += reg[((opcode >> 3) & 7) + 8].I; + if ((opcode & 7) == 7) { + reg[15].I &= 0xFFFFFFFE; + armNextPC = reg[15].I; + reg[15].I += 2; + THUMB_PREFETCH; + clockTicks = codeTicksAccessSeq16(armNextPC) * 2 + + codeTicksAccess16(armNextPC) + 3; + } +} - // ADD Hd, Hs - static INSN_REGPARM void thumb44_3(uint32_t opcode) - { - reg[(opcode & 7) + 8].I += reg[((opcode >> 3) & 7) + 8].I; - if ((opcode & 7) == 7) { - reg[15].I &= 0xFFFFFFFE; - armNextPC = reg[15].I; - reg[15].I += 2; - THUMB_PREFETCH; - clockTicks = codeTicksAccessSeq16(armNextPC) * 2 - + codeTicksAccess16(armNextPC) + 3; - } - } +// CMP Rd, Hs +static INSN_REGPARM void thumb45_1(uint32_t opcode) +{ + int dest = opcode & 7; + uint32_t value = reg[((opcode >> 3) & 7) + 8].I; + CMP_RD_RS; +} - // CMP Rd, Hs - static INSN_REGPARM void thumb45_1(uint32_t opcode) - { - int dest = opcode & 7; - uint32_t value = reg[((opcode >> 3) & 7) + 8].I; - CMP_RD_RS; - } +// CMP Hd, Rs +static INSN_REGPARM void thumb45_2(uint32_t opcode) +{ + int dest = (opcode & 7) + 8; + uint32_t value = reg[(opcode >> 3) & 7].I; + CMP_RD_RS; +} - // CMP Hd, Rs - static INSN_REGPARM void thumb45_2(uint32_t opcode) - { - int dest = (opcode & 7) + 8; - uint32_t value = reg[(opcode >> 3) & 7].I; - CMP_RD_RS; - } +// CMP Hd, Hs +static INSN_REGPARM void thumb45_3(uint32_t opcode) +{ + int dest = (opcode & 7) + 8; + uint32_t value = reg[((opcode >> 3) & 7) + 8].I; + CMP_RD_RS; +} - // CMP Hd, Hs - static INSN_REGPARM void thumb45_3(uint32_t opcode) - { - int dest = (opcode & 7) + 8; - uint32_t value = reg[((opcode >> 3) & 7) + 8].I; - CMP_RD_RS; - } +// MOV Rd, Rs +static INSN_REGPARM void thumb46_0(uint32_t opcode) +{ + reg[opcode & 7].I = reg[((opcode >> 3) & 7)].I; + clockTicks = codeTicksAccessSeq16(armNextPC) + 1; +} - // MOV Rd, Rs - static INSN_REGPARM void thumb46_0(uint32_t opcode) - { - reg[opcode & 7].I = reg[((opcode >> 3) & 7)].I; - clockTicks = codeTicksAccessSeq16(armNextPC) + 1; - } +// MOV Rd, Hs +static INSN_REGPARM void thumb46_1(uint32_t opcode) +{ + reg[opcode & 7].I = reg[((opcode >> 3) & 7) + 8].I; + clockTicks = codeTicksAccessSeq16(armNextPC) + 1; +} - // MOV Rd, Hs - static INSN_REGPARM void thumb46_1(uint32_t opcode) - { - reg[opcode & 7].I = reg[((opcode >> 3) & 7) + 8].I; - clockTicks = codeTicksAccessSeq16(armNextPC) + 1; - } +// MOV Hd, Rs +static INSN_REGPARM void thumb46_2(uint32_t opcode) +{ + reg[(opcode & 7) + 8].I = reg[(opcode >> 3) & 7].I; + if ((opcode & 7) == 7) { + UPDATE_OLDREG; + reg[15].I &= 0xFFFFFFFE; + armNextPC = reg[15].I; + reg[15].I += 2; + THUMB_PREFETCH; + clockTicks = codeTicksAccessSeq16(armNextPC) * 2 + + codeTicksAccess16(armNextPC) + 3; + } +} - // MOV Hd, Rs - static INSN_REGPARM void thumb46_2(uint32_t opcode) - { - reg[(opcode & 7) + 8].I = reg[(opcode >> 3) & 7].I; - if ((opcode & 7) == 7) { - UPDATE_OLDREG; - reg[15].I &= 0xFFFFFFFE; - armNextPC = reg[15].I; - reg[15].I += 2; - THUMB_PREFETCH; - clockTicks = codeTicksAccessSeq16(armNextPC) * 2 - + codeTicksAccess16(armNextPC) + 3; - } - } +// MOV Hd, Hs +static INSN_REGPARM void thumb46_3(uint32_t opcode) +{ + reg[(opcode & 7) + 8].I = reg[((opcode >> 3) & 7) + 8].I; + if ((opcode & 7) == 7) { + UPDATE_OLDREG; + reg[15].I &= 0xFFFFFFFE; + armNextPC = reg[15].I; + reg[15].I += 2; + THUMB_PREFETCH; + clockTicks = codeTicksAccessSeq16(armNextPC) * 2 + + codeTicksAccess16(armNextPC) + 3; + } +} - // MOV Hd, Hs - static INSN_REGPARM void thumb46_3(uint32_t opcode) - { - reg[(opcode & 7) + 8].I = reg[((opcode >> 3) & 7) + 8].I; - if ((opcode & 7) == 7) { - UPDATE_OLDREG; - reg[15].I &= 0xFFFFFFFE; - armNextPC = reg[15].I; - reg[15].I += 2; - THUMB_PREFETCH; - clockTicks = codeTicksAccessSeq16(armNextPC) * 2 - + codeTicksAccess16(armNextPC) + 3; - } - } +// BX Rs +static INSN_REGPARM void thumb47(uint32_t opcode) +{ + int base = (opcode >> 3) & 15; + busPrefetchCount = 0; + UPDATE_OLDREG; + reg[15].I = reg[base].I; + if (reg[base].I & 1) { + armState = false; + reg[15].I &= 0xFFFFFFFE; + armNextPC = reg[15].I; + reg[15].I += 2; + THUMB_PREFETCH; + clockTicks = codeTicksAccessSeq16(armNextPC) * 2 + codeTicksAccess16(armNextPC) + 3; + } else { + armState = true; + reg[15].I &= 0xFFFFFFFC; + armNextPC = reg[15].I; + reg[15].I += 4; + ARM_PREFETCH; + clockTicks = codeTicksAccessSeq32(armNextPC) * 2 + codeTicksAccess32(armNextPC) + 3; + } +} - // BX Rs - static INSN_REGPARM void thumb47(uint32_t opcode) - { - int base = (opcode >> 3) & 15; - busPrefetchCount = 0; - UPDATE_OLDREG; - reg[15].I = reg[base].I; - if (reg[base].I & 1) { - armState = false; - reg[15].I &= 0xFFFFFFFE; - armNextPC = reg[15].I; - reg[15].I += 2; - THUMB_PREFETCH; - clockTicks = codeTicksAccessSeq16(armNextPC) * 2 + codeTicksAccess16(armNextPC) + 3; - } else { - armState = true; - reg[15].I &= 0xFFFFFFFC; - armNextPC = reg[15].I; - reg[15].I += 4; - ARM_PREFETCH; - clockTicks = codeTicksAccessSeq32(armNextPC) * 2 + codeTicksAccess32(armNextPC) + 3; - } - } +// Load/store instructions //////////////////////////////////////////////// - // Load/store instructions //////////////////////////////////////////////// +// LDR R0~R7,[PC, #Imm] +static INSN_REGPARM void thumb48(uint32_t opcode) +{ + uint8_t regist = (opcode >> 8) & 7; + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + uint32_t address = (reg[15].I & 0xFFFFFFFC) + ((opcode & 0xFF) << 2); + reg[regist].I = CPUReadMemoryQuick(address); + busPrefetchCount = 0; + clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC); +} - // LDR R0~R7,[PC, #Imm] - static INSN_REGPARM void thumb48(uint32_t opcode) - { - uint8_t regist = (opcode >> 8) & 7; - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - uint32_t address = (reg[15].I & 0xFFFFFFFC) + ((opcode & 0xFF) << 2); - reg[regist].I = CPUReadMemoryQuick(address); - busPrefetchCount = 0; - clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC); - } +// STR Rd, [Rs, Rn] +static INSN_REGPARM void thumb50(uint32_t opcode) +{ + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I; + CPUWriteMemory(address, reg[opcode & 7].I); + clockTicks = dataTicksAccess32(address) + codeTicksAccess16(armNextPC) + 2; +} - // STR Rd, [Rs, Rn] - static INSN_REGPARM void thumb50(uint32_t opcode) - { - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I; - CPUWriteMemory(address, reg[opcode & 7].I); - clockTicks = dataTicksAccess32(address) + codeTicksAccess16(armNextPC) + 2; - } +// STRH Rd, [Rs, Rn] +static INSN_REGPARM void thumb52(uint32_t opcode) +{ + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I; + CPUWriteHalfWord(address, reg[opcode & 7].W.W0); + clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2; +} - // STRH Rd, [Rs, Rn] - static INSN_REGPARM void thumb52(uint32_t opcode) - { - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I; - CPUWriteHalfWord(address, reg[opcode & 7].W.W0); - clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2; - } +// STRB Rd, [Rs, Rn] +static INSN_REGPARM void thumb54(uint32_t opcode) +{ + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I; + CPUWriteByte(address, reg[opcode & 7].B.B0); + clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2; +} - // STRB Rd, [Rs, Rn] - static INSN_REGPARM void thumb54(uint32_t opcode) - { - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I; - CPUWriteByte(address, reg[opcode & 7].B.B0); - clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2; - } +// LDSB Rd, [Rs, Rn] +static INSN_REGPARM void thumb56(uint32_t opcode) +{ + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I; + reg[opcode & 7].I = (int8_t)CPUReadByte(address); + clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC); +} - // LDSB Rd, [Rs, Rn] - static INSN_REGPARM void thumb56(uint32_t opcode) - { - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I; - reg[opcode & 7].I = (int8_t)CPUReadByte(address); - clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC); - } +// LDR Rd, [Rs, Rn] +static INSN_REGPARM void thumb58(uint32_t opcode) +{ + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I; + reg[opcode & 7].I = CPUReadMemory(address); + clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC); +} - // LDR Rd, [Rs, Rn] - static INSN_REGPARM void thumb58(uint32_t opcode) - { - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I; - reg[opcode & 7].I = CPUReadMemory(address); - clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC); - } +// LDRH Rd, [Rs, Rn] +static INSN_REGPARM void thumb5A(uint32_t opcode) +{ + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I; + reg[opcode & 7].I = CPUReadHalfWord(address); + clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC); +} - // LDRH Rd, [Rs, Rn] - static INSN_REGPARM void thumb5A(uint32_t opcode) - { - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I; - reg[opcode & 7].I = CPUReadHalfWord(address); - clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC); - } +// LDRB Rd, [Rs, Rn] +static INSN_REGPARM void thumb5C(uint32_t opcode) +{ + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I; + reg[opcode & 7].I = CPUReadByte(address); + clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC); +} - // LDRB Rd, [Rs, Rn] - static INSN_REGPARM void thumb5C(uint32_t opcode) - { - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I; - reg[opcode & 7].I = CPUReadByte(address); - clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC); - } +// LDSH Rd, [Rs, Rn] +static INSN_REGPARM void thumb5E(uint32_t opcode) +{ + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I; + reg[opcode & 7].I = (uint32_t)CPUReadHalfWordSigned(address); + clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC); +} - // LDSH Rd, [Rs, Rn] - static INSN_REGPARM void thumb5E(uint32_t opcode) - { - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - uint32_t address = reg[(opcode >> 3) & 7].I + reg[(opcode >> 6) & 7].I; - reg[opcode & 7].I = (uint32_t)CPUReadHalfWordSigned(address); - clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC); - } +// STR Rd, [Rs, #Imm] +static INSN_REGPARM void thumb60(uint32_t opcode) +{ + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + uint32_t address = reg[(opcode >> 3) & 7].I + (((opcode >> 6) & 31) << 2); + CPUWriteMemory(address, reg[opcode & 7].I); + clockTicks = dataTicksAccess32(address) + codeTicksAccess16(armNextPC) + 2; +} - // STR Rd, [Rs, #Imm] - static INSN_REGPARM void thumb60(uint32_t opcode) - { - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - uint32_t address = reg[(opcode >> 3) & 7].I + (((opcode >> 6) & 31) << 2); - CPUWriteMemory(address, reg[opcode & 7].I); - clockTicks = dataTicksAccess32(address) + codeTicksAccess16(armNextPC) + 2; - } +// LDR Rd, [Rs, #Imm] +static INSN_REGPARM void thumb68(uint32_t opcode) +{ + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + uint32_t address = reg[(opcode >> 3) & 7].I + (((opcode >> 6) & 31) << 2); + reg[opcode & 7].I = CPUReadMemory(address); + clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC); +} - // LDR Rd, [Rs, #Imm] - static INSN_REGPARM void thumb68(uint32_t opcode) - { - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - uint32_t address = reg[(opcode >> 3) & 7].I + (((opcode >> 6) & 31) << 2); - reg[opcode & 7].I = CPUReadMemory(address); - clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC); - } +// STRB Rd, [Rs, #Imm] +static INSN_REGPARM void thumb70(uint32_t opcode) +{ + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + uint32_t address = reg[(opcode >> 3) & 7].I + (((opcode >> 6) & 31)); + CPUWriteByte(address, reg[opcode & 7].B.B0); + clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2; +} - // STRB Rd, [Rs, #Imm] - static INSN_REGPARM void thumb70(uint32_t opcode) - { - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - uint32_t address = reg[(opcode >> 3) & 7].I + (((opcode >> 6) & 31)); - CPUWriteByte(address, reg[opcode & 7].B.B0); - clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2; - } +// LDRB Rd, [Rs, #Imm] +static INSN_REGPARM void thumb78(uint32_t opcode) +{ + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + uint32_t address = reg[(opcode >> 3) & 7].I + (((opcode >> 6) & 31)); + reg[opcode & 7].I = CPUReadByte(address); + clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC); +} - // LDRB Rd, [Rs, #Imm] - static INSN_REGPARM void thumb78(uint32_t opcode) - { - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - uint32_t address = reg[(opcode >> 3) & 7].I + (((opcode >> 6) & 31)); - reg[opcode & 7].I = CPUReadByte(address); - clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC); - } +// STRH Rd, [Rs, #Imm] +static INSN_REGPARM void thumb80(uint32_t opcode) +{ + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + uint32_t address = reg[(opcode >> 3) & 7].I + (((opcode >> 6) & 31) << 1); + CPUWriteHalfWord(address, reg[opcode & 7].W.W0); + clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2; +} - // STRH Rd, [Rs, #Imm] - static INSN_REGPARM void thumb80(uint32_t opcode) - { - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - uint32_t address = reg[(opcode >> 3) & 7].I + (((opcode >> 6) & 31) << 1); - CPUWriteHalfWord(address, reg[opcode & 7].W.W0); - clockTicks = dataTicksAccess16(address) + codeTicksAccess16(armNextPC) + 2; - } +// LDRH Rd, [Rs, #Imm] +static INSN_REGPARM void thumb88(uint32_t opcode) +{ + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + uint32_t address = reg[(opcode >> 3) & 7].I + (((opcode >> 6) & 31) << 1); + reg[opcode & 7].I = CPUReadHalfWord(address); + clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC); +} - // LDRH Rd, [Rs, #Imm] - static INSN_REGPARM void thumb88(uint32_t opcode) - { - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - uint32_t address = reg[(opcode >> 3) & 7].I + (((opcode >> 6) & 31) << 1); - reg[opcode & 7].I = CPUReadHalfWord(address); - clockTicks = 3 + dataTicksAccess16(address) + codeTicksAccess16(armNextPC); - } +// STR R0~R7, [SP, #Imm] +static INSN_REGPARM void thumb90(uint32_t opcode) +{ + uint8_t regist = (opcode >> 8) & 7; + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + uint32_t address = reg[13].I + ((opcode & 255) << 2); + CPUWriteMemory(address, reg[regist].I); + clockTicks = dataTicksAccess32(address) + codeTicksAccess16(armNextPC) + 2; +} - // STR R0~R7, [SP, #Imm] - static INSN_REGPARM void thumb90(uint32_t opcode) - { - uint8_t regist = (opcode >> 8) & 7; - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - uint32_t address = reg[13].I + ((opcode & 255) << 2); - CPUWriteMemory(address, reg[regist].I); - clockTicks = dataTicksAccess32(address) + codeTicksAccess16(armNextPC) + 2; - } +// LDR R0~R7, [SP, #Imm] +static INSN_REGPARM void thumb98(uint32_t opcode) +{ + uint8_t regist = (opcode >> 8) & 7; + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + uint32_t address = reg[13].I + ((opcode & 255) << 2); + reg[regist].I = CPUReadMemoryQuick(address); + clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC); +} - // LDR R0~R7, [SP, #Imm] - static INSN_REGPARM void thumb98(uint32_t opcode) - { - uint8_t regist = (opcode >> 8) & 7; - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - uint32_t address = reg[13].I + ((opcode & 255) << 2); - reg[regist].I = CPUReadMemoryQuick(address); - clockTicks = 3 + dataTicksAccess32(address) + codeTicksAccess16(armNextPC); - } +// PC/stack-related /////////////////////////////////////////////////////// - // PC/stack-related /////////////////////////////////////////////////////// +// ADD R0~R7, PC, Imm +static INSN_REGPARM void thumbA0(uint32_t opcode) +{ + uint8_t regist = (opcode >> 8) & 7; + reg[regist].I = (reg[15].I & 0xFFFFFFFC) + ((opcode & 255) << 2); + clockTicks = 1 + codeTicksAccess16(armNextPC); +} - // ADD R0~R7, PC, Imm - static INSN_REGPARM void thumbA0(uint32_t opcode) - { - uint8_t regist = (opcode >> 8) & 7; - reg[regist].I = (reg[15].I & 0xFFFFFFFC) + ((opcode & 255) << 2); - clockTicks = 1 + codeTicksAccess16(armNextPC); - } +// ADD R0~R7, SP, Imm +static INSN_REGPARM void thumbA8(uint32_t opcode) +{ + uint8_t regist = (opcode >> 8) & 7; + reg[regist].I = reg[13].I + ((opcode & 255) << 2); + clockTicks = 1 + codeTicksAccess16(armNextPC); +} - // ADD R0~R7, SP, Imm - static INSN_REGPARM void thumbA8(uint32_t opcode) - { - uint8_t regist = (opcode >> 8) & 7; - reg[regist].I = reg[13].I + ((opcode & 255) << 2); - clockTicks = 1 + codeTicksAccess16(armNextPC); - } +// ADD SP, Imm +static INSN_REGPARM void thumbB0(uint32_t opcode) +{ + int offset = (opcode & 127) << 2; + if (opcode & 0x80) + offset = -offset; + reg[13].I += offset; + clockTicks = 1 + codeTicksAccess16(armNextPC); +} - // ADD SP, Imm - static INSN_REGPARM void thumbB0(uint32_t opcode) - { - int offset = (opcode & 127) << 2; - if (opcode & 0x80) - offset = -offset; - reg[13].I += offset; - clockTicks = 1 + codeTicksAccess16(armNextPC); - } - - // Push and pop /////////////////////////////////////////////////////////// +// Push and pop /////////////////////////////////////////////////////////// #define PUSH_REG(val, r) \ if (opcode & (val)) { \ @@ -1541,99 +1540,99 @@ static INSN_REGPARM void thumbBreakpoint(uint32_t opcode) address += 4; \ } - // PUSH {Rlist} - static INSN_REGPARM void thumbB4(uint32_t opcode) - { - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - int count = 0; - uint32_t temp = reg[13].I - 4 * cpuBitsSet[opcode & 0xff]; - uint32_t address = temp & 0xFFFFFFFC; - PUSH_REG(1, 0); - PUSH_REG(2, 1); - PUSH_REG(4, 2); - PUSH_REG(8, 3); - PUSH_REG(16, 4); - PUSH_REG(32, 5); - PUSH_REG(64, 6); - PUSH_REG(128, 7); - clockTicks += 1 + codeTicksAccess16(armNextPC); - reg[13].I = temp; - } +// PUSH {Rlist} +static INSN_REGPARM void thumbB4(uint32_t opcode) +{ + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + int count = 0; + uint32_t temp = reg[13].I - 4 * cpuBitsSet[opcode & 0xff]; + uint32_t address = temp & 0xFFFFFFFC; + PUSH_REG(1, 0); + PUSH_REG(2, 1); + PUSH_REG(4, 2); + PUSH_REG(8, 3); + PUSH_REG(16, 4); + PUSH_REG(32, 5); + PUSH_REG(64, 6); + PUSH_REG(128, 7); + clockTicks += 1 + codeTicksAccess16(armNextPC); + reg[13].I = temp; +} - // PUSH {Rlist, LR} - static INSN_REGPARM void thumbB5(uint32_t opcode) - { - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - int count = 0; - uint32_t temp = reg[13].I - 4 - 4 * cpuBitsSet[opcode & 0xff]; - uint32_t address = temp & 0xFFFFFFFC; - PUSH_REG(1, 0); - PUSH_REG(2, 1); - PUSH_REG(4, 2); - PUSH_REG(8, 3); - PUSH_REG(16, 4); - PUSH_REG(32, 5); - PUSH_REG(64, 6); - PUSH_REG(128, 7); - PUSH_REG(256, 14); - clockTicks += 1 + codeTicksAccess16(armNextPC); - reg[13].I = temp; - } +// PUSH {Rlist, LR} +static INSN_REGPARM void thumbB5(uint32_t opcode) +{ + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + int count = 0; + uint32_t temp = reg[13].I - 4 - 4 * cpuBitsSet[opcode & 0xff]; + uint32_t address = temp & 0xFFFFFFFC; + PUSH_REG(1, 0); + PUSH_REG(2, 1); + PUSH_REG(4, 2); + PUSH_REG(8, 3); + PUSH_REG(16, 4); + PUSH_REG(32, 5); + PUSH_REG(64, 6); + PUSH_REG(128, 7); + PUSH_REG(256, 14); + clockTicks += 1 + codeTicksAccess16(armNextPC); + reg[13].I = temp; +} - // POP {Rlist} - static INSN_REGPARM void thumbBC(uint32_t opcode) - { - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - int count = 0; - uint32_t address = reg[13].I & 0xFFFFFFFC; - uint32_t temp = reg[13].I + 4 * cpuBitsSet[opcode & 0xFF]; - POP_REG(1, 0); - POP_REG(2, 1); - POP_REG(4, 2); - POP_REG(8, 3); - POP_REG(16, 4); - POP_REG(32, 5); - POP_REG(64, 6); - POP_REG(128, 7); - reg[13].I = temp; - clockTicks = 2 + codeTicksAccess16(armNextPC); - } +// POP {Rlist} +static INSN_REGPARM void thumbBC(uint32_t opcode) +{ + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + int count = 0; + uint32_t address = reg[13].I & 0xFFFFFFFC; + uint32_t temp = reg[13].I + 4 * cpuBitsSet[opcode & 0xFF]; + POP_REG(1, 0); + POP_REG(2, 1); + POP_REG(4, 2); + POP_REG(8, 3); + POP_REG(16, 4); + POP_REG(32, 5); + POP_REG(64, 6); + POP_REG(128, 7); + reg[13].I = temp; + clockTicks = 2 + codeTicksAccess16(armNextPC); +} - // POP {Rlist, PC} - static INSN_REGPARM void thumbBD(uint32_t opcode) - { - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - int count = 0; - uint32_t address = reg[13].I & 0xFFFFFFFC; - uint32_t temp = reg[13].I + 4 + 4 * cpuBitsSet[opcode & 0xFF]; - POP_REG(1, 0); - POP_REG(2, 1); - POP_REG(4, 2); - POP_REG(8, 3); - POP_REG(16, 4); - POP_REG(32, 5); - POP_REG(64, 6); - POP_REG(128, 7); - reg[15].I = (CPUReadMemory(address) & 0xFFFFFFFE); - if (!count) { - clockTicks += 1 + dataTicksAccess32(address); - } else { - clockTicks += 1 + dataTicksAccessSeq32(address); - } - count++; - armNextPC = reg[15].I; - reg[15].I += 2; - reg[13].I = temp; - THUMB_PREFETCH; - busPrefetchCount = 0; - clockTicks += 3 + codeTicksAccess16(armNextPC) + codeTicksAccess16(armNextPC); - } +// POP {Rlist, PC} +static INSN_REGPARM void thumbBD(uint32_t opcode) +{ + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + int count = 0; + uint32_t address = reg[13].I & 0xFFFFFFFC; + uint32_t temp = reg[13].I + 4 + 4 * cpuBitsSet[opcode & 0xFF]; + POP_REG(1, 0); + POP_REG(2, 1); + POP_REG(4, 2); + POP_REG(8, 3); + POP_REG(16, 4); + POP_REG(32, 5); + POP_REG(64, 6); + POP_REG(128, 7); + reg[15].I = (CPUReadMemory(address) & 0xFFFFFFFE); + if (!count) { + clockTicks += 1 + dataTicksAccess32(address); + } else { + clockTicks += 1 + dataTicksAccessSeq32(address); + } + count++; + armNextPC = reg[15].I; + reg[15].I += 2; + reg[13].I = temp; + THUMB_PREFETCH; + busPrefetchCount = 0; + clockTicks += 3 + codeTicksAccess16(armNextPC) + codeTicksAccess16(armNextPC); +} - // Load/store multiple //////////////////////////////////////////////////// +// Load/store multiple //////////////////////////////////////////////////// #define THUMB_STM_REG(val, r, b) \ if (opcode & (val)) { \ @@ -1660,545 +1659,547 @@ static INSN_REGPARM void thumbBreakpoint(uint32_t opcode) address += 4; \ } - // STM R0~7!, {Rlist} - static INSN_REGPARM void thumbC0(uint32_t opcode) - { - uint8_t regist = (opcode >> 8) & 7; - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - uint32_t address = reg[regist].I & 0xFFFFFFFC; - uint32_t temp = reg[regist].I + 4 * cpuBitsSet[opcode & 0xff]; - int count = 0; - // store - THUMB_STM_REG(1, 0, regist); - THUMB_STM_REG(2, 1, regist); - THUMB_STM_REG(4, 2, regist); - THUMB_STM_REG(8, 3, regist); - THUMB_STM_REG(16, 4, regist); - THUMB_STM_REG(32, 5, regist); - THUMB_STM_REG(64, 6, regist); - THUMB_STM_REG(128, 7, regist); - clockTicks = 1 + codeTicksAccess16(armNextPC); - } +// STM R0~7!, {Rlist} +static INSN_REGPARM void thumbC0(uint32_t opcode) +{ + uint8_t regist = (opcode >> 8) & 7; + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + uint32_t address = reg[regist].I & 0xFFFFFFFC; + uint32_t temp = reg[regist].I + 4 * cpuBitsSet[opcode & 0xff]; + int count = 0; + // store + THUMB_STM_REG(1, 0, regist); + THUMB_STM_REG(2, 1, regist); + THUMB_STM_REG(4, 2, regist); + THUMB_STM_REG(8, 3, regist); + THUMB_STM_REG(16, 4, regist); + THUMB_STM_REG(32, 5, regist); + THUMB_STM_REG(64, 6, regist); + THUMB_STM_REG(128, 7, regist); + clockTicks = 1 + codeTicksAccess16(armNextPC); +} - // LDM R0~R7!, {Rlist} - static INSN_REGPARM void thumbC8(uint32_t opcode) - { - uint8_t regist = (opcode >> 8) & 7; - if (busPrefetchCount == 0) - busPrefetch = busPrefetchEnable; - uint32_t address = reg[regist].I & 0xFFFFFFFC; - uint32_t temp = reg[regist].I + 4 * cpuBitsSet[opcode & 0xFF]; - int count = 0; - // load - THUMB_LDM_REG(1, 0); - THUMB_LDM_REG(2, 1); - THUMB_LDM_REG(4, 2); - THUMB_LDM_REG(8, 3); - THUMB_LDM_REG(16, 4); - THUMB_LDM_REG(32, 5); - THUMB_LDM_REG(64, 6); - THUMB_LDM_REG(128, 7); - clockTicks = 2 + codeTicksAccess16(armNextPC); - if (!(opcode & (1 << regist))) - reg[regist].I = temp; - } +// LDM R0~R7!, {Rlist} +static INSN_REGPARM void thumbC8(uint32_t opcode) +{ + uint8_t regist = (opcode >> 8) & 7; + if (busPrefetchCount == 0) + busPrefetch = busPrefetchEnable; + uint32_t address = reg[regist].I & 0xFFFFFFFC; + uint32_t temp = reg[regist].I + 4 * cpuBitsSet[opcode & 0xFF]; + int count = 0; + // load + THUMB_LDM_REG(1, 0); + THUMB_LDM_REG(2, 1); + THUMB_LDM_REG(4, 2); + THUMB_LDM_REG(8, 3); + THUMB_LDM_REG(16, 4); + THUMB_LDM_REG(32, 5); + THUMB_LDM_REG(64, 6); + THUMB_LDM_REG(128, 7); + clockTicks = 2 + codeTicksAccess16(armNextPC); + if (!(opcode & (1 << regist))) + reg[regist].I = temp; +} - // Conditional branches /////////////////////////////////////////////////// +// Conditional branches /////////////////////////////////////////////////// - // BEQ offset - static INSN_REGPARM void thumbD0(uint32_t opcode) - { - UPDATE_OLDREG; - clockTicks = codeTicksAccessSeq16(armNextPC) + 1; - if (Z_FLAG) { - reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; - armNextPC = reg[15].I; - reg[15].I += 2; - THUMB_PREFETCH; - clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; - busPrefetchCount = 0; - } - } +// BEQ offset +static INSN_REGPARM void thumbD0(uint32_t opcode) +{ + UPDATE_OLDREG; + clockTicks = codeTicksAccessSeq16(armNextPC) + 1; + if (Z_FLAG) { + reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; + armNextPC = reg[15].I; + reg[15].I += 2; + THUMB_PREFETCH; + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; + busPrefetchCount = 0; + } +} - // BNE offset - static INSN_REGPARM void thumbD1(uint32_t opcode) - { - UPDATE_OLDREG; - clockTicks = codeTicksAccessSeq16(armNextPC) + 1; - if (!Z_FLAG) { - reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; - armNextPC = reg[15].I; - reg[15].I += 2; - THUMB_PREFETCH; - clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; - busPrefetchCount = 0; - } - } +// BNE offset +static INSN_REGPARM void thumbD1(uint32_t opcode) +{ + UPDATE_OLDREG; + clockTicks = codeTicksAccessSeq16(armNextPC) + 1; + if (!Z_FLAG) { + reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; + armNextPC = reg[15].I; + reg[15].I += 2; + THUMB_PREFETCH; + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; + busPrefetchCount = 0; + } +} - // BCS offset - static INSN_REGPARM void thumbD2(uint32_t opcode) - { - UPDATE_OLDREG; - clockTicks = codeTicksAccessSeq16(armNextPC) + 1; - if (C_FLAG) { - reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; - armNextPC = reg[15].I; - reg[15].I += 2; - THUMB_PREFETCH; - clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; - busPrefetchCount = 0; - } - } +// BCS offset +static INSN_REGPARM void thumbD2(uint32_t opcode) +{ + UPDATE_OLDREG; + clockTicks = codeTicksAccessSeq16(armNextPC) + 1; + if (C_FLAG) { + reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; + armNextPC = reg[15].I; + reg[15].I += 2; + THUMB_PREFETCH; + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; + busPrefetchCount = 0; + } +} - // BCC offset - static INSN_REGPARM void thumbD3(uint32_t opcode) - { - UPDATE_OLDREG; - clockTicks = codeTicksAccessSeq16(armNextPC) + 1; - if (!C_FLAG) { - reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; - armNextPC = reg[15].I; - reg[15].I += 2; - THUMB_PREFETCH; - clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; - busPrefetchCount = 0; - } - } +// BCC offset +static INSN_REGPARM void thumbD3(uint32_t opcode) +{ + UPDATE_OLDREG; + clockTicks = codeTicksAccessSeq16(armNextPC) + 1; + if (!C_FLAG) { + reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; + armNextPC = reg[15].I; + reg[15].I += 2; + THUMB_PREFETCH; + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; + busPrefetchCount = 0; + } +} - // BMI offset - static INSN_REGPARM void thumbD4(uint32_t opcode) - { - UPDATE_OLDREG; - clockTicks = codeTicksAccessSeq16(armNextPC) + 1; - if (N_FLAG) { - reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; - armNextPC = reg[15].I; - reg[15].I += 2; - THUMB_PREFETCH; - clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; - busPrefetchCount = 0; - } - } +// BMI offset +static INSN_REGPARM void thumbD4(uint32_t opcode) +{ + UPDATE_OLDREG; + clockTicks = codeTicksAccessSeq16(armNextPC) + 1; + if (N_FLAG) { + reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; + armNextPC = reg[15].I; + reg[15].I += 2; + THUMB_PREFETCH; + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; + busPrefetchCount = 0; + } +} - // BPL offset - static INSN_REGPARM void thumbD5(uint32_t opcode) - { - UPDATE_OLDREG; - clockTicks = codeTicksAccessSeq16(armNextPC) + 1; - if (!N_FLAG) { - reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; - armNextPC = reg[15].I; - reg[15].I += 2; - THUMB_PREFETCH; - clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; - busPrefetchCount = 0; - } - } +// BPL offset +static INSN_REGPARM void thumbD5(uint32_t opcode) +{ + UPDATE_OLDREG; + clockTicks = codeTicksAccessSeq16(armNextPC) + 1; + if (!N_FLAG) { + reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; + armNextPC = reg[15].I; + reg[15].I += 2; + THUMB_PREFETCH; + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; + busPrefetchCount = 0; + } +} - // BVS offset - static INSN_REGPARM void thumbD6(uint32_t opcode) - { - UPDATE_OLDREG; - clockTicks = codeTicksAccessSeq16(armNextPC) + 1; - if (V_FLAG) { - reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; - armNextPC = reg[15].I; - reg[15].I += 2; - THUMB_PREFETCH; - clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; - busPrefetchCount = 0; - } - } +// BVS offset +static INSN_REGPARM void thumbD6(uint32_t opcode) +{ + UPDATE_OLDREG; + clockTicks = codeTicksAccessSeq16(armNextPC) + 1; + if (V_FLAG) { + reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; + armNextPC = reg[15].I; + reg[15].I += 2; + THUMB_PREFETCH; + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; + busPrefetchCount = 0; + } +} - // BVC offset - static INSN_REGPARM void thumbD7(uint32_t opcode) - { - UPDATE_OLDREG; - clockTicks = codeTicksAccessSeq16(armNextPC) + 1; - if (!V_FLAG) { - reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; - armNextPC = reg[15].I; - reg[15].I += 2; - THUMB_PREFETCH; - clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; - busPrefetchCount = 0; - } - } +// BVC offset +static INSN_REGPARM void thumbD7(uint32_t opcode) +{ + UPDATE_OLDREG; + clockTicks = codeTicksAccessSeq16(armNextPC) + 1; + if (!V_FLAG) { + reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; + armNextPC = reg[15].I; + reg[15].I += 2; + THUMB_PREFETCH; + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; + busPrefetchCount = 0; + } +} - // BHI offset - static INSN_REGPARM void thumbD8(uint32_t opcode) - { - UPDATE_OLDREG; - clockTicks = codeTicksAccessSeq16(armNextPC) + 1; - if (C_FLAG && !Z_FLAG) { - reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; - armNextPC = reg[15].I; - reg[15].I += 2; - THUMB_PREFETCH; - clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; - busPrefetchCount = 0; - } - } +// BHI offset +static INSN_REGPARM void thumbD8(uint32_t opcode) +{ + UPDATE_OLDREG; + clockTicks = codeTicksAccessSeq16(armNextPC) + 1; + if (C_FLAG && !Z_FLAG) { + reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; + armNextPC = reg[15].I; + reg[15].I += 2; + THUMB_PREFETCH; + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; + busPrefetchCount = 0; + } +} - // BLS offset - static INSN_REGPARM void thumbD9(uint32_t opcode) - { - UPDATE_OLDREG; - clockTicks = codeTicksAccessSeq16(armNextPC) + 1; - if (!C_FLAG || Z_FLAG) { - reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; - armNextPC = reg[15].I; - reg[15].I += 2; - THUMB_PREFETCH; - clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; - busPrefetchCount = 0; - } - } +// BLS offset +static INSN_REGPARM void thumbD9(uint32_t opcode) +{ + UPDATE_OLDREG; + clockTicks = codeTicksAccessSeq16(armNextPC) + 1; + if (!C_FLAG || Z_FLAG) { + reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; + armNextPC = reg[15].I; + reg[15].I += 2; + THUMB_PREFETCH; + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; + busPrefetchCount = 0; + } +} - // BGE offset - static INSN_REGPARM void thumbDA(uint32_t opcode) - { - UPDATE_OLDREG; - clockTicks = codeTicksAccessSeq16(armNextPC) + 1; - if (N_FLAG == V_FLAG) { - reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; - armNextPC = reg[15].I; - reg[15].I += 2; - THUMB_PREFETCH; - clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; - busPrefetchCount = 0; - } - } +// BGE offset +static INSN_REGPARM void thumbDA(uint32_t opcode) +{ + UPDATE_OLDREG; + clockTicks = codeTicksAccessSeq16(armNextPC) + 1; + if (N_FLAG == V_FLAG) { + reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; + armNextPC = reg[15].I; + reg[15].I += 2; + THUMB_PREFETCH; + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; + busPrefetchCount = 0; + } +} - // BLT offset - static INSN_REGPARM void thumbDB(uint32_t opcode) - { - UPDATE_OLDREG; - clockTicks = codeTicksAccessSeq16(armNextPC) + 1; - if (N_FLAG != V_FLAG) { - reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; - armNextPC = reg[15].I; - reg[15].I += 2; - THUMB_PREFETCH; - clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; - busPrefetchCount = 0; - } - } +// BLT offset +static INSN_REGPARM void thumbDB(uint32_t opcode) +{ + UPDATE_OLDREG; + clockTicks = codeTicksAccessSeq16(armNextPC) + 1; + if (N_FLAG != V_FLAG) { + reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; + armNextPC = reg[15].I; + reg[15].I += 2; + THUMB_PREFETCH; + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; + busPrefetchCount = 0; + } +} - // BGT offset - static INSN_REGPARM void thumbDC(uint32_t opcode) - { - UPDATE_OLDREG; - clockTicks = codeTicksAccessSeq16(armNextPC) + 1; - if (!Z_FLAG && (N_FLAG == V_FLAG)) { - reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; - armNextPC = reg[15].I; - reg[15].I += 2; - THUMB_PREFETCH; - clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; - busPrefetchCount = 0; - } - } +// BGT offset +static INSN_REGPARM void thumbDC(uint32_t opcode) +{ + UPDATE_OLDREG; + clockTicks = codeTicksAccessSeq16(armNextPC) + 1; + if (!Z_FLAG && (N_FLAG == V_FLAG)) { + reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; + armNextPC = reg[15].I; + reg[15].I += 2; + THUMB_PREFETCH; + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; + busPrefetchCount = 0; + } +} - // BLE offset - static INSN_REGPARM void thumbDD(uint32_t opcode) - { - UPDATE_OLDREG; - clockTicks = codeTicksAccessSeq16(armNextPC); - if (Z_FLAG || (N_FLAG != V_FLAG)) { - reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; - armNextPC = reg[15].I; - reg[15].I += 2; - THUMB_PREFETCH; - clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; - busPrefetchCount = 0; - } - } +// BLE offset +static INSN_REGPARM void thumbDD(uint32_t opcode) +{ + UPDATE_OLDREG; + clockTicks = codeTicksAccessSeq16(armNextPC); + if (Z_FLAG || (N_FLAG != V_FLAG)) { + reg[15].I += ((int8_t)(opcode & 0xFF)) << 1; + armNextPC = reg[15].I; + reg[15].I += 2; + THUMB_PREFETCH; + clockTicks += codeTicksAccessSeq16(armNextPC) + codeTicksAccess16(armNextPC) + 2; + busPrefetchCount = 0; + } +} - // SWI, B, BL ///////////////////////////////////////////////////////////// +// SWI, B, BL ///////////////////////////////////////////////////////////// - // SWI #comment - static INSN_REGPARM void thumbDF(uint32_t opcode) - { - //uint32_t address = 0; - //clockTicks = codeTicksAccessSeq16(address)*2 + codeTicksAccess16(address)+3; - clockTicks = 3; - busPrefetchCount = 0; - CPUSoftwareInterrupt(opcode & 0xFF); - } +// SWI #comment +static INSN_REGPARM void thumbDF(uint32_t opcode) +{ + //uint32_t address = 0; + //clockTicks = codeTicksAccessSeq16(address)*2 + codeTicksAccess16(address)+3; + clockTicks = 3; + busPrefetchCount = 0; + CPUSoftwareInterrupt(opcode & 0xFF); +} - // B offset - static INSN_REGPARM void thumbE0(uint32_t opcode) - { - int offset = (opcode & 0x3FF) << 1; - if (opcode & 0x0400) - offset |= 0xFFFFF800; - reg[15].I += offset; - armNextPC = reg[15].I; - reg[15].I += 2; - THUMB_PREFETCH; - clockTicks = codeTicksAccessSeq16(armNextPC) * 2 + codeTicksAccess16(armNextPC) + 3; - busPrefetchCount = 0; - } +// B offset +static INSN_REGPARM void thumbE0(uint32_t opcode) +{ + int offset = (opcode & 0x3FF) << 1; + if (opcode & 0x0400) + offset |= 0xFFFFF800; + reg[15].I += offset; + armNextPC = reg[15].I; + reg[15].I += 2; + THUMB_PREFETCH; + clockTicks = codeTicksAccessSeq16(armNextPC) * 2 + codeTicksAccess16(armNextPC) + 3; + busPrefetchCount = 0; +} - // BLL #offset (forward) - static INSN_REGPARM void thumbF0(uint32_t opcode) - { - int offset = (opcode & 0x7FF); - reg[14].I = reg[15].I + (offset << 12); - clockTicks = codeTicksAccessSeq16(armNextPC) + 1; - } +// BLL #offset (forward) +static INSN_REGPARM void thumbF0(uint32_t opcode) +{ + int offset = (opcode & 0x7FF); + reg[14].I = reg[15].I + (offset << 12); + clockTicks = codeTicksAccessSeq16(armNextPC) + 1; +} - // BLL #offset (backward) - static INSN_REGPARM void thumbF4(uint32_t opcode) - { - int offset = (opcode & 0x7FF); - reg[14].I = reg[15].I + ((offset << 12) | 0xFF800000); - clockTicks = codeTicksAccessSeq16(armNextPC) + 1; - } +// BLL #offset (backward) +static INSN_REGPARM void thumbF4(uint32_t opcode) +{ + int offset = (opcode & 0x7FF); + reg[14].I = reg[15].I + ((offset << 12) | 0xFF800000); + clockTicks = codeTicksAccessSeq16(armNextPC) + 1; +} - // BLH #offset - static INSN_REGPARM void thumbF8(uint32_t opcode) - { - int offset = (opcode & 0x7FF); - uint32_t temp = reg[15].I - 2; - reg[15].I = (reg[14].I + (offset << 1)) & 0xFFFFFFFE; - armNextPC = reg[15].I; - reg[15].I += 2; - reg[14].I = temp | 1; - THUMB_PREFETCH; - clockTicks = codeTicksAccessSeq16(armNextPC) * 2 + codeTicksAccess16(armNextPC) + 3; - busPrefetchCount = 0; - } +// BLH #offset +static INSN_REGPARM void thumbF8(uint32_t opcode) +{ + int offset = (opcode & 0x7FF); + uint32_t temp = reg[15].I - 2; + reg[15].I = (reg[14].I + (offset << 1)) & 0xFFFFFFFE; + armNextPC = reg[15].I; + reg[15].I += 2; + reg[14].I = temp | 1; + THUMB_PREFETCH; + clockTicks = codeTicksAccessSeq16(armNextPC) * 2 + codeTicksAccess16(armNextPC) + 3; + busPrefetchCount = 0; +} - // Instruction table ////////////////////////////////////////////////////// +// Instruction table ////////////////////////////////////////////////////// - typedef INSN_REGPARM void (*insnfunc_t)(uint32_t opcode); +typedef INSN_REGPARM void (*insnfunc_t)(uint32_t opcode); #define thumbUI thumbUnknownInsn #ifdef BKPT_SUPPORT #define thumbBP thumbBreakpoint #else #define thumbBP thumbUnknownInsn #endif - static insnfunc_t thumbInsnTable[1024] = { - thumb00_00, thumb00_01, thumb00_02, thumb00_03, thumb00_04, thumb00_05, thumb00_06, thumb00_07, // 00 - thumb00_08, thumb00_09, thumb00_0A, thumb00_0B, thumb00_0C, thumb00_0D, thumb00_0E, thumb00_0F, - thumb00_10, thumb00_11, thumb00_12, thumb00_13, thumb00_14, thumb00_15, thumb00_16, thumb00_17, - thumb00_18, thumb00_19, thumb00_1A, thumb00_1B, thumb00_1C, thumb00_1D, thumb00_1E, thumb00_1F, - thumb08_00, thumb08_01, thumb08_02, thumb08_03, thumb08_04, thumb08_05, thumb08_06, thumb08_07, // 08 - thumb08_08, thumb08_09, thumb08_0A, thumb08_0B, thumb08_0C, thumb08_0D, thumb08_0E, thumb08_0F, - thumb08_10, thumb08_11, thumb08_12, thumb08_13, thumb08_14, thumb08_15, thumb08_16, thumb08_17, - thumb08_18, thumb08_19, thumb08_1A, thumb08_1B, thumb08_1C, thumb08_1D, thumb08_1E, thumb08_1F, - thumb10_00, thumb10_01, thumb10_02, thumb10_03, thumb10_04, thumb10_05, thumb10_06, thumb10_07, // 10 - thumb10_08, thumb10_09, thumb10_0A, thumb10_0B, thumb10_0C, thumb10_0D, thumb10_0E, thumb10_0F, - thumb10_10, thumb10_11, thumb10_12, thumb10_13, thumb10_14, thumb10_15, thumb10_16, thumb10_17, - thumb10_18, thumb10_19, thumb10_1A, thumb10_1B, thumb10_1C, thumb10_1D, thumb10_1E, thumb10_1F, - thumb18_0, thumb18_1, thumb18_2, thumb18_3, thumb18_4, thumb18_5, thumb18_6, thumb18_7, // 18 - thumb1A_0, thumb1A_1, thumb1A_2, thumb1A_3, thumb1A_4, thumb1A_5, thumb1A_6, thumb1A_7, - thumb1C_0, thumb1C_1, thumb1C_2, thumb1C_3, thumb1C_4, thumb1C_5, thumb1C_6, thumb1C_7, - thumb1E_0, thumb1E_1, thumb1E_2, thumb1E_3, thumb1E_4, thumb1E_5, thumb1E_6, thumb1E_7, - thumb20, thumb20, thumb20, thumb20, thumb21, thumb21, thumb21, thumb21, // 20 - thumb22, thumb22, thumb22, thumb22, thumb23, thumb23, thumb23, thumb23, - thumb24, thumb24, thumb24, thumb24, thumb25, thumb25, thumb25, thumb25, - thumb26, thumb26, thumb26, thumb26, thumb27, thumb27, thumb27, thumb27, - thumb28, thumb28, thumb28, thumb28, thumb29, thumb29, thumb29, thumb29, // 28 - thumb2A, thumb2A, thumb2A, thumb2A, thumb2B, thumb2B, thumb2B, thumb2B, - thumb2C, thumb2C, thumb2C, thumb2C, thumb2D, thumb2D, thumb2D, thumb2D, - thumb2E, thumb2E, thumb2E, thumb2E, thumb2F, thumb2F, thumb2F, thumb2F, - thumb30, thumb30, thumb30, thumb30, thumb31, thumb31, thumb31, thumb31, // 30 - thumb32, thumb32, thumb32, thumb32, thumb33, thumb33, thumb33, thumb33, - thumb34, thumb34, thumb34, thumb34, thumb35, thumb35, thumb35, thumb35, - thumb36, thumb36, thumb36, thumb36, thumb37, thumb37, thumb37, thumb37, - thumb38, thumb38, thumb38, thumb38, thumb39, thumb39, thumb39, thumb39, // 38 - thumb3A, thumb3A, thumb3A, thumb3A, thumb3B, thumb3B, thumb3B, thumb3B, - thumb3C, thumb3C, thumb3C, thumb3C, thumb3D, thumb3D, thumb3D, thumb3D, - thumb3E, thumb3E, thumb3E, thumb3E, thumb3F, thumb3F, thumb3F, thumb3F, - thumb40_0, thumb40_1, thumb40_2, thumb40_3, thumb41_0, thumb41_1, thumb41_2, thumb41_3, // 40 - thumb42_0, thumb42_1, thumb42_2, thumb42_3, thumb43_0, thumb43_1, thumb43_2, thumb43_3, - thumbUI, thumb44_1, thumb44_2, thumb44_3, thumbUI, thumb45_1, thumb45_2, thumb45_3, - thumb46_0, thumb46_1, thumb46_2, thumb46_3, thumb47, thumb47, thumbUI, thumbUI, - thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, // 48 - thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, - thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, - thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, - thumb50, thumb50, thumb50, thumb50, thumb50, thumb50, thumb50, thumb50, // 50 - thumb52, thumb52, thumb52, thumb52, thumb52, thumb52, thumb52, thumb52, - thumb54, thumb54, thumb54, thumb54, thumb54, thumb54, thumb54, thumb54, - thumb56, thumb56, thumb56, thumb56, thumb56, thumb56, thumb56, thumb56, - thumb58, thumb58, thumb58, thumb58, thumb58, thumb58, thumb58, thumb58, // 58 - thumb5A, thumb5A, thumb5A, thumb5A, thumb5A, thumb5A, thumb5A, thumb5A, - thumb5C, thumb5C, thumb5C, thumb5C, thumb5C, thumb5C, thumb5C, thumb5C, - thumb5E, thumb5E, thumb5E, thumb5E, thumb5E, thumb5E, thumb5E, thumb5E, - thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, // 60 - thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, - thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, - thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, - thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, // 68 - thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, - thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, - thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, - thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, // 70 - thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, - thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, - thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, - thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, // 78 - thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, - thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, - thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, - thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, // 80 - thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, - thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, - thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, - thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, // 88 - thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, - thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, - thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, - thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, // 90 - thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, - thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, - thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, - thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, // 98 - thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, - thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, - thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, - thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, // A0 - thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, - thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, - thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, - thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, // A8 - thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, - thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, - thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, - thumbB0, thumbB0, thumbB0, thumbB0, thumbUI, thumbUI, thumbUI, thumbUI, // B0 - thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, - thumbB4, thumbB4, thumbB4, thumbB4, thumbB5, thumbB5, thumbB5, thumbB5, - thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, - thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, // B8 - thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, - thumbBC, thumbBC, thumbBC, thumbBC, thumbBD, thumbBD, thumbBD, thumbBD, - thumbBP, thumbBP, thumbBP, thumbBP, thumbUI, thumbUI, thumbUI, thumbUI, - thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, // C0 - thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, - thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, - thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, - thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, // C8 - thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, - thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, - thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, - thumbD0, thumbD0, thumbD0, thumbD0, thumbD1, thumbD1, thumbD1, thumbD1, // D0 - thumbD2, thumbD2, thumbD2, thumbD2, thumbD3, thumbD3, thumbD3, thumbD3, - thumbD4, thumbD4, thumbD4, thumbD4, thumbD5, thumbD5, thumbD5, thumbD5, - thumbD6, thumbD6, thumbD6, thumbD6, thumbD7, thumbD7, thumbD7, thumbD7, - thumbD8, thumbD8, thumbD8, thumbD8, thumbD9, thumbD9, thumbD9, thumbD9, // D8 - thumbDA, thumbDA, thumbDA, thumbDA, thumbDB, thumbDB, thumbDB, thumbDB, - thumbDC, thumbDC, thumbDC, thumbDC, thumbDD, thumbDD, thumbDD, thumbDD, - thumbUI, thumbUI, thumbUI, thumbUI, thumbDF, thumbDF, thumbDF, thumbDF, - thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, // E0 - thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, - thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, - thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, - thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, // E8 - thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, - thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, - thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, - thumbF0, thumbF0, thumbF0, thumbF0, thumbF0, thumbF0, thumbF0, thumbF0, // F0 - thumbF0, thumbF0, thumbF0, thumbF0, thumbF0, thumbF0, thumbF0, thumbF0, - thumbF4, thumbF4, thumbF4, thumbF4, thumbF4, thumbF4, thumbF4, thumbF4, - thumbF4, thumbF4, thumbF4, thumbF4, thumbF4, thumbF4, thumbF4, thumbF4, - thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, // F8 - thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, - thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, - thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, - }; - // Wrapper routine (execution loop) /////////////////////////////////////// +static insnfunc_t thumbInsnTable[1024] = { + thumb00_00, thumb00_01, thumb00_02, thumb00_03, thumb00_04, thumb00_05, thumb00_06, thumb00_07, // 00 + thumb00_08, thumb00_09, thumb00_0A, thumb00_0B, thumb00_0C, thumb00_0D, thumb00_0E, thumb00_0F, + thumb00_10, thumb00_11, thumb00_12, thumb00_13, thumb00_14, thumb00_15, thumb00_16, thumb00_17, + thumb00_18, thumb00_19, thumb00_1A, thumb00_1B, thumb00_1C, thumb00_1D, thumb00_1E, thumb00_1F, + thumb08_00, thumb08_01, thumb08_02, thumb08_03, thumb08_04, thumb08_05, thumb08_06, thumb08_07, // 08 + thumb08_08, thumb08_09, thumb08_0A, thumb08_0B, thumb08_0C, thumb08_0D, thumb08_0E, thumb08_0F, + thumb08_10, thumb08_11, thumb08_12, thumb08_13, thumb08_14, thumb08_15, thumb08_16, thumb08_17, + thumb08_18, thumb08_19, thumb08_1A, thumb08_1B, thumb08_1C, thumb08_1D, thumb08_1E, thumb08_1F, + thumb10_00, thumb10_01, thumb10_02, thumb10_03, thumb10_04, thumb10_05, thumb10_06, thumb10_07, // 10 + thumb10_08, thumb10_09, thumb10_0A, thumb10_0B, thumb10_0C, thumb10_0D, thumb10_0E, thumb10_0F, + thumb10_10, thumb10_11, thumb10_12, thumb10_13, thumb10_14, thumb10_15, thumb10_16, thumb10_17, + thumb10_18, thumb10_19, thumb10_1A, thumb10_1B, thumb10_1C, thumb10_1D, thumb10_1E, thumb10_1F, + thumb18_0, thumb18_1, thumb18_2, thumb18_3, thumb18_4, thumb18_5, thumb18_6, thumb18_7, // 18 + thumb1A_0, thumb1A_1, thumb1A_2, thumb1A_3, thumb1A_4, thumb1A_5, thumb1A_6, thumb1A_7, + thumb1C_0, thumb1C_1, thumb1C_2, thumb1C_3, thumb1C_4, thumb1C_5, thumb1C_6, thumb1C_7, + thumb1E_0, thumb1E_1, thumb1E_2, thumb1E_3, thumb1E_4, thumb1E_5, thumb1E_6, thumb1E_7, + thumb20, thumb20, thumb20, thumb20, thumb21, thumb21, thumb21, thumb21, // 20 + thumb22, thumb22, thumb22, thumb22, thumb23, thumb23, thumb23, thumb23, + thumb24, thumb24, thumb24, thumb24, thumb25, thumb25, thumb25, thumb25, + thumb26, thumb26, thumb26, thumb26, thumb27, thumb27, thumb27, thumb27, + thumb28, thumb28, thumb28, thumb28, thumb29, thumb29, thumb29, thumb29, // 28 + thumb2A, thumb2A, thumb2A, thumb2A, thumb2B, thumb2B, thumb2B, thumb2B, + thumb2C, thumb2C, thumb2C, thumb2C, thumb2D, thumb2D, thumb2D, thumb2D, + thumb2E, thumb2E, thumb2E, thumb2E, thumb2F, thumb2F, thumb2F, thumb2F, + thumb30, thumb30, thumb30, thumb30, thumb31, thumb31, thumb31, thumb31, // 30 + thumb32, thumb32, thumb32, thumb32, thumb33, thumb33, thumb33, thumb33, + thumb34, thumb34, thumb34, thumb34, thumb35, thumb35, thumb35, thumb35, + thumb36, thumb36, thumb36, thumb36, thumb37, thumb37, thumb37, thumb37, + thumb38, thumb38, thumb38, thumb38, thumb39, thumb39, thumb39, thumb39, // 38 + thumb3A, thumb3A, thumb3A, thumb3A, thumb3B, thumb3B, thumb3B, thumb3B, + thumb3C, thumb3C, thumb3C, thumb3C, thumb3D, thumb3D, thumb3D, thumb3D, + thumb3E, thumb3E, thumb3E, thumb3E, thumb3F, thumb3F, thumb3F, thumb3F, + thumb40_0, thumb40_1, thumb40_2, thumb40_3, thumb41_0, thumb41_1, thumb41_2, thumb41_3, // 40 + thumb42_0, thumb42_1, thumb42_2, thumb42_3, thumb43_0, thumb43_1, thumb43_2, thumb43_3, + thumbUI, thumb44_1, thumb44_2, thumb44_3, thumbUI, thumb45_1, thumb45_2, thumb45_3, + thumb46_0, thumb46_1, thumb46_2, thumb46_3, thumb47, thumb47, thumbUI, thumbUI, + thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, // 48 + thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, + thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, + thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, thumb48, + thumb50, thumb50, thumb50, thumb50, thumb50, thumb50, thumb50, thumb50, // 50 + thumb52, thumb52, thumb52, thumb52, thumb52, thumb52, thumb52, thumb52, + thumb54, thumb54, thumb54, thumb54, thumb54, thumb54, thumb54, thumb54, + thumb56, thumb56, thumb56, thumb56, thumb56, thumb56, thumb56, thumb56, + thumb58, thumb58, thumb58, thumb58, thumb58, thumb58, thumb58, thumb58, // 58 + thumb5A, thumb5A, thumb5A, thumb5A, thumb5A, thumb5A, thumb5A, thumb5A, + thumb5C, thumb5C, thumb5C, thumb5C, thumb5C, thumb5C, thumb5C, thumb5C, + thumb5E, thumb5E, thumb5E, thumb5E, thumb5E, thumb5E, thumb5E, thumb5E, + thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, // 60 + thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, + thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, + thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, thumb60, + thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, // 68 + thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, + thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, + thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, thumb68, + thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, // 70 + thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, + thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, + thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, thumb70, + thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, // 78 + thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, + thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, + thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, thumb78, + thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, // 80 + thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, + thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, + thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, thumb80, + thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, // 88 + thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, + thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, + thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, thumb88, + thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, // 90 + thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, + thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, + thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, thumb90, + thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, // 98 + thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, + thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, + thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, thumb98, + thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, // A0 + thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, + thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, + thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, thumbA0, + thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, // A8 + thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, + thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, + thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, thumbA8, + thumbB0, thumbB0, thumbB0, thumbB0, thumbUI, thumbUI, thumbUI, thumbUI, // B0 + thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, + thumbB4, thumbB4, thumbB4, thumbB4, thumbB5, thumbB5, thumbB5, thumbB5, + thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, + thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, // B8 + thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, + thumbBC, thumbBC, thumbBC, thumbBC, thumbBD, thumbBD, thumbBD, thumbBD, + thumbBP, thumbBP, thumbBP, thumbBP, thumbUI, thumbUI, thumbUI, thumbUI, + thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, // C0 + thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, + thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, + thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, thumbC0, + thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, // C8 + thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, + thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, + thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, thumbC8, + thumbD0, thumbD0, thumbD0, thumbD0, thumbD1, thumbD1, thumbD1, thumbD1, // D0 + thumbD2, thumbD2, thumbD2, thumbD2, thumbD3, thumbD3, thumbD3, thumbD3, + thumbD4, thumbD4, thumbD4, thumbD4, thumbD5, thumbD5, thumbD5, thumbD5, + thumbD6, thumbD6, thumbD6, thumbD6, thumbD7, thumbD7, thumbD7, thumbD7, + thumbD8, thumbD8, thumbD8, thumbD8, thumbD9, thumbD9, thumbD9, thumbD9, // D8 + thumbDA, thumbDA, thumbDA, thumbDA, thumbDB, thumbDB, thumbDB, thumbDB, + thumbDC, thumbDC, thumbDC, thumbDC, thumbDD, thumbDD, thumbDD, thumbDD, + thumbUI, thumbUI, thumbUI, thumbUI, thumbDF, thumbDF, thumbDF, thumbDF, + thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, // E0 + thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, + thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, + thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, thumbE0, + thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, // E8 + thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, + thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, + thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, thumbUI, + thumbF0, thumbF0, thumbF0, thumbF0, thumbF0, thumbF0, thumbF0, thumbF0, // F0 + thumbF0, thumbF0, thumbF0, thumbF0, thumbF0, thumbF0, thumbF0, thumbF0, + thumbF4, thumbF4, thumbF4, thumbF4, thumbF4, thumbF4, thumbF4, thumbF4, + thumbF4, thumbF4, thumbF4, thumbF4, thumbF4, thumbF4, thumbF4, thumbF4, + thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, // F8 + thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, + thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, + thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, thumbF8, +}; - int thumbExecute() - { - do { - if (cheatsEnabled) { - cpuMasterCodeCheck(); - } +// Wrapper routine (execution loop) /////////////////////////////////////// - //if ((armNextPC & 0x0803FFFF) == 0x08020000) - // busPrefetchCount=0x100; +int thumbExecute() +{ + do { + if (cheatsEnabled) { + cpuMasterCodeCheck(); + } - uint32_t opcode = cpuPrefetch[0]; - cpuPrefetch[0] = cpuPrefetch[1]; + //if ((armNextPC & 0x0803FFFF) == 0x08020000) + // busPrefetchCount=0x100; + + uint32_t opcode = cpuPrefetch[0]; + cpuPrefetch[0] = cpuPrefetch[1]; + + busPrefetch = false; + if (busPrefetchCount & 0xFFFFFF00) + busPrefetchCount = 0x100 | (busPrefetchCount & 0xFF); + clockTicks = 0; + uint32_t oldArmNextPC = armNextPC; - busPrefetch = false; - if (busPrefetchCount & 0xFFFFFF00) - busPrefetchCount = 0x100 | (busPrefetchCount & 0xFF); - clockTicks = 0; - uint32_t oldArmNextPC = armNextPC; #ifndef FINAL_VERSION - if (armNextPC == stop) { - armNextPC++; - } + if (armNextPC == stop) { + armNextPC++; + } #endif - armNextPC = reg[15].I; - reg[15].I += 2; - THUMB_PREFETCH_NEXT; + armNextPC = reg[15].I; + reg[15].I += 2; + THUMB_PREFETCH_NEXT; #ifdef BKPT_SUPPORT - uint32_t memAddr = armNextPC; - memoryMap* m = &map[memAddr >> 24]; - if (m->breakPoints && BreakThumbCheck(m->breakPoints, memAddr & m->mask)) { - if (debuggerBreakOnExecution(memAddr, armState)) { - // Revert tickcount? - debugger = true; - return 0; - } - } + uint32_t memAddr = armNextPC; + memoryMap* m = &map[memAddr >> 24]; + if (m->breakPoints && BreakThumbCheck(m->breakPoints, memAddr & m->mask)) { + if (debuggerBreakOnExecution(memAddr, armState)) { + // Revert tickcount? + debugger = true; + return 0; + } + } #endif - (*thumbInsnTable[opcode >> 6])(opcode); + (*thumbInsnTable[opcode >> 6])(opcode); #ifdef BKPT_SUPPORT - if (enableRegBreak) { - if (lowRegBreakCounter[0]) - breakReg_check(0); - if (lowRegBreakCounter[1]) - breakReg_check(1); - if (lowRegBreakCounter[2]) - breakReg_check(2); - if (lowRegBreakCounter[3]) - breakReg_check(3); - if (medRegBreakCounter[0]) - breakReg_check(4); - if (medRegBreakCounter[1]) - breakReg_check(5); - if (medRegBreakCounter[2]) - breakReg_check(6); - if (medRegBreakCounter[3]) - breakReg_check(7); - if (highRegBreakCounter[0]) - breakReg_check(8); - if (highRegBreakCounter[1]) - breakReg_check(9); - if (highRegBreakCounter[2]) - breakReg_check(10); - if (highRegBreakCounter[3]) - breakReg_check(11); - if (statusRegBreakCounter[0]) - breakReg_check(12); - if (statusRegBreakCounter[1]) - breakReg_check(13); - if (statusRegBreakCounter[2]) - breakReg_check(14); - if (statusRegBreakCounter[3]) - breakReg_check(15); - } + if (enableRegBreak) { + if (lowRegBreakCounter[0]) + breakReg_check(0); + if (lowRegBreakCounter[1]) + breakReg_check(1); + if (lowRegBreakCounter[2]) + breakReg_check(2); + if (lowRegBreakCounter[3]) + breakReg_check(3); + if (medRegBreakCounter[0]) + breakReg_check(4); + if (medRegBreakCounter[1]) + breakReg_check(5); + if (medRegBreakCounter[2]) + breakReg_check(6); + if (medRegBreakCounter[3]) + breakReg_check(7); + if (highRegBreakCounter[0]) + breakReg_check(8); + if (highRegBreakCounter[1]) + breakReg_check(9); + if (highRegBreakCounter[2]) + breakReg_check(10); + if (highRegBreakCounter[3]) + breakReg_check(11); + if (statusRegBreakCounter[0]) + breakReg_check(12); + if (statusRegBreakCounter[1]) + breakReg_check(13); + if (statusRegBreakCounter[2]) + breakReg_check(14); + if (statusRegBreakCounter[3]) + breakReg_check(15); + } #endif - if (clockTicks < 0) - return 0; - if (clockTicks == 0) - clockTicks = codeTicksAccessSeq16(oldArmNextPC) + 1; - cpuTotalTicks += clockTicks; + if (clockTicks < 0) + return 0; + if (clockTicks == 0) + clockTicks = codeTicksAccessSeq16(oldArmNextPC) + 1; + cpuTotalTicks += clockTicks; - } while (cpuTotalTicks < cpuNextEvent && !armState && !holdState && !SWITicks && !debugger); - return 1; - } + } while (cpuTotalTicks < cpuNextEvent && !armState && !holdState && !SWITicks && !debugger); + return 1; +}