ShuriZma
/
visualboyadvance-m
mirror of https://github.com/visualboyadvance-m/visualboyadvance-m.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

patch to correct some behavior in arm tests. 

git-svn-id: https://svn.code.sf.net/p/vbam/code/trunk@1150 a31d4220-a93d-0410-bf67-fe4944624d44
This commit is contained in:
squall-leonhart 2013-01-23 00:38:00 +00:00
parent d94c8037e0
commit 174cbec2a2
1 changed files with 32 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

51
src/gba/GBA-arm.cpp
View File

@ -754,12 +754,16 @@ static void count(u32 opcode, int cond_res)
#ifndef VALUE_LSL_REG_C #ifndef VALUE_LSL_REG_C
#define VALUE_LSL_REG_C \ #define VALUE_LSL_REG_C \
unsigned int shift = reg[(opcode >> 8)&15].B.B0; \ unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
unsigned int rm = reg[opcode & 0x0F].I; \
if(opcode & 0x0F == 15) { \
rm += 4; \
} \
if (LIKELY(shift)) { \ if (LIKELY(shift)) { \
if (shift == 32) { \ if (shift == 32) { \
value = 0; \ value = 0; \
C_OUT = (reg[opcode & 0x0F].I & 1 ? true : false);\ C_OUT = (rm & 1 ? true : false);\
} else if (LIKELY(shift < 32)) { \ } else if (LIKELY(shift < 32)) { \
u32 v = reg[opcode & 0x0F].I; \ u32 v = rm; \
C_OUT = (v >> (32 - shift)) & 1 ? true : false;\ C_OUT = (v >> (32 - shift)) & 1 ? true : false;\
value = v << shift; \ value = v << shift; \
} else { \ } else { \
@ -767,7 +771,7 @@ static void count(u32 opcode, int cond_res)
C_OUT = false; \ C_OUT = false; \
} \ } \
} else { \ } else { \
value = reg[opcode & 0x0F].I; \ value = rm; \
} }
#endif #endif
// OP Rd,Rb,Rm LSR # // OP Rd,Rb,Rm LSR #
@ -787,20 +791,23 @@ static void count(u32 opcode, int cond_res)
#ifndef VALUE_LSR_REG_C #ifndef VALUE_LSR_REG_C
#define VALUE_LSR_REG_C \ #define VALUE_LSR_REG_C \
unsigned int shift = reg[(opcode >> 8)&15].B.B0; \ unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
unsigned int rm = reg[opcode & 0x0F].I; \
if(opcode & 0x0F == 15) { \
rm += 4; \
} \
if (LIKELY(shift)) { \ if (LIKELY(shift)) { \
if (shift == 32) { \ if (shift == 32) { \
value = 0; \ value = 0; \
C_OUT = (reg[opcode & 0x0F].I & 0x80000000 ? true : false);\ C_OUT = (rm & 0x80000000 ? true : false); \
} else if (LIKELY(shift < 32)) { \ } else if (LIKELY(shift < 32)) { \
u32 v = reg[opcode & 0x0F].I; \ C_OUT = (rm >> (shift - 1)) & 1 ? true : false;\
C_OUT = (v >> (shift - 1)) & 1 ? true : false;\ value = rm >> shift; \
value = v >> shift; \
} else { \ } else { \
value = 0; \ value = 0; \
C_OUT = false; \ C_OUT = false; \
} \ } \
} else { \ } else { \
value = reg[opcode & 0x0F].I; \ value = rm; \
} }
#endif #endif
// OP Rd,Rb,Rm ASR # // OP Rd,Rb,Rm ASR #
@ -826,16 +833,19 @@ static void count(u32 opcode, int cond_res)
#ifndef VALUE_ASR_REG_C #ifndef VALUE_ASR_REG_C
#define VALUE_ASR_REG_C \ #define VALUE_ASR_REG_C \
unsigned int shift = reg[(opcode >> 8)&15].B.B0; \ unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
unsigned int rm = reg[opcode & 0x0F].I; \
if(opcode & 0x0F == 15) { \
rm += 4; \
} \
if (LIKELY(shift < 32)) { \ if (LIKELY(shift < 32)) { \
if (LIKELY(shift)) { \ if (LIKELY(shift)) { \
s32 v = reg[opcode & 0x0F].I; \ C_OUT = (rm >> (int)(shift - 1)) & 1 ? true : false;\
C_OUT = (v >> (int)(shift - 1)) & 1 ? true : false;\ value = rm >> (int)shift; \
value = v >> (int)shift; \
} else { \ } else { \
value = reg[opcode & 0x0F].I; \ value = rm; \
} \ } \
} else { \ } else { \
if (reg[opcode & 0x0F].I & 0x80000000) { \ if (rm & 0x80000000) { \
value = 0xFFFFFFFF; \ value = 0xFFFFFFFF; \
C_OUT = true; \ C_OUT = true; \
} else { \ } else { \
@ -864,13 +874,16 @@ static void count(u32 opcode, int cond_res)
#ifndef VALUE_ROR_REG_C #ifndef VALUE_ROR_REG_C
#define VALUE_ROR_REG_C \ #define VALUE_ROR_REG_C \
unsigned int shift = reg[(opcode >> 8)&15].B.B0; \ unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
unsigned int rm = reg[opcode & 0x0F].I; \
if(opcode & 0x0F == 15) { \
rm += 4; \
} \
if (LIKELY(shift & 0x1F)) { \ if (LIKELY(shift & 0x1F)) { \
u32 v = reg[opcode & 0x0F].I; \ C_OUT = (rm >> (shift - 1)) & 1 ? true : false; \
C_OUT = (v >> (shift - 1)) & 1 ? true : false; \ value = ((rm << (32 - shift)) | \
value = ((v << (32 - shift)) | \ (rm >> shift)); \
(v >> shift)); \
} else { \ } else { \
value = reg[opcode & 0x0F].I; \ value = rm; \
if (shift) \ if (shift) \
C_OUT = (value & 0x80000000 ? true : false);\ C_OUT = (value & 0x80000000 ? true : false);\
} }
@ -2947,4 +2960,4 @@ int armExecute()
} while (cpuTotalTicks<cpuNextEvent && armState && !holdState && !SWITicks); } while (cpuTotalTicks<cpuNextEvent && armState && !holdState && !SWITicks);
return 1; return 1;
} }