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visualboyadvance-m
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patch to correct some behavior in arm tests. 

git-svn-id: https://svn.code.sf.net/p/vbam/code/trunk@1150 a31d4220-a93d-0410-bf67-fe4944624d44
This commit is contained in:
squall-leonhart 2013-01-23 00:38:00 +00:00
parent d94c8037e0
commit 174cbec2a2
1 changed files with 32 additions and 19 deletions
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51
src/gba/GBA-arm.cpp
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@ -754,12 +754,16 @@ static void count(u32 opcode, int cond_res)
#ifndef VALUE_LSL_REG_C
#define VALUE_LSL_REG_C \
unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
unsigned int rm = reg[opcode & 0x0F].I; \
if(opcode & 0x0F == 15) { \
rm += 4; \
} \
if (LIKELY(shift)) { \
if (shift == 32) { \
value = 0; \
C_OUT = (reg[opcode & 0x0F].I & 1 ? true : false);\
C_OUT = (rm & 1 ? true : false);\
} else if (LIKELY(shift < 32)) { \
u32 v = reg[opcode & 0x0F].I; \
u32 v = rm; \
C_OUT = (v >> (32 - shift)) & 1 ? true : false;\
value = v << shift; \
} else { \
@ -767,7 +771,7 @@ static void count(u32 opcode, int cond_res)
C_OUT = false; \
} \
} else { \
value = reg[opcode & 0x0F].I; \
value = rm; \
}
#endif
// OP Rd,Rb,Rm LSR #
@ -787,20 +791,23 @@ static void count(u32 opcode, int cond_res)
#ifndef VALUE_LSR_REG_C
#define VALUE_LSR_REG_C \
unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
unsigned int rm = reg[opcode & 0x0F].I; \
if(opcode & 0x0F == 15) { \
rm += 4; \
} \
if (LIKELY(shift)) { \
if (shift == 32) { \
value = 0; \
C_OUT = (reg[opcode & 0x0F].I & 0x80000000 ? true : false);\
C_OUT = (rm & 0x80000000 ? true : false); \
} else if (LIKELY(shift < 32)) { \
u32 v = reg[opcode & 0x0F].I; \
C_OUT = (v >> (shift - 1)) & 1 ? true : false;\
value = v >> shift; \
C_OUT = (rm >> (shift - 1)) & 1 ? true : false;\
value = rm >> shift; \
} else { \
value = 0; \
C_OUT = false; \
} \
} else { \
value = reg[opcode & 0x0F].I; \
value = rm; \
}
#endif
// OP Rd,Rb,Rm ASR #
@ -826,16 +833,19 @@ static void count(u32 opcode, int cond_res)
#ifndef VALUE_ASR_REG_C
#define VALUE_ASR_REG_C \
unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
unsigned int rm = reg[opcode & 0x0F].I; \
if(opcode & 0x0F == 15) { \
rm += 4; \
} \
if (LIKELY(shift < 32)) { \
if (LIKELY(shift)) { \
s32 v = reg[opcode & 0x0F].I; \
C_OUT = (v >> (int)(shift - 1)) & 1 ? true : false;\
value = v >> (int)shift; \
C_OUT = (rm >> (int)(shift - 1)) & 1 ? true : false;\
value = rm >> (int)shift; \
} else { \
value = reg[opcode & 0x0F].I; \
value = rm; \
} \
} else { \
if (reg[opcode & 0x0F].I & 0x80000000) { \
if (rm & 0x80000000) { \
value = 0xFFFFFFFF; \
C_OUT = true; \
} else { \
@ -864,13 +874,16 @@ static void count(u32 opcode, int cond_res)
#ifndef VALUE_ROR_REG_C
#define VALUE_ROR_REG_C \
unsigned int shift = reg[(opcode >> 8)&15].B.B0; \
unsigned int rm = reg[opcode & 0x0F].I; \
if(opcode & 0x0F == 15) { \
rm += 4; \
} \
if (LIKELY(shift & 0x1F)) { \
u32 v = reg[opcode & 0x0F].I; \
C_OUT = (v >> (shift - 1)) & 1 ? true : false; \
value = ((v << (32 - shift)) | \
(v >> shift)); \
C_OUT = (rm >> (shift - 1)) & 1 ? true : false; \
value = ((rm << (32 - shift)) | \
(rm >> shift)); \
} else { \
value = reg[opcode & 0x0F].I; \
value = rm; \
if (shift) \
C_OUT = (value & 0x80000000 ? true : false);\
}
@ -2947,4 +2960,4 @@ int armExecute()
} while (cpuTotalTicks<cpuNextEvent && armState && !holdState && !SWITicks);
return 1;
}
}