mirror of https://git.suyu.dev/suyu/suyu
armstate: Correct FIQ register banking
FIQ has seven banked registers (R8 to R14), not two.
This commit is contained in:
parent
b83e95727f
commit
d53c9cde1a
|
@ -2,6 +2,7 @@
|
||||||
// Licensed under GPLv2 or any later version
|
// Licensed under GPLv2 or any later version
|
||||||
// Refer to the license.txt file included.
|
// Refer to the license.txt file included.
|
||||||
|
|
||||||
|
#include <algorithm>
|
||||||
#include "common/swap.h"
|
#include "common/swap.h"
|
||||||
#include "common/logging/log.h"
|
#include "common/logging/log.h"
|
||||||
#include "core/memory.h"
|
#include "core/memory.h"
|
||||||
|
@ -48,8 +49,7 @@ void ARMul_State::ChangePrivilegeMode(u32 new_mode)
|
||||||
Spsr[UNDEFBANK] = Spsr_copy;
|
Spsr[UNDEFBANK] = Spsr_copy;
|
||||||
break;
|
break;
|
||||||
case FIQ32MODE:
|
case FIQ32MODE:
|
||||||
Reg_firq[0] = Reg[13];
|
std::copy(Reg.begin() + 8, Reg.end() - 1, Reg_firq.begin());
|
||||||
Reg_firq[1] = Reg[14];
|
|
||||||
Spsr[FIQBANK] = Spsr_copy;
|
Spsr[FIQBANK] = Spsr_copy;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -85,8 +85,7 @@ void ARMul_State::ChangePrivilegeMode(u32 new_mode)
|
||||||
Bank = UNDEFBANK;
|
Bank = UNDEFBANK;
|
||||||
break;
|
break;
|
||||||
case FIQ32MODE:
|
case FIQ32MODE:
|
||||||
Reg[13] = Reg_firq[0];
|
std::copy(Reg_firq.begin(), Reg_firq.end(), Reg.begin() + 8);
|
||||||
Reg[14] = Reg_firq[1];
|
|
||||||
Spsr_copy = Spsr[FIQBANK];
|
Spsr_copy = Spsr[FIQBANK];
|
||||||
Bank = FIQBANK;
|
Bank = FIQBANK;
|
||||||
break;
|
break;
|
||||||
|
|
Loading…
Reference in New Issue