mirror of https://git.suyu.dev/suyu/suyu
Merge pull request #559 from lioncash/clean
arm: Some cleanup. Also fixed the initial ARM mode that is emulated.
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commit
c51b23b052
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@ -23,7 +23,7 @@ ARM_DynCom::ARM_DynCom() {
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ARMul_NewState((ARMul_State*)state.get());
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ARMul_NewState((ARMul_State*)state.get());
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state->abort_model = 0;
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state->abort_model = ABORT_BASE_RESTORED;
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state->cpu = (cpu_config_t*)&s_arm11_cpu_info;
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state->cpu = (cpu_config_t*)&s_arm11_cpu_info;
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state->bigendSig = LOW;
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state->bigendSig = LOW;
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@ -34,7 +34,7 @@ ARM_DynCom::ARM_DynCom() {
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ARMul_CoProInit(state.get());
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ARMul_CoProInit(state.get());
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ARMul_Reset(state.get());
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ARMul_Reset(state.get());
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state->NextInstr = RESUME; // NOTE: This will be overwritten by LoadContext
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state->NextInstr = RESUME; // NOTE: This will be overwritten by LoadContext
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state->Emulate = 3;
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state->Emulate = RUN;
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state->Reg[15] = 0x00000000;
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state->Reg[15] = 0x00000000;
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state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
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state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
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@ -74,7 +74,7 @@ ARMul_State* ARMul_NewState(ARMul_State* state)
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for (unsigned int i = 0; i < 7; i++)
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for (unsigned int i = 0; i < 7; i++)
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state->Spsr[i] = 0;
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state->Spsr[i] = 0;
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state->Mode = 0;
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state->Mode = USER32MODE;
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state->VectorCatch = 0;
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state->VectorCatch = 0;
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state->Aborted = false;
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state->Aborted = false;
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@ -35,15 +35,27 @@
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#define BITS(s, a, b) ((s << ((sizeof(s) * 8 - 1) - b)) >> (sizeof(s) * 8 - b + a - 1))
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#define BITS(s, a, b) ((s << ((sizeof(s) * 8 - 1) - b)) >> (sizeof(s) * 8 - b + a - 1))
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#define BIT(s, n) ((s >> (n)) & 1)
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#define BIT(s, n) ((s >> (n)) & 1)
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#define LOW 0
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// Signal levels
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#define HIGH 1
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enum {
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#define LOWHIGH 1
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LOW = 0,
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#define HIGHLOW 2
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HIGH = 1,
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LOWHIGH = 1,
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HIGHLOW = 2
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};
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//the define of cachetype
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// Cache types
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#define NONCACHE 0
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enum {
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#define DATACACHE 1
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NONCACHE = 0,
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#define INSTCACHE 2
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DATACACHE = 1,
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INSTCACHE = 2,
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};
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// Abort models
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enum {
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ABORT_BASE_RESTORED = 0,
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ABORT_EARLY = 1,
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ABORT_BASE_UPDATED = 2
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};
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#define POS(i) ( (~(i)) >> 31 )
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#define POS(i) ( (~(i)) >> 31 )
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#define NEG(i) ( (i) >> 31 )
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#define NEG(i) ( (i) >> 31 )
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@ -76,24 +76,28 @@
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#define R15MODE (state->Reg[15] & R15MODEBITS)
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#define R15MODE (state->Reg[15] & R15MODEBITS)
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// Different ways to start the next instruction.
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// Different ways to start the next instruction.
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#define SEQ 0
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enum {
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#define NONSEQ 1
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SEQ = 0,
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#define PCINCEDSEQ 2
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NONSEQ = 1,
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#define PCINCEDNONSEQ 3
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PCINCEDSEQ = 2,
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#define PRIMEPIPE 4
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PCINCEDNONSEQ = 3,
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#define RESUME 8
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PRIMEPIPE = 4,
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RESUME = 8
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};
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// Values for Emulate.
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enum {
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STOP = 0, // Stop
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CHANGEMODE = 1, // Change mode
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ONCE = 2, // Execute just one interation
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RUN = 3 // Continuous execution
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};
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#define FLUSHPIPE state->NextInstr |= PRIMEPIPE
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#define FLUSHPIPE state->NextInstr |= PRIMEPIPE
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// Macro to rotate n right by b bits.
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// Macro to rotate n right by b bits.
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#define ROTATER(n, b) (((n) >> (b)) | ((n) << (32 - (b))))
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#define ROTATER(n, b) (((n) >> (b)) | ((n) << (32 - (b))))
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// Values for Emulate.
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#define STOP 0 // stop
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#define CHANGEMODE 1 // change mode
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#define ONCE 2 // execute just one interation
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#define RUN 3 // continuous execution
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// Stuff that is shared across modes.
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// Stuff that is shared across modes.
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extern unsigned ARMul_MultTable[]; // Number of I cycles for a mult.
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extern unsigned ARMul_MultTable[]; // Number of I cycles for a mult.
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extern ARMword ARMul_ImmedTable[]; // Immediate DP LHS values.
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extern ARMword ARMul_ImmedTable[]; // Immediate DP LHS values.
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