mirror of https://git.suyu.dev/suyu/suyu
Merge pull request #703 from lioncash/cruft
dyncom: Remove unused/unnecessary VFP cruft
This commit is contained in:
bunnei
commit
a698e15c5d
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@ -6,7 +6,6 @@ set(SRCS
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arm/dyncom/arm_dyncom_interpreter.cpp
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arm/dyncom/arm_dyncom_interpreter.cpp
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arm/dyncom/arm_dyncom_run.cpp
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arm/dyncom/arm_dyncom_run.cpp
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arm/dyncom/arm_dyncom_thumb.cpp
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arm/dyncom/arm_dyncom_thumb.cpp
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arm/interpreter/armcopro.cpp
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arm/interpreter/arminit.cpp
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arm/interpreter/arminit.cpp
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arm/interpreter/armsupp.cpp
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arm/interpreter/armsupp.cpp
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arm/skyeye_common/vfp/vfp.cpp
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arm/skyeye_common/vfp/vfp.cpp
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@ -1,142 +0,0 @@
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/* armcopro.c -- co-processor interface: ARM6 Instruction Emulator.
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Copyright (C) 1994, 2000 Advanced RISC Machines Ltd.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "core/arm/skyeye_common/armdefs.h"
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#include "core/arm/skyeye_common/armemu.h"
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#include "core/arm/skyeye_common/vfp/vfp.h"
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// Dummy Co-processors.
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static unsigned int NoCoPro3R(ARMul_State* state, unsigned int a, ARMword b)
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{
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return ARMul_CANT;
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}
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static unsigned int NoCoPro4R(ARMul_State* state, unsigned int a, ARMword b, ARMword c)
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{
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return ARMul_CANT;
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}
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static unsigned int NoCoPro4W(ARMul_State* state, unsigned int a, ARMword b, ARMword* c)
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{
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return ARMul_CANT;
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}
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static unsigned int NoCoPro5R(ARMul_State* state, unsigned int a, ARMword b, ARMword c, ARMword d)
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{
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return ARMul_CANT;
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}
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static unsigned int NoCoPro5W(ARMul_State* state, unsigned int a, ARMword b, ARMword* c, ARMword* d)
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{
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return ARMul_CANT;
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}
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// Install co-processor instruction handlers in this routine.
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void ARMul_CoProInit(ARMul_State* state)
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{
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// Initialise tham all first.
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for (unsigned int i = 0; i < 16; i++)
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ARMul_CoProDetach(state, i);
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// Install CoPro Instruction handlers here.
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// The format is:
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// ARMul_CoProAttach (state, CP Number, Init routine, Exit routine
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// LDC routine, STC routine, MRC routine, MCR routine,
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// CDP routine, Read Reg routine, Write Reg routine).
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if (state->is_v6) {
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ARMul_CoProAttach(state, 10, VFPInit, NULL, VFPLDC, VFPSTC,
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VFPMRC, VFPMCR, VFPMRRC, VFPMCRR, VFPCDP, NULL, NULL);
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ARMul_CoProAttach(state, 11, VFPInit, NULL, VFPLDC, VFPSTC,
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VFPMRC, VFPMCR, VFPMRRC, VFPMCRR, VFPCDP, NULL, NULL);
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/*ARMul_CoProAttach (state, 15, MMUInit, NULL, NULL, NULL,
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MMUMRC, MMUMCR, NULL, NULL, NULL, NULL, NULL);*/
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}
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// No handlers below here.
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// Call all the initialisation routines.
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for (unsigned int i = 0; i < 16; i++) {
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if (state->CPInit[i])
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(state->CPInit[i]) (state);
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}
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}
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// Install co-processor finalisation routines in this routine.
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void ARMul_CoProExit(ARMul_State * state)
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{
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for (unsigned int i = 0; i < 16; i++)
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if (state->CPExit[i])
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(state->CPExit[i]) (state);
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// Detach all handlers.
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for (unsigned int i = 0; i < 16; i++)
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ARMul_CoProDetach(state, i);
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}
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// Routines to hook Co-processors into ARMulator.
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void
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ARMul_CoProAttach(ARMul_State* state,
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unsigned number,
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ARMul_CPInits* init,
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ARMul_CPExits* exit,
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ARMul_LDCs* ldc,
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ARMul_STCs* stc,
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ARMul_MRCs* mrc,
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ARMul_MCRs* mcr,
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ARMul_MRRCs* mrrc,
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ARMul_MCRRs* mcrr,
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ARMul_CDPs* cdp,
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ARMul_CPReads* read, ARMul_CPWrites* write)
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{
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if (init != NULL)
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state->CPInit[number] = init;
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if (exit != NULL)
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state->CPExit[number] = exit;
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if (ldc != NULL)
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state->LDC[number] = ldc;
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if (stc != NULL)
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state->STC[number] = stc;
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if (mrc != NULL)
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state->MRC[number] = mrc;
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if (mcr != NULL)
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state->MCR[number] = mcr;
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if (mrrc != NULL)
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state->MRRC[number] = mrrc;
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if (mcrr != NULL)
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state->MCRR[number] = mcrr;
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if (cdp != NULL)
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state->CDP[number] = cdp;
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if (read != NULL)
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state->CPRead[number] = read;
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if (write != NULL)
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state->CPWrite[number] = write;
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}
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void ARMul_CoProDetach(ARMul_State* state, unsigned number)
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{
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ARMul_CoProAttach(state, number, NULL, NULL,
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NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R,
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NoCoPro5W, NoCoPro5R, NoCoPro3R, NULL, NULL);
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state->CPInit[number] = NULL;
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state->CPExit[number] = NULL;
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state->CPRead[number] = NULL;
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state->CPWrite[number] = NULL;
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}
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@ -19,6 +19,7 @@
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#include "core/mem_map.h"
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#include "core/mem_map.h"
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#include "core/arm/skyeye_common/armdefs.h"
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#include "core/arm/skyeye_common/armdefs.h"
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#include "core/arm/skyeye_common/armemu.h"
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#include "core/arm/skyeye_common/armemu.h"
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#include "core/arm/skyeye_common/vfp/vfp.h"
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/***************************************************************************\
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/***************************************************************************\
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* Returns a new instantiation of the ARMulator's state *
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* Returns a new instantiation of the ARMulator's state *
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@ -56,15 +57,11 @@ ARMul_State* ARMul_NewState(ARMul_State* state)
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void ARMul_SelectProcessor(ARMul_State* state, unsigned properties)
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void ARMul_SelectProcessor(ARMul_State* state, unsigned properties)
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{
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{
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state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) != 0;
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state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) != 0;
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state->is_v5 = (properties & ARM_v5_Prop) != 0;
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state->is_v5 = (properties & ARM_v5_Prop) != 0;
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state->is_v5e = (properties & ARM_v5e_Prop) != 0;
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state->is_v5e = (properties & ARM_v5e_Prop) != 0;
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state->is_v6 = (properties & ARM_v6_Prop) != 0;
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state->is_v6 = (properties & ARM_v6_Prop) != 0;
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state->is_v7 = (properties & ARM_v7_Prop) != 0;
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state->is_v7 = (properties & ARM_v7_Prop) != 0;
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// Only initialse the coprocessor support once we
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// know what kind of chip we are dealing with.
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ARMul_CoProInit(state);
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}
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}
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// Resets certain MPCore CP15 values to their ARM-defined reset values.
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// Resets certain MPCore CP15 values to their ARM-defined reset values.
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@ -130,6 +127,8 @@ static void ResetMPCoreCP15Registers(ARMul_State* cpu)
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\***************************************************************************/
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\***************************************************************************/
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void ARMul_Reset(ARMul_State* state)
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void ARMul_Reset(ARMul_State* state)
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{
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{
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VFPInit(state);
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state->NextInstr = 0;
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state->NextInstr = 0;
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state->Reg[15] = 0;
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state->Reg[15] = 0;
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@ -55,18 +55,6 @@ typedef u16 ARMhword; // must be 16 bits wide
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typedef u8 ARMbyte; // must be 8 bits wide
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typedef u8 ARMbyte; // must be 8 bits wide
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typedef struct ARMul_State ARMul_State;
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typedef struct ARMul_State ARMul_State;
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typedef unsigned ARMul_CPInits(ARMul_State* state);
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typedef unsigned ARMul_CPExits(ARMul_State* state);
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typedef unsigned ARMul_LDCs(ARMul_State* state, unsigned type, ARMword instr, ARMword value);
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typedef unsigned ARMul_STCs(ARMul_State* state, unsigned type, ARMword instr, ARMword* value);
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typedef unsigned ARMul_MRCs(ARMul_State* state, unsigned type, ARMword instr, ARMword* value);
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typedef unsigned ARMul_MCRs(ARMul_State* state, unsigned type, ARMword instr, ARMword value);
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typedef unsigned ARMul_MRRCs(ARMul_State* state, unsigned type, ARMword instr, ARMword* value1, ARMword* value2);
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typedef unsigned ARMul_MCRRs(ARMul_State* state, unsigned type, ARMword instr, ARMword value1, ARMword value2);
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typedef unsigned ARMul_CDPs(ARMul_State* state, unsigned type, ARMword instr);
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typedef unsigned ARMul_CPReads(ARMul_State* state, unsigned reg, ARMword* value);
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typedef unsigned ARMul_CPWrites(ARMul_State* state, unsigned reg, ARMword value);
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#define VFP_REG_NUM 64
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#define VFP_REG_NUM 64
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struct ARMul_State
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struct ARMul_State
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{
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{
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@ -117,20 +105,6 @@ struct ARMul_State
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unsigned NextInstr;
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unsigned NextInstr;
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unsigned VectorCatch; // Caught exception mask
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unsigned VectorCatch; // Caught exception mask
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ARMul_CPInits* CPInit[16]; // Coprocessor initialisers
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ARMul_CPExits* CPExit[16]; // Coprocessor finalisers
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ARMul_LDCs* LDC[16]; // LDC instruction
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ARMul_STCs* STC[16]; // STC instruction
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ARMul_MRCs* MRC[16]; // MRC instruction
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ARMul_MCRs* MCR[16]; // MCR instruction
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ARMul_MRRCs* MRRC[16]; // MRRC instruction
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ARMul_MCRRs* MCRR[16]; // MCRR instruction
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ARMul_CDPs* CDP[16]; // CDP instruction
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ARMul_CPReads* CPRead[16]; // Read CP register
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ARMul_CPWrites* CPWrite[16]; // Write CP register
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unsigned char* CPData[16]; // Coprocessor data
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unsigned char const* CPRegWords[16]; // Map of coprocessor register sizes
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unsigned NresetSig; // Reset the processor
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unsigned NresetSig; // Reset the processor
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unsigned NfiqSig;
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unsigned NfiqSig;
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unsigned NirqSig;
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unsigned NirqSig;
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@ -57,12 +57,3 @@ enum {
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};
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};
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#define FLUSHPIPE state->NextInstr |= PRIMEPIPE
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#define FLUSHPIPE state->NextInstr |= PRIMEPIPE
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// Coprocessor support functions.
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extern void ARMul_CoProInit(ARMul_State*);
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extern void ARMul_CoProExit(ARMul_State*);
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extern void ARMul_CoProAttach(ARMul_State*, unsigned, ARMul_CPInits*,
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ARMul_CPExits*, ARMul_LDCs*, ARMul_STCs*,
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ARMul_MRCs*, ARMul_MCRs*, ARMul_MRRCs*, ARMul_MCRRs*,
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ARMul_CDPs*, ARMul_CPReads*, ARMul_CPWrites*);
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extern void ARMul_CoProDetach(ARMul_State*, unsigned);
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@ -37,296 +37,18 @@ unsigned VFPInit(ARMul_State* state)
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return 0;
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return 0;
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}
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}
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unsigned VFPMRC(ARMul_State* state, unsigned type, u32 instr, u32* value)
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void VMSR(ARMul_State* state, ARMword reg, ARMword Rt)
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{
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{
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/* MRC<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>} */
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if (reg == 1)
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int CoProc = BITS(instr, 8, 11); /* 10 or 11 */
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int OPC_1 = BITS(instr, 21, 23);
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int Rt = BITS(instr, 12, 15);
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int CRn = BITS(instr, 16, 19);
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int CRm = BITS(instr, 0, 3);
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int OPC_2 = BITS(instr, 5, 7);
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/* TODO check access permission */
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/* CRn/opc1 CRm/opc2 */
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if (CoProc == 10 || CoProc == 11)
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{
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{
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if (OPC_1 == 0x0 && CRm == 0 && (OPC_2 & 0x3) == 0)
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state->VFP[VFP_FPSCR] = state->Reg[Rt];
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{
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/* VMOV r to s */
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/* Transfering Rt is not mandatory, as the value of interest is pointed by value */
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VMOVBRS(state, BIT(instr, 20), Rt, BIT(instr, 7)|CRn<<1, value);
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return ARMul_DONE;
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}
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if (OPC_1 == 0x7 && CRm == 0 && OPC_2 == 0)
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{
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VMRS(state, CRn, Rt, value);
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return ARMul_DONE;
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}
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}
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}
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LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n",
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else if (reg == 8)
|
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instr, CoProc, OPC_1, Rt, CRn, CRm, OPC_2);
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return ARMul_CANT;
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}
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unsigned VFPMCR(ARMul_State* state, unsigned type, u32 instr, u32 value)
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|
||||||
{
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/* MCR<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>} */
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int CoProc = BITS(instr, 8, 11); /* 10 or 11 */
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int OPC_1 = BITS(instr, 21, 23);
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int Rt = BITS(instr, 12, 15);
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int CRn = BITS(instr, 16, 19);
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int CRm = BITS(instr, 0, 3);
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int OPC_2 = BITS(instr, 5, 7);
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/* TODO check access permission */
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/* CRn/opc1 CRm/opc2 */
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if (CoProc == 10 || CoProc == 11)
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{
|
{
|
||||||
if (OPC_1 == 0x0 && CRm == 0 && (OPC_2 & 0x3) == 0)
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state->VFP[VFP_FPEXC] = state->Reg[Rt];
|
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{
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/* VMOV s to r */
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||||||
/* Transfering Rt is not mandatory, as the value of interest is pointed by value */
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|
||||||
VMOVBRS(state, BIT(instr, 20), Rt, BIT(instr, 7)|CRn<<1, &value);
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||||||
return ARMul_DONE;
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|
||||||
}
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|
||||||
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|
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if (OPC_1 == 0x7 && CRm == 0 && OPC_2 == 0)
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|
||||||
{
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|
||||||
VMSR(state, CRn, Rt);
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|
||||||
return ARMul_DONE;
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|
||||||
}
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|
||||||
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if ((OPC_1 & 0x4) == 0 && CoProc == 11 && CRm == 0)
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|
||||||
{
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|
||||||
VFP_DEBUG_UNIMPLEMENTED(VMOVBRC);
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|
||||||
return ARMul_DONE;
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|
||||||
}
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|
||||||
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|
||||||
if (CoProc == 11 && CRm == 0)
|
|
||||||
{
|
|
||||||
VFP_DEBUG_UNIMPLEMENTED(VMOVBCR);
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|
||||||
return ARMul_DONE;
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|
||||||
}
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|
||||||
}
|
}
|
||||||
LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n",
|
|
||||||
instr, CoProc, OPC_1, Rt, CRn, CRm, OPC_2);
|
|
||||||
|
|
||||||
return ARMul_CANT;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
unsigned VFPMRRC(ARMul_State* state, unsigned type, u32 instr, u32* value1, u32* value2)
|
|
||||||
{
|
|
||||||
/* MCRR<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm> */
|
|
||||||
int CoProc = BITS(instr, 8, 11); /* 10 or 11 */
|
|
||||||
int OPC_1 = BITS(instr, 4, 7);
|
|
||||||
int Rt = BITS(instr, 12, 15);
|
|
||||||
int Rt2 = BITS(instr, 16, 19);
|
|
||||||
int CRm = BITS(instr, 0, 3);
|
|
||||||
|
|
||||||
if (CoProc == 10 || CoProc == 11)
|
|
||||||
{
|
|
||||||
if (CoProc == 10 && (OPC_1 & 0xD) == 1)
|
|
||||||
{
|
|
||||||
VMOVBRRSS(state, BIT(instr, 20), Rt, Rt2, BIT(instr, 5)<<4|CRm, value1, value2);
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (CoProc == 11 && (OPC_1 & 0xD) == 1)
|
|
||||||
{
|
|
||||||
/* Transfering Rt and Rt2 is not mandatory, as the value of interest is pointed by value1 and value2 */
|
|
||||||
VMOVBRRD(state, BIT(instr, 20), Rt, Rt2, BIT(instr, 5)<<4|CRm, value1, value2);
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n",
|
|
||||||
instr, CoProc, OPC_1, Rt, Rt2, CRm);
|
|
||||||
|
|
||||||
return ARMul_CANT;
|
|
||||||
}
|
|
||||||
|
|
||||||
unsigned VFPMCRR(ARMul_State* state, unsigned type, u32 instr, u32 value1, u32 value2)
|
|
||||||
{
|
|
||||||
/* MCRR<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm> */
|
|
||||||
int CoProc = BITS(instr, 8, 11); /* 10 or 11 */
|
|
||||||
int OPC_1 = BITS(instr, 4, 7);
|
|
||||||
int Rt = BITS(instr, 12, 15);
|
|
||||||
int Rt2 = BITS(instr, 16, 19);
|
|
||||||
int CRm = BITS(instr, 0, 3);
|
|
||||||
|
|
||||||
/* TODO check access permission */
|
|
||||||
|
|
||||||
/* CRn/opc1 CRm/opc2 */
|
|
||||||
|
|
||||||
if (CoProc == 11 || CoProc == 10)
|
|
||||||
{
|
|
||||||
if (CoProc == 10 && (OPC_1 & 0xD) == 1)
|
|
||||||
{
|
|
||||||
VMOVBRRSS(state, BIT(instr, 20), Rt, Rt2, BIT(instr, 5)<<4|CRm, &value1, &value2);
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (CoProc == 11 && (OPC_1 & 0xD) == 1)
|
|
||||||
{
|
|
||||||
/* Transfering Rt and Rt2 is not mandatory, as the value of interest is pointed by value1 and value2 */
|
|
||||||
VMOVBRRD(state, BIT(instr, 20), Rt, Rt2, BIT(instr, 5)<<4|CRm, &value1, &value2);
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n",
|
|
||||||
instr, CoProc, OPC_1, Rt, Rt2, CRm);
|
|
||||||
|
|
||||||
return ARMul_CANT;
|
|
||||||
}
|
|
||||||
|
|
||||||
unsigned VFPSTC(ARMul_State* state, unsigned type, u32 instr, u32 * value)
|
|
||||||
{
|
|
||||||
/* STC{L}<c> <coproc>,<CRd>,[<Rn>],<option> */
|
|
||||||
int CoProc = BITS(instr, 8, 11); /* 10 or 11 */
|
|
||||||
int CRd = BITS(instr, 12, 15);
|
|
||||||
int Rn = BITS(instr, 16, 19);
|
|
||||||
int imm8 = BITS(instr, 0, 7);
|
|
||||||
int P = BIT(instr, 24);
|
|
||||||
int U = BIT(instr, 23);
|
|
||||||
int D = BIT(instr, 22);
|
|
||||||
int W = BIT(instr, 21);
|
|
||||||
|
|
||||||
/* TODO check access permission */
|
|
||||||
|
|
||||||
/* VSTM */
|
|
||||||
if ( (P|U|D|W) == 0 ) {
|
|
||||||
LOG_ERROR(Core_ARM11, "In %s, UNDEFINED\n", __FUNCTION__);
|
|
||||||
exit(-1);
|
|
||||||
}
|
|
||||||
if (CoProc == 10 || CoProc == 11) {
|
|
||||||
#if 1
|
|
||||||
if (P == 0 && U == 0 && W == 0) {
|
|
||||||
LOG_ERROR(Core_ARM11, "VSTM Related encodings\n");
|
|
||||||
exit(-1);
|
|
||||||
}
|
|
||||||
if (P == U && W == 1) {
|
|
||||||
LOG_ERROR(Core_ARM11, "UNDEFINED\n");
|
|
||||||
exit(-1);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
if (P == 1 && W == 0)
|
|
||||||
{
|
|
||||||
return VSTR(state, type, instr, value);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (P == 1 && U == 0 && W == 1 && Rn == 0xD)
|
|
||||||
{
|
|
||||||
return VPUSH(state, type, instr, value);
|
|
||||||
}
|
|
||||||
|
|
||||||
return VSTM(state, type, instr, value);
|
|
||||||
}
|
|
||||||
LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n",
|
|
||||||
instr, CoProc, CRd, Rn, imm8, P, U, D, W);
|
|
||||||
|
|
||||||
return ARMul_CANT;
|
|
||||||
}
|
|
||||||
|
|
||||||
unsigned VFPLDC(ARMul_State* state, unsigned type, u32 instr, u32 value)
|
|
||||||
{
|
|
||||||
/* LDC{L}<c> <coproc>,<CRd>,[<Rn>] */
|
|
||||||
int CoProc = BITS(instr, 8, 11); /* 10 or 11 */
|
|
||||||
int CRd = BITS(instr, 12, 15);
|
|
||||||
int Rn = BITS(instr, 16, 19);
|
|
||||||
int imm8 = BITS(instr, 0, 7);
|
|
||||||
int P = BIT(instr, 24);
|
|
||||||
int U = BIT(instr, 23);
|
|
||||||
int D = BIT(instr, 22);
|
|
||||||
int W = BIT(instr, 21);
|
|
||||||
|
|
||||||
/* TODO check access permission */
|
|
||||||
|
|
||||||
if ( (P|U|D|W) == 0 ) {
|
|
||||||
LOG_ERROR(Core_ARM11, "In %s, UNDEFINED\n", __FUNCTION__);
|
|
||||||
exit(-1);
|
|
||||||
}
|
|
||||||
if (CoProc == 10 || CoProc == 11)
|
|
||||||
{
|
|
||||||
if (P == 1 && W == 0)
|
|
||||||
{
|
|
||||||
return VLDR(state, type, instr, value);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (P == 0 && U == 1 && W == 1 && Rn == 0xD)
|
|
||||||
{
|
|
||||||
return VPOP(state, type, instr, value);
|
|
||||||
}
|
|
||||||
|
|
||||||
return VLDM(state, type, instr, value);
|
|
||||||
}
|
|
||||||
LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n",
|
|
||||||
instr, CoProc, CRd, Rn, imm8, P, U, D, W);
|
|
||||||
|
|
||||||
return ARMul_CANT;
|
|
||||||
}
|
|
||||||
|
|
||||||
unsigned VFPCDP(ARMul_State* state, unsigned type, u32 instr)
|
|
||||||
{
|
|
||||||
/* CDP<c> <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2> */
|
|
||||||
int CoProc = BITS(instr, 8, 11); /* 10 or 11 */
|
|
||||||
int OPC_1 = BITS(instr, 20, 23);
|
|
||||||
int CRd = BITS(instr, 12, 15);
|
|
||||||
int CRn = BITS(instr, 16, 19);
|
|
||||||
int CRm = BITS(instr, 0, 3);
|
|
||||||
int OPC_2 = BITS(instr, 5, 7);
|
|
||||||
|
|
||||||
/* TODO check access permission */
|
|
||||||
|
|
||||||
/* CRn/opc1 CRm/opc2 */
|
|
||||||
|
|
||||||
if (CoProc == 10 || CoProc == 11)
|
|
||||||
{
|
|
||||||
if ((OPC_1 & 0xB) == 0xB && BITS(instr, 4, 7) == 0)
|
|
||||||
{
|
|
||||||
unsigned int single = BIT(instr, 8) == 0;
|
|
||||||
unsigned int d = (single ? BITS(instr, 12,15)<<1 | BIT(instr, 22) : BITS(instr, 12,15) | BIT(instr, 22)<<4);
|
|
||||||
unsigned int imm;
|
|
||||||
instr = BITS(instr, 16, 19) << 4 | BITS(instr, 0, 3); // FIXME dirty workaround to get a correct imm
|
|
||||||
|
|
||||||
if (single)
|
|
||||||
imm = BIT(instr, 7)<<31 | (BIT(instr, 6)==0)<<30 | (BIT(instr, 6) ? 0x1f : 0)<<25 | BITS(instr, 0, 5)<<19;
|
|
||||||
else
|
|
||||||
imm = BIT(instr, 7)<<31 | (BIT(instr, 6)==0)<<30 | (BIT(instr, 6) ? 0xff : 0)<<22 | BITS(instr, 0, 5)<<16;
|
|
||||||
|
|
||||||
VMOVI(state, single, d, imm);
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
|
|
||||||
if ((OPC_1 & 0xB) == 0xB && CRn == 0 && (OPC_2 & 0x6) == 0x2)
|
|
||||||
{
|
|
||||||
unsigned int single = BIT(instr, 8) == 0;
|
|
||||||
unsigned int d = (single ? BITS(instr, 12,15)<<1 | BIT(instr, 22) : BITS(instr, 12,15) | BIT(instr, 22)<<4);
|
|
||||||
unsigned int m = (single ? BITS(instr, 0, 3)<<1 | BIT(instr, 5) : BITS(instr, 0, 3) | BIT(instr, 5)<<4);
|
|
||||||
VMOVR(state, single, d, m);
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
|
|
||||||
int exceptions = 0;
|
|
||||||
if (CoProc == 10)
|
|
||||||
exceptions = vfp_single_cpdo(state, instr, state->VFP[VFP_FPSCR]);
|
|
||||||
else
|
|
||||||
exceptions = vfp_double_cpdo(state, instr, state->VFP[VFP_FPSCR]);
|
|
||||||
|
|
||||||
vfp_raise_exceptions(state, exceptions, instr, state->VFP[VFP_FPSCR]);
|
|
||||||
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
LOG_WARNING(Core_ARM11, "Can't identify %x\n", instr);
|
|
||||||
return ARMul_CANT;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* ----------- MRC ------------ */
|
|
||||||
void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword* value)
|
void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword* value)
|
||||||
{
|
{
|
||||||
if (to_arm)
|
if (to_arm)
|
||||||
|
|
@ -338,43 +60,7 @@ void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword*
|
||||||
state->ExtReg[n] = *value;
|
state->ExtReg[n] = *value;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
void VMRS(ARMul_State* state, ARMword reg, ARMword Rt, ARMword* value)
|
|
||||||
{
|
|
||||||
if (reg == 1)
|
|
||||||
{
|
|
||||||
if (Rt != 15)
|
|
||||||
{
|
|
||||||
*value = state->VFP[VFP_FPSCR];
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
*value = state->VFP[VFP_FPSCR] ;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
switch (reg)
|
|
||||||
{
|
|
||||||
case 0:
|
|
||||||
*value = state->VFP[VFP_FPSID];
|
|
||||||
break;
|
|
||||||
case 6:
|
|
||||||
/* MVFR1, VFPv3 only ? */
|
|
||||||
LOG_TRACE(Core_ARM11, "\tr%d <= MVFR1 unimplemented\n", Rt);
|
|
||||||
break;
|
|
||||||
case 7:
|
|
||||||
/* MVFR0, VFPv3 only? */
|
|
||||||
LOG_TRACE(Core_ARM11, "\tr%d <= MVFR0 unimplemented\n", Rt);
|
|
||||||
break;
|
|
||||||
case 8:
|
|
||||||
*value = state->VFP[VFP_FPEXC];
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
LOG_TRACE(Core_ARM11, "\tSUBARCHITECTURE DEFINED\n");
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2)
|
void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2)
|
||||||
{
|
{
|
||||||
if (to_arm)
|
if (to_arm)
|
||||||
|
|
@ -402,301 +88,6 @@ void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMwor
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/* ----------- MCR ------------ */
|
|
||||||
void VMSR(ARMul_State* state, ARMword reg, ARMword Rt)
|
|
||||||
{
|
|
||||||
if (reg == 1)
|
|
||||||
{
|
|
||||||
state->VFP[VFP_FPSCR] = state->Reg[Rt];
|
|
||||||
}
|
|
||||||
else if (reg == 8)
|
|
||||||
{
|
|
||||||
state->VFP[VFP_FPEXC] = state->Reg[Rt];
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Memory operation are not inlined, as old Interpreter and Fast interpreter
|
|
||||||
don't have the same memory operation interface.
|
|
||||||
Old interpreter framework does one access to coprocessor per data, and
|
|
||||||
handles already data write, as well as address computation,
|
|
||||||
which is not the case for Fast interpreter. Therefore, implementation
|
|
||||||
of vfp instructions in old interpreter and fast interpreter are separate. */
|
|
||||||
|
|
||||||
/* ----------- STC ------------ */
|
|
||||||
int VSTR(ARMul_State* state, int type, ARMword instr, ARMword* value)
|
|
||||||
{
|
|
||||||
static int i = 0;
|
|
||||||
static int single_reg, add, d, n, imm32, regs;
|
|
||||||
if (type == ARMul_FIRST)
|
|
||||||
{
|
|
||||||
single_reg = BIT(instr, 8) == 0; // Double precision
|
|
||||||
add = BIT(instr, 23);
|
|
||||||
imm32 = BITS(instr, 0,7)<<2; // may not be used
|
|
||||||
d = single_reg ? BITS(instr, 12, 15)<<1|BIT(instr, 22) : BIT(instr, 22)<<4|BITS(instr, 12, 15); /* Base register */
|
|
||||||
n = BITS(instr, 16, 19); // destination register
|
|
||||||
|
|
||||||
i = 0;
|
|
||||||
regs = 1;
|
|
||||||
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
else if (type == ARMul_DATA)
|
|
||||||
{
|
|
||||||
if (single_reg)
|
|
||||||
{
|
|
||||||
*value = state->ExtReg[d+i];
|
|
||||||
i++;
|
|
||||||
if (i < regs)
|
|
||||||
return ARMul_INC;
|
|
||||||
else
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* FIXME Careful of endianness, may need to rework this */
|
|
||||||
*value = state->ExtReg[d*2+i];
|
|
||||||
i++;
|
|
||||||
if (i < regs*2)
|
|
||||||
return ARMul_INC;
|
|
||||||
else
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
int VPUSH(ARMul_State* state, int type, ARMword instr, ARMword* value)
|
|
||||||
{
|
|
||||||
static int i = 0;
|
|
||||||
static int single_regs, d, imm32, regs;
|
|
||||||
if (type == ARMul_FIRST)
|
|
||||||
{
|
|
||||||
single_regs = BIT(instr, 8) == 0; // Single precision
|
|
||||||
d = single_regs ? BITS(instr, 12, 15)<<1|BIT(instr, 22) : BIT(instr, 22)<<4|BITS(instr, 12, 15); // Base register
|
|
||||||
imm32 = BITS(instr, 0,7)<<2; // may not be used
|
|
||||||
regs = single_regs ? BITS(instr, 0, 7) : BITS(instr, 1, 7); // FSTMX if regs is odd
|
|
||||||
|
|
||||||
state->Reg[R13] = state->Reg[R13] - imm32;
|
|
||||||
|
|
||||||
i = 0;
|
|
||||||
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
else if (type == ARMul_DATA)
|
|
||||||
{
|
|
||||||
if (single_regs)
|
|
||||||
{
|
|
||||||
*value = state->ExtReg[d + i];
|
|
||||||
i++;
|
|
||||||
if (i < regs)
|
|
||||||
return ARMul_INC;
|
|
||||||
else
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* FIXME Careful of endianness, may need to rework this */
|
|
||||||
*value = state->ExtReg[d*2 + i];
|
|
||||||
i++;
|
|
||||||
if (i < regs*2)
|
|
||||||
return ARMul_INC;
|
|
||||||
else
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
int VSTM(ARMul_State* state, int type, ARMword instr, ARMword* value)
|
|
||||||
{
|
|
||||||
static int i = 0;
|
|
||||||
static int single_regs, add, wback, d, n, imm32, regs;
|
|
||||||
if (type == ARMul_FIRST)
|
|
||||||
{
|
|
||||||
single_regs = BIT(instr, 8) == 0; // Single precision
|
|
||||||
add = BIT(instr, 23);
|
|
||||||
wback = BIT(instr, 21); // write-back
|
|
||||||
d = single_regs ? BITS(instr, 12, 15)<<1|BIT(instr, 22) : BIT(instr, 22)<<4|BITS(instr, 12, 15); // Base register
|
|
||||||
n = BITS(instr, 16, 19); // destination register
|
|
||||||
imm32 = BITS(instr, 0,7) * 4; // may not be used
|
|
||||||
regs = single_regs ? BITS(instr, 0, 7) : BITS(instr, 0, 7)>>1; // FSTMX if regs is odd
|
|
||||||
|
|
||||||
if (wback) {
|
|
||||||
state->Reg[n] = (add ? state->Reg[n] + imm32 : state->Reg[n] - imm32);
|
|
||||||
}
|
|
||||||
|
|
||||||
i = 0;
|
|
||||||
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
else if (type == ARMul_DATA)
|
|
||||||
{
|
|
||||||
if (single_regs)
|
|
||||||
{
|
|
||||||
*value = state->ExtReg[d + i];
|
|
||||||
i++;
|
|
||||||
if (i < regs)
|
|
||||||
return ARMul_INC;
|
|
||||||
else
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* FIXME Careful of endianness, may need to rework this */
|
|
||||||
*value = state->ExtReg[d*2 + i];
|
|
||||||
i++;
|
|
||||||
if (i < regs*2)
|
|
||||||
return ARMul_INC;
|
|
||||||
else
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* ----------- LDC ------------ */
|
|
||||||
int VPOP(ARMul_State* state, int type, ARMword instr, ARMword value)
|
|
||||||
{
|
|
||||||
static int i = 0;
|
|
||||||
static int single_regs, d, imm32, regs;
|
|
||||||
if (type == ARMul_FIRST)
|
|
||||||
{
|
|
||||||
single_regs = BIT(instr, 8) == 0; // Single precision
|
|
||||||
d = single_regs ? BITS(instr, 12, 15)<<1|BIT(instr, 22) : BIT(instr, 22)<<4|BITS(instr, 12, 15); // Base register
|
|
||||||
imm32 = BITS(instr, 0, 7)<<2; // may not be used
|
|
||||||
regs = single_regs ? BITS(instr, 0, 7) : BITS(instr, 1, 7); // FLDMX if regs is odd
|
|
||||||
|
|
||||||
state->Reg[R13] = state->Reg[R13] + imm32;
|
|
||||||
|
|
||||||
i = 0;
|
|
||||||
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
else if (type == ARMul_TRANSFER)
|
|
||||||
{
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
else if (type == ARMul_DATA)
|
|
||||||
{
|
|
||||||
if (single_regs)
|
|
||||||
{
|
|
||||||
state->ExtReg[d + i] = value;
|
|
||||||
i++;
|
|
||||||
if (i < regs)
|
|
||||||
return ARMul_INC;
|
|
||||||
else
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* FIXME Careful of endianness, may need to rework this */
|
|
||||||
state->ExtReg[d*2 + i] = value;
|
|
||||||
i++;
|
|
||||||
if (i < regs*2)
|
|
||||||
return ARMul_INC;
|
|
||||||
else
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
int VLDR(ARMul_State* state, int type, ARMword instr, ARMword value)
|
|
||||||
{
|
|
||||||
static int i = 0;
|
|
||||||
static int single_reg, add, d, n, imm32, regs;
|
|
||||||
if (type == ARMul_FIRST)
|
|
||||||
{
|
|
||||||
single_reg = BIT(instr, 8) == 0; // Double precision
|
|
||||||
add = BIT(instr, 23);
|
|
||||||
imm32 = BITS(instr, 0, 7)<<2; // may not be used
|
|
||||||
d = single_reg ? BITS(instr, 12, 15)<<1|BIT(instr, 22) : BIT(instr, 22)<<4|BITS(instr, 12, 15); // Base register
|
|
||||||
n = BITS(instr, 16, 19); // destination register
|
|
||||||
|
|
||||||
i = 0;
|
|
||||||
regs = 1;
|
|
||||||
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
else if (type == ARMul_TRANSFER)
|
|
||||||
{
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
else if (type == ARMul_DATA)
|
|
||||||
{
|
|
||||||
if (single_reg)
|
|
||||||
{
|
|
||||||
state->ExtReg[d+i] = value;
|
|
||||||
i++;
|
|
||||||
if (i < regs)
|
|
||||||
return ARMul_INC;
|
|
||||||
else
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* FIXME Careful of endianness, may need to rework this */
|
|
||||||
state->ExtReg[d*2+i] = value;
|
|
||||||
i++;
|
|
||||||
if (i < regs*2)
|
|
||||||
return ARMul_INC;
|
|
||||||
else
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
int VLDM(ARMul_State* state, int type, ARMword instr, ARMword value)
|
|
||||||
{
|
|
||||||
static int i = 0;
|
|
||||||
static int single_regs, add, wback, d, n, imm32, regs;
|
|
||||||
if (type == ARMul_FIRST)
|
|
||||||
{
|
|
||||||
single_regs = BIT(instr, 8) == 0; // Single precision
|
|
||||||
add = BIT(instr, 23);
|
|
||||||
wback = BIT(instr, 21); // write-back
|
|
||||||
d = single_regs ? BITS(instr, 12, 15)<<1|BIT(instr, 22) : BIT(instr, 22)<<4|BITS(instr, 12, 15); // Base register
|
|
||||||
n = BITS(instr, 16, 19); // destination register
|
|
||||||
imm32 = BITS(instr, 0, 7) * 4; // may not be used
|
|
||||||
regs = single_regs ? BITS(instr, 0, 7) : BITS(instr, 0, 7)>>1; // FLDMX if regs is odd
|
|
||||||
|
|
||||||
if (wback) {
|
|
||||||
state->Reg[n] = (add ? state->Reg[n] + imm32 : state->Reg[n] - imm32);
|
|
||||||
}
|
|
||||||
|
|
||||||
i = 0;
|
|
||||||
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
else if (type == ARMul_DATA)
|
|
||||||
{
|
|
||||||
if (single_regs)
|
|
||||||
{
|
|
||||||
state->ExtReg[d + i] = value;
|
|
||||||
i++;
|
|
||||||
if (i < regs)
|
|
||||||
return ARMul_INC;
|
|
||||||
else
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* FIXME Careful of endianness, may need to rework this */
|
|
||||||
state->ExtReg[d*2 + i] = value;
|
|
||||||
i++;
|
|
||||||
if (i < regs*2)
|
|
||||||
return ARMul_INC;
|
|
||||||
else
|
|
||||||
return ARMul_DONE;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* ----------- CDP ------------ */
|
|
||||||
void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm)
|
void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm)
|
||||||
{
|
{
|
||||||
if (single)
|
if (single)
|
||||||
|
|
|
||||||
|
|
@ -28,13 +28,6 @@
|
||||||
#define CHECK_VFP_CDP_RET vfp_raise_exceptions(cpu, ret, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
|
#define CHECK_VFP_CDP_RET vfp_raise_exceptions(cpu, ret, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
|
||||||
|
|
||||||
unsigned VFPInit(ARMul_State* state);
|
unsigned VFPInit(ARMul_State* state);
|
||||||
unsigned VFPMRC(ARMul_State* state, unsigned type, ARMword instr, ARMword* value);
|
|
||||||
unsigned VFPMCR(ARMul_State* state, unsigned type, ARMword instr, ARMword value);
|
|
||||||
unsigned VFPMRRC(ARMul_State* state, unsigned type, ARMword instr, ARMword* value1, ARMword* value2);
|
|
||||||
unsigned VFPMCRR(ARMul_State* state, unsigned type, ARMword instr, ARMword value1, ARMword value2);
|
|
||||||
unsigned VFPSTC(ARMul_State* state, unsigned type, ARMword instr, ARMword* value);
|
|
||||||
unsigned VFPLDC(ARMul_State* state, unsigned type, ARMword instr, ARMword value);
|
|
||||||
unsigned VFPCDP(ARMul_State* state, unsigned type, ARMword instr);
|
|
||||||
|
|
||||||
s32 vfp_get_float(ARMul_State* state, u32 reg);
|
s32 vfp_get_float(ARMul_State* state, u32 reg);
|
||||||
void vfp_put_float(ARMul_State* state, s32 val, u32 reg);
|
void vfp_put_float(ARMul_State* state, s32 val, u32 reg);
|
||||||
|
|
@ -44,23 +37,10 @@ void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpsc
|
||||||
u32 vfp_single_cpdo(ARMul_State* state, u32 inst, u32 fpscr);
|
u32 vfp_single_cpdo(ARMul_State* state, u32 inst, u32 fpscr);
|
||||||
u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr);
|
u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr);
|
||||||
|
|
||||||
// MRC
|
void VMSR(ARMul_State* state, ARMword reg, ARMword Rt);
|
||||||
void VMRS(ARMul_State* state, ARMword reg, ARMword Rt, ARMword* value);
|
|
||||||
void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword* value);
|
void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword* value);
|
||||||
void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2);
|
void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2);
|
||||||
void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2);
|
void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2);
|
||||||
void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm);
|
void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm);
|
||||||
void VMOVR(ARMul_State* state, ARMword single, ARMword d, ARMword imm);
|
void VMOVR(ARMul_State* state, ARMword single, ARMword d, ARMword imm);
|
||||||
|
|
||||||
// MCR
|
|
||||||
void VMSR(ARMul_State* state, ARMword reg, ARMword Rt);
|
|
||||||
|
|
||||||
// STC
|
|
||||||
int VSTM(ARMul_State* state, int type, ARMword instr, ARMword* value);
|
|
||||||
int VPUSH(ARMul_State* state, int type, ARMword instr, ARMword* value);
|
|
||||||
int VSTR(ARMul_State* state, int type, ARMword instr, ARMword* value);
|
|
||||||
|
|
||||||
// LDC
|
|
||||||
int VLDM(ARMul_State* state, int type, ARMword instr, ARMword value);
|
|
||||||
int VPOP(ARMul_State* state, int type, ARMword instr, ARMword value);
|
|
||||||
int VLDR(ARMul_State* state, int type, ARMword instr, ARMword value);
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue