mirror of https://git.suyu.dev/suyu/suyu
vk_pipeline_cache: Initial implementation
Given a pipeline key, this cache returns a pipeline abstraction (for graphics or compute).
This commit is contained in:
ReinUsesLisp
parent
2effdeb924
commit
6888d776ff
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@ -2,16 +2,368 @@
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <algorithm>
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#include <cstddef>
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#include <memory>
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#include <vector>
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#include "common/microprofile.h"
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#include "core/core.h"
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#include "core/memory.h"
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#include "video_core/engines/kepler_compute.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/memory_manager.h"
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#include "video_core/renderer_vulkan/declarations.h"
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#include "video_core/renderer_vulkan/fixed_pipeline_state.h"
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#include "video_core/renderer_vulkan/maxwell_to_vk.h"
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#include "video_core/renderer_vulkan/vk_compute_pipeline.h"
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#include "video_core/renderer_vulkan/vk_descriptor_pool.h"
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#include "video_core/renderer_vulkan/vk_device.h"
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#include "video_core/renderer_vulkan/vk_graphics_pipeline.h"
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#include "video_core/renderer_vulkan/vk_pipeline_cache.h"
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#include "video_core/renderer_vulkan/vk_rasterizer.h"
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#include "video_core/renderer_vulkan/vk_renderpass_cache.h"
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#include "video_core/renderer_vulkan/vk_resource_manager.h"
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#include "video_core/renderer_vulkan/vk_scheduler.h"
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#include "video_core/renderer_vulkan/vk_update_descriptor.h"
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#include "video_core/shader/compiler_settings.h"
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namespace Vulkan {
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MICROPROFILE_DECLARE(Vulkan_PipelineCache);
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using Tegra::Engines::ShaderType;
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namespace {
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constexpr VideoCommon::Shader::CompilerSettings compiler_settings{
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VideoCommon::Shader::CompileDepth::FullDecompile};
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/// Gets the address for the specified shader stage program
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GPUVAddr GetShaderAddress(Core::System& system, Maxwell::ShaderProgram program) {
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const auto& gpu{system.GPU().Maxwell3D()};
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const auto& shader_config{gpu.regs.shader_config[static_cast<std::size_t>(program)]};
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return gpu.regs.code_address.CodeAddress() + shader_config.offset;
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}
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/// Gets if the current instruction offset is a scheduler instruction
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constexpr bool IsSchedInstruction(std::size_t offset, std::size_t main_offset) {
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// Sched instructions appear once every 4 instructions.
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constexpr std::size_t SchedPeriod = 4;
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const std::size_t absolute_offset = offset - main_offset;
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return (absolute_offset % SchedPeriod) == 0;
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}
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/// Calculates the size of a program stream
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std::size_t CalculateProgramSize(const ProgramCode& program, bool is_compute) {
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const std::size_t start_offset = is_compute ? 0 : 10;
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// This is the encoded version of BRA that jumps to itself. All Nvidia
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// shaders end with one.
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constexpr u64 self_jumping_branch = 0xE2400FFFFF07000FULL;
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constexpr u64 mask = 0xFFFFFFFFFF7FFFFFULL;
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std::size_t offset = start_offset;
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while (offset < program.size()) {
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const u64 instruction = program[offset];
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if (!IsSchedInstruction(offset, start_offset)) {
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if ((instruction & mask) == self_jumping_branch) {
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// End on Maxwell's "nop" instruction
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break;
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}
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if (instruction == 0) {
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break;
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}
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}
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++offset;
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}
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// The last instruction is included in the program size
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return std::min(offset + 1, program.size());
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}
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/// Gets the shader program code from memory for the specified address
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ProgramCode GetShaderCode(Tegra::MemoryManager& memory_manager, const GPUVAddr gpu_addr,
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const u8* host_ptr, bool is_compute) {
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ProgramCode program_code(VideoCommon::Shader::MAX_PROGRAM_LENGTH);
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ASSERT_OR_EXECUTE(host_ptr != nullptr, {
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std::fill(program_code.begin(), program_code.end(), 0);
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return program_code;
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});
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memory_manager.ReadBlockUnsafe(gpu_addr, program_code.data(),
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program_code.size() * sizeof(u64));
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program_code.resize(CalculateProgramSize(program_code, is_compute));
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return program_code;
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}
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constexpr std::size_t GetStageFromProgram(std::size_t program) {
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return program == 0 ? 0 : program - 1;
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}
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constexpr ShaderType GetStageFromProgram(Maxwell::ShaderProgram program) {
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return static_cast<ShaderType>(GetStageFromProgram(static_cast<std::size_t>(program)));
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}
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ShaderType GetShaderType(Maxwell::ShaderProgram program) {
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switch (program) {
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case Maxwell::ShaderProgram::VertexB:
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return ShaderType::Vertex;
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case Maxwell::ShaderProgram::TesselationControl:
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return ShaderType::TesselationControl;
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case Maxwell::ShaderProgram::TesselationEval:
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return ShaderType::TesselationEval;
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case Maxwell::ShaderProgram::Geometry:
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return ShaderType::Geometry;
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case Maxwell::ShaderProgram::Fragment:
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return ShaderType::Fragment;
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default:
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UNIMPLEMENTED_MSG("program={}", static_cast<u32>(program));
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return ShaderType::Vertex;
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}
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}
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u32 FillDescriptorLayout(const ShaderEntries& entries,
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std::vector<vk::DescriptorSetLayoutBinding>& bindings,
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Maxwell::ShaderProgram program_type, u32 base_binding) {
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const ShaderType stage = GetStageFromProgram(program_type);
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const vk::ShaderStageFlags stage_flags = MaxwellToVK::ShaderStage(stage);
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u32 binding = base_binding;
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const auto AddBindings = [&](vk::DescriptorType descriptor_type, std::size_t num_entries) {
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for (std::size_t i = 0; i < num_entries; ++i) {
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bindings.emplace_back(binding++, descriptor_type, 1, stage_flags, nullptr);
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}
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};
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AddBindings(vk::DescriptorType::eUniformBuffer, entries.const_buffers.size());
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AddBindings(vk::DescriptorType::eStorageBuffer, entries.global_buffers.size());
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AddBindings(vk::DescriptorType::eUniformTexelBuffer, entries.texel_buffers.size());
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AddBindings(vk::DescriptorType::eCombinedImageSampler, entries.samplers.size());
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AddBindings(vk::DescriptorType::eStorageImage, entries.images.size());
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return binding;
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}
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} // Anonymous namespace
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CachedShader::CachedShader(Core::System& system, Tegra::Engines::ShaderType stage,
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GPUVAddr gpu_addr, VAddr cpu_addr, u8* host_ptr,
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ProgramCode program_code, u32 main_offset)
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: RasterizerCacheObject{host_ptr}, gpu_addr{gpu_addr}, cpu_addr{cpu_addr},
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program_code{std::move(program_code)}, locker{stage, GetEngine(system, stage)},
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shader_ir{this->program_code, main_offset, compiler_settings, locker},
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entries{GenerateShaderEntries(shader_ir)} {}
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CachedShader::~CachedShader() = default;
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Tegra::Engines::ConstBufferEngineInterface& CachedShader::GetEngine(
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Core::System& system, Tegra::Engines::ShaderType stage) {
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if (stage == Tegra::Engines::ShaderType::Compute) {
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return system.GPU().KeplerCompute();
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} else {
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return system.GPU().Maxwell3D();
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}
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}
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VKPipelineCache::VKPipelineCache(Core::System& system, RasterizerVulkan& rasterizer,
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const VKDevice& device, VKScheduler& scheduler,
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VKDescriptorPool& descriptor_pool,
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VKUpdateDescriptorQueue& update_descriptor_queue)
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: RasterizerCache{rasterizer}, system{system}, device{device}, scheduler{scheduler},
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descriptor_pool{descriptor_pool}, update_descriptor_queue{update_descriptor_queue},
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renderpass_cache(device) {}
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VKPipelineCache::~VKPipelineCache() = default;
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std::array<Shader, Maxwell::MaxShaderProgram> VKPipelineCache::GetShaders() {
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const auto& gpu = system.GPU().Maxwell3D();
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auto& dirty = system.GPU().Maxwell3D().dirty.shaders;
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if (!dirty) {
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return last_shaders;
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}
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dirty = false;
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std::array<Shader, Maxwell::MaxShaderProgram> shaders;
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for (std::size_t index = 0; index < Maxwell::MaxShaderProgram; ++index) {
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const auto& shader_config = gpu.regs.shader_config[index];
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const auto program{static_cast<Maxwell::ShaderProgram>(index)};
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// Skip stages that are not enabled
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if (!gpu.regs.IsShaderConfigEnabled(index)) {
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continue;
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}
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auto& memory_manager{system.GPU().MemoryManager()};
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const GPUVAddr program_addr{GetShaderAddress(system, program)};
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const auto host_ptr{memory_manager.GetPointer(program_addr)};
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auto shader = TryGet(host_ptr);
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if (!shader) {
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// No shader found - create a new one
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constexpr u32 stage_offset = 10;
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const auto stage = static_cast<Tegra::Engines::ShaderType>(index == 0 ? 0 : index - 1);
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auto code = GetShaderCode(memory_manager, program_addr, host_ptr, false);
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const std::optional cpu_addr = memory_manager.GpuToCpuAddress(program_addr);
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ASSERT(cpu_addr);
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shader = std::make_shared<CachedShader>(system, stage, program_addr, *cpu_addr,
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host_ptr, std::move(code), stage_offset);
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Register(shader);
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}
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shaders[index] = std::move(shader);
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}
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return last_shaders = shaders;
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}
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VKGraphicsPipeline& VKPipelineCache::GetGraphicsPipeline(const GraphicsPipelineCacheKey& key) {
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MICROPROFILE_SCOPE(Vulkan_PipelineCache);
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if (last_graphics_pipeline && last_graphics_key == key) {
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return *last_graphics_pipeline;
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}
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last_graphics_key = key;
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const auto [pair, is_cache_miss] = graphics_cache.try_emplace(key);
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auto& entry = pair->second;
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if (is_cache_miss) {
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LOG_INFO(Render_Vulkan, "Compile 0x{:016X}", key.Hash());
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const auto [program, bindings] = DecompileShaders(key);
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entry = std::make_unique<VKGraphicsPipeline>(device, scheduler, descriptor_pool,
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update_descriptor_queue, renderpass_cache, key,
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bindings, program);
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}
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return *(last_graphics_pipeline = entry.get());
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}
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VKComputePipeline& VKPipelineCache::GetComputePipeline(const ComputePipelineCacheKey& key) {
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MICROPROFILE_SCOPE(Vulkan_PipelineCache);
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const auto [pair, is_cache_miss] = compute_cache.try_emplace(key);
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auto& entry = pair->second;
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if (!is_cache_miss) {
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return *entry;
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}
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LOG_INFO(Render_Vulkan, "Compile 0x{:016X}", key.Hash());
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auto& memory_manager = system.GPU().MemoryManager();
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const auto program_addr = key.shader;
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const auto host_ptr = memory_manager.GetPointer(program_addr);
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auto shader = TryGet(host_ptr);
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if (!shader) {
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// No shader found - create a new one
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const auto cpu_addr = memory_manager.GpuToCpuAddress(program_addr);
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ASSERT(cpu_addr);
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auto code = GetShaderCode(memory_manager, program_addr, host_ptr, true);
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constexpr u32 kernel_main_offset = 0;
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shader = std::make_shared<CachedShader>(system, Tegra::Engines::ShaderType::Compute,
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program_addr, *cpu_addr, host_ptr, std::move(code),
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kernel_main_offset);
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Register(shader);
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}
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Specialization specialization;
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specialization.workgroup_size = key.workgroup_size;
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specialization.shared_memory_size = key.shared_memory_size;
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const SPIRVShader spirv_shader{
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Decompile(device, shader->GetIR(), ShaderType::Compute, specialization),
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shader->GetEntries()};
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entry = std::make_unique<VKComputePipeline>(device, scheduler, descriptor_pool,
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update_descriptor_queue, spirv_shader);
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return *entry;
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}
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void VKPipelineCache::Unregister(const Shader& shader) {
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bool finished = false;
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const auto Finish = [&] {
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// TODO(Rodrigo): Instead of finishing here, wait for the fences that use this pipeline and
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// flush.
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if (finished) {
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return;
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}
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finished = true;
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scheduler.Finish();
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};
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const GPUVAddr invalidated_addr = shader->GetGpuAddr();
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for (auto it = graphics_cache.begin(); it != graphics_cache.end();) {
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auto& entry = it->first;
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if (std::find(entry.shaders.begin(), entry.shaders.end(), invalidated_addr) ==
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entry.shaders.end()) {
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++it;
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continue;
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}
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Finish();
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it = graphics_cache.erase(it);
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}
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for (auto it = compute_cache.begin(); it != compute_cache.end();) {
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auto& entry = it->first;
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if (entry.shader != invalidated_addr) {
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++it;
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continue;
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}
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Finish();
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it = compute_cache.erase(it);
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}
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RasterizerCache::Unregister(shader);
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}
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std::pair<SPIRVProgram, std::vector<vk::DescriptorSetLayoutBinding>>
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VKPipelineCache::DecompileShaders(const GraphicsPipelineCacheKey& key) {
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const auto& fixed_state = key.fixed_state;
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auto& memory_manager = system.GPU().MemoryManager();
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const auto& gpu = system.GPU().Maxwell3D();
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Specialization specialization;
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specialization.primitive_topology = fixed_state.input_assembly.topology;
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if (specialization.primitive_topology == Maxwell::PrimitiveTopology::Points) {
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ASSERT(fixed_state.input_assembly.point_size != 0.0f);
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specialization.point_size = fixed_state.input_assembly.point_size;
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}
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for (std::size_t i = 0; i < Maxwell::NumVertexAttributes; ++i) {
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specialization.attribute_types[i] = fixed_state.vertex_input.attributes[i].type;
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}
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specialization.ndc_minus_one_to_one = fixed_state.rasterizer.ndc_minus_one_to_one;
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specialization.tessellation.primitive = fixed_state.tessellation.primitive;
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specialization.tessellation.spacing = fixed_state.tessellation.spacing;
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specialization.tessellation.clockwise = fixed_state.tessellation.clockwise;
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for (const auto& rt : key.renderpass_params.color_attachments) {
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specialization.enabled_rendertargets.set(rt.index);
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}
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SPIRVProgram program;
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std::vector<vk::DescriptorSetLayoutBinding> bindings;
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for (std::size_t index = 0; index < Maxwell::MaxShaderProgram; ++index) {
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const auto program_enum = static_cast<Maxwell::ShaderProgram>(index);
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// Skip stages that are not enabled
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if (!gpu.regs.IsShaderConfigEnabled(index)) {
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continue;
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}
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const GPUVAddr gpu_addr = GetShaderAddress(system, program_enum);
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const auto host_ptr = memory_manager.GetPointer(gpu_addr);
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const auto shader = TryGet(host_ptr);
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ASSERT(shader);
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const std::size_t stage = index == 0 ? 0 : index - 1; // Stage indices are 0 - 5
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const auto program_type = GetShaderType(program_enum);
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const auto& entries = shader->GetEntries();
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program[stage] = {Decompile(device, shader->GetIR(), program_type, specialization),
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entries};
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if (program_enum == Maxwell::ShaderProgram::VertexA) {
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// VertexB was combined with VertexA, so we skip the VertexB iteration
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++index;
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}
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const u32 old_binding = specialization.base_binding;
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specialization.base_binding =
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FillDescriptorLayout(entries, bindings, program_enum, specialization.base_binding);
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ASSERT(old_binding + entries.NumBindings() == specialization.base_binding);
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}
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return {std::move(program), std::move(bindings)};
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}
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void FillDescriptorUpdateTemplateEntries(
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const VKDevice& device, const ShaderEntries& entries, u32& binding, u32& offset,
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std::vector<vk::DescriptorUpdateTemplateEntry>& template_entries) {
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@ -6,23 +6,49 @@
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#include <array>
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#include <cstddef>
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#include <memory>
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#include <tuple>
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#include <type_traits>
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#include <unordered_map>
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#include <utility>
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#include <vector>
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#include <boost/functional/hash.hpp>
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#include "common/common_types.h"
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#include "video_core/engines/const_buffer_engine_interface.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/rasterizer_cache.h"
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#include "video_core/renderer_vulkan/declarations.h"
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#include "video_core/renderer_vulkan/fixed_pipeline_state.h"
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#include "video_core/renderer_vulkan/vk_graphics_pipeline.h"
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#include "video_core/renderer_vulkan/vk_renderpass_cache.h"
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#include "video_core/renderer_vulkan/vk_resource_manager.h"
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#include "video_core/renderer_vulkan/vk_shader_decompiler.h"
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#include "video_core/shader/const_buffer_locker.h"
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#include "video_core/shader/shader_ir.h"
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#include "video_core/surface.h"
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namespace Core {
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class System;
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}
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namespace Vulkan {
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class RasterizerVulkan;
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class VKComputePipeline;
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class VKDescriptorPool;
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class VKDevice;
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class VKFence;
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class VKScheduler;
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class VKUpdateDescriptorQueue;
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class CachedShader;
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using Shader = std::shared_ptr<CachedShader>;
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using Maxwell = Tegra::Engines::Maxwell3D::Regs;
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using ProgramCode = std::vector<u64>;
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struct GraphicsPipelineCacheKey {
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FixedPipelineState fixed_state;
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std::array<GPUVAddr, Maxwell::MaxShaderProgram> shaders;
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@ -84,7 +110,88 @@ struct hash<Vulkan::ComputePipelineCacheKey> {
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namespace Vulkan {
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class VKDevice;
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class CachedShader final : public RasterizerCacheObject {
|
||||
public:
|
||||
explicit CachedShader(Core::System& system, Tegra::Engines::ShaderType stage, GPUVAddr gpu_addr,
|
||||
VAddr cpu_addr, u8* host_ptr, ProgramCode program_code, u32 main_offset);
|
||||
~CachedShader();
|
||||
|
||||
GPUVAddr GetGpuAddr() const {
|
||||
return gpu_addr;
|
||||
}
|
||||
|
||||
VAddr GetCpuAddr() const override {
|
||||
return cpu_addr;
|
||||
}
|
||||
|
||||
std::size_t GetSizeInBytes() const override {
|
||||
return program_code.size() * sizeof(u64);
|
||||
}
|
||||
|
||||
VideoCommon::Shader::ShaderIR& GetIR() {
|
||||
return shader_ir;
|
||||
}
|
||||
|
||||
const VideoCommon::Shader::ShaderIR& GetIR() const {
|
||||
return shader_ir;
|
||||
}
|
||||
|
||||
const ShaderEntries& GetEntries() const {
|
||||
return entries;
|
||||
}
|
||||
|
||||
private:
|
||||
static Tegra::Engines::ConstBufferEngineInterface& GetEngine(Core::System& system,
|
||||
Tegra::Engines::ShaderType stage);
|
||||
|
||||
GPUVAddr gpu_addr{};
|
||||
VAddr cpu_addr{};
|
||||
ProgramCode program_code;
|
||||
VideoCommon::Shader::ConstBufferLocker locker;
|
||||
VideoCommon::Shader::ShaderIR shader_ir;
|
||||
ShaderEntries entries;
|
||||
};
|
||||
|
||||
class VKPipelineCache final : public RasterizerCache<Shader> {
|
||||
public:
|
||||
explicit VKPipelineCache(Core::System& system, RasterizerVulkan& rasterizer,
|
||||
const VKDevice& device, VKScheduler& scheduler,
|
||||
VKDescriptorPool& descriptor_pool,
|
||||
VKUpdateDescriptorQueue& update_descriptor_queue);
|
||||
~VKPipelineCache();
|
||||
|
||||
std::array<Shader, Maxwell::MaxShaderProgram> GetShaders();
|
||||
|
||||
VKGraphicsPipeline& GetGraphicsPipeline(const GraphicsPipelineCacheKey& key);
|
||||
|
||||
VKComputePipeline& GetComputePipeline(const ComputePipelineCacheKey& key);
|
||||
|
||||
protected:
|
||||
void Unregister(const Shader& shader) override;
|
||||
|
||||
void FlushObjectInner(const Shader& object) override {}
|
||||
|
||||
private:
|
||||
std::pair<SPIRVProgram, std::vector<vk::DescriptorSetLayoutBinding>> DecompileShaders(
|
||||
const GraphicsPipelineCacheKey& key);
|
||||
|
||||
Core::System& system;
|
||||
const VKDevice& device;
|
||||
VKScheduler& scheduler;
|
||||
VKDescriptorPool& descriptor_pool;
|
||||
VKUpdateDescriptorQueue& update_descriptor_queue;
|
||||
|
||||
VKRenderPassCache renderpass_cache;
|
||||
|
||||
std::array<Shader, Maxwell::MaxShaderProgram> last_shaders;
|
||||
|
||||
GraphicsPipelineCacheKey last_graphics_key;
|
||||
VKGraphicsPipeline* last_graphics_pipeline = nullptr;
|
||||
|
||||
std::unordered_map<GraphicsPipelineCacheKey, std::unique_ptr<VKGraphicsPipeline>>
|
||||
graphics_cache;
|
||||
std::unordered_map<ComputePipelineCacheKey, std::unique_ptr<VKComputePipeline>> compute_cache;
|
||||
};
|
||||
|
||||
void FillDescriptorUpdateTemplateEntries(
|
||||
const VKDevice& device, const ShaderEntries& entries, u32& binding, u32& offset,
|
||||
|
|
|
|||
Loading…
Reference in New Issue