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shader_ir: Rename Get/SetTemporal to Get/SetTemporary 

This is more accurate in terms of describing what the functions are
actually doing. Temporal relates to time, not the setting of a temporary
itself.
This commit is contained in:
Lioncash 2019-07-16 10:31:17 -04:00
parent 44d87ff641
commit 60926ac16b
5 changed files with 36 additions and 36 deletions
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22
src/video_core/shader/decode/memory.cpp
View File

@ -95,10 +95,10 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
const Node op_b = const Node op_b =
GetConstBufferIndirect(instr.cbuf36.index, instr.cbuf36.GetOffset() + 4, index); GetConstBufferIndirect(instr.cbuf36.index, instr.cbuf36.GetOffset() + 4, index);
SetTemporal(bb, 0, op_a); SetTemporary(bb, 0, op_a);
SetTemporal(bb, 1, op_b); SetTemporary(bb, 1, op_b);
SetRegister(bb, instr.gpr0, GetTemporal(0)); SetRegister(bb, instr.gpr0, GetTemporary(0));
SetRegister(bb, instr.gpr0.Value() + 1, GetTemporal(1)); SetRegister(bb, instr.gpr0.Value() + 1, GetTemporary(1));
break; break;
} }
default: default:
@ -136,9 +136,9 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
} }
}(); }();
for (u32 i = 0; i < count; ++i) for (u32 i = 0; i < count; ++i)
SetTemporal(bb, i, GetLmem(i * 4)); SetTemporary(bb, i, GetLmem(i * 4));
for (u32 i = 0; i < count; ++i) for (u32 i = 0; i < count; ++i)
SetRegister(bb, instr.gpr0.Value() + i, GetTemporal(i)); SetRegister(bb, instr.gpr0.Value() + i, GetTemporary(i));
break; break;
} }
default: default:
@ -172,10 +172,10 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
Operation(OperationCode::UAdd, NO_PRECISE, real_address_base, it_offset); Operation(OperationCode::UAdd, NO_PRECISE, real_address_base, it_offset);
const Node gmem = MakeNode<GmemNode>(real_address, base_address, descriptor); const Node gmem = MakeNode<GmemNode>(real_address, base_address, descriptor);
SetTemporal(bb, i, gmem); SetTemporary(bb, i, gmem);
} }
for (u32 i = 0; i < count; ++i) { for (u32 i = 0; i < count; ++i) {
SetRegister(bb, instr.gpr0.Value() + i, GetTemporal(i)); SetRegister(bb, instr.gpr0.Value() + i, GetTemporary(i));
} }
break; break;
} }
@ -253,11 +253,11 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
TrackAndGetGlobalMemory(bb, instr, true); TrackAndGetGlobalMemory(bb, instr, true);
// Encode in temporary registers like this: real_base_address, {registers_to_be_written...} // Encode in temporary registers like this: real_base_address, {registers_to_be_written...}
SetTemporal(bb, 0, real_address_base); SetTemporary(bb, 0, real_address_base);
const u32 count = GetUniformTypeElementsCount(type); const u32 count = GetUniformTypeElementsCount(type);
for (u32 i = 0; i < count; ++i) { for (u32 i = 0; i < count; ++i) {
SetTemporal(bb, i + 1, GetRegister(instr.gpr0.Value() + i)); SetTemporary(bb, i + 1, GetRegister(instr.gpr0.Value() + i));
} }
for (u32 i = 0; i < count; ++i) { for (u32 i = 0; i < count; ++i) {
const Node it_offset = Immediate(i * 4); const Node it_offset = Immediate(i * 4);
@ -265,7 +265,7 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
Operation(OperationCode::UAdd, NO_PRECISE, real_address_base, it_offset); Operation(OperationCode::UAdd, NO_PRECISE, real_address_base, it_offset);
const Node gmem = MakeNode<GmemNode>(real_address, base_address, descriptor); const Node gmem = MakeNode<GmemNode>(real_address, base_address, descriptor);
bb.push_back(Operation(OperationCode::Assign, gmem, GetTemporal(i + 1))); bb.push_back(Operation(OperationCode::Assign, gmem, GetTemporary(i + 1)));
} }
break; break;
} }

26
src/video_core/shader/decode/texture.cpp
View File

@ -181,10 +181,10 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
const Node value = const Node value =
Operation(OperationCode::TextureQueryDimensions, meta, Operation(OperationCode::TextureQueryDimensions, meta,
GetRegister(instr.gpr8.Value() + (is_bindless ? 1 : 0))); GetRegister(instr.gpr8.Value() + (is_bindless ? 1 : 0)));
SetTemporal(bb, indexer++, value); SetTemporary(bb, indexer++, value);
} }
for (u32 i = 0; i < indexer; ++i) { for (u32 i = 0; i < indexer; ++i) {
SetRegister(bb, instr.gpr0.Value() + i, GetTemporal(i)); SetRegister(bb, instr.gpr0.Value() + i, GetTemporary(i));
} }
break; break;
} }
@ -238,10 +238,10 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
auto params = coords; auto params = coords;
MetaTexture meta{sampler, {}, {}, {}, {}, {}, {}, element}; MetaTexture meta{sampler, {}, {}, {}, {}, {}, {}, element};
const Node value = Operation(OperationCode::TextureQueryLod, meta, std::move(params)); const Node value = Operation(OperationCode::TextureQueryLod, meta, std::move(params));
SetTemporal(bb, indexer++, value); SetTemporary(bb, indexer++, value);
} }
for (u32 i = 0; i < indexer; ++i) { for (u32 i = 0; i < indexer; ++i) {
SetRegister(bb, instr.gpr0.Value() + i, GetTemporal(i)); SetRegister(bb, instr.gpr0.Value() + i, GetTemporary(i));
} }
break; break;
} }
@ -336,11 +336,11 @@ void ShaderIR::WriteTexInstructionFloat(NodeBlock& bb, Instruction instr, const
// Skip disabled components // Skip disabled components
continue; continue;
} }
SetTemporal(bb, dest_elem++, components[elem]); SetTemporary(bb, dest_elem++, components[elem]);
} }
// After writing values in temporals, move them to the real registers // After writing values in temporals, move them to the real registers
for (u32 i = 0; i < dest_elem; ++i) { for (u32 i = 0; i < dest_elem; ++i) {
SetRegister(bb, instr.gpr0.Value() + i, GetTemporal(i)); SetRegister(bb, instr.gpr0.Value() + i, GetTemporary(i));
} }
} }
@ -353,17 +353,17 @@ void ShaderIR::WriteTexsInstructionFloat(NodeBlock& bb, Instruction instr,
for (u32 component = 0; component < 4; ++component) { for (u32 component = 0; component < 4; ++component) {
if (!instr.texs.IsComponentEnabled(component)) if (!instr.texs.IsComponentEnabled(component))
continue; continue;
SetTemporal(bb, dest_elem++, components[component]); SetTemporary(bb, dest_elem++, components[component]);
} }
for (u32 i = 0; i < dest_elem; ++i) { for (u32 i = 0; i < dest_elem; ++i) {
if (i < 2) { if (i < 2) {
// Write the first two swizzle components to gpr0 and gpr0+1 // Write the first two swizzle components to gpr0 and gpr0+1
SetRegister(bb, instr.gpr0.Value() + i % 2, GetTemporal(i)); SetRegister(bb, instr.gpr0.Value() + i % 2, GetTemporary(i));
} else { } else {
ASSERT(instr.texs.HasTwoDestinations()); ASSERT(instr.texs.HasTwoDestinations());
// Write the rest of the swizzle components to gpr28 and gpr28+1 // Write the rest of the swizzle components to gpr28 and gpr28+1
SetRegister(bb, instr.gpr28.Value() + i % 2, GetTemporal(i)); SetRegister(bb, instr.gpr28.Value() + i % 2, GetTemporary(i));
} }
} }
} }
@ -391,11 +391,11 @@ void ShaderIR::WriteTexsInstructionHalfFloat(NodeBlock& bb, Instruction instr,
return; return;
} }
SetTemporal(bb, 0, first_value); SetTemporary(bb, 0, first_value);
SetTemporal(bb, 1, Operation(OperationCode::HPack2, values[2], values[3])); SetTemporary(bb, 1, Operation(OperationCode::HPack2, values[2], values[3]));
SetRegister(bb, instr.gpr0, GetTemporal(0)); SetRegister(bb, instr.gpr0, GetTemporary(0));
SetRegister(bb, instr.gpr28, GetTemporal(1)); SetRegister(bb, instr.gpr28, GetTemporary(1));
} }
Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type, Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type,

12
src/video_core/shader/decode/xmad.cpp
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@ -73,8 +73,8 @@ u32 ShaderIR::DecodeXmad(NodeBlock& bb, u32 pc) {
if (is_psl) { if (is_psl) {
product = Operation(OperationCode::ILogicalShiftLeft, NO_PRECISE, product, Immediate(16)); product = Operation(OperationCode::ILogicalShiftLeft, NO_PRECISE, product, Immediate(16));
} }
SetTemporal(bb, 0, product); SetTemporary(bb, 0, product);
product = GetTemporal(0); product = GetTemporary(0);
const Node original_c = op_c; const Node original_c = op_c;
const Tegra::Shader::XmadMode set_mode = mode; // Workaround to clang compile error const Tegra::Shader::XmadMode set_mode = mode; // Workaround to clang compile error
@ -98,13 +98,13 @@ u32 ShaderIR::DecodeXmad(NodeBlock& bb, u32 pc) {
} }
}(); }();
SetTemporal(bb, 1, op_c); SetTemporary(bb, 1, op_c);
op_c = GetTemporal(1); op_c = GetTemporary(1);
// TODO(Rodrigo): Use an appropiate sign for this operation // TODO(Rodrigo): Use an appropiate sign for this operation
Node sum = Operation(OperationCode::IAdd, product, op_c); Node sum = Operation(OperationCode::IAdd, product, op_c);
SetTemporal(bb, 2, sum); SetTemporary(bb, 2, sum);
sum = GetTemporal(2); sum = GetTemporary(2);
if (is_merge) { if (is_merge) {
const Node a = BitfieldExtract(sum, 0, 16); const Node a = BitfieldExtract(sum, 0, 16);
const Node b = const Node b =

4
src/video_core/shader/shader_ir.cpp
View File

@ -137,7 +137,7 @@ Node ShaderIR::GetLocalMemory(Node address) {
return MakeNode<LmemNode>(address); return MakeNode<LmemNode>(address);
} }
Node ShaderIR::GetTemporal(u32 id) { Node ShaderIR::GetTemporary(u32 id) {
return GetRegister(Register::ZeroIndex + 1 + id); return GetRegister(Register::ZeroIndex + 1 + id);
} }
@ -373,7 +373,7 @@ void ShaderIR::SetLocalMemory(NodeBlock& bb, Node address, Node value) {
bb.push_back(Operation(OperationCode::Assign, GetLocalMemory(address), value)); bb.push_back(Operation(OperationCode::Assign, GetLocalMemory(address), value));
} }
void ShaderIR::SetTemporal(NodeBlock& bb, u32 id, Node value) { void ShaderIR::SetTemporary(NodeBlock& bb, u32 id, Node value) {
SetRegister(bb, Register::ZeroIndex + 1 + id, value); SetRegister(bb, Register::ZeroIndex + 1 + id, value);
} }

8
src/video_core/shader/shader_ir.h
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@ -207,8 +207,8 @@ private:
Node GetInternalFlag(InternalFlag flag, bool negated = false); Node GetInternalFlag(InternalFlag flag, bool negated = false);
/// Generates a node representing a local memory address /// Generates a node representing a local memory address
Node GetLocalMemory(Node address); Node GetLocalMemory(Node address);
/// Generates a temporal, internally it uses a post-RZ register /// Generates a temporary, internally it uses a post-RZ register
Node GetTemporal(u32 id); Node GetTemporary(u32 id);
/// Sets a register. src value must be a number-evaluated node. /// Sets a register. src value must be a number-evaluated node.
void SetRegister(NodeBlock& bb, Tegra::Shader::Register dest, Node src); void SetRegister(NodeBlock& bb, Tegra::Shader::Register dest, Node src);
@ -218,8 +218,8 @@ private:
void SetInternalFlag(NodeBlock& bb, InternalFlag flag, Node value); void SetInternalFlag(NodeBlock& bb, InternalFlag flag, Node value);
/// Sets a local memory address. address and value must be a number-evaluated node /// Sets a local memory address. address and value must be a number-evaluated node
void SetLocalMemory(NodeBlock& bb, Node address, Node value); void SetLocalMemory(NodeBlock& bb, Node address, Node value);
/// Sets a temporal. Internally it uses a post-RZ register /// Sets a temporary. Internally it uses a post-RZ register
void SetTemporal(NodeBlock& bb, u32 id, Node value); void SetTemporary(NodeBlock& bb, u32 id, Node value);
/// Sets internal flags from a float /// Sets internal flags from a float
void SetInternalFlagsFromFloat(NodeBlock& bb, Node value, bool sets_cc = true); void SetInternalFlagsFromFloat(NodeBlock& bb, Node value, bool sets_cc = true);