schemes that have multiples areas of RAM. Converted F4SC, F6SC, F8SC,
FASC to this new functionality.
Added ability to modify extended RAM in 3E, CV, E7 and EFSC ROMs.
Note that these ROMs can swap RAM in and out dynamically, so what
you see in the RAM area won't always be RAM.
Updated debugger CpuWidget; decimal and binary values for SP/A/X/Y
are now all shown at the same time (previously the registers had to
share a decimal/binary view).
Updated debugger documentation for recent additions.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1748 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
the debugger RAM UI. A scrollbar is now present, which can scroll
through each 128 byte 'bank'. Labels indicate the current readport,
so you can distinguish between different areas of RAM. For now,
F4SC, F6SC, F8SC, and FASC have been converted, but I'm looking into the
other schemes now.
The RAM UI takes care of all read/write port issues. From the POV of
the UI, the RAM can be treated as zero-page; translation is done
behind the scene. Searching/comparing and change-tracking are also
supported.
The 'ram' command in the debugger prompt now reflects all RAM, and
readport/writeport addresses are shown, making it easier to use the
command withot having to look up the offsets.
Debugger width has been bumped to 1050 pixels wide to accomodate the
new functionality. We'll see how much trouble this causes ...
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1747 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
stephena