Removed reference to disassembly 'SKIP' command, since it isn't implemented
yet.
Decided on Nov. 15 for the 3.3 release date, and updated all relevant files.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2181 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
Added 'ramrandom' commmandline argument, used to toggle randomizing or
zeroing or all RAM in the system (both zero-page and SARA).
Disassembler now properly supports all test cases, including rewinding
within the debugger.
Added preliminary support for disassembling from zero-page RAM.
Bumped version # for final release.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2100 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
to 'resolvedata', since that more accurately describes what it does.
Also, it now accepts arguments as strings (never, always, auto)
instead of 0, 1, 2.
Updated main documentation for changes in OSX port 'basedir'.
Updated debugger documentation for recent command additions, and
provided new snapshots where the UI has changed.
It seems to be getting close to a new release - perhaps this
coming Friday.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1999 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
schemes that have multiples areas of RAM. Converted F4SC, F6SC, F8SC,
FASC to this new functionality.
Added ability to modify extended RAM in 3E, CV, E7 and EFSC ROMs.
Note that these ROMs can swap RAM in and out dynamically, so what
you see in the RAM area won't always be RAM.
Updated debugger CpuWidget; decimal and binary values for SP/A/X/Y
are now all shown at the same time (previously the registers had to
share a decimal/binary view).
Updated debugger documentation for recent additions.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1748 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
stephena