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Removed some debugging code from 4A50 handler (thanks again to Eckhard). 

The 4A50 scheme now works on all test ROMs I have, whether or not display
autodetection is activated.

I noticed there's some graphical glitches in the various 'Ruby Runner'
demos below the lowest wall of the maze.  I'm not sure if this is a
bankswitching issue or TIA emulation problem, but I'm leaning towards the
latter.  More testing is required ...


git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1402 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
This commit is contained in:
stephena 2008-02-22 16:27:07 +00:00
parent f3c1b6308a
commit e3ee622633
1 changed files with 37 additions and 41 deletions
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78
stella/src/emucore/Cart4A50.cxx
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@ -13,7 +13,7 @@
// See the file "license" for information on usage and redistribution of // See the file "license" for information on usage and redistribution of
// this file, and for a DISCLAIMER OF ALL WARRANTIES. // this file, and for a DISCLAIMER OF ALL WARRANTIES.
// //
// $Id: Cart4A50.cxx,v 1.12 2008-02-21 23:58:09 stephena Exp $ // $Id: Cart4A50.cxx,v 1.13 2008-02-22 16:27:07 stephena Exp $
//============================================================================ //============================================================================
#include <cassert> #include <cassert>
@ -234,49 +234,45 @@ void Cartridge4A50::checkBankSwitch(uInt16 address, uInt8 value)
} }
} }
// Handle hotspots that mirror TIA or RIOT // Zero-page hotspots for upper page
if((address >= 0x80) && (address < 0x100)) // 0xf4, 0xf6, 0xfc, 0xfe for ROM
// 0xf5, 0xf7, 0xfd, 0xff for RAM
// 0x74 - 0x7f (0x80 bytes lower)
if((address & 0xf75) == 0x74) // Enable 256B of ROM at 0x1e00 - 0x1eff
{ {
// Zero-page hotspots for upper page myIsRomHigh = true;
// 0xf4, 0xf6, 0xfc, 0xfe for ROM mySliceHigh = value << 8;
// 0xf5, 0xf7, 0xfd, 0xff for RAM }
// 0x74 - 0x7f (0x80 bytes lower) else if((address & 0xf75) == 0x75) // Enable 256B of RAM at 0x1e00 - 0x1eff
if((address & 0xf75) == 0x74) // Enable 256B of ROM at 0x1e00 - 0x1eff {
{ myIsRomHigh = false;
myIsRomHigh = true; mySliceHigh = (value & 0x7f) << 8;
mySliceHigh = value << 8; }
}
else if((address & 0xf75) == 0x75) // Enable 256B of RAM at 0x1e00 - 0x1eff
{
myIsRomHigh = false;
mySliceHigh = (value & 0x7f) << 8;
}
// Zero-page hotspots for lower and middle blocks // Zero-page hotspots for lower and middle blocks
// 0xf8, 0xf9, 0xfa, 0xfb // 0xf8, 0xf9, 0xfa, 0xfb
// 0x78, 0x79, 0x7a, 0x7b (0x80 bytes lower) // 0x78, 0x79, 0x7a, 0x7b (0x80 bytes lower)
else if((address & 0xf7c) == 0x78) else if((address & 0xf7c) == 0x78)
{
if((value & 0xf0) == 0) // Enable 2K of ROM at 0x1000 - 0x17ff
{ {
if((value & 0xf0) == 0) // Enable 2K of ROM at 0x1000 - 0x17ff myIsRomLow = true;
{ mySliceLow = (value & 0xf) << 11;
myIsRomLow = true; }
mySliceLow = (value & 0xf) << 11; else if((value & 0xf0) == 0x40) // Enable 2K of RAM at 0x1000 - 0x17ff
} {
else if((value & 0xf0) == 0x40) // Enable 2K of RAM at 0x1000 - 0x17ff myIsRomLow = false;
{ mySliceLow = (value & 0xf) << 11;
myIsRomLow = false; }
mySliceLow = (value & 0xf) << 11; else if((value & 0xf0) == 0x90) // Enable 1.5K of ROM at 0x1800 - 0x1dff
} {
else if((value & 0xf0) == 0x90) // Enable 1.5K of ROM at 0x1800 - 0x1dff myIsRomMiddle = true;
{ mySliceMiddle = ((value & 0xf) | 0x10) << 11;
myIsRomMiddle = true; }
mySliceMiddle = ((value & 0xf) | 0x10) << 11; else if((value & 0xf0) == 0xc0) // Enable 1.5K of RAM at 0x1800 - 0x1dff
} {
else if((value & 0xf0) == 0xc0) // Enable 1.5K of RAM at 0x1800 - 0x1dff myIsRomMiddle = false;
{ mySliceMiddle = (value & 0xf) << 11;
myIsRomMiddle = false;
mySliceMiddle = (value & 0xf) << 11;
}
} }
} }
} }