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A little more optimization to 3E scheme.

This commit is contained in:
Stephen Anthony 2020-04-02 20:44:13 -02:30
parent 29fcc9644f
commit defeee600e
1 changed files with 19 additions and 23 deletions
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42
src/emucore/Cart3E.cxx
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@ -75,25 +75,19 @@ uInt8 Cartridge3E::peek(uInt16 address)
uInt16 peekAddress = address; uInt16 peekAddress = address;
address &= 0x0FFF; address &= 0x0FFF;
if(address < 0x0800) // Due to the way paging is set up, the only way to get here is a TIA read or
// attempting to read from the RAM write port
if(address < 0x0040) // TIA access
return mySystem->tia().peek(address);
else if(myCurrentBank >= 256)
{ {
if(myCurrentBank < 256) // Reading from the write port triggers an unwanted write
return myImage[(address & 0x07FF) + (myCurrentBank << 11)]; return peekRAM(myRAM[(address & 0x03FF) + ((myCurrentBank - 256) << 10)], peekAddress);
else
{
if(address < 0x0400)
return myRAM[(address & 0x03FF) + ((myCurrentBank - 256) << 10)];
else
{
// Reading from the write port triggers an unwanted write
return peekRAM(myRAM[(address & 0x03FF) + ((myCurrentBank - 256) << 10)], peekAddress);
}
}
}
else
{
return myImage[(address & 0x07FF) + mySize - 2048];
} }
// Make compiler happy; should never get here
return myImage[(address & 0x07FF) + mySize - 2048];
} }
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
@ -113,16 +107,17 @@ bool Cartridge3E::poke(uInt16 address, uInt8 value)
return mySystem->tia().poke(address, value); return mySystem->tia().poke(address, value);
} }
else else if(myCurrentBank >= 256)
{ {
if(address & 0x0400 && myCurrentBank >= 256) if(address & 0x0400)
{ {
pokeRAM(myRAM[(address & 0x03FF) + ((myCurrentBank - 256) << 10)], pokeAddress, value); pokeRAM(myRAM[(address & 0x03FF) + ((myCurrentBank - 256) << 10)],
pokeAddress, value);
return true; return true;
} }
else else
{ {
// Writing to the read port or to ROM should be ignored, but trigger a break if option enabled // Writing to the read port should be ignored, but trigger a break if option enabled
uInt8 dummy; uInt8 dummy;
pokeRAM(dummy, pokeAddress, value); pokeRAM(dummy, pokeAddress, value);
@ -130,6 +125,7 @@ bool Cartridge3E::poke(uInt16 address, uInt8 value)
return false; return false;
} }
} }
return false;
} }
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
@ -178,6 +174,7 @@ bool Cartridge3E::bank(uInt16 bank)
System::PageAccess access(this, System::PageAccessType::READ); System::PageAccess access(this, System::PageAccessType::READ);
// Map read-port RAM image into the system // Map read-port RAM image into the system
// Writes are mapped to poke(), to check for write to the read port
for(uInt16 addr = 0x1000; addr < 0x1400; addr += System::PAGE_SIZE) for(uInt16 addr = 0x1000; addr < 0x1400; addr += System::PAGE_SIZE)
{ {
access.directPeekBase = &myRAM[offset + (addr & 0x03FF)]; access.directPeekBase = &myRAM[offset + (addr & 0x03FF)];
@ -191,8 +188,7 @@ bool Cartridge3E::bank(uInt16 bank)
access.type = System::PageAccessType::WRITE; access.type = System::PageAccessType::WRITE;
// Map write-port RAM image into the system // Map write-port RAM image into the system
// Map access to this class, since we need to inspect all accesses to // Reads are mapped to peek(), to check for read from write port
// check if RWP happens
for(uInt16 addr = 0x1400; addr < 0x1800; addr += System::PAGE_SIZE) for(uInt16 addr = 0x1400; addr < 0x1800; addr += System::PAGE_SIZE)
{ {
access.romAccessBase = &myRomAccessBase[mySize + offset + (addr & 0x03FF)]; access.romAccessBase = &myRomAccessBase[mySize + offset + (addr & 0x03FF)];