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Fix timing to properly account for "fractional" system clocks -> bang! runs glitch free.

This commit is contained in:
Christian Speckner 2016-11-23 23:59:32 +01:00
parent cac9bf76c7
commit d2c9813da1
2 changed files with 10 additions and 3 deletions
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12
src/emucore/tia/core_6502ts/TIA.cxx
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@ -93,6 +93,7 @@ void TIA::reset()
myColorBk = 0; myColorBk = 0;
myLastCycle = 0; myLastCycle = 0;
mySubClock = 2;
myPlayfield.reset(); myPlayfield.reset();
myMissile0.reset(); myMissile0.reset();
@ -168,8 +169,9 @@ bool TIA::poke(uInt16 address, uInt8 value)
switch (address) switch (address)
{ {
case WSYNC: case WSYNC:
// TODO: Make sure that we understand the +1... :) mySubClock += (228 - myHctr) % 228;
mySystem->incrementCycles((227 - myHctr) / 3 + 1); mySystem->incrementCycles(mySubClock / 3);
mySubClock %= 3;
break; break;
case VSYNC: case VSYNC:
@ -539,8 +541,12 @@ void TIA::updateEmulation()
{ {
const uInt32 cycles = mySystem->cycles(); const uInt32 cycles = mySystem->cycles();
cycle(3 * (cycles - myLastCycle)); if (mySubClock > 2)
throw runtime_error("subclock exceeds range");
cycle(3 * (cycles - myLastCycle) + mySubClock);
mySubClock = 0;
myLastCycle = cycles; myLastCycle = cycles;
} }

1
src/emucore/tia/core_6502ts/TIA.hxx
View File

@ -181,6 +181,7 @@ class TIA : public AbstractTIA
Priority myPriority; Priority myPriority;
uInt8 mySubClock;
uInt32 myLastCycle; uInt32 myLastCycle;
uInt8 myColorBk; uInt8 myColorBk;