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some code cleanup

This commit is contained in:
Thomas Jentzsch 2022-12-02 19:51:24 +01:00
parent 6399147174
commit ccc4b6c832
1 changed files with 65 additions and 157 deletions
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222
src/emucore/Thumbulator.cxx
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@ -123,6 +123,12 @@ using Common::Base;
#define INC_ARM_CYCLES(m) #define INC_ARM_CYCLES(m)
#endif #endif
#ifdef THUMB_STATS
#define THUMB_STAT(statement) ++statement;
#else
#define THUMB_STAT(statement)
#endif
#define do_znflags(x) znFlags=(x) #define do_znflags(x) znFlags=(x)
#define do_cflag_bit(x) cFlag = (x) #define do_cflag_bit(x) cFlag = (x)
#define do_vflag_bit(x) vFlag = (x) #define do_vflag_bit(x) vFlag = (x)
@ -364,10 +370,7 @@ void Thumbulator::write16(uInt32 addr, uInt32 data)
if(addr & 1) if(addr & 1)
fatalError("write16", addr, "abort - misaligned"); fatalError("write16", addr, "abort - misaligned");
#endif #endif
#ifdef THUMB_STATS THUMB_STAT(_stats.writes)
++_stats.writes;
#endif
DO_DBUG(statusMsg << "write16(" << Base::HEX8 << addr << "," << Base::HEX8 << data << ")" << endl); DO_DBUG(statusMsg << "write16(" << Base::HEX8 << addr << "," << Base::HEX8 << data << ")" << endl);
switch(addr & 0xF0000000) switch(addr & 0xF0000000)
@ -622,9 +625,7 @@ uInt32 Thumbulator::read16(uInt32 addr)
if(addr & 1) if(addr & 1)
fatalError("read16", addr, "abort - misaligned"); fatalError("read16", addr, "abort - misaligned");
#endif #endif
#ifdef THUMB_STATS THUMB_STAT(_stats.reads)
++_stats.reads;
#endif
switch(addr & 0xF0000000) switch(addr & 0xF0000000)
{ {
@ -808,9 +809,7 @@ FORCE_INLINE void Thumbulator::write_register(uInt32 reg, uInt32 data, bool isFl
data &= ~1; data &= ~1;
if(isFlowBreak) if(isFlowBreak)
{ {
#ifdef THUMB_STATS THUMB_STAT(_stats.taken)
++_stats.taken;
#endif
// dummy fetch + fill the pipeline // dummy fetch + fill the pipeline
//INC_N_CYCLES(reg_norm[15] - 2, AccessType::prefetch); //INC_N_CYCLES(reg_norm[15] - 2, AccessType::prefetch);
//INC_S_CYCLES(data - 2, AccessType::branch); //INC_S_CYCLES(data - 2, AccessType::branch);
@ -1147,6 +1146,7 @@ FORCE_INLINE int Thumbulator::execute() // NOLINT (readability-function-size)
uInt32 pc = read_register(15); uInt32 pc = read_register(15);
const uInt32 instructionPtr = pc - 2; const uInt32 instructionPtr = pc - 2;
const uInt32 instructionPtr2 = instructionPtr >> 1;
inst = fetch16(instructionPtr); inst = fetch16(instructionPtr);
pc += 2; pc += 2;
@ -1160,9 +1160,9 @@ FORCE_INLINE int Thumbulator::execute() // NOLINT (readability-function-size)
Op decodedOp{}; Op decodedOp{};
#ifndef UNSAFE_OPTIMIZATIONS #ifndef UNSAFE_OPTIMIZATIONS
if ((instructionPtr & 0xF0000000) == 0 && instructionPtr < romSize) if ((instructionPtr & 0xF0000000) == 0 && instructionPtr < romSize)
decodedOp = decodedRom[instructionPtr >> 1]; decodedOp = decodedRom[instructionPtr2];
else else
decodedOp = decodeInstructionWord(inst, pc); decodedOp = decodeInstructionWord(CONV_RAMROM(rom[instructionPtr2]), instructionPtr);
#else #else
decodedOp = decodedRom[(instructionPtr & ROMADDMASK) >> 1]; decodedOp = decodedRom[(instructionPtr & ROMADDMASK) >> 1];
#endif #endif
@ -1392,175 +1392,114 @@ FORCE_INLINE int Thumbulator::execute() // NOLINT (readability-function-size)
//B(1) conditional branch variants: //B(1) conditional branch variants:
// (beq, bne, bcs, bcc, bmi, bpl, bvs, bvc, bhi, bls, bge, blt, bgt, ble) // (beq, bne, bcs, bcc, bmi, bpl, bvs, bvc, bhi, bls, bge, blt, bgt, ble)
case Op::beq: { case Op::beq: {
#ifdef THUMB_STATS THUMB_STAT(_stats.branches)
++_stats.branches;
#endif
rb = decodedParam[instructionPtr >> 1];
DO_DISS(statusMsg << "beq 0x" << Base::HEX8 << (rb-3) << endl);
if(!znFlags) if(!znFlags)
write_register(15, rb); write_register(15, decodedParam[instructionPtr2]);
return 0; return 0;
} }
case Op::bne: { case Op::bne: {
#ifdef THUMB_STATS THUMB_STAT(_stats.branches)
++_stats.branches;
#endif
rb = decodedParam[instructionPtr >> 1];
DO_DISS(statusMsg << "bne 0x" << Base::HEX8 << (rb-3) << endl);
if(znFlags) if(znFlags)
write_register(15, rb); write_register(15, decodedParam[instructionPtr2]);
return 0; return 0;
} }
case Op::bcs: { case Op::bcs: {
#ifdef THUMB_STATS THUMB_STAT(_stats.branches)
++_stats.branches;
#endif
rb = decodedParam[instructionPtr >> 1];
DO_DISS(statusMsg << "bcs 0x" << Base::HEX8 << (rb-3) << endl);
if(cFlag) if(cFlag)
write_register(15, rb); write_register(15, decodedParam[instructionPtr2]);
return 0; return 0;
} }
case Op::bcc: { case Op::bcc: {
#ifdef THUMB_STATS THUMB_STAT(_stats.branches)
++_stats.branches;
#endif
rb = decodedParam[instructionPtr >> 1];
DO_DISS(statusMsg << "bcc 0x" << Base::HEX8 << (rb-3) << endl);
if(!cFlag) if(!cFlag)
write_register(15, rb); write_register(15, decodedParam[instructionPtr2]);
return 0; return 0;
} }
case Op::bmi: { case Op::bmi: {
#ifdef THUMB_STATS THUMB_STAT(_stats.branches)
++_stats.branches;
#endif
rb = decodedParam[instructionPtr >> 1];
DO_DISS(statusMsg << "bmi 0x" << Base::HEX8 << (rb-3) << endl);
if(znFlags & 0x80000000) if(znFlags & 0x80000000)
write_register(15, rb); write_register(15, decodedParam[instructionPtr2]);
return 0; return 0;
} }
case Op::bpl: { case Op::bpl: {
#ifdef THUMB_STATS THUMB_STAT(_stats.branches)
++_stats.branches;
#endif
rb = decodedParam[instructionPtr >> 1];
DO_DISS(statusMsg << "bpl 0x" << Base::HEX8 << (rb-3) << endl);
if(!(znFlags & 0x80000000)) if(!(znFlags & 0x80000000))
write_register(15, rb); write_register(15, decodedParam[instructionPtr2]);
return 0; return 0;
} }
case Op::bvs: { case Op::bvs: {
#ifdef THUMB_STATS THUMB_STAT(_stats.branches)
++_stats.branches;
#endif
rb = decodedParam[instructionPtr >> 1];
DO_DISS(statusMsg << "bvs 0x" << Base::HEX8 << (rb-3) << endl);
if(vFlag) if(vFlag)
write_register(15, rb); write_register(15, decodedParam[instructionPtr2]);
return 0; return 0;
} }
case Op::bvc: { case Op::bvc: {
#ifdef THUMB_STATS THUMB_STAT(_stats.branches)
++_stats.branches;
#endif
rb = decodedParam[instructionPtr >> 1];
DO_DISS(statusMsg << "bvc 0x" << Base::HEX8 << (rb-3) << endl);
if(!vFlag) if(!vFlag)
write_register(15, rb); write_register(15, decodedParam[instructionPtr2]);
return 0; return 0;
} }
case Op::bhi: { case Op::bhi: {
#ifdef THUMB_STATS THUMB_STAT(_stats.branches)
++_stats.branches;
#endif
rb = decodedParam[instructionPtr >> 1];
DO_DISS(statusMsg << "bhi 0x" << Base::HEX8 << (rb-3) << endl);
if(cFlag && znFlags) if(cFlag && znFlags)
write_register(15, rb); write_register(15, decodedParam[instructionPtr2]);
return 0; return 0;
} }
case Op::bls: { case Op::bls: {
#ifdef THUMB_STATS THUMB_STAT(_stats.branches)
++_stats.branches;
#endif
rb = decodedParam[instructionPtr >> 1];
DO_DISS(statusMsg << "bls 0x" << Base::HEX8 << (rb-3) << endl);
if(!znFlags || !cFlag) if(!znFlags || !cFlag)
write_register(15, rb); write_register(15, decodedParam[instructionPtr2]);
return 0; return 0;
} }
case Op::bge: { case Op::bge: {
#ifdef THUMB_STATS THUMB_STAT(_stats.branches)
++_stats.branches;
#endif
rb = decodedParam[instructionPtr >> 1];
DO_DISS(statusMsg << "bge 0x" << Base::HEX8 << (rb-3) << endl);
if(((znFlags & 0x80000000) && vFlag) || if(((znFlags & 0x80000000) && vFlag) ||
((!(znFlags & 0x80000000)) && !vFlag)) ((!(znFlags & 0x80000000)) && !vFlag))
write_register(15, rb); write_register(15, decodedParam[instructionPtr2]);
return 0; return 0;
} }
case Op::blt: { case Op::blt: {
#ifdef THUMB_STATS THUMB_STAT(_stats.branches)
++_stats.branches;
#endif
rb = decodedParam[instructionPtr >> 1];
DO_DISS(statusMsg << "blt 0x" << Base::HEX8 << (rb-3) << endl);
if((!(znFlags & 0x80000000) && vFlag) || if((!(znFlags & 0x80000000) && vFlag) ||
(((znFlags & 0x80000000)) && !vFlag)) (((znFlags & 0x80000000)) && !vFlag))
write_register(15, rb); write_register(15, decodedParam[instructionPtr2]);
return 0; return 0;
} }
case Op::bgt: { case Op::bgt: {
#ifdef THUMB_STATS THUMB_STAT(_stats.branches)
++_stats.branches;
#endif
rb = decodedParam[instructionPtr >> 1];
DO_DISS(statusMsg << "bgt 0x" << Base::HEX8 << (rb-3) << endl);
if(znFlags) if(znFlags)
{ {
if(((znFlags & 0x80000000) && vFlag) || if(((znFlags & 0x80000000) && vFlag) ||
((!(znFlags & 0x80000000)) && !vFlag)) ((!(znFlags & 0x80000000)) && !vFlag))
write_register(15, rb); write_register(15, decodedParam[instructionPtr2]); }
}
return 0; return 0;
} }
case Op::ble: { case Op::ble: {
#ifdef THUMB_STATS THUMB_STAT(_stats.branches)
++_stats.branches;
#endif
rb = decodedParam[instructionPtr >> 1];
DO_DISS(statusMsg << "ble 0x" << Base::HEX8 << (rb-3) << endl);
if(!znFlags || if(!znFlags ||
(!(znFlags & 0x80000000) && vFlag) || (!(znFlags & 0x80000000) && vFlag) ||
(((znFlags & 0x80000000)) && !vFlag)) (((znFlags & 0x80000000)) && !vFlag))
write_register(15, rb); write_register(15, decodedParam[instructionPtr2]);
return 0; return 0;
} }
//B(2) unconditional branch //B(2) unconditional branch
case Op::b2: { case Op::b2: {
#ifdef THUMB_STATS THUMB_STAT(_stats.branches)
++_stats.branches; write_register(15, decodedParam[instructionPtr2]);
#endif
rb = decodedParam[instructionPtr >> 1];
DO_DISS(statusMsg << "B 0x" << Base::HEX8 << (rb-3) << endl);
write_register(15, rb);
return 0; return 0;
} }
@ -2880,18 +2819,20 @@ FORCE_INLINE int Thumbulator::execute() // NOLINT (readability-function-size)
//SWI //SWI
case Op::swi: { // never used case Op::swi: { // never used
#if 0
rb = inst & 0xFF; // NOLINT: clang-analyzer-deadcode.DeadStores rb = inst & 0xFF; // NOLINT: clang-analyzer-deadcode.DeadStores
DO_DISS(statusMsg << "swi 0x" << Base::HEX2 << rb << endl); DO_DISS(statusMsg << "swi 0x" << Base::HEX2 << rb << endl);
//if(rb == 0xCC) if(rb == 0xCC)
//{ {
// write_register(0, cpsr); write_register(0, cpsr);
// return 0; return 0;
//} }
//else else
{ {
#if defined(THUMB_DISS) #if defined(THUMB_DISS)
statusMsg << endl << endl << "swi 0x" << Base::HEX2 << rb << endl; statusMsg << endl << endl << "swi 0x" << Base::HEX2 << rb << endl;
#endif
#endif #endif
return 1; return 1;
} }
@ -3085,44 +3026,31 @@ bool Thumbulator::isMamBuffered(uInt32 addr, AccessType accessType)
case AccessType::prefetch: case AccessType::prefetch:
if(addr != _prefetchBufferAddr[0] && addr != _branchBufferAddr[0]) if(addr != _prefetchBufferAddr[0] && addr != _branchBufferAddr[0])
{ {
#ifdef THUMB_STATS THUMB_STAT(_stats.mamPrefetchMisses)
++_stats.mamPrefetchMisses;
#endif
_prefetchBufferAddr[0] = addr; _prefetchBufferAddr[0] = addr;
return false; return false;
} }
#ifdef THUMB_STATS THUMB_STAT(_stats.mamPrefetchHits)
++_stats.mamPrefetchHits;
#endif
break; break;
case AccessType::branch: case AccessType::branch:
if(addr != _prefetchBufferAddr[0] && addr != _branchBufferAddr[0]) if(addr != _prefetchBufferAddr[0] && addr != _branchBufferAddr[0])
{ {
#ifdef THUMB_STATS THUMB_STAT(_stats.mamBranchMisses)
++_stats.mamBranchMisses;
#endif
_branchBufferAddr[0] = addr; _branchBufferAddr[0] = addr;
return false; return false;
} }
#ifdef THUMB_STATS THUMB_STAT(_stats.mamBranchHits)
++_stats.mamBranchHits;
#endif
break; break;
default: // AccessType::data default: // AccessType::data
if(addr != _dataBufferAddr) if(addr != _dataBufferAddr)
{ {
#ifdef THUMB_STATS THUMB_STAT(_stats.mamDataMisses)
++_stats.mamDataMisses;
#endif
_dataBufferAddr = addr; _dataBufferAddr = addr;
return false; return false;
} }
#ifdef THUMB_STATS THUMB_STAT(_stats.mamDataHits)
++_stats.mamDataHits;
#endif
break; break;
} }
} }
@ -3140,45 +3068,33 @@ bool Thumbulator::isMamBuffered(uInt32 addr, AccessType accessType)
_prefetchBufferAddr[bank ^ 1] = addr + 0x80; _prefetchBufferAddr[bank ^ 1] = addr + 0x80;
if(addr != _prefetchBufferAddr[bank] && addr != _branchBufferAddr[bank]) if(addr != _prefetchBufferAddr[bank] && addr != _branchBufferAddr[bank])
{ {
#ifdef THUMB_STATS THUMB_STAT(_stats.mamPrefetchMisses)
++_stats.mamPrefetchMisses;
#endif
_prefetchBufferAddr[bank] = addr; _prefetchBufferAddr[bank] = addr;
return false; return false;
} }
#ifdef THUMB_STATS THUMB_STAT(_stats.mamPrefetchHits)
++_stats.mamPrefetchHits;
#endif
break; break;
case AccessType::branch: case AccessType::branch:
if(addr != _prefetchBufferAddr[bank] && addr != _branchBufferAddr[bank]) if(addr != _prefetchBufferAddr[bank] && addr != _branchBufferAddr[bank])
{ {
#ifdef THUMB_STATS THUMB_STAT(_stats.mamBranchMisses)
++_stats.mamBranchMisses;
#endif
// load both branch trail buffers at once // load both branch trail buffers at once
_branchBufferAddr[bank] = addr; _branchBufferAddr[bank] = addr;
_branchBufferAddr[bank ^ 1] = addr + 0x80; _branchBufferAddr[bank ^ 1] = addr + 0x80;
return false; return false;
} }
#ifdef THUMB_STATS THUMB_STAT(_stats.mamBranchHits)
++_stats.mamBranchHits;
#endif
break; break;
default: // AccessType::data default: // AccessType::data
if(addr != _dataBufferAddr) if(addr != _dataBufferAddr)
{ {
#ifdef THUMB_STATS THUMB_STAT(_stats.mamDataMisses)
++_stats.mamDataMisses;
#endif
_dataBufferAddr = addr; _dataBufferAddr = addr;
return false; return false;
} }
#ifdef THUMB_STATS THUMB_STAT(_stats.mamDataHits)
++_stats.mamDataHits;
#endif
break; break;
} }
} }
@ -3264,10 +3180,7 @@ void Thumbulator::incCycles(AccessType accessType, uInt32 cycles)
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
void Thumbulator::incSCycles(uInt32 addr, AccessType accessType) void Thumbulator::incSCycles(uInt32 addr, AccessType accessType)
{ {
#ifdef THUMB_STATS THUMB_STAT(_stats.sCylces)
++_stats.sCylces;
#endif
uInt32 cycles = 0; uInt32 cycles = 0;
if(addr & 0xC0000000) // RAM, peripherals if(addr & 0xC0000000) // RAM, peripherals
@ -3327,10 +3240,7 @@ void Thumbulator::incSCycles(uInt32 addr, AccessType accessType)
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
void Thumbulator::incNCycles(uInt32 addr, AccessType accessType) void Thumbulator::incNCycles(uInt32 addr, AccessType accessType)
{ {
#ifdef THUMB_STATS THUMB_STAT(_stats.nCylces)
++_stats.nCylces;
#endif
uInt32 cycles = 0; uInt32 cycles = 0;
if(addr & 0xC0000000) // RAM, peripherals if(addr & 0xC0000000) // RAM, peripherals
@ -3357,9 +3267,7 @@ void Thumbulator::incNCycles(uInt32 addr, AccessType accessType)
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
void Thumbulator::incICycles(uInt32 m) void Thumbulator::incICycles(uInt32 m)
{ {
#ifdef THUMB_STATS THUMB_STAT(_stats.iCylces)
++_stats.iCylces;
#endif
#ifdef EMULATE_PIPELINE #ifdef EMULATE_PIPELINE
_fetchPipeline += m; _fetchPipeline += m;