mirror of https://github.com/stella-emu/stella.git
Updated documentation for Chetiry (CTY) bankswitch scheme in the
source code header file. As you can see, this is one of the more complex schemes (and it isn't even finished yet!). git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2490 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
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@ -26,7 +26,83 @@ class System;
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#include "Cart.hxx"
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/**
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TODO - add description from cd-w.
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The 'Chetiry' bankswitch scheme was developed by Chris D. Walton for a
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Tetris clone game by the same name. It makes use of a Harmony cart,
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whereby ARM code in bank 0 is executed to implement the bankswitch scheme.
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The implementation here does not execute this ARM code, and instead
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implements the bankswitching directly. Its functionality is similar to
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several other schemes, as follows:
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F4SC:
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The scheme contains 8 4K banks, with the first bank being inaccessible
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(due to containing ARM code). The remaining banks (1 - 7) are accessed
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at hotspots $FF5 - $FFB, exactly the same as F4SC.
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There is 64 bytes of RAM (vs. 128 bytes in F4SC) at $1000 - $107F
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($1000 - $103F is write port, $1040 - $107F is read port).
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FA2:
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The first four bytes of RAM are actually a kind of hotspot, with the
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following functionality. Data is accessed from Harmony EEPROM in
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the same fashion as the FA2 scheme.
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Write Addresses:
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$1000 = Operation Type (see discussion of hotspot $1FF4 below)
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$1001 = Set Random Seed Value
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$1002 = Reset Fetcher To Beginning Of Tune
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$1003 = Advance Fetcher To Next Tune Position
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Read Addresses:
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$1040 = Error Code after operation
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$1041 = Get Next Random Number (8-bit LFSR)
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$1042 = Get Tune Position (Low Byte)
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$1043 = Get Tune Position (High Byte)
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RAM Load And Save Operations:
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Address $1FF4 is used as a special hotspot to trigger loading and saving
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of the RAM, similar to FA2 bankswitching. The operation to perform is
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given using the first byte of the extra RAM. The format of this byte is
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XXXXYYYY, where XXXX is an index and YYYY is the operation to perform.
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There are 4 different operation types:
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1 = Load Tune (index = tune)
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2 = Load Score Table (index = table)
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3 = Save Score Table (index = table)
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4 = Wipe All Score Tables (set all 256 bytes of EEPROM to $00)
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The score table functionality is based on 256 bytes from Harmony
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EEPROM, of which there are 4 64-byte 'tables'. The 'index' for
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operations 2 and 3 can therefore be in the range 0 - 3, indicating
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which table to use. For this implementation, the 256 byte EEPROM
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is serialized to a file.
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The tune table functionality is also based on Harmony EEPROM, where
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7 4K tunes are stored (28K total). The 'index' for operation 1 can
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therefore be in the range 0 - 6, indicating which tune to load.
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For this implementation, the 28K tune data is in the 'CartCTYTunes'
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header file.
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DPC+:
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The music functionality is quite similar to the DPC+ scheme.
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Fast Fetcher
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The music frequency value is fetched using a fast fetcher operation.
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This operation is aliased to the instruction "LDA #$F2". Whenever this
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instruction is executed, the $F2 value is replaced with the frequency
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value calculated from the tune data. The pointer to the tune data does
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not advance until address $1003 is written. When a new tune is loaded,
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the pointer is reset to the beginning of the tune. This also happens
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when the end of the tune is reached or when address $1002 is written to.
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The calculation of the frequency value is essentially the same as DPC.
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There are 3 different channels that are combined together, and only a
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square waveform is used. The data is formatted so that the three notes
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for each position appear consecutively (note0, note1, note2). Moving
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to the next tune position means incrementing by 3 bytes. The end of the
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tune is marked by a note value of 1. A note value of 0 means that the
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current value should not be updated, i.e continue with the previous
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non-zero value.
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@author Stephen Anthony and Chris D. Walton
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@version $Id$
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@ -184,12 +260,12 @@ class CartridgeCTY : public Cartridge
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// The time after which the first request of a load/save operation
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// will actually be completed
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// Due to flash RAM constraints, a read/write isn't instantaneous,
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// Due to Harmony EEPROM constraints, a read/write isn't instantaneous,
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// so we need to emulate the delay as well
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uInt64 myRamAccessTimeout;
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// Full pathname of the file to use when emulating load/save
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// of internal RAM to Harmony cart flash
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// of internal RAM to Harmony cart EEPROM
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string myEEPROMFile;
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};
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