mirror of https://github.com/stella-emu/stella.git
added emulation of merged I-S cycles
improved ARM timers fixed MAMCR register emulation
This commit is contained in:
Thomas Jentzsch
parent
43a813958a
commit
c3220e0532
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@ -53,6 +53,7 @@ using Common::Base;
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#endif
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#ifdef THUMB_CYCLE_COUNT
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#define MERGE_I_S
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#define INC_S_CYCLES(addr, accessType) \
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if(_countCycles) \
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incSCycles(addr, accessType)
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@ -68,7 +69,7 @@ using Common::Base;
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#define INC_CYCLES(m) \
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_totalCycles += m
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#define FETCH_TYPE_N \
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_fetchCycleType = CycleType::N
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_prefetchCycleType = CycleType::N
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#else
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#define INC_S_CYCLES(addr, accessType)
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#define INC_N_CYCLES(addr, accessType)
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@ -168,13 +169,13 @@ void Thumbulator::updateTimer(uInt32 cycles)
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if(T0TCR & 1) // bit 0 controls timer on/off
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{
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T0TC += static_cast<uInt32>(cycles * timing_factor);
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tim0Cycles = 0;
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tim0Total = 0;
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}
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#endif
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if(T1TCR & 1) // bit 0 controls timer on/off
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{
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T1TC += static_cast<uInt32>(cycles * timing_factor);
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tim1Cycles = 0;
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tim1Total = 0;
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}
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}
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@ -245,15 +246,22 @@ uInt32 Thumbulator::fetch16(uInt32 addr)
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uInt32 data;
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#ifdef THUMB_CYCLE_COUNT
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if(_fetchCycleType == CycleType::S)
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if(_prefetchCycleType == CycleType::S)
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{
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#ifdef MERGE_I_S
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//if(_countCycles && _lastCycleType == CycleType::I)
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//{
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// --_totalCycles;
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// _lastCycleType == CycleType::S;
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//}
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#endif
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INC_S_CYCLES(addr, AccessType::prefetch);
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}
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else
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{
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INC_N_CYCLES(addr, AccessType::prefetch);
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_prefetchCycleType = CycleType::S; // default
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}
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_fetchCycleType = CycleType::S;
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#endif
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switch(addr & 0xF0000000)
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@ -308,18 +316,8 @@ void Thumbulator::write16(uInt32 addr, uInt32 data)
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ram[addr] = CONV_DATA(data);
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return;
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#ifndef UNSAFE_OPTIMIZATIONS
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case 0xE0000000: //MAMCR
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#else
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default:
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#endif
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if(addr == 0xE01FC000)
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{
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DO_DBUG(statusMsg << "write16(" << Base::HEX8 << "MAMCR" << "," << Base::HEX8 << data << ") *" << endl);
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if(!_lockMamcr)
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mamcr = static_cast<MamModeType>(data);
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return;
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}
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break;
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}
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#ifndef UNSAFE_OPTIMIZATIONS
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fatalError("write16", addr, data, "abort");
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@ -355,23 +353,51 @@ void Thumbulator::write32(uInt32 addr, uInt32 data)
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#endif
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#ifdef TIMER_0
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case 0xE0004004: // T0TCR - Timer 0 Control Register
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#ifdef THUMB_CYCLE_COUNT
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if((T0TCR ^ data) & 1)
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{
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// timer changed counter state
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if(data & 1)
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// timer switched to counting
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tim0Start = _totalCycles;
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else
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// timer switched to disabled
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tim0Total += _totalCycles - tim0Start;
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}
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#endif
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T0TCR = data;
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break;
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case 0xE0004008: // T0TC - Timer 0 Counter
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#ifdef THUMB_CYCLE_COUNT
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tim0Start = _totalCycles;
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tim0Total = data / _armCyclesFactor;
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#endif
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T0TC = data;
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tim0Cycles = _totalCycles;
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break;
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#endif
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case 0xE0008004: // T1TCR - Timer 1 Control Register
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#ifdef THUMB_CYCLE_COUNT
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if((T1TCR ^ data) & 1)
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{
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// timer changed counter state
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if(data & 1)
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// timer switched to counting
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tim1Start = _totalCycles;
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else
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// timer switched to disabled
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tim1Total += _totalCycles - tim1Start;
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}
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#endif
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T1TCR = data;
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break;
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case 0xE0008008: // T1TC - Timer 1 Counter
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T1TC = data;
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#ifdef THUMB_CYCLE_COUNT
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tim1Cycles = _totalCycles;
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tim1Start = _totalCycles;
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tim1Total = data / _armCyclesFactor;
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#endif
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T1TC = data;
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break;
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case 0xE000E010:
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@ -398,6 +424,15 @@ void Thumbulator::write32(uInt32 addr, uInt32 data)
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systick_calibrate = data & 0x00FFFFFF;
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break;
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#ifdef THUMB_CYCLE_COUNT
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case 0xE01FC000: //MAMCR
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DO_DBUG(statusMsg << "write32(" << Base::HEX8 << "MAMCR" << ","
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<< Base::HEX8 << data << ") *" << endl);
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if(!_lockMamcr)
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mamcr = static_cast<MamModeType>(data);
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break;
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#endif
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default:
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break;
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}
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@ -501,16 +536,7 @@ uInt32 Thumbulator::read16(uInt32 addr)
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DO_DBUG(statusMsg << "read16(" << Base::HEX8 << addr << ")=" << Base::HEX4 << data << endl);
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return data;
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#ifndef UNSAFE_OPTIMIZATIONS
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case 0xE0000000: //MAMCR
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if(addr == 0xE01FC000)
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#else
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default:
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#endif
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{
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DO_DBUG(statusMsg << "read16(" << "MAMCR" << addr << ")=" << mamcr << " *");
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return static_cast<uInt32>(mamcr);
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}
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default: break;
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}
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#ifndef UNSAFE_OPTIMIZATIONS
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return fatalError("read16", addr, "abort");
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@ -543,6 +569,13 @@ uInt32 Thumbulator::read32(uInt32 addr)
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{
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switch(addr)
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{
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#ifdef THUMB_CYCLE_COUNT
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case 0xE01FC000: //MAMCR
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DO_DBUG(statusMsg << "read32(" << "MAMCR" << addr << ")=" << mamcr << " *");
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data = static_cast<uInt32>(mamcr);
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return data;
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#endif
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#ifdef TIMER_0
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case 0xE0004004: // T0TCR - Timer 0 Control Register
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data = T0TCR;
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@ -550,7 +583,12 @@ uInt32 Thumbulator::read32(uInt32 addr)
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case 0xE0004008: // T0TC - Timer 0 Counter
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#ifdef THUMB_CYCLE_COUNT
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data = T0TC + (_totalCycles - tim0Cycles) * _armCyclesFactor;
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if(T0TCR & 1)
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// timer is counting
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data = T0TC + (tim0Total + (_totalCycles - tim0Start)) * _armCyclesFactor;
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else
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// timer is disabled
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data = T0TC + tim0Total * _armCyclesFactor;
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#else
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data = T0TC;
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#endif
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@ -562,7 +600,12 @@ uInt32 Thumbulator::read32(uInt32 addr)
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case 0xE0008008: // T1TC - Timer 1 Counter
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#ifdef THUMB_CYCLE_COUNT
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data = T1TC + (_totalCycles - tim1Cycles) * _armCyclesFactor;
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if(T1TCR & 1)
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// timer is counting
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data = T1TC + (tim1Total + (_totalCycles - tim1Start)) * _armCyclesFactor;
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else
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// timer is disabled
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data = T1TC + tim1Total * _armCyclesFactor;
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#else
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data = T1TC;
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#endif
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@ -1771,10 +1814,10 @@ int Thumbulator::execute()
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sp += 4;
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}
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}
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INC_I_CYCLES; // Note: destination PC not possible, see pop instead
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//there is a write back exception.
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if((inst & (1 << rn)) == 0)
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write_register(rn, sp);
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INC_I_CYCLES;
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return 0;
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}
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@ -1787,9 +1830,9 @@ int Thumbulator::execute()
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DO_DISS(statusMsg << "ldr r" << dec << rd << ",[r" << dec << rn << ",#0x" << Base::HEX2 << rb << "]" << endl);
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rb = read_register(rn) + rb;
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rc = read32(rb);
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write_register(rd, rc);
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INC_N_CYCLES(rb, AccessType::data);
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INC_I_CYCLES;
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write_register(rd, rc);
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return 0;
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}
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@ -1801,9 +1844,9 @@ int Thumbulator::execute()
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DO_DISS(statusMsg << "ldr r" << dec << rd << ",[r" << dec << rn << ",r" << dec << "]" << endl);
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rb = read_register(rn) + read_register(rm);
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rc = read32(rb);
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write_register(rd, rc);
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INC_N_CYCLES(rb, AccessType::data);
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INC_I_CYCLES;
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write_register(rd, rc);
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return 0;
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}
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@ -1818,9 +1861,9 @@ int Thumbulator::execute()
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rb += ra;
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DO_DISS(statusMsg << ";@ 0x" << Base::HEX2 << rb << endl);
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rc = read32(rb);
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write_register(rd, rc);
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INC_N_CYCLES(rb, AccessType::data);
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INC_I_CYCLES;
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write_register(rd, rc);
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return 0;
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}
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@ -1834,9 +1877,9 @@ int Thumbulator::execute()
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//ra&=~3;
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rb += ra;
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rc = read32(rb);
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write_register(rd, rc);
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INC_N_CYCLES(rb, AccessType::data);
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INC_I_CYCLES;
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write_register(rd, rc);
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return 0;
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}
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@ -1859,9 +1902,9 @@ int Thumbulator::execute()
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else
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{
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}
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write_register(rd, rc & 0xFF);
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INC_N_CYCLES(rb & (~1U), AccessType::data);
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INC_I_CYCLES;
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write_register(rd, rc & 0xFF);
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return 0;
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}
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@ -1881,9 +1924,9 @@ int Thumbulator::execute()
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{
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rc >>= 8;
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}
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write_register(rd, rc & 0xFF);
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INC_N_CYCLES(rb & (~1U), AccessType::data);
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INC_I_CYCLES;
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write_register(rd, rc & 0xFF);
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return 0;
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}
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@ -1896,9 +1939,9 @@ int Thumbulator::execute()
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DO_DISS(statusMsg << "ldrh r" << dec << rd << ",[r" << dec << rn << ",#0x" << Base::HEX2 << rb << "]" << endl);
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rb = read_register(rn) + rb;
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rc = read16(rb);
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write_register(rd, rc & 0xFFFF);
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INC_N_CYCLES(rb, AccessType::data);
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INC_I_CYCLES;
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write_register(rd, rc & 0xFFFF);
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return 0;
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}
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@ -1935,9 +1978,9 @@ int Thumbulator::execute()
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rc &= 0xFF;
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if(rc & 0x80)
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rc |= ((~0U) << 8);
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write_register(rd, rc);
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INC_N_CYCLES(rb & (~1U), AccessType::data);
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INC_I_CYCLES;
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write_register(rd, rc);
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return 0;
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}
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@ -1952,9 +1995,9 @@ int Thumbulator::execute()
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rc &= 0xFFFF;
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if(rc & 0x8000)
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rc |= ((~0U) << 16);
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write_register(rd, rc);
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INC_N_CYCLES(rb, AccessType::data);
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INC_I_CYCLES;
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write_register(rd, rc);
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return 0;
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}
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@ -2233,6 +2276,7 @@ int Thumbulator::execute()
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sp += 4;
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}
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}
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INC_I_CYCLES; // ??? (copied from ldmia)
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if(inst & 0x100)
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{
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rc = read32(sp);
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@ -2249,7 +2293,6 @@ int Thumbulator::execute()
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sp += 4;
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}
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write_register(13, sp);
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INC_I_CYCLES; // ??? (copied from stmia)
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return 0;
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}
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@ -2322,8 +2365,7 @@ int Thumbulator::execute()
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}
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}
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write_register(13, sp);
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INC_I_CYCLES; // ??? (copied from ldmia)
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FETCH_TYPE_N; // ??? (copied from ldmia)
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FETCH_TYPE_N; // ??? (copied from stmia)
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return 0;
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}
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@ -2470,7 +2512,6 @@ int Thumbulator::execute()
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}
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}
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write_register(rn, sp);
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INC_I_CYCLES;
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FETCH_TYPE_N;
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return 0;
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}
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@ -3005,7 +3046,17 @@ void Thumbulator::incSCycles(uInt32 addr, AccessType accessType)
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cycles = _flashCycles;
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}
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}
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#ifdef MERGE_I_S
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if(_lastCycleType[1] == CycleType::I)
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--cycles;
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#endif
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incCycles(accessType, cycles);
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#ifdef MERGE_I_S
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_lastCycleType[1] = _lastCycleType[0];
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_lastCycleType[0] = CycleType::S;
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#endif
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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@ -3026,6 +3077,10 @@ void Thumbulator::incNCycles(uInt32 addr, AccessType accessType)
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cycles = _flashCycles;
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}
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incCycles(accessType, cycles);
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#ifdef MERGE_I_S
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_lastCycleType[1] = _lastCycleType[0];
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_lastCycleType[0] = CycleType::N;
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#endif
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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@ -3047,6 +3102,10 @@ void Thumbulator::incICycles(uInt32 m)
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}
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#endif
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_totalCycles += m;
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#ifdef MERGE_I_S
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_lastCycleType[1] = _lastCycleType[0];
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_lastCycleType[0] = CycleType::I;
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#endif
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}
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#endif // THUMB_CYCLE_COUNT
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@ -283,13 +283,15 @@ class Thumbulator
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// Register names from documentation:
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// http://www.nxp.com/documents/user_manual/UM10161.pdf
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#ifdef TIMER_0
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uInt32 T0TCR{0}; // Timer 0 Timer Control Register
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uInt32 T0TC{0}; // Timer 0 Timer Counter
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uInt32 tim0Cycles{0};
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uInt32 T0TCR{0}; // Timer 0 Timer Control Register
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uInt32 T0TC{0}; // Timer 0 Timer Counter
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uInt32 tim0Start{0}; // _totalCycles when Timer 0 got started last time
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uInt32 tim0Total{0}; // total cycles of Timer 0
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#endif
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uInt32 T1TCR{0}; // Timer 1 Timer Control Register
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uInt32 T1TC{0}; // Timer 1 Timer Counter
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uInt32 tim1Cycles{0};
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uInt32 T1TCR{0}; // Timer 1 Timer Control Register
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uInt32 T1TC{0}; // Timer 1 Timer Counter
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uInt32 tim1Start{0}; // _totalCycles when Timer 1 got started last time
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uInt32 tim1Total{0}; // total cycles of Timer 1
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double timing_factor{0.0};
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#ifndef UNSAFE_OPTIMIZATIONS
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@ -301,7 +303,8 @@ class Thumbulator
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#ifdef THUMB_CYCLE_COUNT
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double _armCyclesFactor{1.05};
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CycleType _fetchCycleType{CycleType::S};
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CycleType _prefetchCycleType{CycleType::S};
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CycleType _lastCycleType[2]{CycleType::S};
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#ifdef EMULATE_PIPELINE
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uInt32 _fetchPipeline{0}; // reserve fetch cycles resulting from pipelining (execution stage)
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uInt32 _memory0Pipeline{0}, _memory1Pipeline{0};
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