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add missing register 0 to ARM dump

This commit is contained in:
thrust26 2019-12-21 08:20:19 +01:00
parent ec470d17cb
commit 99ec454fd4
2 changed files with 8 additions and 8 deletions
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14
src/emucore/CartDetector.cxx
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@ -1005,15 +1005,15 @@ bool CartDetector::isProbablyUA(const ByteBuffer& image, size_t size)
{ {
// UA cart bankswitching switches to bank 1 by accessing address 0x240 // UA cart bankswitching switches to bank 1 by accessing address 0x240
// using 'STA $240' or 'LDA $240' // using 'STA $240' or 'LDA $240'
// Similar Brazilian cart bankswitching switches to bank 1 by accessing address 0x2C0 // Similar Brazilian (Digivison) cart bankswitching switches to bank 1 by accessing address 0x2C0
// using 'BIT $2C0', 'STA $2C0' or 'LDA $2C0' // using 'BIT $2C0', 'STA $2C0' or 'LDA $2C0'
uInt8 signature[6][3] = { uInt8 signature[6][3] = {
{ 0x8D, 0x40, 0x02 }, // STA $240 { 0x8D, 0x40, 0x02 }, // STA $240 (Funky Fish, Pleiades)
{ 0xAD, 0x40, 0x02 }, // LDA $240 { 0xAD, 0x40, 0x02 }, // LDA $240 (???)
{ 0xBD, 0x1F, 0x02 }, // LDA $21F,X { 0xBD, 0x1F, 0x02 }, // LDA $21F,X (Gingerbread Man)
{ 0x2C, 0xC0, 0x02 }, // BIT $2C0 { 0x2C, 0xC0, 0x02 }, // BIT $2C0 (Time Pilot)
{ 0x8D, 0xC0, 0x02 }, // STA $2C0 { 0x8D, 0xC0, 0x02 }, // STA $2C0 (Fathom, Vanguard)
{ 0xAD, 0xC0, 0x02 } // LDA $2C0 { 0xAD, 0xC0, 0x02 } // LDA $2C0 (Mickey)
}; };
for(uInt32 i = 0; i < 6; ++i) for(uInt32 i = 0; i < 6; ++i)
if(searchForBytes(image.get(), size, signature[i], 3, 1)) if(searchForBytes(image.get(), size, signature[i], 3, 1))

2
src/emucore/Thumbulator.cxx
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@ -165,7 +165,7 @@ void Thumbulator::dump_counters()
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
void Thumbulator::dump_regs() void Thumbulator::dump_regs()
{ {
for (int cnt = 1; cnt < 14; cnt++) for (int cnt = 0; cnt < 14; cnt++)
{ {
statusMsg << "R" << cnt << " = " << Base::HEX8 << reg_norm[cnt-1] << " "; statusMsg << "R" << cnt << " = " << Base::HEX8 << reg_norm[cnt-1] << " ";
if(cnt % 4 == 0) statusMsg << endl; if(cnt % 4 == 0) statusMsg << endl;