mirror of https://github.com/stella-emu/stella.git
some magic numbers replaced
(and fixed a bug regarding offset into myCodeAccessBase)
This commit is contained in:
thrust26
parent
b0a373285b
commit
8d42af251e
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@ -87,7 +87,7 @@ uInt8 CartridgeMNetwork::peek(uInt16 address)
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// Switch banks if necessary
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checkSwitchBank(address);
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if((myCurrentSlice[0] == myRAMSlice) && (address < 0x0400))
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if((myCurrentSlice[0] == myRAMSlice) && (address < BANK_SIZE / 2))
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{
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// Reading from the 1K write port @ $1000 triggers an unwanted write
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uInt8 value = mySystem->getDataBusState(0xFF);
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@ -97,7 +97,7 @@ uInt8 CartridgeMNetwork::peek(uInt16 address)
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else
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{
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triggerReadFromWritePort(peekAddress);
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return myRAM[address & 0x03FF] = value;
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return myRAM[address & (BANK_SIZE / 2 - 1)] = value;
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}
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}
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else if((address >= 0x0800) && (address <= 0x08FF))
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@ -114,7 +114,7 @@ uInt8 CartridgeMNetwork::peek(uInt16 address)
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}
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}
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else
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return myImage[(myCurrentSlice[address >> 11] << 11) + (address & (BANK_SIZE-1))];
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return myImage[(myCurrentSlice[address >> 11] << 11) + (address & (BANK_SIZE - 1))];
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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@ -138,7 +138,7 @@ void CartridgeMNetwork::bankRAM(uInt16 bank)
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// Remember what bank we're in
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myCurrentRAM = bank;
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uInt16 offset = bank << 8;
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uInt16 offset = bank << 8; // * RAM_SLICE_SIZE (256)
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// Setup the page access methods for the current bank
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System::PageAccess access(this, System::PA_WRITE);
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@ -147,7 +147,7 @@ void CartridgeMNetwork::bankRAM(uInt16 bank)
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for(uInt16 addr = 0x1800; addr < 0x1900; addr += System::PAGE_SIZE)
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{
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access.directPokeBase = &myRAM[1024 + offset + (addr & 0x00FF)];
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access.codeAccessBase = &myCodeAccessBase[0x2000 + 1024 + offset + (addr & 0x00FF)];
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access.codeAccessBase = &myCodeAccessBase[bankCount() * BANK_SIZE + BANK_SIZE / 2 + offset + (addr & 0x00FF)];
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mySystem->setPageAccess(addr, access);
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}
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@ -157,7 +157,7 @@ void CartridgeMNetwork::bankRAM(uInt16 bank)
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for(uInt16 addr = 0x1900; addr < 0x1A00; addr += System::PAGE_SIZE)
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{
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access.directPeekBase = &myRAM[1024 + offset + (addr & 0x00FF)];
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access.codeAccessBase = &myCodeAccessBase[0x2000 + 1024 + offset + (addr & 0x00FF)];
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access.codeAccessBase = &myCodeAccessBase[bankCount() * BANK_SIZE + BANK_SIZE / 2 + offset + (addr & 0x00FF)];
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mySystem->setPageAccess(addr, access);
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}
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myBankChanged = true;
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@ -170,7 +170,7 @@ bool CartridgeMNetwork::bank(uInt16 slice)
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// Remember what bank we're in
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myCurrentSlice[0] = slice;
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uInt16 offset = slice << 11;
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uInt16 offset = slice << 11; // * BANK_SIZE (2048)
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// Setup the page access methods for the current bank
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if(slice != myRAMSlice)
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@ -178,10 +178,10 @@ bool CartridgeMNetwork::bank(uInt16 slice)
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System::PageAccess access(this, System::PA_READ);
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// Map ROM image into first segment
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for(uInt16 addr = 0x1000; addr < 0x1800; addr += System::PAGE_SIZE)
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for(uInt16 addr = 0x1000; addr < 0x1000 + BANK_SIZE; addr += System::PAGE_SIZE)
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{
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access.directPeekBase = &myImage[offset + (addr & (BANK_SIZE-1))];
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access.codeAccessBase = &myCodeAccessBase[offset + (addr & (BANK_SIZE-1))];
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access.directPeekBase = &myImage[offset + (addr & (BANK_SIZE - 1))];
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access.codeAccessBase = &myCodeAccessBase[offset + (addr & (BANK_SIZE - 1))];
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mySystem->setPageAccess(addr, access);
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}
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}
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@ -190,20 +190,20 @@ bool CartridgeMNetwork::bank(uInt16 slice)
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System::PageAccess access(this, System::PA_WRITE);
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// Set the page accessing method for the 1K slice of RAM writing pages
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for(uInt16 addr = 0x1000; addr < 0x1400; addr += System::PAGE_SIZE)
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for(uInt16 addr = 0x1000; addr < 0x1000 + BANK_SIZE / 2; addr += System::PAGE_SIZE)
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{
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access.directPokeBase = &myRAM[addr & 0x03FF];
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access.codeAccessBase = &myCodeAccessBase[0x2000 + (addr & 0x03FF)];
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access.directPokeBase = &myRAM[addr & (BANK_SIZE/2-1)];
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access.codeAccessBase = &myCodeAccessBase[bankCount() * BANK_SIZE + (addr & (BANK_SIZE / 2 - 1))];
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mySystem->setPageAccess(addr, access);
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}
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// Set the page accessing method for the 1K slice of RAM reading pages
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access.directPokeBase = nullptr;
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access.type = System::PA_READ;
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for(uInt16 addr = 0x1400; addr < 0x1800; addr += System::PAGE_SIZE)
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for(uInt16 addr = 0x1000 + BANK_SIZE / 2; addr < 0x1000 + BANK_SIZE; addr += System::PAGE_SIZE)
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{
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access.directPeekBase = &myRAM[addr & 0x03FF];
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access.codeAccessBase = &myCodeAccessBase[0x2000 + (addr & 0x03FF)];
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access.directPeekBase = &myRAM[addr & (BANK_SIZE / 2 - 1)];
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access.codeAccessBase = &myCodeAccessBase[bankCount() * BANK_SIZE + (addr & (BANK_SIZE / 2 - 1))];
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mySystem->setPageAccess(addr, access);
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}
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}
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@ -259,7 +259,7 @@ bool CartridgeMNetwork::save(Serializer& out) const
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try
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{
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out.putString(name());
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out.putShortArray(myCurrentSlice, 2);
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out.putShortArray(myCurrentSlice, NUM_SEGMENTS);
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out.putShort(myCurrentRAM);
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out.putByteArray(myRAM, RAM_SIZE);
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} catch(...)
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@ -279,7 +279,7 @@ bool CartridgeMNetwork::load(Serializer& in)
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if(in.getString() != name())
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return false;
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in.getShortArray(myCurrentSlice, 2);
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in.getShortArray(myCurrentSlice, NUM_SEGMENTS);
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myCurrentRAM = in.getShort();
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in.getByteArray(myRAM, RAM_SIZE);
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} catch(...)
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@ -166,8 +166,12 @@ class CartridgeMNetwork : public Cartridge
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void bankRAM(uInt16 bank);
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private:
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const uInt32 BANK_SIZE = 0x800;
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const uInt32 RAM_SIZE = 0x800;
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// Size of a ROM or RAM bank
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static const uInt32 BANK_SIZE = 0x800; // 2K
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// Size of RAM in the cart
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static const uInt32 RAM_SIZE = 0x800; // 1K + 4 * 256B = 2K
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// number of slices with 4K address space
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static const uInt32 NUM_SEGMENTS = 2;
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/**
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Check hotspots and switch bank if triggered.
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@ -175,14 +179,14 @@ class CartridgeMNetwork : public Cartridge
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virtual void checkSwitchBank(uInt16 address) = 0;
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private:
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// The 16K ROM image of the cartridge
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uInt8 myImage[16384];
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// The 16K ROM image of the cartridge (works for E78K too)
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uInt8 myImage[BANK_SIZE * 8];
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// The 2048 bytes of RAM
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uInt8 myRAM[2048];
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// The 2K of RAM
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uInt8 myRAM[RAM_SIZE];
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// Indicates which slice is in the segment
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uInt16 myCurrentSlice[2];
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uInt16 myCurrentSlice[NUM_SEGMENTS];
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// Indicates which 256 byte bank of RAM is being used
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uInt16 myCurrentRAM;
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