mirror of https://github.com/stella-emu/stella.git
Fixed DASH scheme to work according to spec; it now works with the
test ROM from Thomas. Still TODO is work on patch support, and add debugger tabs for bankswitching and extra RAM. git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2962 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
This commit is contained in:
stephena
parent
756a55fd82
commit
82ef198585
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@ -29,18 +29,15 @@ CartridgeDASH::CartridgeDASH(const uInt8* image, uInt32 size, const Settings& se
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Cartridge(settings), mySize(size) {
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// Allocate array for the ROM image
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myImage = new uInt8[mySize+65536];
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myImage = new uInt8[mySize];
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// Copy the ROM image into my buffer
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memcpy(myImage, image, mySize);
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createCodeAccessBase(mySize + 65536); //RAM_TOTAL_SIZE); // TODO: how does the RAM write offset affect the size we need?
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// This cart can address 4 banks of RAM, each 512 bytes @ 1000, 1200, 1400, 1600
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// However, it may not be addressable all the time (it may be swapped out)
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createCodeAccessBase(mySize + RAM_TOTAL_SIZE);
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// Remember startup bank (0 per spec, rather than last per 3E scheme).
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// Set this to go to 3rd 1K Bank.
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myStartBank = 0; //(3 << BANK_BITS) | 0;
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myStartBank = 0;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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@ -58,9 +55,15 @@ void CartridgeDASH::reset() {
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else
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memset(myRAM, 0, RAM_TOTAL_SIZE);
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// We'll map the startup bank (0) from the image into the third 1K bank upon reset
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// Initialise bank values for all ROM/RAM access
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// This is used to reverse-lookup from address to bank location
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for (uInt32 b = 0; b < 8; b++)
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bankInUse[b] = BANK_UNDEFINED; // bank is undefined and inaccessible!
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initializeBankState();
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bankROM(myStartBank);
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// We'll map the startup banks 0 and 3 from the image into the third 1K bank upon reset
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bankROM((0 << BANK_BITS) | 0);
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bankROM((3 << BANK_BITS) | 0);
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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@ -83,32 +86,26 @@ void CartridgeDASH::install(System& system) {
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for (uInt32 i = 0x00; i < 0x40; i += (1 << shift))
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mySystem->setPageAccess(i >> shift, access);
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// Setup the last segment (of 4, each 1K) to point to the first ROM slice
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// Actually we DO NOT want "always". It's just on bootup, and can be out switched later
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access.type = System::PA_READ;
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for (uInt32 address = (0x2000 - ROM_BANK_SIZE); address < 0x2000; address += (1 << shift)) {
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access.directPeekBase = &myImage[address & (ROM_BANK_SIZE - 1)]; // from base address 0x0000 in image
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access.codeAccessBase = &myCodeAccessBase[address & (ROM_BANK_SIZE - 1)];
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mySystem->setPageAccess(address >> shift, access);
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}
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// Initialise bank values for the 4x 1K bank areas
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// Initialise bank values for all ROM/RAM access
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// This is used to reverse-lookup from address to bank location
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for (uInt32 b = 0; b < 8; b++)
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bankInUse[b] = BANK_UNDEFINED; // bank is undefined and inaccessible!
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initializeBankState();
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// Install pages for the startup bank into the first segment
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bankROM(myStartBank);
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// Setup the last segment (of 4, each 1K) to point to the first ROM slice
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// Actually we DO NOT want "always". It's just on bootup, and can be out switched later
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bankROM((0 << BANK_BITS) | 0);
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bankROM((3 << BANK_BITS) | 0);
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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uInt8 CartridgeDASH::peek(uInt16 address) {
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uInt16 peekAddress = address;
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address &= 0x0FFF; // restrict to 4K address range
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uInt8 value = 0;
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uInt32 bank = (address >> (ROM_BANK_TO_POWER - 1)) & 7; // convert to 512 byte bank index (0-7)
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uInt32 bank = (address >> (ROM_BANK_TO_POWER - 1)) & 7; // convert to 512 byte bank index (0-7)
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Int16 imageBank = bankInUse[bank]; // the ROM/RAM bank that's here
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if (imageBank == BANK_UNDEFINED) { // an uninitialised bank?
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@ -116,19 +113,22 @@ uInt8 CartridgeDASH::peek(uInt16 address) {
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// accessing invalid bank, so return should be... random?
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value = mySystem->randGenerator().next();
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} else if (imageBank & BITMASK_ROMRAM) { // a RAM bank
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} else if (imageBank & BITMASK_ROMRAM) { // a RAM bank
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Int32 ramBank = imageBank & BIT_BANK_MASK; // discard irrelevant bits
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Int32 offset = ramBank << RAM_BANK_TO_POWER; // base bank address in RAM
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offset += (address & BITMASK_RAM_BANK); // + byte offset in RAM bank
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value = myRAM[offset];
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// Reading from the write port triggers an unwanted write
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value = mySystem->getDataBusState(0xFF);
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} else { // accessing ROM
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if(bankLocked())
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return value;
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else
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{
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triggerReadFromWritePort(peekAddress);
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Int32 romBank = imageBank & BIT_BANK_MASK; // discard irrelevant bits
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Int32 offset = romBank << ROM_BANK_TO_POWER; // base bank address in image
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offset += (address & BITMASK_ROM_BANK); // + byte offset in image bank
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value = myImage[offset];
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Int32 ramBank = imageBank & BIT_BANK_MASK; // discard irrelevant bits
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Int32 offset = ramBank << RAM_BANK_TO_POWER; // base bank address in RAM
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offset += (address & BITMASK_RAM_BANK); // + byte offset in RAM bank
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return myRAM[offset] = value;
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}
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}
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return value;
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@ -139,8 +139,6 @@ bool CartridgeDASH::poke(uInt16 address, uInt8 value) {
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bool myBankChanged = false;
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//address &= 0x0FFF; // restrict to 4K address range
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// Check for write to the bank switch address. RAM/ROM and bank # are encoded in 'value'
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// There are NO mirrored hotspots.
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@ -162,83 +160,125 @@ bool CartridgeDASH::poke(uInt16 address, uInt8 value) {
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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bool CartridgeDASH::bankRAM(uInt8 bank) {
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bool changed = false;
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if (bankLocked()) // debugger can lock RAM
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return false;
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// Each RAM bank uses two slots, separated by 0x800 in memory -- one read, one write.
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bankRAMSlot(bank | BITMASK_ROMRAM | 0);
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bankRAMSlot(bank | BITMASK_ROMRAM | BITMASK_LOWERUPPER);
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return true;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void CartridgeDASH::bankRAMSlot(uInt16 bank) {
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uInt16 shift = mySystem->pageShift();
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uInt16 bankNumber = (bank >> BANK_BITS) & 3; // which bank # we are switching TO (BITS D6,D7) to 512 byte block
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uInt16 currentBank = bank & BIT_BANK_MASK; // Wrap around/restrict to valid range
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uInt16 bankNumber = (bank >> BANK_BITS) & 3; // which bank # we are switching TO (BITS D6,D7) to 512 byte block
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uInt16 currentBank = bank & BIT_BANK_MASK; // Wrap around/restrict to valid range
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bool upper = bank & BITMASK_LOWERUPPER; // is this the read or write port
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// Each RAM bank uses two slots, separated by 0x800 in memory -- one read, one write.
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bankInUse[bankNumber] = bankInUse[bankNumber + 4] = (Int16) (BITMASK_ROMRAM | currentBank); // Record which bank switched in (marked as RAM)
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uInt32 startCurrentBank = currentBank << RAM_BANK_TO_POWER; // Effectively * 512 bytes
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uInt32 blockSize = 1 << shift;
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// Setup the page access methods for the current bank
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System::PageAccess access(this, System::PA_READ);
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uInt32 startCurrentBank = currentBank << RAM_BANK_TO_POWER; // Effectively * 512 bytes
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uInt32 base = 0x1000 + startCurrentBank;
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uInt32 blockSize = 1 << shift;
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uInt32 blockMask = blockSize - 1;
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if (upper) { // We're mapping the write port
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/*for (uInt32 address = base; address < base + RAM_BANK_SIZE; address += blockSize) {
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access.directPeekBase = &myRAM[startCurrentBank + (address & blockMask)];
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access.codeAccessBase = &myCodeAccessBase[65536 + startCurrentBank + (address & blockMask)];
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bankInUse[bankNumber + 4] = (Int16) bank;
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access.type = System::PA_WRITE;
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} else { // We're mapping the read port
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bankInUse[bankNumber] = (Int16) bank;
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access.type = System::PA_READ;
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}
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uInt32 start = 0x1000 + (bankNumber << RAM_BANK_TO_POWER) + (upper ? RAM_WRITE_OFFSET : 0);
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uInt32 end = start + RAM_BANK_SIZE - 1;
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for (uInt32 address = start; address <= end; address += blockSize) {
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if(upper)
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access.directPokeBase = &myRAM[startCurrentBank + (address & (RAM_BANK_SIZE - 1))];
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else
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access.directPeekBase = &myRAM[startCurrentBank + (address & (RAM_BANK_SIZE - 1))];
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access.codeAccessBase = &myCodeAccessBase[mySize + startCurrentBank + (address & (RAM_BANK_SIZE - 1))];
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mySystem->setPageAccess(address >> shift, access);
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}*/
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access.directPeekBase = 0;
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access.type = System::PA_WRITE;
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base += RAM_WRITE_OFFSET;
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/*for (uInt32 address = base; address < base + RAM_BANK_SIZE; address += blockSize) {
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access.directPokeBase = &myRAM[startCurrentBank + (address&blockMask)];
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access.codeAccessBase = &myCodeAccessBase[65536 + startCurrentBank + (address & blockMask)];
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mySystem->setPageAccess(address >> shift, access);
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}*/
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return changed = true;
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}
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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bool CartridgeDASH::bankROM(uInt8 bank) {
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bool changed = false;
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if (bankLocked()) // debugger can lock ROM
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return false;
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if (!bankLocked()) { // debugger can lock ROM
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// Map ROM bank image into the system into the correct slot
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// Memory map is 1K slots at 0x1000, 0x1400, 0x1800, 0x1C00
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// Each ROM uses 2 consecutive 512 byte slots
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bankROMSlot(bank | 0);
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bankROMSlot(bank | BITMASK_LOWERUPPER);
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uInt16 shift = mySystem->pageShift();
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return true;
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}
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uInt16 bankNumber = (bank >> BANK_BITS) & 3; // which bank # we are switching TO (BITS D6,D7)
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uInt16 currentBank = bank & BIT_BANK_MASK; // Wrap around/restrict to valid range
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void CartridgeDASH::bankROMSlot(uInt16 bank) {
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// Map ROM bank image into the system into the correct slot
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// Memory map is 1K slots at 0x1000, 0x1400, 0x1800, 0x1C00
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// Each ROM uses 2 consecutive 512 byte slots
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uInt16 shift = mySystem->pageShift();
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bankInUse[bankNumber * 2] = bankInUse[bankNumber * 2 + 1] = (Int16) currentBank; // Record which bank switched in (as ROM)
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uInt16 bankNumber = (bank >> BANK_BITS) & 3; // which bank # we are switching TO (BITS D6,D7)
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uInt16 currentBank = bank & BIT_BANK_MASK; // Wrap around/restrict to valid range
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bool upper = bank & BITMASK_LOWERUPPER; // is this the lower or upper 512b
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uInt32 startCurrentBank = currentBank << ROM_BANK_TO_POWER; // Effectively *1K
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bankInUse[bankNumber * 2 + (upper ? 1 : 0)] = (Int16) bank; // Record which bank switched in (as ROM)
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// Setup the page access methods for the current bank
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System::PageAccess access(this, System::PA_READ);
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uInt32 startCurrentBank = currentBank << ROM_BANK_TO_POWER; // Effectively *1K
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uInt32 base = 0x1000 + (bankNumber << ROM_BANK_TO_POWER);
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for (uInt32 address = base; address < base + ROM_BANK_SIZE; address += (1 << shift)) {
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access.directPeekBase = &myImage[startCurrentBank + (address & (ROM_BANK_SIZE - 1))];
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access.codeAccessBase = &myCodeAccessBase[startCurrentBank + (address & (ROM_BANK_SIZE - 1))];
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mySystem->setPageAccess(address >> shift, access);
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}
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// Setup the page access methods for the current bank
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System::PageAccess access(this, System::PA_READ);
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changed = true;
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uInt32 start = 0x1000 + (bankNumber << ROM_BANK_TO_POWER) + (upper ? ROM_BANK_SIZE / 2 : 0);
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uInt32 end = start + ROM_BANK_SIZE / 2 - 1;
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for (uInt32 address = start; address <= end; address += (1 << shift)) {
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access.directPeekBase = &myImage[startCurrentBank + (address & (ROM_BANK_SIZE - 1))];
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access.codeAccessBase = &myCodeAccessBase[startCurrentBank + (address & (ROM_BANK_SIZE - 1))];
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mySystem->setPageAccess(address >> shift, access);
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}
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}
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return changed;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void CartridgeDASH::initializeBankState() {
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const uInt16& shift = mySystem->pageShift();
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// Switch in each 512b slot
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for (uInt32 b = 0; b < 8; b++) {
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if (bankInUse[b] == BANK_UNDEFINED) {
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// Setup the page access methods for the current bank
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System::PageAccess access(this, System::PA_READ);
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uInt32 start = 0x1000 + (b << RAM_BANK_TO_POWER);
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uInt32 end = start + RAM_BANK_SIZE - 1;
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for (uInt32 address = start; address <= end; address += (1 << shift))
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mySystem->setPageAccess(address >> shift, access);
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}
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else if (bankInUse[b] & BITMASK_ROMRAM)
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bankRAMSlot(bankInUse[b]);
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else
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bankROMSlot(bankInUse[b]);
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}
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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bool CartridgeDASH::patch(uInt16 address, uInt8 value) {
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#if 0
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// Patch the cartridge ROM (for debugger)
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myBankChanged = true;
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@ -267,6 +307,9 @@ bool CartridgeDASH::patch(uInt16 address, uInt8 value) {
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}
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return myBankChanged;
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#else
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return false;
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#endif
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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@ -277,10 +320,10 @@ const uInt8* CartridgeDASH::getImage(int& size) const {
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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bool CartridgeDASH::save(Serializer& out) const {
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try {
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out.putString(name());
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for (uInt32 b = 0; b < 8; b++)
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out.putShort(bankInUse[b]);
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out.putShortArray((uInt16*)bankInUse, 8);
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out.putByteArray(myRAM, RAM_TOTAL_SIZE);
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} catch (...) {
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cerr << "ERROR: CartridgeDASH::save" << endl;
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@ -291,16 +334,17 @@ bool CartridgeDASH::save(Serializer& out) const {
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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bool CartridgeDASH::load(Serializer& in) {
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try {
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if (in.getString() != name())
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return false;
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for (uInt32 b = 0; b < 8; b++) {
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bank(bankInUse[b] = in.getShort()); // read, and switch it in
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}
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in.getShortArray((uInt16*)bankInUse, 8);
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in.getByteArray(myRAM, RAM_TOTAL_SIZE);
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} catch (...) {
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cerr << "ERROR: CartridgeDASH::load" << endl;
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return false;
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}
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initializeBankState();
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return true;
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}
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@ -233,8 +233,10 @@ private:
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bool bankRAM(uInt8 bank); // switch a RAM bank
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bool bankROM(uInt8 bank); // switch a ROM bank
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void bankRAMSlot(uInt16 bank); // switch in a 512b RAM slot (lower or upper 1/2 bank)
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void bankROMSlot(uInt16 bank); // switch in a 512b RAM slot (read or write port)
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void initializeBankState(); // set all banks according to current bankInUse state
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// We have an array that indicates for each of the 8 512 byte areas of the address space, which ROM/RAM
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// bank is used in that area. ROM switches 1K so occupies 2 successive entries for each switch. RAM occupies
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@ -248,7 +250,8 @@ private:
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static const uInt8 BANK_BITS = 6; // # bits for bank
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static const uInt8 BIT_BANK_MASK = (1 << BANK_BITS) - 1; // mask for those bits
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static const uInt8 BITMASK_ROMRAM = 0x80; // flags ROM or RAM bank switching (D7--> 1==RAM)
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static const uInt16 BITMASK_LOWERUPPER = 0x100; // flags lower or upper section of bank (1==upper)
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static const uInt16 BITMASK_ROMRAM = 0x200; // flags ROM or RAM bank switching (1==RAM)
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static const uInt16 MAXIMUM_BANK_COUNT = (1<<BANK_BITS);
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static const uInt16 RAM_BANK_TO_POWER = 9; // 2^n = 512
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@ -268,7 +271,7 @@ private:
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uInt32 mySize; // Size of the ROM image
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uInt8* myImage; // Pointer to a dynamically allocated ROM image of the cartridge
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uInt8* myRAM; // on the heap, not stack :)
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uInt8 myRAM[RAM_TOTAL_SIZE];
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};
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#endif
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