Some cleanup of ASM output; only print headers for various constants

if they are actually used in the disassembly.


git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2741 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
This commit is contained in:
stephena 2013-05-21 16:57:12 +00:00
parent e053ed4e0e
commit 7931699eb7
2 changed files with 45 additions and 27 deletions

View File

@ -921,12 +921,13 @@ string CartDebug::saveDisassembly()
const string& propsname = const string& propsname =
myConsole.properties().get(Cartridge_Name) + ".asm"; myConsole.properties().get(Cartridge_Name) + ".asm";
FilesystemNode case0(FilesystemNode(myOSystem.romFile()).getParent().getPath() + FilesystemNode case0(
propsname); FilesystemNode(myOSystem.romFile()).getParent().getPath() + propsname);
if(case0.getParent().isWritable()) if(case0.getParent().isWritable())
myDisasmFile = case0.getPath(); myDisasmFile = case0.getPath();
else else
return DebuggerParser::red("disassembly file not writable:\n " + case0.getShortPath()); return DebuggerParser::red("disassembly file not writable:\n " +
case0.getShortPath());
} }
FilesystemNode node(myDisasmFile); FilesystemNode node(myDisasmFile);
@ -936,8 +937,6 @@ string CartDebug::saveDisassembly()
#define ALIGN(x) setfill(' ') << left << setw(x) #define ALIGN(x) setfill(' ') << left << setw(x)
AddrToLabel::const_iterator iter;
// We can't print the header to the disassembly until it's actually // We can't print the header to the disassembly until it's actually
// been processed; therefore buffer output to a string first // been processed; therefore buffer output to a string first
ostringstream buf; ostringstream buf;
@ -1028,7 +1027,7 @@ string CartDebug::saveDisassembly()
// Some boilerplate, similar to what DiStella adds // Some boilerplate, similar to what DiStella adds
time_t currtime; time_t currtime;
time(&currtime); time(&currtime);
out << "; Disassembly of " << myOSystem.romFile() << "\n" out << "; Disassembly of " << FilesystemNode(myOSystem.romFile()).getShortPath() << "\n"
<< "; Disassembled " << ctime(&currtime) << "; Disassembled " << ctime(&currtime)
<< "; Using Stella " << STELLA_VERSION << "\n;\n" << "; Using Stella " << STELLA_VERSION << "\n;\n"
<< "; ROM properties name : " << myConsole.properties().get(Cartridge_Name) << "\n" << "; ROM properties name : " << myConsole.properties().get(Cartridge_Name) << "\n"
@ -1040,35 +1039,52 @@ string CartDebug::saveDisassembly()
<< "; P = PGFX directive, shown as '*' (stored in playfield)\n\n" << "; P = PGFX directive, shown as '*' (stored in playfield)\n\n"
<< " processor 6502\n\n"; << " processor 6502\n\n";
out << ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n" bool addrUsed = false;
<< "; TIA AND IO CONSTANTS\n"
<< ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n\n";
for(uInt16 addr = 0x00; addr <= 0x0F; ++addr) for(uInt16 addr = 0x00; addr <= 0x0F; ++addr)
if(myReserved.TIARead[addr] && ourTIAMnemonicR[addr]) addrUsed = addrUsed || myReserved.TIARead[addr];
out << ALIGN(6) << ourTIAMnemonicR[addr] << " = $"
<< HEX2 << right << addr << " ; (R)\n";
for(uInt16 addr = 0x00; addr <= 0x3F; ++addr) for(uInt16 addr = 0x00; addr <= 0x3F; ++addr)
if(myReserved.TIAWrite[addr] && ourTIAMnemonicW[addr]) addrUsed = addrUsed || myReserved.TIAWrite[addr];
out << ALIGN(6) << ourTIAMnemonicW[addr] << " = $"
<< HEX2 << right << addr << " ; (W)\n";
for(uInt16 addr = 0x00; addr <= 0x17; ++addr) for(uInt16 addr = 0x00; addr <= 0x17; ++addr)
if(myReserved.IOReadWrite[addr] && ourIOMnemonic[addr]) addrUsed = addrUsed || myReserved.IOReadWrite[addr];
out << ALIGN(6) << ourIOMnemonic[addr] << " = $" if(addrUsed)
<< HEX4 << right << (addr+0x280) << "\n";
out << "\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
<< "; RIOT RAM (zero-page)\n"
<< ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n\n";
for(uInt16 addr = 0x80; addr <= 0xFF; ++addr)
{ {
if(myReserved.ZPRAM[addr-0x80] && out << ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
myUserLabels.find(addr) == myUserLabels.end()) << "; TIA AND IO CONSTANTS\n"
<< ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n\n";
for(uInt16 addr = 0x00; addr <= 0x0F; ++addr)
if(myReserved.TIARead[addr] && ourTIAMnemonicR[addr])
out << ALIGN(6) << ourTIAMnemonicR[addr] << " = $"
<< HEX2 << right << addr << " ; (R)\n";
for(uInt16 addr = 0x00; addr <= 0x3F; ++addr)
if(myReserved.TIAWrite[addr] && ourTIAMnemonicW[addr])
out << ALIGN(6) << ourTIAMnemonicW[addr] << " = $"
<< HEX2 << right << addr << " ; (W)\n";
for(uInt16 addr = 0x00; addr <= 0x17; ++addr)
if(myReserved.IOReadWrite[addr] && ourIOMnemonic[addr])
out << ALIGN(6) << ourIOMnemonic[addr] << " = $"
<< HEX4 << right << (addr+0x280) << "\n";
}
addrUsed = false;
for(uInt16 addr = 0x80; addr <= 0xFF; ++addr)
addrUsed = addrUsed || myReserved.ZPRAM[addr-0x80];
if(addrUsed)
{
out << "\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
<< "; RIOT RAM (zero-page)\n"
<< ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n\n";
for(uInt16 addr = 0x80; addr <= 0xFF; ++addr)
{ {
out << ALIGN(6) << ourZPMnemonic[addr-0x80] << " = $" if(myReserved.ZPRAM[addr-0x80] &&
<< HEX2 << right << (addr) << "\n"; myUserLabels.find(addr) == myUserLabels.end())
{
out << ALIGN(6) << ourZPMnemonic[addr-0x80] << " = $"
<< HEX2 << right << (addr) << "\n";
}
} }
} }
AddrToLabel::const_iterator iter;
if(myReserved.Label.size() > 0) if(myReserved.Label.size() > 0)
{ {
out << "\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n" out << "\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"

View File

@ -299,6 +299,7 @@ class CartDebug : public DebuggerSystem
DirectiveList directiveList; // overrides for automatic code determination DirectiveList directiveList; // overrides for automatic code determination
BankInfo() : start(0), end(0), offset(0), size(0) { } BankInfo() : start(0), end(0), offset(0), size(0) { }
#if 0
friend ostream& operator<<(ostream& os, const BankInfo& b) friend ostream& operator<<(ostream& os, const BankInfo& b)
{ {
os << "start=$" << HEX4 << b.start << ", end=$" << HEX4 << b.end os << "start=$" << HEX4 << b.start << ", end=$" << HEX4 << b.end
@ -310,6 +311,7 @@ class CartDebug : public DebuggerSystem
os << HEX4 << *i << " "; os << HEX4 << *i << " ";
return os; return os;
} }
#endif
}; };
// Address type information determined by Distella // Address type information determined by Distella