mirror of https://github.com/stella-emu/stella.git
A new BIOS has been added to the Supercharger emulation based on code
from Eckhard Stolberg. This version simulates the progress bar and leaves the TIA in a state more like the real thing. This fixes some display problems with games (e.g., Mindmaster). In addtion, the bank switching and RAM writing emulation has been improved. git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@63 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
This commit is contained in:
bwmott
parent
5898941bf0
commit
62b7ae6038
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@ -8,12 +8,12 @@
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// SS SS tt ee ll ll aa aa
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// SSSS ttt eeeee llll llll aaaaa
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//
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// Copyright (c) 1995-1999 by Bradford W. Mott
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// Copyright (c) 1995-2002 by Bradford W. Mott
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//
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// See the file "license" for information on usage and redistribution of
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// this file, and for a DISCLAIMER OF ALL WARRANTIES.
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//
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// $Id: CartAR.cxx,v 1.1.1.1 2001-12-27 19:54:19 bwmott Exp $
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// $Id: CartAR.cxx,v 1.2 2002-04-05 02:18:23 bwmott Exp $
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//============================================================================
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#include <assert.h>
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@ -41,11 +41,8 @@ CartridgeAR::CartridgeAR(const uInt8* image, uInt32 size)
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myImage[i] = random.next();
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}
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// Initialize ROM with an invalid 6502 opcode
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for(i = 6 * 1024; i < 8 * 1024; ++i)
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{
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myImage[i] = 0xFF;
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}
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// Initialize SC BIOS ROM
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initializeROM();
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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@ -63,20 +60,16 @@ const char* CartridgeAR::name() const
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void CartridgeAR::reset()
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{
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// Try to load the first load into RAM upon reset
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loadIntoRAM(0);
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myPower = true;
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myPowerRomCycle = 0;
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myPowerRomCycle = mySystem->cycles();
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myWriteEnabled = false;
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myLastAccess = 0;
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myDataHoldRegister = 0;
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myNumberOfDistinctAccesses = 0;
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myWritePending = false;
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// Set bank configuration upon reset so ROM is selected
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myImageOffset[0] = 0 * 2048;
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myImageOffset[1] = 3 * 2048;
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// Set bank configuration upon reset so ROM is selected and powered up
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bankConfiguration(0);
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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@ -116,49 +109,30 @@ void CartridgeAR::install(System& system)
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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uInt8 CartridgeAR::peek(uInt16 addr)
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{
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// Check to see if the Supercharger ROM is being accessed?
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if(myImageOffset[1] == 3 * 2048)
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// Is the "dummy" SC BIOS hotspot for reading a load being accessed?
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if(((addr & 0x1FFF) == 0x1850) && (myImageOffset[1] == (3 * 2048)))
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{
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Int32 cycles = mySystem->cycles();
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// Get load that's being accessed (BIOS places load number at 0x80)
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uInt8 load = mySystem->peek(0x0080);
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// Is the tape rewind routine being accessed?
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if((addr & 0x1FFF) == 0x180A)
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{
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// See if the ROM has been powered up long enough
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if(!myPower || (myPower && ((myPowerRomCycle + 7) > cycles)))
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{
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cerr << "ERROR: Supercharger ROM has not been powered up!\n";
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}
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else
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{
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cerr << "ERROR: Supercharger code doesn't handle rewinding tape!\n";
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}
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}
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// Is the multiload routine being accessed?
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else if((addr & 0x1FFF) == 0x1800)
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{
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// See if the ROM has been powered up long enough
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if(!myPower || (myPower && ((myPowerRomCycle + 7) > cycles)))
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{
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cerr << "ERROR: Supercharger ROM has not been powered up!\n";
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}
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else
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{
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// Get the load they're trying to access
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uInt8 load = mySystem->peek(0x00FA);
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// Read the specified load into RAM
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loadIntoRAM(load);
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// Load the specified load into RAM
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loadIntoRAM(load);
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return myImage[(addr & 0x07FF) + myImageOffset[1]];
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}
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}
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return myImage[(addr & 0x07FF) + myImageOffset[1]];
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}
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// Are the "value" registers being accessed?
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// Cancel any pending write if more than 5 distinct accesses have occurred
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// TODO: Modify to handle when the distinct counter wraps around...
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if(myWritePending &&
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(my6502->distinctAccesses() > myNumberOfDistinctAccesses + 5))
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{
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myWritePending = false;
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}
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// Is the data hold register being set?
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if(!(addr & 0x0F00) && (!myWriteEnabled || !myWritePending))
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{
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myLastAccess = addr;
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myDataHoldRegister = addr;
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myNumberOfDistinctAccesses = my6502->distinctAccesses();
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myWritePending = true;
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}
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@ -167,22 +141,17 @@ uInt8 CartridgeAR::peek(uInt16 addr)
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{
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// Yes, so handle bank configuration
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myWritePending = false;
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bankConfiguration(myLastAccess);
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bankConfiguration(myDataHoldRegister);
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}
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// Handle poke if writing enabled
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else if(myWriteEnabled && myWritePending)
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else if(myWriteEnabled && myWritePending &&
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(my6502->distinctAccesses() == (myNumberOfDistinctAccesses + 5)))
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{
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if(my6502->distinctAccesses() >= myNumberOfDistinctAccesses + 5)
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{
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if(my6502->distinctAccesses() == myNumberOfDistinctAccesses + 5)
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{
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if((addr & 0x0800) == 0)
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myImage[(addr & 0x07FF) + myImageOffset[0]] = myLastAccess;
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else if(myImageOffset[1] != 3 * 2048) // Can't poke to ROM :-)
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myImage[(addr & 0x07FF) + myImageOffset[1]] = myLastAccess;
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}
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myWritePending = false;
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}
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if((addr & 0x0800) == 0)
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myImage[(addr & 0x07FF) + myImageOffset[0]] = myDataHoldRegister;
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else if(myImageOffset[1] != 3 * 2048) // Can't poke to ROM :-)
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myImage[(addr & 0x07FF) + myImageOffset[1]] = myDataHoldRegister;
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myWritePending = false;
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}
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return myImage[(addr & 0x07FF) + myImageOffset[(addr & 0x0800) ? 1 : 0]];
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@ -191,10 +160,18 @@ uInt8 CartridgeAR::peek(uInt16 addr)
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void CartridgeAR::poke(uInt16 addr, uInt8)
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{
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// Are the "value" registers being accessed?
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// Cancel any pending write if more than 5 distinct accesses have occurred
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// TODO: Modify to handle when the distinct counter wraps around...
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if(myWritePending &&
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(my6502->distinctAccesses() > myNumberOfDistinctAccesses + 5))
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{
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myWritePending = false;
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}
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// Is the data hold register being set?
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if(!(addr & 0x0F00) && (!myWriteEnabled || !myWritePending))
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{
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myLastAccess = addr;
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myDataHoldRegister = addr;
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myNumberOfDistinctAccesses = my6502->distinctAccesses();
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myWritePending = true;
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}
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@ -203,22 +180,17 @@ void CartridgeAR::poke(uInt16 addr, uInt8)
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{
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// Yes, so handle bank configuration
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myWritePending = false;
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bankConfiguration(myLastAccess);
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bankConfiguration(myDataHoldRegister);
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}
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// Handle poke if writing enabled
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else if(myWriteEnabled && myWritePending)
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else if(myWriteEnabled && myWritePending &&
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(my6502->distinctAccesses() == (myNumberOfDistinctAccesses + 5)))
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{
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if(my6502->distinctAccesses() >= myNumberOfDistinctAccesses + 5)
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{
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if(my6502->distinctAccesses() == myNumberOfDistinctAccesses + 5)
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{
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if((addr & 0x0800) == 0)
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myImage[(addr & 0x07FF) + myImageOffset[0]] = myLastAccess;
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else if(myImageOffset[1] != 3 * 2048) // Can't poke to ROM :-)
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myImage[(addr & 0x07FF) + myImageOffset[1]] = myLastAccess;
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}
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myWritePending = false;
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}
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if((addr & 0x0800) == 0)
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myImage[(addr & 0x07FF) + myImageOffset[0]] = myDataHoldRegister;
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else if(myImageOffset[1] != 3 * 2048) // Can't poke to ROM :-)
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myImage[(addr & 0x07FF) + myImageOffset[1]] = myDataHoldRegister;
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myWritePending = false;
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}
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}
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@ -314,45 +286,67 @@ void CartridgeAR::bankConfiguration(uInt8 configuration)
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void CartridgeAR::setupROM()
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void CartridgeAR::initializeROM()
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{
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static uInt8 dummyROMCode[] = {
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0xa9, 0x0, 0xa2, 0x0, 0x95, 0x80, 0xe8, 0xe0,
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0x80, 0xd0, 0xf9, 0x4c, 0x2b, 0xfa, 0xff, 0xff,
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0xa5, 0xfa, 0x85, 0x80, 0x4c, 0x18, 0xf8, 0xff,
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0xff, 0xff, 0x78, 0xd8, 0xa0, 0x0, 0xa2, 0x0,
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0x94, 0x0, 0xe8, 0xd0, 0xfb, 0x4c, 0x50, 0xf8,
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0xa2, 0x0, 0xbd, 0x6, 0xf0, 0xad, 0xf8, 0xff,
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0xa2, 0x0, 0xad, 0x0, 0xf0, 0xea, 0xbd, 0x0,
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0xf7, 0xca, 0xd0, 0xf6, 0x4c, 0x50, 0xf8, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xa9, 0x0, 0xa2, 0x0, 0x95, 0x80, 0xe8, 0xe0,
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0x1e, 0xd0, 0xf9, 0xa2, 0x0, 0xbd, 0x45, 0xfa,
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0x95, 0xfa, 0xe8, 0xe0, 0x6, 0xd0, 0xf6, 0xa2,
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0xff, 0xa0, 0x0, 0xa9, 0x0, 0x85, 0x80, 0xcd,
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0x0, 0xf0, 0x4c, 0xfa, 0x0, 0xad, 0xf8, 0xff,
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0x4c, 0x0, 0x0
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xa2, 0x3, 0xbc, 0x1d, 0xf9, 0x94, 0xfa, 0xca,
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0x10, 0xf8, 0xa0, 0x0, 0xa2, 0x28, 0x94, 0x4,
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0xca, 0x10, 0xfb, 0xa2, 0x1c, 0x94, 0x81, 0xca,
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0x10, 0xfb, 0xa9, 0x0, 0x85, 0x1b, 0x85, 0x1c,
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0x85, 0x1d, 0x85, 0x1e, 0x85, 0x1f, 0x85, 0x19,
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0x85, 0x1a, 0x85, 0x8, 0x85, 0x1, 0xa9, 0x10,
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0x85, 0x21, 0x85, 0x2, 0xa2, 0x7, 0xca, 0xca,
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0xd0, 0xfd, 0xa9, 0x0, 0x85, 0x20, 0x85, 0x10,
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0x85, 0x11, 0x85, 0x2, 0x85, 0x2a, 0xa9, 0x5,
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0x85, 0xa, 0xa9, 0xff, 0x85, 0xd, 0x85, 0xe,
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0x85, 0xf, 0x85, 0x84, 0x85, 0x85, 0xa9, 0xf0,
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0x85, 0x83, 0xa9, 0x74, 0x85, 0x9, 0xa9, 0xc,
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0x85, 0x15, 0xa9, 0x1f, 0x85, 0x17, 0x85, 0x82,
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0xa9, 0x7, 0x85, 0x19, 0xa2, 0x8, 0xa0, 0x0,
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0x85, 0x2, 0x88, 0xd0, 0xfb, 0x85, 0x2, 0x85,
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0x2, 0xa9, 0x2, 0x85, 0x2, 0x85, 0x0, 0x85,
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0x2, 0x85, 0x2, 0x85, 0x2, 0xa9, 0x0, 0x85,
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0x0, 0xca, 0x10, 0xe4, 0x6, 0x83, 0x66, 0x84,
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0x26, 0x85, 0xa5, 0x83, 0x85, 0xd, 0xa5, 0x84,
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0x85, 0xe, 0xa5, 0x85, 0x85, 0xf, 0xa6, 0x82,
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0xca, 0x86, 0x82, 0x86, 0x17, 0xe0, 0xa, 0xd0,
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0xc3, 0xa9, 0x2, 0x85, 0x1, 0xa2, 0x1c, 0xa0,
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0x0, 0x84, 0x19, 0x84, 0x9, 0x94, 0x81, 0xca,
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0x10, 0xfb, 0xa6, 0x80, 0xdd, 0x0, 0xf0, 0xa5,
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0x80, 0x45, 0xfe, 0x45, 0xff, 0xa2, 0xff, 0xa0,
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0x0, 0x9a, 0x4c, 0xfa, 0x0, 0xcd, 0xf8, 0xff,
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0x4c
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};
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int size = sizeof(dummyROMCode);
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uInt32 size = sizeof(dummyROMCode);
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// Copy the "dummy" ROM code into the ROM area
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for(int i = 0; i < size; ++i)
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// Initialize ROM with illegal 6502 opcode that causes a real 6502 to jam
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for(uInt32 i = 0; i < 2048; ++i)
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{
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myImage[0x1A00 + i] = dummyROMCode[i];
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myImage[3 * 2048 + i] = 0x02;
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}
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// Put a JMP $FA20 at multiload entry point ($F800)
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myImage[0x1800] = 0x4C;
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myImage[0x1801] = 0x20;
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myImage[0x1802] = 0xFA;
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// Copy the "dummy" Supercharger BIOS code into the ROM area
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for(uInt32 j = 0; j < size; ++j)
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{
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myImage[3 * 2048 + j] = dummyROMCode[j];
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}
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// Update ROM code to have the correct reset address and bank configuration
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myImage[0x1A00 + size - 2] = myHeader[0];
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myImage[0x1A00 + size - 1] = myHeader[1];
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myImage[0x1A00 + size - 11] = myHeader[2];
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myImage[0x1A00 + size - 15] = myHeader[2];
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// Finally set 6502 vectors to point to this "dummy" code at 0xFA00
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myImage[3 * 2048 + 2044] = 0x00;
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myImage[3 * 2048 + 2045] = 0xFA;
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myImage[3 * 2048 + 2046] = 0x00;
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myImage[3 * 2048 + 2047] = 0xFA;
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// Finally set 6502 vectors to point to initial load code at 0xF80A of BIOS
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myImage[3 * 2048 + 2044] = 0x0A;
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myImage[3 * 2048 + 2045] = 0xF8;
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myImage[3 * 2048 + 2046] = 0x0A;
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myImage[3 * 2048 + 2047] = 0xF8;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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@ -403,12 +397,19 @@ void CartridgeAR::loadIntoRAM(uInt8 load)
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invalidPageChecksumSeen = true;
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}
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// Copy page to Supercharger RAM
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memcpy(myImage + (bank * 2048) + (page * 256), src, 256);
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// Copy page to Supercharger RAM (don't allow a copy into ROM area)
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if(bank < 3)
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{
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memcpy(myImage + (bank * 2048) + (page * 256), src, 256);
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}
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}
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// Make sure the "dummy" ROM is installed
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setupROM();
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// Copy the bank switching byte and starting address into the 2600's
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// RAM for the "dummy" SC BIOS to access it
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mySystem->poke(0xfe, myHeader[0]);
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mySystem->poke(0xff, myHeader[1]);
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mySystem->poke(0x80, myHeader[2]);
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return;
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}
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}
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@ -8,12 +8,12 @@
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// SS SS tt ee ll ll aa aa
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// SSSS ttt eeeee llll llll aaaaa
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//
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// Copyright (c) 1995-1999 by Bradford W. Mott
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// Copyright (c) 1995-2002 by Bradford W. Mott
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//
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// See the file "license" for information on usage and redistribution of
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// this file, and for a DISCLAIMER OF ALL WARRANTIES.
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//
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// $Id: CartAR.hxx,v 1.1.1.1 2001-12-27 19:54:19 bwmott Exp $
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// $Id: CartAR.hxx,v 1.2 2002-04-05 02:18:23 bwmott Exp $
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//============================================================================
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#ifndef CARTRIDGEAR_HXX
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@ -28,13 +28,14 @@ class M6502High;
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/**
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This is the cartridge class for Arcadia (aka Starpath) Supercharger
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games. Christopher Salomon provided most of the technical details
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used in creating this class.
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used in creating this class. A good description of the Supercharger
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is provided in the Cuttle Cart's manual.
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The Supercharger has four 2K banks. There are three banks of RAM
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and one bank of ROM. All 6K of the RAM can be read and written.
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@author Bradford W. Mott
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@version $Id: CartAR.hxx,v 1.1.1.1 2001-12-27 19:54:19 bwmott Exp $
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@version $Id: CartAR.hxx,v 1.2 2002-04-05 02:18:23 bwmott Exp $
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*/
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class CartridgeAR : public Cartridge
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{
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@ -106,8 +107,8 @@ class CartridgeAR : public Cartridge
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// Load the specified load into SC RAM
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void loadIntoRAM(uInt8 load);
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// Sets up a "dummy" bootstrap ROM in the ROM bank of the cartridge
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void setupROM();
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// Sets up a "dummy" BIOS ROM in the ROM bank of the cartridge
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void initializeROM();
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private:
|
||||
// Pointer to the 6502 processor in the system
|
||||
|
|
@ -137,10 +138,10 @@ class CartridgeAR : public Cartridge
|
|||
// Indicates when the power was last turned on
|
||||
Int32 myPowerRomCycle;
|
||||
|
||||
// Indicates the "value" address which was accessed
|
||||
uInt16 myLastAccess;
|
||||
// Data hold register used for writing
|
||||
uInt8 myDataHoldRegister;
|
||||
|
||||
// Indicates the number of distinct accesses when "value" was set
|
||||
// Indicates number of distinct accesses when data hold register was set
|
||||
uInt32 myNumberOfDistinctAccesses;
|
||||
|
||||
// Indicates if a write is pending or not
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
Simple program that produces a hex list of a binary object file
|
||||
|
||||
@author Bradford W. Mott
|
||||
@version $Id: romtohex.cxx,v 1.1.1.1 2001-12-27 19:54:32 bwmott Exp $
|
||||
@version $Id: romtohex.cxx,v 1.2 2002-04-05 02:18:23 bwmott Exp $
|
||||
*/
|
||||
|
||||
#include <iomanip.h>
|
||||
|
|
@ -10,7 +10,9 @@
|
|||
|
||||
main()
|
||||
{
|
||||
ifstream in("rom.o");
|
||||
ifstream in("scrom.bin");
|
||||
|
||||
cout << " ";
|
||||
|
||||
for(int t = 0; ; ++t)
|
||||
{
|
||||
|
|
@ -23,7 +25,7 @@ main()
|
|||
cout << "0x" << hex << (int)c << ", ";
|
||||
|
||||
if((t % 8) == 7)
|
||||
cout << endl;
|
||||
cout << endl << " ";
|
||||
}
|
||||
cout << endl;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -8,74 +8,234 @@
|
|||
;; SS SS tt ee ll ll aa aa
|
||||
;; SSSS ttt eeeee llll llll aaaaa
|
||||
;;
|
||||
;; Copyright (c) 1995-1998 by Bradford W. Mott
|
||||
;; Copyright (c) 1995-2002 by Bradford W. Mott
|
||||
;;
|
||||
;; See the file "license" for information on usage and redistribution of
|
||||
;; this file, and for a DISCLAIMER OF ALL WARRANTIES.
|
||||
;;
|
||||
;; $Id: scrom.asm,v 1.1.1.1 2001-12-27 19:54:32 bwmott Exp $
|
||||
;; $Id: scrom.asm,v 1.2 2002-04-05 02:18:23 bwmott Exp $
|
||||
;;============================================================================
|
||||
;;
|
||||
;; This file contains a "dummy" Supercharger ROM for Stella. It basically
|
||||
;; contains some bootstrapping code to get the game up and running.
|
||||
;; This file contains a "dummy" Supercharger BIOS for Stella. It is based
|
||||
;; on routines developed by Eckhard Stolberg.
|
||||
;;
|
||||
;;============================================================================
|
||||
|
||||
processor 6502
|
||||
|
||||
org $FA00
|
||||
VSYNC equ $00
|
||||
VBLANK equ $01
|
||||
WSYNC equ $02
|
||||
COLUPF equ $08
|
||||
COLUBK equ $09
|
||||
CTRLPF equ $0a
|
||||
PF0 equ $0d
|
||||
PF1 equ $0e
|
||||
PF2 equ $0f
|
||||
RESP0 equ $10
|
||||
RESP1 equ $11
|
||||
AUDC0 equ $15
|
||||
AUDF0 equ $17
|
||||
AUDV0 equ $19
|
||||
AUDV1 equ $1a
|
||||
GRP0 equ $1b
|
||||
GRP1 equ $1c
|
||||
ENAM0 equ $1d
|
||||
ENAM1 equ $1e
|
||||
ENABL equ $1f
|
||||
HMP0 equ $20
|
||||
HMP1 equ $21
|
||||
HMOVE equ $2a
|
||||
|
||||
;;
|
||||
;; Entry point for multi-load reading
|
||||
;;
|
||||
org $F800
|
||||
|
||||
LDA $FA ; Grab the load number and store it in $80 where the
|
||||
STA $80 ; emulator will grab it when it does the loading
|
||||
JMP clrp7 ; Go clear page 7 of RAM bank 1 like the real SC
|
||||
|
||||
;;
|
||||
;; Normal clear page zero routine for initial program load
|
||||
;; Entry point for initial load (invoked when the system is reset)
|
||||
;;
|
||||
LDA #0
|
||||
LDX #0
|
||||
clear STA $80,X
|
||||
INX
|
||||
CPX #$80
|
||||
BNE clear
|
||||
JMP cpcode
|
||||
org $F80A
|
||||
|
||||
start SEI
|
||||
CLD
|
||||
|
||||
;;
|
||||
;; Clear page zero routine for multi-load
|
||||
;; Clear page zero routine for initial load (e.g., RAM and TIA registers)
|
||||
;;
|
||||
org $FA20
|
||||
|
||||
LDA #0
|
||||
LDX #0
|
||||
mlclr STA $80,X
|
||||
INX
|
||||
CPX #$1E
|
||||
BNE mlclr
|
||||
|
||||
;;
|
||||
;; Now, copy some code into page zero to do the initial bank switch
|
||||
;;
|
||||
cpcode LDX #0
|
||||
copy LDA code,X
|
||||
STA $fa,X
|
||||
INX
|
||||
CPX #6
|
||||
BNE copy
|
||||
|
||||
;;
|
||||
;; Initialize X and Y registers
|
||||
;;
|
||||
LDX #$ff
|
||||
LDY #$00
|
||||
LDX #$00
|
||||
ilclr STY $00,X
|
||||
INX
|
||||
BNE ilclr
|
||||
|
||||
JMP load
|
||||
|
||||
;;
|
||||
;; Store the bank configuration in $80 and in CMP instruction
|
||||
;; Clear page 7 of RAM bank 1 (used for stars in the real SC)
|
||||
;;
|
||||
LDA #$00 ;; $00 is changed by emulator to the correct value
|
||||
STA $80
|
||||
clrp7 LDX #$00
|
||||
LDA $F006,X
|
||||
LDA $FFF8
|
||||
LDX #$00
|
||||
mlclr3 LDA $F000
|
||||
NOP
|
||||
LDA $F700,X
|
||||
DEX
|
||||
BNE mlclr3
|
||||
JMP load
|
||||
|
||||
;;
|
||||
;; NOTE: The emulator does the actual reading of the new load when the
|
||||
;; next instruction is accessed. The emulator expects the load number to
|
||||
;; to be stored in location $80. As a side-effect the emulator sets $80
|
||||
;; to contain the bank selection byte from the load's header and sets
|
||||
;; $FE and $FF to contain the starting address from the load's header.
|
||||
;;
|
||||
load org $F850
|
||||
|
||||
;;
|
||||
;; Copy code into page zero to do the bank switching
|
||||
;;
|
||||
LDX #$03
|
||||
copy LDY code,X
|
||||
STY $FA,X
|
||||
DEX
|
||||
BPL copy
|
||||
|
||||
;;
|
||||
;; Clear some of the 2600's RAM and TIA registers like the real SC BIOS does
|
||||
;;
|
||||
LDY #$00
|
||||
LDX #$28
|
||||
mlclr1 STY $04,X
|
||||
DEX
|
||||
BPL mlclr1
|
||||
|
||||
LDX #$1C
|
||||
mlclr2 STY $81,X
|
||||
DEX
|
||||
BPL mlclr2
|
||||
|
||||
;;
|
||||
;; Display the "emulated" Supercharger loading progress bar
|
||||
;;
|
||||
LDA #$00
|
||||
STA GRP0
|
||||
STA GRP1
|
||||
STA ENAM0
|
||||
STA ENAM1
|
||||
STA ENABL
|
||||
STA AUDV0
|
||||
STA AUDV1
|
||||
STA COLUPF
|
||||
STA VBLANK
|
||||
|
||||
LDA #$10
|
||||
STA HMP1
|
||||
STA WSYNC
|
||||
LDX #$07
|
||||
DEX
|
||||
pos DEX
|
||||
BNE pos
|
||||
LDA #$00
|
||||
STA HMP0
|
||||
STA RESP0
|
||||
STA RESP1
|
||||
STA WSYNC
|
||||
STA HMOVE
|
||||
|
||||
LDA #%00000101
|
||||
STA CTRLPF
|
||||
LDA #$FF
|
||||
STA PF0
|
||||
STA PF1
|
||||
STA PF2
|
||||
STA $84
|
||||
STA $85
|
||||
LDA #$F0
|
||||
STA $83
|
||||
LDA #$74
|
||||
STA COLUBK
|
||||
LDA #$0C
|
||||
STA AUDC0
|
||||
LDA #$1F
|
||||
STA AUDF0
|
||||
STA $82
|
||||
LDA #$07
|
||||
STA AUDV0
|
||||
a1
|
||||
LDX #$08
|
||||
LDY #$00
|
||||
a2
|
||||
STA WSYNC
|
||||
DEY
|
||||
BNE a2
|
||||
STA WSYNC
|
||||
STA WSYNC
|
||||
LDA #$02
|
||||
STA WSYNC
|
||||
STA VSYNC
|
||||
STA WSYNC
|
||||
STA WSYNC
|
||||
STA WSYNC
|
||||
LDA #$00
|
||||
STA VSYNC
|
||||
DEX
|
||||
BPL a2
|
||||
ASL $83
|
||||
ROR $84
|
||||
ROL $85
|
||||
LDA $83
|
||||
STA PF0
|
||||
LDA $84
|
||||
STA PF1
|
||||
LDA $85
|
||||
STA PF2
|
||||
LDX $82
|
||||
DEX
|
||||
STX $82
|
||||
STX AUDF0
|
||||
CPX #$0A
|
||||
BNE a1
|
||||
|
||||
LDA #%00000010
|
||||
STA VBLANK
|
||||
|
||||
LDX #$1C
|
||||
LDY #$00
|
||||
STY AUDV0
|
||||
STY COLUBK
|
||||
clear:
|
||||
STY $81,x
|
||||
DEX
|
||||
BPL clear
|
||||
|
||||
;;
|
||||
;; Setup value to be stored in the bank switching control register
|
||||
;;
|
||||
LDX $80
|
||||
CMP $F000,X
|
||||
|
||||
;;
|
||||
;; Initialize A, X, Y, and SP registers
|
||||
;;
|
||||
LDA $80
|
||||
EOR $FE
|
||||
EOR $FF
|
||||
LDX #$FF
|
||||
LDY #$00
|
||||
TXS
|
||||
|
||||
CMP $f000 ;; $00 is changed by emulator to the correct value
|
||||
;;
|
||||
;; Execute the code to do bank switch and start running cartridge code
|
||||
;;
|
||||
JMP $fa
|
||||
JMP $FA
|
||||
|
||||
code dc.b $ad, $f8, $ff ;; LDA $fff8
|
||||
dc.b $4c, $00, $00 ;; JMP $???? ($???? is filled in by emulator)
|
||||
code dc.b $cd, $f8, $ff ;; CMP $fff8
|
||||
dc.b $4c ;; JMP $????
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue