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2nd part of Distella updates

This commit is contained in:
thrust26 2017-09-15 14:56:54 +02:00
parent 78d73976dc
commit 5f68b0565d
10 changed files with 1149 additions and 739 deletions
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88
src/debugger/CartDebug.cxx
View File

@ -82,8 +82,9 @@ CartDebug::CartDebug(Debugger& dbg, Console& console, const OSystem& osystem)
myBankInfo.push_back(info); myBankInfo.push_back(info);
// We know the address for the startup bank right now // We know the address for the startup bank right now
myBankInfo[myConsole.cartridge().startBank()].addressList.push_back(myDebugger.dpeek(0xfffc)); myBankInfo[myConsole.cartridge().startBank()].addressList.push_front(myDebugger.dpeek(0xfffc));
addLabel("START", myDebugger.dpeek(0xfffc)); addLabel("Start", myDebugger.dpeek(0xfffc, DATA));
addLabel("Break", myDebugger.dpeek(0xfffe));
// Add system equates // Add system equates
for(uInt16 addr = 0x00; addr <= 0x0F; ++addr) for(uInt16 addr = 0x00; addr <= 0x0F; ++addr)
@ -114,16 +115,17 @@ CartDebug::CartDebug(Debugger& dbg, Console& console, const OSystem& osystem)
myDisassembly.list.reserve(2048); myDisassembly.list.reserve(2048);
// Add settings for Distella // Add settings for Distella
DiStella::settings.gfx_format = DiStella::settings.gfxFormat =
myOSystem.settings().getInt("dis.gfxformat") == 16 ? Base::F_16 : Base::F_2; myOSystem.settings().getInt("dis.gfxformat") == 16 ? Base::F_16 : Base::F_2;
DiStella::settings.resolve_code = DiStella::settings.resolveCode =
myOSystem.settings().getBool("dis.resolve"); myOSystem.settings().getBool("dis.resolve");
DiStella::settings.show_addresses = DiStella::settings.showAddresses =
myOSystem.settings().getBool("dis.showaddr"); myOSystem.settings().getBool("dis.showaddr");
DiStella::settings.aflag = false; // Not currently configurable DiStella::settings.aFlag = false; // Not currently configurable
DiStella::settings.fflag = true; // Not currently configurable DiStella::settings.fFlag = true; // Not currently configurable
DiStella::settings.rflag = myOSystem.settings().getBool("dis.relocate"); DiStella::settings.rFlag = myOSystem.settings().getBool("dis.relocate");
DiStella::settings.bwidth = 9; // TODO - configure based on window size DiStella::settings.bFlag = true; // Not currently configurable
DiStella::settings.bytesWidth = 8+1; // TODO - configure based on window size
} }
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
@ -263,34 +265,28 @@ bool CartDebug::disassemble(bool force)
// Only add addresses when absolutely necessary, to cut down on the // Only add addresses when absolutely necessary, to cut down on the
// work that Distella has to do // work that Distella has to do
// Distella expects the addresses to be unique and in sorted order
if(bankChanged || !pcfound) if(bankChanged || !pcfound)
{ {
AddressList::const_iterator i; AddressList::const_iterator i;
for(i = addresses.cbegin(); i != addresses.cend(); ++i) for(i = addresses.cbegin(); i != addresses.cend(); ++i)
{ {
if(PC < *i) if (PC == *i) // already present
{
addresses.insert(i, PC);
break;
}
else if(PC == *i) // already present
break; break;
} }
// Otherwise, add the item at the end // Otherwise, add the item at the end
if(i == addresses.end()) if (i == addresses.end())
addresses.push_back(PC); addresses.push_back(PC);
} }
// Always attempt to resolve code sections unless it's been // Always attempt to resolve code sections unless it's been
// specifically disabled // specifically disabled
bool found = fillDisassemblyList(info, PC); bool found = fillDisassemblyList(info, PC);
if(!found && DiStella::settings.resolve_code) if(!found && DiStella::settings.resolveCode)
{ {
// Temporarily turn off code resolution // Temporarily turn off code resolution
DiStella::settings.resolve_code = false; DiStella::settings.resolveCode = false;
fillDisassemblyList(info, PC); fillDisassemblyList(info, PC);
DiStella::settings.resolve_code = true; DiStella::settings.resolveCode = true;
} }
} }
@ -973,20 +969,21 @@ string CartDebug::saveDisassembly()
// We can't print the header to the disassembly until it's actually // We can't print the header to the disassembly until it's actually
// been processed; therefore buffer output to a string first // been processed; therefore buffer output to a string first
ostringstream buf; ostringstream buf;
buf << "\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n;\n" buf << "\n\n;***********************************************************\n"
<< "; MAIN PROGRAM\n" << "; Program Code + Data\n"
<< ";\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n\n"; << ";***********************************************************\n\n";
// Use specific settings for disassembly output // Use specific settings for disassembly output
// This will most likely differ from what you see in the debugger // This will most likely differ from what you see in the debugger
DiStella::Settings settings; DiStella::Settings settings;
settings.gfx_format = DiStella::settings.gfx_format; settings.gfxFormat = DiStella::settings.gfxFormat;
settings.resolve_code = true; settings.resolveCode = true;
settings.show_addresses = false; settings.showAddresses = false;
settings.aflag = false; // Otherwise DASM gets confused settings.aFlag = false; // Otherwise DASM gets confused
settings.fflag = DiStella::settings.fflag; settings.fFlag = DiStella::settings.fFlag;
settings.rflag = DiStella::settings.rflag; settings.rFlag = DiStella::settings.rFlag;
settings.bwidth = 8+1; // same as Stella debugger settings.bytesWidth = 8+1; // same as Stella debugger
settings.bFlag = DiStella::settings.bFlag;; // process break routine (TODO)
Disassembly disasm; Disassembly disasm;
disasm.list.reserve(2048); disasm.list.reserve(2048);
@ -1002,6 +999,9 @@ string CartDebug::saveDisassembly()
DiStella distella(*this, disasm.list, info, settings, DiStella distella(*this, disasm.list, info, settings,
myDisLabels, myDisDirectives, myReserved); myDisLabels, myDisDirectives, myReserved);
//if (myReserved.breakFound)
// addLabel("BREAK", myDebugger.dpeek(0xfffe));
buf << " SEG CODE\n" buf << " SEG CODE\n"
<< " ORG $" << Base::HEX4 << info.offset << "\n\n"; << " ORG $" << Base::HEX4 << info.offset << "\n\n";
@ -1031,7 +1031,7 @@ string CartDebug::saveDisassembly()
} }
case CartDebug::GFX: case CartDebug::GFX:
{ {
buf << ".byte " << (settings.gfx_format == Base::F_2 ? "%" : "$") buf << ".byte " << (settings.gfxFormat == Base::F_2 ? "%" : "$")
<< tag.bytes << " ; |"; << tag.bytes << " ; |";
for(int c = 12; c < 20; ++c) for(int c = 12; c < 20; ++c)
buf << ((tag.disasm[c] == '\x1e') ? "#" : " "); buf << ((tag.disasm[c] == '\x1e') ? "#" : " ");
@ -1040,7 +1040,7 @@ string CartDebug::saveDisassembly()
} }
case CartDebug::PGFX: case CartDebug::PGFX:
{ {
buf << ".byte " << (settings.gfx_format == Base::F_2 ? "%" : "$") buf << ".byte " << (settings.gfxFormat == Base::F_2 ? "%" : "$")
<< tag.bytes << " ; |"; << tag.bytes << " ; |";
for(int c = 12; c < 20; ++c) for(int c = 12; c < 20; ++c)
buf << ((tag.disasm[c] == '\x1f') ? "*" : " "); buf << ((tag.disasm[c] == '\x1f') ? "*" : " ");
@ -1087,9 +1087,9 @@ string CartDebug::saveDisassembly()
addrUsed = addrUsed || myReserved.IOReadWrite[addr]; addrUsed = addrUsed || myReserved.IOReadWrite[addr];
if(addrUsed) if(addrUsed)
{ {
out << ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n" out << "\n;-----------------------------------------------------------\n"
<< "; TIA AND IO CONSTANTS\n" << "; TIA and IO constants accessed\n"
<< ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n\n"; << ";-----------------------------------------------------------\n\n";
for(uInt16 addr = 0x00; addr <= 0x0F; ++addr) for(uInt16 addr = 0x00; addr <= 0x0F; ++addr)
if(myReserved.TIARead[addr] && ourTIAMnemonicR[addr]) if(myReserved.TIARead[addr] && ourTIAMnemonicR[addr])
out << ALIGN(16) << ourTIAMnemonicR[addr] << "= $" out << ALIGN(16) << ourTIAMnemonicR[addr] << "= $"
@ -1109,9 +1109,9 @@ string CartDebug::saveDisassembly()
addrUsed = addrUsed || myReserved.ZPRAM[addr-0x80]; addrUsed = addrUsed || myReserved.ZPRAM[addr-0x80];
if(addrUsed) if(addrUsed)
{ {
out << "\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n" out << "\n\n;-----------------------------------------------------------\n"
<< "; RIOT RAM (zero-page)\n" << "; RIOT RAM (zero-page) labels\n"
<< ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n\n"; << ";-----------------------------------------------------------\n\n";
for(uInt16 addr = 0x80; addr <= 0xFF; ++addr) for(uInt16 addr = 0x80; addr <= 0xFF; ++addr)
{ {
if(myReserved.ZPRAM[addr-0x80] && if(myReserved.ZPRAM[addr-0x80] &&
@ -1125,18 +1125,18 @@ string CartDebug::saveDisassembly()
if(myReserved.Label.size() > 0) if(myReserved.Label.size() > 0)
{ {
out << "\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n" out << "\n\n;-----------------------------------------------------------\n"
<< "; NON LOCATABLE\n" << "; Non Locatable Labels\n"
<< ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n\n"; << ";-----------------------------------------------------------\n\n";
for(const auto& iter: myReserved.Label) for(const auto& iter: myReserved.Label)
out << ALIGN(16) << iter.second << "= $" << iter.first << "\n"; out << ALIGN(16) << iter.second << "= $" << iter.first << "\n";
} }
if(myUserLabels.size() > 0) if(myUserLabels.size() > 0)
{ {
out << "\n;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n" out << "\n\n;-----------------------------------------------------------\n"
<< "; USER DEFINED\n" << "; User Defined Labels\n"
<< ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n\n"; << ";-----------------------------------------------------------\n\n";
int max_len = 16; int max_len = 16;
for(const auto& iter: myUserLabels) for(const auto& iter: myUserLabels)
max_len = std::max(max_len, int(iter.second.size())); max_len = std::max(max_len, int(iter.second.size()));

17
src/debugger/CartDebug.hxx
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@ -52,9 +52,9 @@ class CartDebug : public DebuggerSystem
public: public:
enum DisasmType { enum DisasmType {
NONE = 0, NONE = 0,
REFERENCED = 1 << 0, /* code somewhere in the program references it, REFERENCED = 1 << 0, /* 0x01, code somewhere in the program references it,
i.e. LDA $F372 referenced $F372 */ i.e. LDA $F372 referenced $F372 */
VALID_ENTRY = 1 << 1, /* addresses that can have a label placed in front of it. VALID_ENTRY = 1 << 1, /* 0x02, addresses that can have a label placed in front of it.
A good counterexample would be "FF00: LDA $FE00"; $FF01 A good counterexample would be "FF00: LDA $FE00"; $FF01
would be in the middle of a multi-byte instruction, and would be in the middle of a multi-byte instruction, and
therefore cannot be labelled. */ therefore cannot be labelled. */
@ -63,12 +63,12 @@ class CartDebug : public DebuggerSystem
// debugger, or specified in a Distella cfg file, and are listed in order // debugger, or specified in a Distella cfg file, and are listed in order
// of decreasing hierarchy // of decreasing hierarchy
// //
CODE = 1 << 7, // disassemble-able code segments CODE = 1 << 7, // 0x80, disassemble-able code segments
TCODE = 1 << 6, // (tentative) disassemble-able code segments TCODE = 1 << 6, // 0x40, (tentative) disassemble-able code segments
GFX = 1 << 5, // addresses loaded into GRPx registers GFX = 1 << 5, // 0x20, addresses loaded into GRPx registers
PGFX = 1 << 4, // addresses loaded into PFx registers PGFX = 1 << 4, // 0x10, addresses loaded into PFx registers
DATA = 1 << 3, // addresses loaded into registers other than GRPx / PFx DATA = 1 << 3, // 0x08, addresses loaded into registers other than GRPx / PFx
ROW = 1 << 2 // all other addresses ROW = 1 << 2 // 0x04, all other addresses
}; };
struct DisassemblyTag { struct DisassemblyTag {
DisasmType type; DisasmType type;
@ -317,6 +317,7 @@ class CartDebug : public DebuggerSystem
bool IOReadWrite[24]; bool IOReadWrite[24];
bool ZPRAM[128]; bool ZPRAM[128];
AddrToLabel Label; AddrToLabel Label;
bool breakFound;
}; };
ReservedEquates myReserved; ReservedEquates myReserved;

4
src/debugger/Debugger.hxx
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@ -206,8 +206,8 @@ class Debugger : public DialogContainer
static Debugger& debugger() { return *myStaticDebugger; } static Debugger& debugger() { return *myStaticDebugger; }
/* These are now exposed so Expressions can use them. */ /* These are now exposed so Expressions can use them. */
int peek(int addr) { return mySystem.peek(addr); } int peek(int addr, uInt8 flags = 0) { return mySystem.peek(addr, flags); }
int dpeek(int addr) { return mySystem.peek(addr) | (mySystem.peek(addr+1) << 8); } int dpeek(int addr, uInt8 flags = 0) { return mySystem.peek(addr, flags) | (mySystem.peek(addr+1, flags) << 8); }
int getAccessFlags(uInt16 addr) const int getAccessFlags(uInt16 addr) const
{ return mySystem.getAccessFlags(addr); } { return mySystem.getAccessFlags(addr); }
void setAccessFlags(uInt16 addr, uInt8 flags) void setAccessFlags(uInt16 addr, uInt8 flags)

919
src/debugger/DiStella.cxx
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File diff suppressed because it is too large Load Diff

24
src/debugger/DiStella.hxx
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@ -42,13 +42,14 @@ class DiStella
// This will eventually grow to include all options supported by // This will eventually grow to include all options supported by
// standalone Distella // standalone Distella
struct Settings { struct Settings {
Common::Base::Format gfx_format; Common::Base::Format gfxFormat;
bool resolve_code; // Attempt to detect code vs. data sections bool resolveCode; // Attempt to detect code vs. data sections
bool show_addresses; // Show PC addresses (always off for external output) bool showAddresses; // Show PC addresses (always off for external output)
bool aflag; // Turns 'A' off in accumulator instructions (-a in Distella) bool aFlag; // Turns 'A' off in accumulator instructions (-a in Distella)
bool fflag; // Forces correct address length (-f in Distella) bool fFlag; // Forces correct address length (-f in Distella)
bool rflag; // Relocate calls out of address range (-r in Distella) bool rFlag; // Relocate calls out of address range (-r in Distella)
int bwidth; // Number of bytes to use per line (with .byte xxx) bool bFlag; // Process break routine (-b in Distella)
int bytesWidth; // Number of bytes to use per line (with .byte xxx)
}; };
static Settings settings; // Default settings static Settings settings; // Default settings
@ -81,11 +82,13 @@ class DiStella
// These functions are part of the original Distella code // These functions are part of the original Distella code
void disasm(uInt32 distart, int pass); void disasm(uInt32 distart, int pass);
void disasmPass1(uInt32 distart);
bool check_range(uInt16 start, uInt16 end) const; bool check_range(uInt16 start, uInt16 end) const;
int mark(uInt32 address, uInt8 mask, bool directive = false); int mark(uInt32 address, uInt8 mask, bool directive = false);
bool checkBit(uInt16 address, uInt8 mask) const; bool checkBit(uInt16 address, uInt8 mask, bool useDebugger = true) const;
bool DiStella::checkBits(uInt16 address, uInt8 mask, uInt8 notMask) const; bool checkBits(uInt16 address, uInt8 mask, uInt8 notMask, bool useDebugger = true) const;
void outputGraphics(); void outputGraphics();
void outputBytes(CartDebug::DisasmType type); void outputBytes(CartDebug::DisasmType type);
@ -118,7 +121,7 @@ class DiStella
CartDebug::ReservedEquates& myReserved; CartDebug::ReservedEquates& myReserved;
stringstream myDisasmBuf; stringstream myDisasmBuf;
std::queue<uInt16> myAddressQueue; std::queue<uInt16> myAddressQueue;
uInt16 myOffset, myPC, myPCEnd, myPass; uInt16 myOffset, myPC, myPCEnd;
uInt16 mySegType; uInt16 mySegType;
struct resource { struct resource {
@ -184,6 +187,7 @@ class DiStella
AccessMode source; AccessMode source;
ReadWriteMode rw_mode; ReadWriteMode rw_mode;
uInt8 cycles; uInt8 cycles;
uInt8 bytes;
}; };
static const Instruction_tag ourLookup[256]; static const Instruction_tag ourLookup[256];

2
src/debugger/gui/RomListWidget.cxx
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@ -582,7 +582,7 @@ void RomListWidget::startEditMode()
{ {
case CartDebug::GFX: case CartDebug::GFX:
case CartDebug::PGFX: case CartDebug::PGFX:
_base = DiStella::settings.gfx_format; _base = DiStella::settings.gfxFormat;
break; break;
default: default:
_base = Common::Base::format(); _base = Common::Base::format();

16
src/debugger/gui/RomWidget.cxx
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@ -122,18 +122,18 @@ void RomWidget::handleCommand(CommandSender* sender, int cmd, int data, int id)
case RomListWidget::kTentativeCodeCmd: case RomListWidget::kTentativeCodeCmd:
{ {
// 'data' is the boolean value // 'data' is the boolean value
DiStella::settings.resolve_code = data; DiStella::settings.resolveCode = data;
instance().settings().setValue("dis.resolve", instance().settings().setValue("dis.resolve",
DiStella::settings.resolve_code); DiStella::settings.resolveCode);
invalidate(); invalidate();
break; break;
} }
case RomListWidget::kPCAddressesCmd: case RomListWidget::kPCAddressesCmd:
// 'data' is the boolean value // 'data' is the boolean value
DiStella::settings.show_addresses = data; DiStella::settings.showAddresses = data;
instance().settings().setValue("dis.showaddr", instance().settings().setValue("dis.showaddr",
DiStella::settings.show_addresses); DiStella::settings.showAddresses);
invalidate(); invalidate();
break; break;
@ -141,12 +141,12 @@ void RomWidget::handleCommand(CommandSender* sender, int cmd, int data, int id)
// 'data' is the boolean value // 'data' is the boolean value
if(data) if(data)
{ {
DiStella::settings.gfx_format = Common::Base::F_2; DiStella::settings.gfxFormat = Common::Base::F_2;
instance().settings().setValue("dis.gfxformat", "2"); instance().settings().setValue("dis.gfxformat", "2");
} }
else else
{ {
DiStella::settings.gfx_format = Common::Base::F_16; DiStella::settings.gfxFormat = Common::Base::F_16;
instance().settings().setValue("dis.gfxformat", "16"); instance().settings().setValue("dis.gfxformat", "16");
} }
invalidate(); invalidate();
@ -154,9 +154,9 @@ void RomWidget::handleCommand(CommandSender* sender, int cmd, int data, int id)
case RomListWidget::kAddrRelocationCmd: case RomListWidget::kAddrRelocationCmd:
// 'data' is the boolean value // 'data' is the boolean value
DiStella::settings.rflag = data; DiStella::settings.rFlag = data;
instance().settings().setValue("dis.relocate", instance().settings().setValue("dis.relocate",
DiStella::settings.rflag); DiStella::settings.rFlag);
invalidate(); invalidate();
break; break;
} }

558
src/emucore/M6502.ins
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File diff suppressed because it is too large Load Diff

244
src/emucore/M6502.m4
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@ -38,7 +38,7 @@
#ifndef CLEAR_LAST_PEEK #ifndef CLEAR_LAST_PEEK
#ifdef DEBUGGER_SUPPORT #ifdef DEBUGGER_SUPPORT
#define CLEAR_LAST_PEEK(_addr) _addr = -1; #define CLEAR_LAST_PEEK(_addr) _addr = 0;
#else #else
#define CLEAR_LAST_PEEK(_addr) #define CLEAR_LAST_PEEK(_addr)
#endif #endif
@ -83,25 +83,29 @@ define(M6502_ABSOLUTEX_READ, `{
uInt16 low = peek(PC++, DISASM_CODE); uInt16 low = peek(PC++, DISASM_CODE);
uInt16 high = (uInt16(peek(PC++, DISASM_CODE)) << 8); uInt16 high = (uInt16(peek(PC++, DISASM_CODE)) << 8);
intermediateAddress = high | uInt8(low + X); intermediateAddress = high | uInt8(low + X);
operand = peek(intermediateAddress, DISASM_DATA);
if((low + X) > 0xFF) if((low + X) > 0xFF)
{ {
operand = peek(intermediateAddress, DISASM_NONE);
intermediateAddress = (high | low) + X; intermediateAddress = (high | low) + X;
operand = peek(intermediateAddress, DISASM_DATA); operand = peek(intermediateAddress, DISASM_DATA);
} }
else
{
operand = peek(intermediateAddress, DISASM_DATA);
}
}') }')
define(M6502_ABSOLUTEX_WRITE, `{ define(M6502_ABSOLUTEX_WRITE, `{
uInt16 low = peek(PC++, DISASM_CODE); uInt16 low = peek(PC++, DISASM_CODE);
uInt16 high = (uInt16(peek(PC++, DISASM_CODE)) << 8); uInt16 high = (uInt16(peek(PC++, DISASM_CODE)) << 8);
peek(high | uInt8(low + X), DISASM_DATA); peek(high | uInt8(low + X), DISASM_NONE);
operandAddress = (high | low) + X; operandAddress = (high | low) + X;
}') }')
define(M6502_ABSOLUTEX_READMODIFYWRITE, `{ define(M6502_ABSOLUTEX_READMODIFYWRITE, `{
uInt16 low = peek(PC++, DISASM_CODE); uInt16 low = peek(PC++, DISASM_CODE);
uInt16 high = (uInt16(peek(PC++, DISASM_CODE)) << 8); uInt16 high = (uInt16(peek(PC++, DISASM_CODE)) << 8);
peek(high | uInt8(low + X), DISASM_DATA); peek(high | uInt8(low + X), DISASM_NONE);
operandAddress = (high | low) + X; operandAddress = (high | low) + X;
operand = peek(operandAddress, DISASM_DATA); operand = peek(operandAddress, DISASM_DATA);
poke(operandAddress, operand); poke(operandAddress, operand);
@ -111,25 +115,29 @@ define(M6502_ABSOLUTEY_READ, `{
uInt16 low = peek(PC++, DISASM_CODE); uInt16 low = peek(PC++, DISASM_CODE);
uInt16 high = (uInt16(peek(PC++, DISASM_CODE)) << 8); uInt16 high = (uInt16(peek(PC++, DISASM_CODE)) << 8);
intermediateAddress = high | uInt8(low + Y); intermediateAddress = high | uInt8(low + Y);
operand = peek(intermediateAddress, DISASM_DATA);
if((low + Y) > 0xFF) if((low + Y) > 0xFF)
{ {
operand = peek(intermediateAddress, DISASM_NONE);
intermediateAddress = (high | low) + Y; intermediateAddress = (high | low) + Y;
operand = peek(intermediateAddress, DISASM_DATA); operand = peek(intermediateAddress, DISASM_DATA);
} }
else
{
operand = peek(intermediateAddress, DISASM_DATA);
}
}') }')
define(M6502_ABSOLUTEY_WRITE, `{ define(M6502_ABSOLUTEY_WRITE, `{
uInt16 low = peek(PC++, DISASM_CODE); uInt16 low = peek(PC++, DISASM_CODE);
uInt16 high = (uInt16(peek(PC++, DISASM_CODE)) << 8); uInt16 high = (uInt16(peek(PC++, DISASM_CODE)) << 8);
peek(high | uInt8(low + Y), DISASM_DATA); peek(high | uInt8(low + Y), DISASM_NONE);
operandAddress = (high | low) + Y; operandAddress = (high | low) + Y;
}') }')
define(M6502_ABSOLUTEY_READMODIFYWRITE, `{ define(M6502_ABSOLUTEY_READMODIFYWRITE, `{
uInt16 low = peek(PC++, DISASM_CODE); uInt16 low = peek(PC++, DISASM_CODE);
uInt16 high = (uInt16(peek(PC++, DISASM_CODE)) << 8); uInt16 high = (uInt16(peek(PC++, DISASM_CODE)) << 8);
peek(high | uInt8(low + Y), DISASM_DATA); peek(high | uInt8(low + Y), DISASM_NONE);
operandAddress = (high | low) + Y; operandAddress = (high | low) + Y;
operand = peek(operandAddress, DISASM_DATA); operand = peek(operandAddress, DISASM_DATA);
poke(operandAddress, operand); poke(operandAddress, operand);
@ -152,20 +160,20 @@ define(M6502_ZERO_READMODIFYWRITE, `{
define(M6502_ZEROX_READ, `{ define(M6502_ZEROX_READ, `{
intermediateAddress = peek(PC++, DISASM_CODE); intermediateAddress = peek(PC++, DISASM_CODE);
peek(intermediateAddress, DISASM_DATA); peek(intermediateAddress, DISASM_NONE);
intermediateAddress += X; intermediateAddress += X;
operand = peek(intermediateAddress, DISASM_DATA); operand = peek(intermediateAddress, DISASM_DATA);
}') }')
define(M6502_ZEROX_WRITE, `{ define(M6502_ZEROX_WRITE, `{
operandAddress = peek(PC++, DISASM_CODE); operandAddress = peek(PC++, DISASM_CODE);
peek(operandAddress, DISASM_DATA); peek(operandAddress, DISASM_NONE);
operandAddress = (operandAddress + X) & 0xFF; operandAddress = (operandAddress + X) & 0xFF;
}') }')
define(M6502_ZEROX_READMODIFYWRITE, `{ define(M6502_ZEROX_READMODIFYWRITE, `{
operandAddress = peek(PC++, DISASM_CODE); operandAddress = peek(PC++, DISASM_CODE);
peek(operandAddress, DISASM_DATA); peek(operandAddress, DISASM_NONE);
operandAddress = (operandAddress + X) & 0xFF; operandAddress = (operandAddress + X) & 0xFF;
operand = peek(operandAddress, DISASM_DATA); operand = peek(operandAddress, DISASM_DATA);
poke(operandAddress, operand); poke(operandAddress, operand);
@ -173,20 +181,20 @@ define(M6502_ZEROX_READMODIFYWRITE, `{
define(M6502_ZEROY_READ, `{ define(M6502_ZEROY_READ, `{
intermediateAddress = peek(PC++, DISASM_CODE); intermediateAddress = peek(PC++, DISASM_CODE);
peek(intermediateAddress, DISASM_DATA); peek(intermediateAddress, DISASM_NONE);
intermediateAddress += Y; intermediateAddress += Y;
operand = peek(intermediateAddress, DISASM_DATA); operand = peek(intermediateAddress, DISASM_DATA);
}') }')
define(M6502_ZEROY_WRITE, `{ define(M6502_ZEROY_WRITE, `{
operandAddress = peek(PC++, DISASM_CODE); operandAddress = peek(PC++, DISASM_CODE);
peek(operandAddress, DISASM_DATA); peek(operandAddress, DISASM_NONE);
operandAddress = (operandAddress + Y) & 0xFF; operandAddress = (operandAddress + Y) & 0xFF;
}') }')
define(M6502_ZEROY_READMODIFYWRITE, `{ define(M6502_ZEROY_READMODIFYWRITE, `{
operandAddress = peek(PC++, DISASM_CODE); operandAddress = peek(PC++, DISASM_CODE);
peek(operandAddress, DISASM_DATA); peek(operandAddress, DISASM_NONE);
operandAddress = (operandAddress + Y) & 0xFF; operandAddress = (operandAddress + Y) & 0xFF;
operand = peek(operandAddress, DISASM_DATA); operand = peek(operandAddress, DISASM_DATA);
poke(operandAddress, operand); poke(operandAddress, operand);
@ -205,7 +213,7 @@ define(M6502_INDIRECT, `{
define(M6502_INDIRECTX_READ, `{ define(M6502_INDIRECTX_READ, `{
uInt8 pointer = peek(PC++, DISASM_CODE); uInt8 pointer = peek(PC++, DISASM_CODE);
peek(pointer, DISASM_DATA); peek(pointer, DISASM_NONE);
pointer += X; pointer += X;
intermediateAddress = peek(pointer++, DISASM_DATA); intermediateAddress = peek(pointer++, DISASM_DATA);
intermediateAddress |= (uInt16(peek(pointer, DISASM_DATA)) << 8); intermediateAddress |= (uInt16(peek(pointer, DISASM_DATA)) << 8);
@ -214,7 +222,7 @@ define(M6502_INDIRECTX_READ, `{
define(M6502_INDIRECTX_WRITE, `{ define(M6502_INDIRECTX_WRITE, `{
uInt8 pointer = peek(PC++, DISASM_CODE); uInt8 pointer = peek(PC++, DISASM_CODE);
peek(pointer, DISASM_DATA); peek(pointer, DISASM_NONE);
pointer += X; pointer += X;
operandAddress = peek(pointer++, DISASM_DATA); operandAddress = peek(pointer++, DISASM_DATA);
operandAddress |= (uInt16(peek(pointer, DISASM_DATA)) << 8); operandAddress |= (uInt16(peek(pointer, DISASM_DATA)) << 8);
@ -222,7 +230,7 @@ define(M6502_INDIRECTX_WRITE, `{
define(M6502_INDIRECTX_READMODIFYWRITE, `{ define(M6502_INDIRECTX_READMODIFYWRITE, `{
uInt8 pointer = peek(PC++, DISASM_CODE); uInt8 pointer = peek(PC++, DISASM_CODE);
peek(pointer, DISASM_DATA); peek(pointer, DISASM_NONE);
pointer += X; pointer += X;
operandAddress = peek(pointer++, DISASM_DATA); operandAddress = peek(pointer++, DISASM_DATA);
operandAddress |= (uInt16(peek(pointer, DISASM_DATA)) << 8); operandAddress |= (uInt16(peek(pointer, DISASM_DATA)) << 8);
@ -235,19 +243,23 @@ define(M6502_INDIRECTY_READ, `{
uInt16 low = peek(pointer++, DISASM_DATA); uInt16 low = peek(pointer++, DISASM_DATA);
uInt16 high = (uInt16(peek(pointer, DISASM_DATA)) << 8); uInt16 high = (uInt16(peek(pointer, DISASM_DATA)) << 8);
intermediateAddress = high | uInt8(low + Y); intermediateAddress = high | uInt8(low + Y);
operand = peek(intermediateAddress, DISASM_DATA);
if((low + Y) > 0xFF) if((low + Y) > 0xFF)
{ {
operand = peek(intermediateAddress, DISASM_NONE);
intermediateAddress = (high | low) + Y; intermediateAddress = (high | low) + Y;
operand = peek(intermediateAddress, DISASM_DATA); operand = peek(intermediateAddress, DISASM_DATA);
} }
else
{
operand = peek(intermediateAddress, DISASM_DATA);
}
}') }')
define(M6502_INDIRECTY_WRITE, `{ define(M6502_INDIRECTY_WRITE, `{
uInt8 pointer = peek(PC++, DISASM_CODE); uInt8 pointer = peek(PC++, DISASM_CODE);
uInt16 low = peek(pointer++, DISASM_DATA); uInt16 low = peek(pointer++, DISASM_DATA);
uInt16 high = (uInt16(peek(pointer, DISASM_DATA)) << 8); uInt16 high = (uInt16(peek(pointer, DISASM_DATA)) << 8);
peek(high | uInt8(low + Y), DISASM_DATA); peek(high | uInt8(low + Y), DISASM_NONE);
operandAddress = (high | low) + Y; operandAddress = (high | low) + Y;
}') }')
@ -255,13 +267,12 @@ define(M6502_INDIRECTY_READMODIFYWRITE, `{
uInt8 pointer = peek(PC++, DISASM_CODE); uInt8 pointer = peek(PC++, DISASM_CODE);
uInt16 low = peek(pointer++, DISASM_DATA); uInt16 low = peek(pointer++, DISASM_DATA);
uInt16 high = (uInt16(peek(pointer, DISASM_DATA)) << 8); uInt16 high = (uInt16(peek(pointer, DISASM_DATA)) << 8);
peek(high | uInt8(low + Y), DISASM_DATA); peek(high | uInt8(low + Y), DISASM_NONE);
operandAddress = (high | low) + Y; operandAddress = (high | low) + Y;
operand = peek(operandAddress, DISASM_DATA); operand = peek(operandAddress, DISASM_DATA);
poke(operandAddress, operand); poke(operandAddress, operand);
}') }')
define(M6502_BCC, `{ define(M6502_BCC, `{
if(!C) if(!C)
{ {
@ -484,7 +495,7 @@ define(M6502_BIT, `{
}') }')
define(M6502_BRK, `{ define(M6502_BRK, `{
peek(PC++, DISASM_CODE); peek(PC++, DISASM_NONE);
B = true; B = true;
@ -494,8 +505,8 @@ define(M6502_BRK, `{
I = true; I = true;
PC = peek(0xfffe, DISASM_NONE); PC = peek(0xfffe, DISASM_DATA);
PC |= (uInt16(peek(0xffff, DISASM_NONE)) << 8); PC |= (uInt16(peek(0xffff, DISASM_DATA)) << 8);
}') }')
define(M6502_CLC, `{ define(M6502_CLC, `{
@ -996,7 +1007,8 @@ define(M6502_TYA, `{
N = A & 0x80; N = A & 0x80;
}') }')
//////////////////////////////////////////////////
// ADC
case 0x69: case 0x69:
M6502_IMMEDIATE_READ M6502_IMMEDIATE_READ
M6502_ADC M6502_ADC
@ -1037,20 +1049,23 @@ M6502_INDIRECTY_READ
M6502_ADC M6502_ADC
break; break;
//////////////////////////////////////////////////
// ASR
case 0x4b: case 0x4b:
M6502_IMMEDIATE_READ M6502_IMMEDIATE_READ
M6502_ASR M6502_ASR
break; break;
//////////////////////////////////////////////////
// ANC
case 0x0b: case 0x0b:
case 0x2b: case 0x2b:
M6502_IMMEDIATE_READ M6502_IMMEDIATE_READ
M6502_ANC M6502_ANC
break; break;
//////////////////////////////////////////////////
// AND
case 0x29: case 0x29:
M6502_IMMEDIATE_READ M6502_IMMEDIATE_READ
M6502_AND M6502_AND
@ -1091,19 +1106,22 @@ M6502_INDIRECTY_READ
M6502_AND M6502_AND
break; break;
//////////////////////////////////////////////////
// ANE
case 0x8b: case 0x8b:
M6502_IMMEDIATE_READ M6502_IMMEDIATE_READ
M6502_ANE M6502_ANE
break; break;
//////////////////////////////////////////////////
// ARR
case 0x6b: case 0x6b:
M6502_IMMEDIATE_READ M6502_IMMEDIATE_READ
M6502_ARR M6502_ARR
break; break;
//////////////////////////////////////////////////
// ASL
case 0x0a: case 0x0a:
M6502_IMPLIED M6502_IMPLIED
M6502_ASLA M6502_ASLA
@ -1129,7 +1147,20 @@ M6502_ABSOLUTEX_READMODIFYWRITE
M6502_ASL M6502_ASL
break; break;
//////////////////////////////////////////////////
// BIT
case 0x24:
M6502_ZERO_READ
M6502_BIT
break;
case 0x2C:
M6502_ABSOLUTE_READ
M6502_BIT
break;
//////////////////////////////////////////////////
// Branches
case 0x90: case 0x90:
M6502_IMMEDIATE_READ M6502_IMMEDIATE_READ
M6502_BCC M6502_BCC
@ -1148,17 +1179,6 @@ M6502_BEQ
break; break;
case 0x24:
M6502_ZERO_READ
M6502_BIT
break;
case 0x2C:
M6502_ABSOLUTE_READ
M6502_BIT
break;
case 0x30: case 0x30:
M6502_IMMEDIATE_READ M6502_IMMEDIATE_READ
M6502_BMI M6502_BMI
@ -1177,11 +1197,6 @@ M6502_BPL
break; break;
case 0x00:
M6502_BRK
break;
case 0x50: case 0x50:
M6502_IMMEDIATE_READ M6502_IMMEDIATE_READ
M6502_BVC M6502_BVC
@ -1193,31 +1208,42 @@ M6502_IMMEDIATE_READ
M6502_BVS M6502_BVS
break; break;
//////////////////////////////////////////////////
// BRK
case 0x00:
M6502_BRK
break;
//////////////////////////////////////////////////
// CLC
case 0x18: case 0x18:
M6502_IMPLIED M6502_IMPLIED
M6502_CLC M6502_CLC
break; break;
//////////////////////////////////////////////////
// CLD
case 0xd8: case 0xd8:
M6502_IMPLIED M6502_IMPLIED
M6502_CLD M6502_CLD
break; break;
//////////////////////////////////////////////////
// CLI
case 0x58: case 0x58:
M6502_IMPLIED M6502_IMPLIED
M6502_CLI M6502_CLI
break; break;
//////////////////////////////////////////////////
// CLV
case 0xb8: case 0xb8:
M6502_IMPLIED M6502_IMPLIED
M6502_CLV M6502_CLV
break; break;
//////////////////////////////////////////////////
// CMP
case 0xc9: case 0xc9:
M6502_IMMEDIATE_READ M6502_IMMEDIATE_READ
M6502_CMP M6502_CMP
@ -1258,7 +1284,8 @@ M6502_INDIRECTY_READ
M6502_CMP M6502_CMP
break; break;
//////////////////////////////////////////////////
// CPX
case 0xe0: case 0xe0:
M6502_IMMEDIATE_READ M6502_IMMEDIATE_READ
M6502_CPX M6502_CPX
@ -1274,7 +1301,8 @@ M6502_ABSOLUTE_READ
M6502_CPX M6502_CPX
break; break;
//////////////////////////////////////////////////
// CPY
case 0xc0: case 0xc0:
M6502_IMMEDIATE_READ M6502_IMMEDIATE_READ
M6502_CPY M6502_CPY
@ -1290,7 +1318,8 @@ M6502_ABSOLUTE_READ
M6502_CPY M6502_CPY
break; break;
//////////////////////////////////////////////////
// DCP
case 0xcf: case 0xcf:
M6502_ABSOLUTE_READMODIFYWRITE M6502_ABSOLUTE_READMODIFYWRITE
M6502_DCP M6502_DCP
@ -1326,7 +1355,8 @@ M6502_INDIRECTY_READMODIFYWRITE
M6502_DCP M6502_DCP
break; break;
//////////////////////////////////////////////////
// DEC
case 0xc6: case 0xc6:
M6502_ZERO_READMODIFYWRITE M6502_ZERO_READMODIFYWRITE
M6502_DEC M6502_DEC
@ -1347,19 +1377,22 @@ M6502_ABSOLUTEX_READMODIFYWRITE
M6502_DEC M6502_DEC
break; break;
//////////////////////////////////////////////////
// DEX
case 0xca: case 0xca:
M6502_IMPLIED M6502_IMPLIED
M6502_DEX M6502_DEX
break; break;
//////////////////////////////////////////////////
// DEY
case 0x88: case 0x88:
M6502_IMPLIED M6502_IMPLIED
M6502_DEY M6502_DEY
break; break;
//////////////////////////////////////////////////
// EOR
case 0x49: case 0x49:
M6502_IMMEDIATE_READ M6502_IMMEDIATE_READ
M6502_EOR M6502_EOR
@ -1400,7 +1433,8 @@ M6502_INDIRECTY_READ
M6502_EOR M6502_EOR
break; break;
//////////////////////////////////////////////////
// INC
case 0xe6: case 0xe6:
M6502_ZERO_READMODIFYWRITE M6502_ZERO_READMODIFYWRITE
M6502_INC M6502_INC
@ -1421,19 +1455,22 @@ M6502_ABSOLUTEX_READMODIFYWRITE
M6502_INC M6502_INC
break; break;
//////////////////////////////////////////////////
// INX
case 0xe8: case 0xe8:
M6502_IMPLIED M6502_IMPLIED
M6502_INX M6502_INX
break; break;
//////////////////////////////////////////////////
// INY
case 0xc8: case 0xc8:
M6502_IMPLIED M6502_IMPLIED
M6502_INY M6502_INY
break; break;
//////////////////////////////////////////////////
// ISB
case 0xef: case 0xef:
M6502_ABSOLUTE_READMODIFYWRITE M6502_ABSOLUTE_READMODIFYWRITE
M6502_ISB M6502_ISB
@ -1469,7 +1506,8 @@ M6502_INDIRECTY_READMODIFYWRITE
M6502_ISB M6502_ISB
break; break;
//////////////////////////////////////////////////
// JMP
case 0x4c: case 0x4c:
M6502_ABSOLUTE_WRITE M6502_ABSOLUTE_WRITE
M6502_JMP M6502_JMP
@ -1480,12 +1518,14 @@ M6502_INDIRECT
M6502_JMP M6502_JMP
break; break;
//////////////////////////////////////////////////
// JSR
case 0x20: case 0x20:
M6502_JSR M6502_JSR
break; break;
//////////////////////////////////////////////////
// LAS
case 0xbb: case 0xbb:
M6502_ABSOLUTEY_READ M6502_ABSOLUTEY_READ
M6502_LAS M6502_LAS
@ -1657,7 +1697,8 @@ M6502_LDY
break; break;
////////////////////////////////////////////////// //////////////////////////////////////////////////
//////////////////////////////////////////////////
// LSR
case 0x4a: case 0x4a:
M6502_IMPLIED M6502_IMPLIED
M6502_LSRA M6502_LSRA
@ -1684,13 +1725,15 @@ M6502_ABSOLUTEX_READMODIFYWRITE
M6502_LSR M6502_LSR
break; break;
//////////////////////////////////////////////////
// LXA
case 0xab: case 0xab:
M6502_IMMEDIATE_READ M6502_IMMEDIATE_READ
M6502_LXA M6502_LXA
break; break;
//////////////////////////////////////////////////
// NOP
case 0x1a: case 0x1a:
case 0x3a: case 0x3a:
case 0x5a: case 0x5a:
@ -1795,35 +1838,40 @@ M6502_ORA
break; break;
////////////////////////////////////////////////// //////////////////////////////////////////////////
//////////////////////////////////////////////////
// PHA
case 0x48: case 0x48:
M6502_IMPLIED M6502_IMPLIED
// TODO - add tracking for this opcode // TODO - add tracking for this opcode
M6502_PHA M6502_PHA
break; break;
//////////////////////////////////////////////////
// PHP
case 0x08: case 0x08:
M6502_IMPLIED M6502_IMPLIED
// TODO - add tracking for this opcode // TODO - add tracking for this opcode
M6502_PHP M6502_PHP
break; break;
//////////////////////////////////////////////////
// PLA
case 0x68: case 0x68:
M6502_IMPLIED M6502_IMPLIED
// TODO - add tracking for this opcode // TODO - add tracking for this opcode
M6502_PLA M6502_PLA
break; break;
//////////////////////////////////////////////////
// PLP
case 0x28: case 0x28:
M6502_IMPLIED M6502_IMPLIED
// TODO - add tracking for this opcode // TODO - add tracking for this opcode
M6502_PLP M6502_PLP
break; break;
//////////////////////////////////////////////////
// RLA
case 0x2f: case 0x2f:
M6502_ABSOLUTE_READMODIFYWRITE M6502_ABSOLUTE_READMODIFYWRITE
M6502_RLA M6502_RLA
@ -1859,13 +1907,13 @@ M6502_INDIRECTY_READMODIFYWRITE
M6502_RLA M6502_RLA
break; break;
//////////////////////////////////////////////////
// ROL
case 0x2a: case 0x2a:
M6502_IMPLIED M6502_IMPLIED
M6502_ROLA M6502_ROLA
break; break;
case 0x26: case 0x26:
M6502_ZERO_READMODIFYWRITE M6502_ZERO_READMODIFYWRITE
M6502_ROL M6502_ROL
@ -1886,7 +1934,8 @@ M6502_ABSOLUTEX_READMODIFYWRITE
M6502_ROL M6502_ROL
break; break;
//////////////////////////////////////////////////
// ROR
case 0x6a: case 0x6a:
M6502_IMPLIED M6502_IMPLIED
M6502_RORA M6502_RORA
@ -1912,7 +1961,8 @@ M6502_ABSOLUTEX_READMODIFYWRITE
M6502_ROR M6502_ROR
break; break;
//////////////////////////////////////////////////
// RRA
case 0x6f: case 0x6f:
M6502_ABSOLUTE_READMODIFYWRITE M6502_ABSOLUTE_READMODIFYWRITE
M6502_RRA M6502_RRA
@ -1948,19 +1998,22 @@ M6502_INDIRECTY_READMODIFYWRITE
M6502_RRA M6502_RRA
break; break;
//////////////////////////////////////////////////
// RTI
case 0x40: case 0x40:
M6502_IMPLIED M6502_IMPLIED
M6502_RTI M6502_RTI
break; break;
//////////////////////////////////////////////////
// RTS
case 0x60: case 0x60:
M6502_IMPLIED M6502_IMPLIED
M6502_RTS M6502_RTS
break; break;
//////////////////////////////////////////////////
// SAX
case 0x8f: case 0x8f:
M6502_ABSOLUTE_WRITE M6502_ABSOLUTE_WRITE
M6502_SAX M6502_SAX
@ -1981,7 +2034,8 @@ M6502_INDIRECTX_WRITE
M6502_SAX M6502_SAX
break; break;
//////////////////////////////////////////////////
// SBC
case 0xe9: case 0xe9:
case 0xeb: case 0xeb:
M6502_IMMEDIATE_READ M6502_IMMEDIATE_READ
@ -2023,31 +2077,36 @@ M6502_INDIRECTY_READ
M6502_SBC M6502_SBC
break; break;
//////////////////////////////////////////////////
// SBX
case 0xcb: case 0xcb:
M6502_IMMEDIATE_READ M6502_IMMEDIATE_READ
M6502_SBX M6502_SBX
break; break;
//////////////////////////////////////////////////
// SEC
case 0x38: case 0x38:
M6502_IMPLIED M6502_IMPLIED
M6502_SEC M6502_SEC
break; break;
//////////////////////////////////////////////////
// SED
case 0xf8: case 0xf8:
M6502_IMPLIED M6502_IMPLIED
M6502_SED M6502_SED
break; break;
//////////////////////////////////////////////////
// SEI
case 0x78: case 0x78:
M6502_IMPLIED M6502_IMPLIED
M6502_SEI M6502_SEI
break; break;
//////////////////////////////////////////////////
// SHA
case 0x9f: case 0x9f:
M6502_ABSOLUTEY_WRITE M6502_ABSOLUTEY_WRITE
M6502_SHA M6502_SHA
@ -2058,25 +2117,29 @@ M6502_INDIRECTY_WRITE
M6502_SHA M6502_SHA
break; break;
//////////////////////////////////////////////////
// SHS
case 0x9b: case 0x9b:
M6502_ABSOLUTEY_WRITE M6502_ABSOLUTEY_WRITE
M6502_SHS M6502_SHS
break; break;
//////////////////////////////////////////////////
// SHX
case 0x9e: case 0x9e:
M6502_ABSOLUTEY_WRITE M6502_ABSOLUTEY_WRITE
M6502_SHX M6502_SHX
break; break;
//////////////////////////////////////////////////
// SHY
case 0x9c: case 0x9c:
M6502_ABSOLUTEX_WRITE M6502_ABSOLUTEX_WRITE
M6502_SHY M6502_SHY
break; break;
//////////////////////////////////////////////////
// SLO
case 0x0f: case 0x0f:
M6502_ABSOLUTE_READMODIFYWRITE M6502_ABSOLUTE_READMODIFYWRITE
M6502_SLO M6502_SLO
@ -2112,7 +2175,8 @@ M6502_INDIRECTY_READMODIFYWRITE
M6502_SLO M6502_SLO
break; break;
//////////////////////////////////////////////////
// SRE
case 0x4f: case 0x4f:
M6502_ABSOLUTE_READMODIFYWRITE M6502_ABSOLUTE_READMODIFYWRITE
M6502_SRE M6502_SRE

8
src/emucore/System.cxx
View File

@ -113,6 +113,9 @@ uInt8 System::peek(uInt16 addr, uInt8 flags)
{ {
PageAccess& access = myPageAccessTable[(addr & ADDRESS_MASK) >> PAGE_SHIFT]; PageAccess& access = myPageAccessTable[(addr & ADDRESS_MASK) >> PAGE_SHIFT];
if (addr == 0xf52c /*0xf505*/)
addr = addr;
#ifdef DEBUGGER_SUPPORT #ifdef DEBUGGER_SUPPORT
// Set access type // Set access type
if(access.codeAccessBase) if(access.codeAccessBase)
@ -142,6 +145,9 @@ void System::poke(uInt16 addr, uInt8 value)
uInt16 page = (addr & ADDRESS_MASK) >> PAGE_SHIFT; uInt16 page = (addr & ADDRESS_MASK) >> PAGE_SHIFT;
PageAccess& access = myPageAccessTable[page]; PageAccess& access = myPageAccessTable[page];
if (addr == 0xf52c /*0xf505*/)
addr = addr;
// See if this page uses direct accessing or not // See if this page uses direct accessing or not
if(access.directPokeBase) if(access.directPokeBase)
{ {
@ -181,6 +187,8 @@ void System::setAccessFlags(uInt16 addr, uInt8 flags)
{ {
#ifdef DEBUGGER_SUPPORT #ifdef DEBUGGER_SUPPORT
PageAccess& access = myPageAccessTable[(addr & ADDRESS_MASK) >> PAGE_SHIFT]; PageAccess& access = myPageAccessTable[(addr & ADDRESS_MASK) >> PAGE_SHIFT];
if (addr == 0xf52c /*0xf505*/)
addr = addr;
if(access.codeAccessBase) if(access.codeAccessBase)
*(access.codeAccessBase + (addr & PAGE_MASK)) |= flags; *(access.codeAccessBase + (addr & PAGE_MASK)) |= flags;