diff --git a/src/emucore/elf/BusTransactionQueue.cxx b/src/emucore/elf/BusTransactionQueue.cxx index bdbca66ea..d9a2cb294 100644 --- a/src/emucore/elf/BusTransactionQueue.cxx +++ b/src/emucore/elf/BusTransactionQueue.cxx @@ -92,6 +92,13 @@ BusTransactionQueue& BusTransactionQueue::injectROM(uInt8 value, uInt16 address) return *this; } +BusTransactionQueue& BusTransactionQueue::stuffByte(uInt8 value, uInt16 address) +{ + push(Transaction::transactionDrive(address, value)); + + return *this; +} + // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - BusTransactionQueue& BusTransactionQueue::yield(uInt16 address) { diff --git a/src/emucore/elf/BusTransactionQueue.hxx b/src/emucore/elf/BusTransactionQueue.hxx index 0e2c17ab9..c6449c4be 100644 --- a/src/emucore/elf/BusTransactionQueue.hxx +++ b/src/emucore/elf/BusTransactionQueue.hxx @@ -43,12 +43,17 @@ class BusTransactionQueue { BusTransactionQueue& injectROM(uInt8 value); BusTransactionQueue& injectROM(uInt8 value, uInt16 address); + BusTransactionQueue& stuffByte(uInt8 value, uInt16 address); BusTransactionQueue& yield(uInt16 address); bool hasPendingTransaction() const; Transaction* getNextTransaction(uInt16 address); + inline size_t size() const { + return myQueueSize; + } + private: void push(const Transaction& transaction); diff --git a/src/emucore/elf/VcsLib.cxx b/src/emucore/elf/VcsLib.cxx index ada92a472..f4213215c 100644 --- a/src/emucore/elf/VcsLib.cxx +++ b/src/emucore/elf/VcsLib.cxx @@ -146,7 +146,14 @@ CortexM0::err_t VcsLib::fetch16(uInt32 address, uInt16& value, uInt8& op, Cortex return returnFromStub(value, op); case ADDR_VCS_WRITE3: - FatalEmulationError::raise("unimplemented: vcsWrite3"); + arg = cortex.getRegister(0); + + myTransactionQueue + .injectROM(0x85) + .injectROM(arg) + .stuffByte(arg, cortex.getRegister(1)); + + return returnFromStub(value, op); case ADDR_VCS_JMP3: myTransactionQueue