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Updated RWP stuff for 'E7' scheme.

This commit is contained in:
Stephen Anthony 2018-12-18 14:32:49 -03:30
parent a26288c788
commit 471cf1ad4d
1 changed files with 19 additions and 27 deletions
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46
src/emucore/CartMNetwork.cxx
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@ -69,10 +69,10 @@ void CartridgeMNetwork::setAccess(uInt16 addrFrom, uInt16 size,
for(uInt16 addr = addrFrom; addr < addrFrom + size; addr += System::PAGE_SIZE) for(uInt16 addr = addrFrom; addr < addrFrom + size; addr += System::PAGE_SIZE)
{ {
if (type == System::PA_READ) if(type == System::PA_READ)
access.directPeekBase = &directData[directOffset + (addr & addrMask)]; access.directPeekBase = &directData[directOffset + (addr & addrMask)];
if(type == System::PA_WRITE) else if(type == System::PA_WRITE) // all RAM writes mapped to ::poke()
access.directPokeBase = &directData[directOffset + (addr & addrMask)]; access.directPokeBase = nullptr;
access.codeAccessBase = &myCodeAccessBase[codeOffset + (addr & addrMask)]; access.codeAccessBase = &myCodeAccessBase[codeOffset + (addr & addrMask)];
mySystem->setPageAccess(addr, access); mySystem->setPageAccess(addr, access);
} }
@ -117,46 +117,38 @@ uInt8 CartridgeMNetwork::peek(uInt16 address)
if((myCurrentSlice[0] == myRAMSlice) && (address < BANK_SIZE / 2)) if((myCurrentSlice[0] == myRAMSlice) && (address < BANK_SIZE / 2))
{ {
// Reading from the 1K write port @ $1000 triggers an unwanted write // Reading from the 1K write port @ $1000 triggers an unwanted write
uInt8 value = mySystem->getDataBusState(0xFF); return peekRAM(myRAM[address & (BANK_SIZE / 2 - 1)], peekAddress);
if(bankLocked())
return value;
else
{
myRAM[address & (BANK_SIZE / 2 - 1)] = value;
triggerReadFromWritePort(peekAddress);
return value;
}
} }
else if((address >= 0x0800) && (address <= 0x08FF)) else if((address >= 0x0800) && (address <= 0x08FF))
{ {
// Reading from the 256B write port @ $1800 triggers an unwanted write // Reading from the 256B write port @ $1800 triggers an unwanted write
uInt8 value = mySystem->getDataBusState(0xFF); return peekRAM(myRAM[1024 + (myCurrentRAM << 8) + (address & 0x00FF)], peekAddress);
if(bankLocked())
return value;
else
{
myRAM[1024 + (myCurrentRAM << 8) + (address & 0x00FF)] = value;
triggerReadFromWritePort(peekAddress);
return value;
}
} }
else else
return myImage[(myCurrentSlice[address >> 11] << 11) + (address & (BANK_SIZE - 1))]; return myImage[(myCurrentSlice[address >> 11] << 11) + (address & (BANK_SIZE - 1))];
} }
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
bool CartridgeMNetwork::poke(uInt16 address, uInt8) bool CartridgeMNetwork::poke(uInt16 address, uInt8 value)
{ {
uInt16 pokeAddress = address;
address &= 0x0FFF; address &= 0x0FFF;
// Switch banks if necessary // Switch banks if necessary
checkSwitchBank(address); checkSwitchBank(address);
// NOTE: This does not handle writing to RAM, however, this // All RAM writes are mapped here
// method should never be called for RAM because of the if((myCurrentSlice[0] == myRAMSlice) && (address < BANK_SIZE / 2))
// way page accessing has been setup {
pokeRAM(myRAM[address & (BANK_SIZE / 2 - 1)], pokeAddress, value);
return true;
}
else if((address >= 0x0800) && (address <= 0x08FF))
{
pokeRAM(myRAM[1024 + (myCurrentRAM << 8) + (address & 0x00FF)], pokeAddress, value);
return true;
}
return false; return false;
} }