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stella
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Sub2K ROMs now show only the actual data in the binary. This allows 

the saved disassembly to be compiled to the exact same binary.


git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2669 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
This commit is contained in:
stephena 2013-03-13 21:16:14 +00:00
parent 895fd7b263
commit 467ac0a280
3 changed files with 27 additions and 18 deletions
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7
Changes.txt
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@ -21,12 +21,17 @@
accurate. It also automatically differentiates between accurate. It also automatically differentiates between
CODE/PGFX/GFX/DATA/ROW areas, whereas normal Distella CODE/PGFX/GFX/DATA/ROW areas, whereas normal Distella
only differentiates between CODE/GFX/ROW. For now, only only differentiates between CODE/GFX/ROW. For now, only
single-bank (4K) ROMs are supported. single-bank (4K and smaller) ROMs are supported.
- The disassembly now recognizes various TIA read/write mirrors, - The disassembly now recognizes various TIA read/write mirrors,
and marks them as such (for example, INPT4.30 instead of INPT4 and marks them as such (for example, INPT4.30 instead of INPT4
for address $3C). for address $3C).
- ROMS less than 2K in size (so called 'Sub2K' ROMs) now show only
the actual data in the binary. This means, for example, that a
256byte ROM will show only 256 bytes in the disassembly, instead
of padding garbage/duplicated data to 2K boundary.
- Fixed labelling in ROW directives; it wasn't accurately setting - Fixed labelling in ROW directives; it wasn't accurately setting
a label in the case where it occurred in the middle of the data. a label in the case where it occurred in the middle of the data.

10
src/debugger/CartDebug.cxx
View File

@ -47,12 +47,16 @@ CartDebug::CartDebug(Debugger& dbg, Console& console, const OSystem& osystem)
addRamArea(i->start, i->size, i->roffset, i->woffset); addRamArea(i->start, i->size, i->roffset, i->woffset);
// Create bank information for each potential bank, and an extra one for ZP RAM // Create bank information for each potential bank, and an extra one for ZP RAM
uInt16 banksize = // Banksizes greater than 4096 indicate multi-bank ROMs, but we handle only
!BSPF_equalsIgnoreCase(myConsole.cartridge().name(), "Cartridge2K") ? 4096 : 2048; // 4K pieces at a time
// Banksizes less than 4K use the actual value
int banksize = 4096;
myConsole.cartridge().getImage(banksize);
banksize = BSPF_min(banksize, 4096);
BankInfo info; BankInfo info;
for(int i = 0; i < myConsole.cartridge().bankCount(); ++i) for(int i = 0; i < myConsole.cartridge().bankCount(); ++i)
{ {
info.size = banksize; // TODO - get this from Cart class info.size = banksize;
myBankInfo.push_back(info); myBankInfo.push_back(info);
} }
info.size = 128; // ZP RAM info.size = 128; // ZP RAM

28
src/debugger/DiStella.cxx
View File

@ -43,6 +43,7 @@ DiStella::DiStella(const CartDebug& dbg, CartDebug::DisassemblyList& list,
CartDebug::AddressList::iterator it = addresses.begin(); CartDebug::AddressList::iterator it = addresses.begin();
uInt16 start = *it++; uInt16 start = *it++;
myOffset = info.offset;
if(start & 0x1000) if(start & 0x1000)
{ {
if(info.size == 4096) // 4K ROM space if(info.size == 4096) // 4K ROM space
@ -56,38 +57,37 @@ DiStella::DiStella(const CartDebug& dbg, CartDebug::DisassemblyList& list,
Offset to code = $D000 Offset to code = $D000
Code range = $D000-$DFFF Code range = $D000-$DFFF
=============================================*/ =============================================*/
myAppData.start = 0x0000; info.start = myAppData.start = 0x0000;
myAppData.end = 0x0FFF; info.end = myAppData.end = 0x0FFF;
myOffset = (start - (start % 0x1000));
// Keep previous offset; it may be different between banks
if(info.offset == 0)
info.offset = myOffset = (start - (start % 0x1000));
} }
else // 2K ROM space else // 2K ROM space (also includes 'Sub2K' ROMs)
{ {
/*============================================ /*============================================
The offset is the address where the code segment The offset is the address where the code segment
starts. For a 2K game, it is usually 0xf800, starts. For a 2K game, it is usually 0xf800,
but can also be 0xf000. but can also be 0xf000.
=============================================*/ =============================================*/
myAppData.start = 0x0000; info.start = myAppData.start = 0x0000;
myAppData.end = 0x07FF; info.end = myAppData.end = info.size - 1;
myOffset = (start & 0xF800); info.offset = myOffset = (start - (start % info.size));
} }
} }
else // ZP RAM else // ZP RAM
{ {
// For now, we assume all accesses below $1000 are zero-page // For now, we assume all accesses below $1000 are zero-page
myAppData.start = 0x0080; info.start = myAppData.start = 0x0080;
myAppData.end = 0x00FF; info.end = myAppData.end = 0x00FF;
myOffset = 0; info.offset = myOffset = 0;
// Resolve data is never used in ZP RAM mode // Resolve data is never used in ZP RAM mode
resolvedata = false; resolvedata = false;
} }
myAppData.length = info.size; myAppData.length = info.size;
info.start = myAppData.start;
info.end = myAppData.end;
info.offset = myOffset;
memset(myLabels, 0, 0x1000); memset(myLabels, 0, 0x1000);
memset(myDirectives, 0, 0x1000); memset(myDirectives, 0, 0x1000);
myAddressQueue.push(start); myAddressQueue.push(start);