mirror of https://github.com/stella-emu/stella.git
autoformatted. still stabilising to stella standard.
Tabs removed, replaced with 2-char spacing. constants for bit masking added corrected the patch code for the bit-allocations for RAM/ROM banks switch git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2900 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
This commit is contained in:
adavie
parent
6d6dd7632f
commit
40c8c81245
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@ -24,11 +24,9 @@
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#include "TIA.hxx"
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#include "CartDASH.hxx"
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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CartridgeDASH::CartridgeDASH(const uInt8* image, uInt32 size, const Settings& settings)
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: Cartridge(settings),
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mySize(size)
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{
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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CartridgeDASH::CartridgeDASH(const uInt8* image, uInt32 size, const Settings& settings) :
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Cartridge(settings), mySize(size) {
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// Allocate array for the ROM image
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myImage = new uInt8[mySize];
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@ -46,20 +44,20 @@ CartridgeDASH::CartridgeDASH(const uInt8* image, uInt32 size, const Settings& se
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registerRamArea(0x1400, RAM_BANK_SIZE, 0x00, RAM_WRITE_OFFSET); // 512 bytes RAM @ 0x1400
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registerRamArea(0x1600, RAM_BANK_SIZE, 0x00, RAM_WRITE_OFFSET); // 512 bytes RAM @ 0x1600
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myCurrentBank = -1; // nothing switched
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// Remember startup bank (0 per spec, rather than last per 3E scheme).
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// Set this to go to 3rd 1K Bank.
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myStartBank = (3 << BANK_BITS) | 0;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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CartridgeDASH::~CartridgeDASH()
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{
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CartridgeDASH::~CartridgeDASH() {
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delete[] myImage;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void CartridgeDASH::reset()
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{
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void CartridgeDASH::reset() {
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// Initialize RAM
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if (mySettings.getBool("ramrandom"))
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for (uInt32 i = 0; i < RAM_TOTAL_SIZE; ++i)
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@ -73,8 +71,7 @@ void CartridgeDASH::reset()
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void CartridgeDASH::install(System& system)
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{
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void CartridgeDASH::install(System& system) {
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mySystem = &system;
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uInt16 shift = mySystem->pageShift();
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@ -95,12 +92,11 @@ void CartridgeDASH::install(System& system)
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// Setup the last segment (of 4, each 1K) to point to the first ROM slice
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// Actually we DO NOT want "always". It's just on bootup, and can be out switched later
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access.type = System::PA_READ;
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for (uInt32 byte = 0; byte < ROM_BANK_SIZE; byte++)
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{
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uInt32 address = (0x1000 - ROM_BANK_SIZE) + (byte<<shift); // which byte in last bank of 2600 address space
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for (uInt32 byte = 0; byte < ROM_BANK_SIZE; byte++) {
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uInt32 address = (0x1000 - ROM_BANK_SIZE) + (byte << shift); // which byte in last bank of 2600 address space
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access.directPeekBase = &myImage[byte]; // from base address 0x0000 in image, so just use 'byte'
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access.codeAccessBase = &myCodeAccessBase[byte];
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mySystem->setPageAccess(address>>shift, access);
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mySystem->setPageAccess(address >> shift, access);
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// TODO: Stephen: in this and other implementations we appear to be using "shift" as a system-dependant mangle for
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// different access types (byte/int/32bit) on different architectures. I think I understand that much. However,
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@ -112,7 +108,7 @@ void CartridgeDASH::install(System& system)
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// Initialise bank values for the 4x 1K bank areas
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// This is used to reverse-lookup from address to bank location
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for(uInt32 b = 0; b < 3; b++)
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for (uInt32 b = 0; b < 3; b++)
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bankInUse[b] = BANK_UNDEFINED; // bank is undefined and inaccessible!
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// Install pages for the startup bank into the first segment
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@ -120,31 +116,29 @@ void CartridgeDASH::install(System& system)
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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uInt8 CartridgeDASH::peek(uInt16 address)
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{
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uInt8 CartridgeDASH::peek(uInt16 address) {
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uInt8 value = 0;
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uInt32 bank = (address >> ROM_BANK_TO_POWER) & 3; // convert to 1K bank index (0-3)
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Int16 imageBank = bankInUse[bank]; // the ROM/RAM bank that's here
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if(imageBank == BANK_UNDEFINED) // an uninitialised bank?
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{
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if (imageBank == BANK_UNDEFINED) { // an uninitialised bank?
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// accessing invalid bank, so return should be... random?
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// TODO: Stephen -- throw some sort of error; looking at undefined data
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assert(false);
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value = mySystem->randGenerator().next();
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}
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else if (imageBank & ROMRAM) // a RAM bank
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{
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Int32 ramBank = imageBank & BIT_BANK_MASK; // discard irrelevant bits
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Int32 offset = ramBank << RAM_BANK_TO_POWER; // base bank address in RAM
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offset += (address & (RAM_BANK_SIZE-1)); // + byte offset in RAM bank
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value = myRAM[offset];
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}
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else // accessing ROM
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{
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} else if (imageBank & BITMASK_ROMRAM) { // a RAM bank
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Int32 ramBank = imageBank & BIT_BANK_MASK; // discard irrelevant bits
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Int32 offset = ramBank << RAM_BANK_TO_POWER; // base bank address in RAM
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offset += (address & BITMASK_RAM_BANK); // + byte offset in RAM bank
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value = myRAM[offset];
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} else { // accessing ROM
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Int32 offset = imageBank << ROM_BANK_TO_POWER; // base bank address in image
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offset += (address & (ROM_BANK_SIZE-1)); // + byte offset in image bank
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offset += (address & BITMASK_ROM_BANK); // + byte offset in image bank
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value = myImage[offset];
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}
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@ -152,15 +146,14 @@ uInt8 CartridgeDASH::peek(uInt16 address)
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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bool CartridgeDASH::poke(uInt16 address, uInt8 value)
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{
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bool CartridgeDASH::poke(uInt16 address, uInt8 value) {
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address &= 0x0FFF; // restrict to 4K address range
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// Check for write to the bank switch address. RAM/ROM and bank # are encoded in 'value'
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// There are NO mirrored hotspots.
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if ( address == BANK_SWITCH_HOTSPOT)
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bank(value);
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if (address == BANK_SWITCH_HOTSPOT)
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bank(value);
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// Pass the poke through to the TIA. In a real Atari, both the cart and the
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// TIA see the address lines, and both react accordingly. In Stella, each
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@ -172,9 +165,8 @@ bool CartridgeDASH::poke(uInt16 address, uInt8 value)
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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bool CartridgeDASH::bank(uInt16 bank)
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{
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if(bankLocked())
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bool CartridgeDASH::bank(uInt16 bank) {
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if (bankLocked())
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return false; // TODO: Stephen -- ? no idea
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uInt16 shift = mySystem->pageShift();
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uInt16 bankNumber = (bank >> BANK_BITS) & 3; // which bank # we are switching TO (BITS D6,D7)
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uInt16 bankID = bank & BIT_BANK_MASK; // The actual bank # to switch in (BITS D5-D0)
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if(bank & ROMRAM) // switching to a 512 byte RAM bank
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{
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if (bank & BITMASK_ROMRAM) { // switching to a 512 byte RAM bank
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// Wrap around/restrict to valid range
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uInt16 currentBank = (bank & BIT_BANK_MASK) % RAM_BANK_COUNT;
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uInt16 currentBank = bank & BIT_BANK_MASK;
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// Record which bank switched in (marked as RAM)
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myCurrentBank = bankInUse[bankNumber] = (Int16) (ROM_BANK_COUNT + currentBank);
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myCurrentBank = bankInUse[bankNumber] = (Int16) (BITMASK_ROMRAM | currentBank);
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// Effectively * 512 bytes
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uInt32 startCurrentBank = currentBank << RAM_BANK_TO_POWER;
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System::PageAccess access(0, 0, 0, this, System::PA_READ);
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// Map read-port RAM image into the system
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for(uInt32 byte = 0; byte < RAM_BANK_SIZE; byte += (1 << shift))
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{
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for (uInt32 byte = 0; byte < RAM_BANK_SIZE; byte += (1 << shift)) {
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access.directPeekBase = &myRAM[startCurrentBank + byte];
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// TODO: Stephen please explain/review the use of mySize as an offset for RAM access here....
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access.type = System::PA_WRITE;
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// Map write-port RAM image into the system
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for (uInt32 byte = 0; byte < RAM_BANK_SIZE; byte += (1 << shift))
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{
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for (uInt32 byte = 0; byte < RAM_BANK_SIZE; byte += (1 << shift)) {
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access.directPokeBase = &myRAM[startCurrentBank + RAM_WRITE_OFFSET + byte];
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access.codeAccessBase = &myCodeAccessBase[mySize + startCurrentBank + RAM_WRITE_OFFSET + byte];
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mySystem->setPageAccess((startCurrentBank + byte) >> shift, access);
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}
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}
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else // ROM 1K banks
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} else // ROM 1K banks
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{
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// Map ROM bank image into the system into the correct slot
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// Memory map is 1K slots at 0x1000, 0x1400, 0x1800, 0x1C00
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@ -231,8 +220,7 @@ bool CartridgeDASH::bank(uInt16 bank)
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uInt32 bankStart = 0x1000 + (bankNumber << ROM_BANK_TO_POWER); // *1K
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for (uInt32 byte = 0; byte < ROM_BANK_SIZE; byte += (1 << shift))
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{
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for (uInt32 byte = 0; byte < ROM_BANK_SIZE; byte += (1 << shift)) {
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access.directPeekBase = &myImage[startCurrentBank + byte];
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access.codeAccessBase = &myCodeAccessBase[startCurrentBank + byte];
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mySystem->setPageAccess((bankStart + byte) >> shift, access);
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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uInt16 CartridgeDASH::bank() const
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{
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uInt16 CartridgeDASH::bank() const {
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// TODO: Stephen -- what to do here? We don't really HAVE a "current bank"; we have 4 banks
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// and they are defined in bankInUse[...].
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// What I've done is kept track of the last switched bank, and return that. But that doesn't tell us WHERE. :(
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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uInt16 CartridgeDASH::bankCount() const
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{
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// Because the RAM banks always start above the ROM banks (see ROM_BANK_COUNT) for value,
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// we require the number of ROM banks to be == ROM_BANK_COUNT. Banks are therefore 0-63 ROM 64-127 RAM
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// TODO: Stephen -- ROM banks are 1K. RAM banks are 512 bytes. How does this affect what this routine should return?
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uInt16 CartridgeDASH::bankCount() const {
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// We have a constant # banks for this scheme; 32 ROM and 32 RAM (or, at least, RAM_BANK_COUNT and ROM_BANK_COUNT)
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// See usage of bank bits.
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// TODO: Stephen -- What should this return, given the mangled bank value?
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return ROM_BANK_COUNT + RAM_BANK_COUNT;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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bool CartridgeDASH::patch(uInt16 address, uInt8 value)
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{
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bool CartridgeDASH::patch(uInt16 address, uInt8 value) {
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// Patch the cartridge ROM
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// TODO: Stephen... I assume this is for some sort of debugger support....?
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myBankChanged = true;
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uInt32 bankNumber = (address >> 10) & 3; // now 1K bank # (ie: 0-3)
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uInt32 bankNumber = (address >> ROM_BANK_TO_POWER) & 3; // now 1K bank # (ie: 0-3)
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Int32 whichBankIsThere = bankInUse[bankNumber]; // ROM or RAM bank reference
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if(whichBankIsThere <= BANK_UNDEFINED)
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{
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if (whichBankIsThere == BANK_UNDEFINED) {
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// We're trying to access undefined memory (no bank here yet)
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// TODO: Stephen -- what to do here? Fail silently?
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@ -281,64 +267,58 @@ bool CartridgeDASH::patch(uInt16 address, uInt8 value)
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assert(false);
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myBankChanged = false;
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}
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else if(whichBankIsThere < ROM_BANK_COUNT) // patching ROM (1K banks)
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{
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uInt32 byteOffset = address & (ROM_BANK_SIZE-1);
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} else if (whichBankIsThere & BITMASK_ROMRAM) { // patching RAM (512 byte banks)
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uInt32 byteOffset = address & BITMASK_RAM_BANK;
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uInt32 baseAddress = ((whichBankIsThere & BIT_BANK_MASK) << RAM_BANK_TO_POWER) + byteOffset;
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myRAM[baseAddress] = value; // write to RAM
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} else { // patching ROM (1K banks)
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uInt32 byteOffset = address & BITMASK_ROM_BANK;
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uInt32 baseAddress = (whichBankIsThere << ROM_BANK_TO_POWER) + byteOffset;
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myImage[baseAddress] = value; // write to the image
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}
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else // patching RAM (512 byte banks)
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{
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uInt32 byteOffset = address & (RAM_BANK_SIZE-1);
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uInt32 baseAddress = ((whichBankIsThere - ROM_BANK_COUNT) << RAM_BANK_TO_POWER) + byteOffset;
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myRAM[baseAddress] = value; // write to RAM
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}
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return myBankChanged;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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const uInt8* CartridgeDASH::getImage(int& size) const
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{
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const uInt8* CartridgeDASH::getImage(int& size) const {
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size = mySize;
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return myImage;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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bool CartridgeDASH::save(Serializer& out) const
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{
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try
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{
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bool CartridgeDASH::save(Serializer& out) const {
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try {
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out.putString(name());
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out.putShort(myCurrentBank);
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for(uInt32 bank = 0; bank < 4; bank++)
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for (uInt32 bank = 0; bank < 4; bank++)
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out.putShort(bankInUse[bank]);
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out.putByteArray(myRAM, RAM_TOTAL_SIZE);
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}
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catch (...)
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{
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} catch (...) {
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cerr << "ERROR: CartridgeDASH::save" << endl;
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return false;
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}
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{
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return true;
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return false;
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}
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return true;
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}
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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bool CartridgeDASH::load(Serializer& in)
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{
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try
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{
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if(in.getString() != name())
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bool CartridgeDASH::load(Serializer& in) {
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try {
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if (in.getString() != name())
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return false;
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myCurrentBank = in.getShort();
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for(uInt32 bank = 0; bank < 4; bank++)
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for (uInt32 bank = 0; bank < 4; bank++)
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bankInUse[bank] = in.getShort();
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in.getByteArray(myRAM, RAM_TOTAL_SIZE);
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}
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catch (...)
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{
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} catch (...) {
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cerr << "ERROR: CartridgeDASH::load" << endl;
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return false;
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}
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@ -26,252 +26,255 @@ class System;
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#include "Cart.hxx"
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#ifdef DEBUGGER_SUPPORT
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class CartridgeDASHWidget;
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class CartridgeDASHWidget;
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// #include "CartDASHWidget.hxx"
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#endif
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/**
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Cartridge class for new tiling engine "Boulder Dash" format games with RAM.
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Kind of a combination of 3F and 3E, with better switchability.
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B.Watson's Cart3E was used as a template for building this implementation.
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Cartridge class for new tiling engine "Boulder Dash" format games with RAM.
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Kind of a combination of 3F and 3E, with better switchability.
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B.Watson's Cart3E was used as a template for building this implementation.
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Because a single bank number is used to define both the destination (0-3)
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AND the type (ROM/RAM) there are only 5 bits left to indicate the actual bank
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number. This sets the limits of 32K ROM and 16K RAM.
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Because a single bank number is used to define both the destination (0-3)
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AND the type (ROM/RAM) there are only 5 bits left to indicate the actual bank
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number. This sets the limits of 32K ROM and 16K RAM.
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D7 RAM/ROM flag (1=RAM)
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D6D5 indicate the bank number (0-3)
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D4D3D2D1D0 indicate the actual # (0-31) from the image/ram
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D7 RAM/ROM flag (1=RAM)
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D6D5 indicate the bank number (0-3)
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D4D3D2D1D0 indicate the actual # (0-31) from the image/ram
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Hotspot 0x3F is used for bank-switching, with the encoded bank # as above.
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Hotspot 0x3F is used for bank-switching, with the encoded bank # as above.
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ROM:
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ROM:
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In this scheme, the 4K address space is broken into four 1K ROM segments.
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living at 0x1000, 0x1400, 0x1800, 0x1C00 (or, same thing, 0xF000... etc.),
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and four 512 byte RAM segments, living at 0x1000, 0x1200, 0x1400, 0x1600
|
||||
with write-mirrors +0x800 of these. The last 1K ROM ($FC00-$FFFF) segment
|
||||
is initialised to point to the FIRST 1K of the ROM image, but it may be
|
||||
switched out at any time. Note, this is DIFFERENT to 3E which switches in
|
||||
the UPPER bank and this bank is fixed. This allows variable sized ROM
|
||||
without having to detect size. First bank (0) in ROM is the default fixed
|
||||
bank mapped to $FC00.
|
||||
In this scheme, the 4K address space is broken into four 1K ROM segments.
|
||||
living at 0x1000, 0x1400, 0x1800, 0x1C00 (or, same thing, 0xF000... etc.),
|
||||
and four 512 byte RAM segments, living at 0x1000, 0x1200, 0x1400, 0x1600
|
||||
with write-mirrors +0x800 of these. The last 1K ROM ($FC00-$FFFF) segment
|
||||
is initialised to point to the FIRST 1K of the ROM image, but it may be
|
||||
switched out at any time. Note, this is DIFFERENT to 3E which switches in
|
||||
the UPPER bank and this bank is fixed. This allows variable sized ROM
|
||||
without having to detect size. First bank (0) in ROM is the default fixed
|
||||
bank mapped to $FC00.
|
||||
|
||||
The system requires the reset vectors to be valid on a reset, so either the
|
||||
hardware first switches in the first bank, or the programmer must ensure
|
||||
that the reset vector is present in ALL ROM banks which might be switched
|
||||
into the last bank area. Currently the latter (programmer onus) is required,
|
||||
but it would be nice for the cartridge hardware to auto-switch on reset.
|
||||
The system requires the reset vectors to be valid on a reset, so either the
|
||||
hardware first switches in the first bank, or the programmer must ensure
|
||||
that the reset vector is present in ALL ROM banks which might be switched
|
||||
into the last bank area. Currently the latter (programmer onus) is required,
|
||||
but it would be nice for the cartridge hardware to auto-switch on reset.
|
||||
|
||||
ROM switching (write of block+bank number to $3F) D7=0 and D6D5 upper 2 bits of bank #
|
||||
indicates the destination segment (0-3, corresponding to $F000, $F400, $F800, $FC00),
|
||||
and lower 5 bits indicate the 1K bank to switch in. Can handle 32 x 1K ROM banks (32K total).
|
||||
ROM switching (write of block+bank number to $3F) D7=0 and D6D5 upper 2 bits of bank #
|
||||
indicates the destination segment (0-3, corresponding to $F000, $F400, $F800, $FC00),
|
||||
and lower 5 bits indicate the 1K bank to switch in. Can handle 32 x 1K ROM banks (32K total).
|
||||
|
||||
D7 D6 D5 D4D3D2D1D0
|
||||
0 0 0 x x x x x switch a 1K ROM bank xxxxx to $F000
|
||||
0 0 1 switch a 1K ROM bank xxxxx to $F400
|
||||
0 1 0 switch a 1K ROM bank xxxxx to $F800
|
||||
0 1 1 switch a 1K ROM bank xxxxx to $FC00
|
||||
D7 D6 D5 D4D3D2D1D0
|
||||
0 0 0 x x x x x switch a 1K ROM bank xxxxx to $F000
|
||||
0 0 1 switch a 1K ROM bank xxxxx to $F400
|
||||
0 1 0 switch a 1K ROM bank xxxxx to $F800
|
||||
0 1 1 switch a 1K ROM bank xxxxx to $FC00
|
||||
|
||||
RAM switching (write of segment+bank number to $3F) with D7=1 and D6D5 upper 2 bits of bank #
|
||||
indicates the destination RAM segment (0-3, corresponding to $F000, $F200, $F400, $F600).
|
||||
Note that this allows contiguous 2K of RAM to be configured by setting 4 consecutive RAM segments
|
||||
each 512 bytes with consecutive addresses. However, as the write address of RAM is +0x800, this
|
||||
invalidates ROM access as described below.
|
||||
RAM switching (write of segment+bank number to $3F) with D7=1 and D6D5 upper 2 bits of bank #
|
||||
indicates the destination RAM segment (0-3, corresponding to $F000, $F200, $F400, $F600).
|
||||
Note that this allows contiguous 2K of RAM to be configured by setting 4 consecutive RAM segments
|
||||
each 512 bytes with consecutive addresses. However, as the write address of RAM is +0x800, this
|
||||
invalidates ROM access as described below.
|
||||
|
||||
can handle 32 x 512 byte RAM banks (16K total)
|
||||
can handle 32 x 512 byte RAM banks (16K total)
|
||||
|
||||
D7 D6 D5 D4D3D2D1D0
|
||||
1 0 0 x x x x x switch a 512 byte RAM bank xxxxx to $F000 with write @ $F800
|
||||
0 1 switch a 512 byte RAM bank xxxxx to $F200 with write @ $FA00
|
||||
1 0 switch a 512 byte RAM bank xxxxx to $F400 with write @ $FC00
|
||||
1 1 switch a 512 byte RAM bank xxxxx to $F600 with write @ $FE00
|
||||
D7 D6 D5 D4D3D2D1D0
|
||||
1 0 0 x x x x x switch a 512 byte RAM bank xxxxx to $F000 with write @ $F800
|
||||
0 1 switch a 512 byte RAM bank xxxxx to $F200 with write @ $FA00
|
||||
1 0 switch a 512 byte RAM bank xxxxx to $F400 with write @ $FC00
|
||||
1 1 switch a 512 byte RAM bank xxxxx to $F600 with write @ $FE00
|
||||
|
||||
It is possible to switch multiple RAM banks and ROM banks together
|
||||
It is possible to switch multiple RAM banks and ROM banks together
|
||||
|
||||
For example,
|
||||
F000-F1FF RAM bank A (512 byte READ)
|
||||
F200-F3FF high 512 bytes of ROM bank previously loaded at F000
|
||||
F400 ROM bank 0 (1K)
|
||||
F800 RAM bank A (512 byte WRITE)
|
||||
FA00-FBFF high 512 bytes of ROM bank previously loaded at F400
|
||||
FC00 ROM bank 1
|
||||
For example,
|
||||
F000-F1FF RAM bank A (512 byte READ)
|
||||
F200-F3FF high 512 bytes of ROM bank previously loaded at F000
|
||||
F400 ROM bank 0 (1K)
|
||||
F800 RAM bank A (512 byte WRITE)
|
||||
FA00-FBFF high 512 bytes of ROM bank previously loaded at F400
|
||||
FC00 ROM bank 1
|
||||
|
||||
This example shows 512 bytes of RAM, and 2 1K ROM banks and two 512 byte ROM
|
||||
bank halves.
|
||||
This example shows 512 bytes of RAM, and 2 1K ROM banks and two 512 byte ROM
|
||||
bank halves.
|
||||
|
||||
Switching RAM blocks (D7D6 of $3E) partially invalidates ROM blocks, as below...
|
||||
Switching RAM blocks (D7D6 of $3E) partially invalidates ROM blocks, as below...
|
||||
|
||||
RAM block Invalidates ROM block
|
||||
0 0 (lower half), 2 (lower half)
|
||||
1 0 (upper half), 2 (upper half)
|
||||
2 1 (lower half), 3 (upper half)
|
||||
3 1 (upper half), 3 (lower half)
|
||||
RAM block Invalidates ROM block
|
||||
0 0 (lower half), 2 (lower half)
|
||||
1 0 (upper half), 2 (upper half)
|
||||
2 1 (lower half), 3 (upper half)
|
||||
3 1 (upper half), 3 (lower half)
|
||||
|
||||
For example, RAM block 1 uses address $F200-$F3FF and $FA00-$FBFF
|
||||
ROM block 0 uses address $F000-$F3FF, and ROM block 2 uses address $F800-$FBFF
|
||||
Switching in RAM block 1 makes F200-F3FF ROM inaccessible, however F000-F1FF is
|
||||
still readable. So, care must be paid.
|
||||
For example, RAM block 1 uses address $F200-$F3FF and $FA00-$FBFF
|
||||
ROM block 0 uses address $F000-$F3FF, and ROM block 2 uses address $F800-$FBFF
|
||||
Switching in RAM block 1 makes F200-F3FF ROM inaccessible, however F000-F1FF is
|
||||
still readable. So, care must be paid.
|
||||
|
||||
TODO: THe partial reading of ROM blocks switched out by RAM is not yet implemented!!
|
||||
TODO: THe partial reading of ROM blocks switched out by RAM is not yet implemented!!
|
||||
|
||||
This crazy RAM layout is useful as it allows contiguous RAM to be switched in,
|
||||
up to 2K in one sequentially accessible block. This means you CAN have 2K of
|
||||
consecutive RAM. If you don't detect ROM write area, then you would have NO ROM
|
||||
switched in (don't forget to copy your reset vectors!)
|
||||
This crazy RAM layout is useful as it allows contiguous RAM to be switched in,
|
||||
up to 2K in one sequentially accessible block. This means you CAN have 2K of
|
||||
consecutive RAM. If you don't detect ROM write area, then you would have NO ROM
|
||||
switched in (don't forget to copy your reset vectors!)
|
||||
|
||||
@author Andrew Davie
|
||||
*/
|
||||
@author Andrew Davie
|
||||
*/
|
||||
|
||||
class CartridgeDASH: public Cartridge
|
||||
{
|
||||
class CartridgeDASH: public Cartridge {
|
||||
friend class CartridgeDASHWidget;
|
||||
|
||||
public:
|
||||
/**
|
||||
Create a new cartridge using the specified image and size
|
||||
public:
|
||||
/**
|
||||
Create a new cartridge using the specified image and size
|
||||
|
||||
@param image Pointer to the ROM image
|
||||
@param size The size of the ROM image
|
||||
@param settings A reference to the various settings (read-only)
|
||||
*/
|
||||
CartridgeDASH(const uInt8* image, uInt32 size, const Settings& settings);
|
||||
@param image Pointer to the ROM image
|
||||
@param size The size of the ROM image
|
||||
@param settings A reference to the various settings (read-only)
|
||||
*/
|
||||
CartridgeDASH(const uInt8* image, uInt32 size, const Settings& settings);
|
||||
|
||||
/**
|
||||
Destructor
|
||||
*/
|
||||
virtual ~CartridgeDASH();
|
||||
/**
|
||||
Destructor
|
||||
*/
|
||||
virtual ~CartridgeDASH();
|
||||
|
||||
public:
|
||||
/**
|
||||
Reset device to its power-on state
|
||||
*/
|
||||
void reset();
|
||||
public:
|
||||
/**
|
||||
Reset device to its power-on state
|
||||
*/
|
||||
void reset();
|
||||
|
||||
/**
|
||||
Install cartridge in the specified system. Invoked by the system
|
||||
when the cartridge is attached to it.
|
||||
/**
|
||||
Install cartridge in the specified system. Invoked by the system
|
||||
when the cartridge is attached to it.
|
||||
|
||||
@param system The system the device should install itself in
|
||||
*/
|
||||
void install(System& system);
|
||||
@param system The system the device should install itself in
|
||||
*/
|
||||
void install(System& system);
|
||||
|
||||
/**
|
||||
Install pages for the specified bank in the system.
|
||||
/**
|
||||
Install pages for the specified bank in the system.
|
||||
|
||||
@param bank The bank that should be installed in the system
|
||||
*/
|
||||
bool bank(uInt16 bank);
|
||||
@param bank The bank that should be installed in the system
|
||||
*/
|
||||
bool bank(uInt16 bank);
|
||||
|
||||
/**
|
||||
Get the current bank.
|
||||
*/
|
||||
uInt16 bank() const;
|
||||
/**
|
||||
Get the current bank.
|
||||
*/
|
||||
uInt16 bank() const;
|
||||
|
||||
/**
|
||||
Query the number of banks supported by the cartridge.
|
||||
*/
|
||||
uInt16 bankCount() const;
|
||||
/**
|
||||
Query the number of banks supported by the cartridge.
|
||||
*/
|
||||
uInt16 bankCount() const;
|
||||
|
||||
/**
|
||||
Patch the cartridge ROM.
|
||||
/**
|
||||
Patch the cartridge ROM.
|
||||
|
||||
@param address The ROM address to patch
|
||||
@param value The value to place into the address
|
||||
@return Success or failure of the patch operation
|
||||
*/
|
||||
bool patch(uInt16 address, uInt8 value);
|
||||
@param address The ROM address to patch
|
||||
@param value The value to place into the address
|
||||
@return Success or failure of the patch operation
|
||||
*/
|
||||
bool patch(uInt16 address, uInt8 value);
|
||||
|
||||
/**
|
||||
Access the internal ROM image for this cartridge.
|
||||
/**
|
||||
Access the internal ROM image for this cartridge.
|
||||
|
||||
@param size Set to the size of the internal ROM image data
|
||||
@return A pointer to the internal ROM image data
|
||||
*/
|
||||
const uInt8* getImage(int& size) const;
|
||||
@param size Set to the size of the internal ROM image data
|
||||
@return A pointer to the internal ROM image data
|
||||
*/
|
||||
const uInt8* getImage(int& size) const;
|
||||
|
||||
/**
|
||||
Save the current state of this cart to the given Serializer.
|
||||
/**
|
||||
Save the current state of this cart to the given Serializer.
|
||||
|
||||
@param out The Serializer object to use
|
||||
@return False on any errors, else true
|
||||
*/
|
||||
bool save(Serializer& out) const;
|
||||
@param out The Serializer object to use
|
||||
@return False on any errors, else true
|
||||
*/
|
||||
bool save(Serializer& out) const;
|
||||
|
||||
/**
|
||||
Load the current state of this cart from the given Serializer.
|
||||
/**
|
||||
Load the current state of this cart from the given Serializer.
|
||||
|
||||
@param in The Serializer object to use
|
||||
@return False on any errors, else true
|
||||
*/
|
||||
bool load(Serializer& in);
|
||||
@param in The Serializer object to use
|
||||
@return False on any errors, else true
|
||||
*/
|
||||
bool load(Serializer& in);
|
||||
|
||||
/**
|
||||
Get a descriptor for the device name (used in error checking).
|
||||
/**
|
||||
Get a descriptor for the device name (used in error checking).
|
||||
|
||||
@return The name of the object
|
||||
*/
|
||||
string name() const { return "CartridgeDASH"; }
|
||||
@return The name of the object
|
||||
*/
|
||||
string name() const {
|
||||
return "CartridgeDASH";
|
||||
}
|
||||
|
||||
#ifdef DEBUGGER_SUPPORT
|
||||
/**
|
||||
Get debugger widget responsible for accessing the inner workings
|
||||
of the cart.
|
||||
*/
|
||||
CartDebugWidget* debugWidget(GuiObject* boss, const GUI::Font& lfont,
|
||||
const GUI::Font& nfont, int x, int y, int w, int h)
|
||||
{
|
||||
return 0;//new CartridgeDASHWidget(boss, lfont, nfont, x, y, w, h, *this);
|
||||
}
|
||||
/**
|
||||
Get debugger widget responsible for accessing the inner workings
|
||||
of the cart.
|
||||
*/
|
||||
CartDebugWidget* debugWidget(GuiObject* boss, const GUI::Font& lfont,
|
||||
const GUI::Font& nfont, int x, int y, int w, int h)
|
||||
{
|
||||
return 0; //new CartridgeDASHWidget(boss, lfont, nfont, x, y, w, h, *this);
|
||||
}
|
||||
#endif
|
||||
|
||||
public:
|
||||
/**
|
||||
Get the byte at the specified address
|
||||
public:
|
||||
/**
|
||||
Get the byte at the specified address
|
||||
|
||||
@return The byte at the specified address
|
||||
*/
|
||||
uInt8 peek(uInt16 address);
|
||||
@return The byte at the specified address
|
||||
*/
|
||||
uInt8 peek(uInt16 address);
|
||||
|
||||
/**
|
||||
Change the byte at the specified address to the given value
|
||||
/**
|
||||
Change the byte at the specified address to the given value
|
||||
|
||||
@param address The address where the value should be stored
|
||||
@param value The value to be stored at the address
|
||||
@return True if the poke changed the device address space, else false
|
||||
*/
|
||||
bool poke(uInt16 address, uInt8 value);
|
||||
@param address The address where the value should be stored
|
||||
@param value The value to be stored at the address
|
||||
@return True if the poke changed the device address space, else false
|
||||
*/
|
||||
bool poke(uInt16 address, uInt8 value);
|
||||
|
||||
private:
|
||||
uInt16 myCurrentBank; // whatever the LAST switched bank was...
|
||||
private:
|
||||
Int16 myCurrentBank; // whatever the LAST switched bank was...
|
||||
|
||||
uInt32 mySize; // Size of the ROM image
|
||||
uInt8* myImage; // Pointer to a dynamically allocated ROM image of the cartridge
|
||||
uInt32 mySize; // Size of the ROM image
|
||||
uInt8* myImage; // Pointer to a dynamically allocated ROM image of the cartridge
|
||||
|
||||
Int16 bankInUse[4]; // bank being used for ROM/RAM (-1 = undefined)
|
||||
Int16 bankInUse[4]; // bank being used for ROM/RAM (-1 = undefined)
|
||||
|
||||
static const uInt16 BANK_SWITCH_HOTSPOT = 0x3F; // writes to this address cause bankswitching
|
||||
static const uInt16 BANK_SWITCH_HOTSPOT = 0x3F; // writes to this address cause bankswitching
|
||||
|
||||
static const uInt8 BANK_BITS = 5; // # bits for bank
|
||||
static const uInt8 BIT_BANK_MASK = (1 << BANK_BITS) - 1; // mask for those bits
|
||||
static const uInt8 ROMRAM = 0x80; // flags ROM or RAM bank switching (1==RAM)
|
||||
static const uInt8 BANK_BITS = 5; // # bits for bank
|
||||
static const uInt8 BIT_BANK_MASK = (1 << BANK_BITS) - 1; // mask for those bits
|
||||
static const uInt8 BITMASK_ROMRAM = 0x80; // flags ROM or RAM bank switching (1==RAM)
|
||||
|
||||
static const uInt16 RAM_BANK_COUNT = 32;
|
||||
static const uInt16 RAM_BANK_TO_POWER = 9; // 2^n = 512
|
||||
static const uInt16 RAM_BANK_SIZE = (1 << RAM_BANK_TO_POWER);
|
||||
static const uInt32 RAM_TOTAL_SIZE = RAM_BANK_COUNT * RAM_BANK_SIZE;
|
||||
static const uInt16 RAM_BANK_COUNT = 32;
|
||||
static const uInt16 RAM_BANK_TO_POWER = 9; // 2^n = 512
|
||||
static const uInt16 RAM_BANK_SIZE = (1 << RAM_BANK_TO_POWER);
|
||||
static const uInt16 BITMASK_RAM_BANK = (RAM_BANK_SIZE - 1);
|
||||
static const uInt32 RAM_TOTAL_SIZE = RAM_BANK_COUNT * RAM_BANK_SIZE;
|
||||
|
||||
static const uInt16 ROM_BANK_TO_POWER = 10; // 2^n = 1024
|
||||
static const uInt16 ROM_BANK_SIZE = (1 << ROM_BANK_TO_POWER);
|
||||
static const uInt16 ROM_BANK_TO_POWER = 10; // 2^n = 1024
|
||||
static const uInt16 ROM_BANK_SIZE = (1 << ROM_BANK_TO_POWER);
|
||||
static const uInt16 BITMASK_ROM_BANK = (ROM_BANK_SIZE -1);
|
||||
|
||||
static const uInt16 ROM_BANK_COUNT = 32;
|
||||
static const uInt16 ROM_BANK_MASK = (ROM_BANK_COUNT - 1);
|
||||
static const uInt16 ROM_BANK_COUNT = 32;
|
||||
static const uInt16 BITMASK_ROM_BANK = (ROM_BANK_COUNT - 1);
|
||||
|
||||
static const uInt16 RAM_WRITE_OFFSET = 0x800;
|
||||
static const uInt16 RAM_WRITE_OFFSET = 0x800;
|
||||
|
||||
static const Int16 BANK_UNDEFINED = -1; // bank is undefined and inaccessible
|
||||
static const Int16 BANK_UNDEFINED = -1; // bank is undefined and inaccessible
|
||||
|
||||
uInt8 myRAM[RAM_TOTAL_SIZE];
|
||||
uInt8 myRAM[RAM_TOTAL_SIZE];
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue