mirror of https://github.com/stella-emu/stella.git
Added more accurate functionality for the _rwport debugger command. It now
properly distinguishes between intermediate reads which are part of writes, and ordinary reads. In the former case, only a read which has a different address than a write is flagged as an error; intermediate reads acting on the same address as the corresponding write are considered normal, and won't trigger a break. git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1901 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
This commit is contained in:
parent
00f8ffb686
commit
19f146038d
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@ -198,9 +198,7 @@ void Debugger::setConsole(Console* console)
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// Register any RAM areas in the Cartridge
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// Register any RAM areas in the Cartridge
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// Zero-page RAM is automatically recognized by RamDebug
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// Zero-page RAM is automatically recognized by RamDebug
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const Cartridge::RamAreaList& areas = myConsole->cartridge().ramAreas();
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myRamDebug->addRamArea(myConsole->cartridge().ramAreas());
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for(Cartridge::RamAreaList::const_iterator i = areas.begin(); i != areas.end(); ++i)
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myRamDebug->addRamArea(i->start, i->size, i->roffset, i->woffset);
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delete myRiotDebug;
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delete myRiotDebug;
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myRiotDebug = new RiotDebug(*this, *myConsole);
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myRiotDebug = new RiotDebug(*this, *myConsole);
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@ -23,8 +23,7 @@
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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RamDebug::RamDebug(Debugger& dbg, Console& console)
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RamDebug::RamDebug(Debugger& dbg, Console& console)
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: DebuggerSystem(dbg, console),
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: DebuggerSystem(dbg, console)
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myReadFromWritePortAddress(0)
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{
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{
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// Zero-page RAM is always present
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// Zero-page RAM is always present
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addRamArea(0x80, 128, 0, 0);
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addRamArea(0x80, 128, 0, 0);
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@ -51,6 +50,14 @@ void RamDebug::addRamArea(uInt16 start, uInt16 size,
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}
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}
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}
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void RamDebug::addRamArea(const RamAreaList& areas)
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{
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myRamAreas = areas;
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for(RamAreaList::const_iterator i = areas.begin(); i != areas.end(); ++i)
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addRamArea(i->start, i->size, i->roffset, i->woffset);
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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const DebuggerState& RamDebug::getState()
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const DebuggerState& RamDebug::getState()
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{
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{
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@ -84,17 +91,19 @@ void RamDebug::write(uInt16 addr, uInt8 value)
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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int RamDebug::readFromWritePort()
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int RamDebug::readFromWritePort()
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{
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{
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int retval = myReadFromWritePortAddress;
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uInt16 addr = mySystem.m6502().lastReadAddress();
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if(retval > 0)
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if(addr & 0x1000)
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myReadFromWritePortAddress = 0;
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{
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addr &= 0x0FFF;
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return retval;
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for(RamAreaList::const_iterator i = myRamAreas.begin(); i != myRamAreas.end(); ++i)
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}
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{
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uInt16 start = (i->start + i->woffset) & 0x0FFF;
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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uInt16 end = (i->start + i->woffset + i->size) & 0x0FFF;
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void RamDebug::setReadFromWritePort(uInt16 address)
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if(addr >= start && addr < end)
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{
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return addr;
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myReadFromWritePortAddress = address;
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}
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}
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return 0;
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}
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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@ -23,6 +23,7 @@ class System;
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#include "bspf.hxx"
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#include "bspf.hxx"
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#include "Array.hxx"
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#include "Array.hxx"
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#include "Cart.hxx"
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#include "DebuggerSystem.hxx"
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#include "DebuggerSystem.hxx"
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// pointer types for RamDebug instance methods
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// pointer types for RamDebug instance methods
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@ -53,6 +54,7 @@ class RamDebug : public DebuggerSystem
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@param woffset Offset to use when writing to RAM (write port)
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@param woffset Offset to use when writing to RAM (write port)
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*/
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*/
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void addRamArea(uInt16 start, uInt16 size, uInt16 roffset, uInt16 woffset);
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void addRamArea(uInt16 start, uInt16 size, uInt16 roffset, uInt16 woffset);
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void addRamArea(const RamAreaList& areas);
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const DebuggerState& getState();
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const DebuggerState& getState();
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const DebuggerState& getOldState() { return myOldState; }
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const DebuggerState& getOldState() { return myOldState; }
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@ -66,22 +68,15 @@ class RamDebug : public DebuggerSystem
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uInt8 read(uInt16 addr);
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uInt8 read(uInt16 addr);
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void write(uInt16 addr, uInt8 value);
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void write(uInt16 addr, uInt8 value);
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// These methods are used by the debugger when we wish to know
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// Return the address at which an invalid read was performed in a
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// if an illegal read from a write port has been performed.
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// write port area.
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// It's up to each Cartridge to report the error, and a
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// conditional breakpoint must be set in the debugger to check
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// for occurrences of this.
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//
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// Note that each time readFromWritePort() returns a hit, the status
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// is reset.
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int readFromWritePort();
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int readFromWritePort();
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void setReadFromWritePort(uInt16 address);
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private:
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private:
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RamState myState;
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RamState myState;
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RamState myOldState;
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RamState myOldState;
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uInt16 myReadFromWritePortAddress;
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RamAreaList myRamAreas;
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};
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};
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#endif
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#endif
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@ -251,20 +251,13 @@ bool Cartridge::save(ofstream& out)
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void Cartridge::registerRamArea(uInt16 start, uInt16 size,
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void Cartridge::registerRamArea(uInt16 start, uInt16 size,
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uInt16 roffset, uInt16 woffset)
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uInt16 roffset, uInt16 woffset)
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{
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{
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#ifdef DEBUGGER_SUPPORT
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RamArea area;
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RamArea area;
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area.start = start;
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area.start = start;
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area.size = size;
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area.size = size;
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area.roffset = roffset;
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area.roffset = roffset;
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area.woffset = woffset;
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area.woffset = woffset;
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myRamAreaList.push_back(area);
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myRamAreaList.push_back(area);
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void Cartridge::triggerReadFromWritePort(uInt16 address)
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{
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#ifdef DEBUGGER_SUPPORT
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if(&Debugger::debugger().ramDebug())
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Debugger::debugger().ramDebug().setReadFromWritePort(address);
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#endif
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#endif
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}
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}
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#include "Array.hxx"
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#include "Array.hxx"
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#include "Device.hxx"
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#include "Device.hxx"
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#ifdef DEBUGGER_SUPPORT
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struct RamArea {
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uInt16 start; uInt16 size; uInt16 roffset; uInt16 woffset;
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};
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typedef Common::Array<RamArea> RamAreaList;
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#endif
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/**
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/**
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A cartridge is a device which contains the machine code for a
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A cartridge is a device which contains the machine code for a
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game and handles any bankswitching performed by the cartridge.
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game and handles any bankswitching performed by the cartridge.
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void lockBank() { myBankLocked = true; }
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void lockBank() { myBankLocked = true; }
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void unlockBank() { myBankLocked = false; }
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void unlockBank() { myBankLocked = false; }
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public:
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#ifdef DEBUGGER_SUPPORT
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/**
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The following list contains addressable areas of ROM that are mapped
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to RAM (usually Superchip, but there are other types). Since such
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RAM is normally mapped in at different addresses for read and write
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ports, read and write offsets must be considered.
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@return List of addressable RAM areas (can be empty)
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*/
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struct RamArea {
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uInt16 start; uInt16 size; uInt16 roffset; uInt16 woffset;
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};
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typedef Common::Array<RamArea> RamAreaList;
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const RamAreaList& ramAreas() { return myRamAreaList; }
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const RamAreaList& ramAreas() { return myRamAreaList; }
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#endif
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public:
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public:
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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*/
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*/
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void registerRamArea(uInt16 start, uInt16 size, uInt16 roffset, uInt16 woffset);
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void registerRamArea(uInt16 start, uInt16 size, uInt16 roffset, uInt16 woffset);
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/**
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Indicate that an illegal read from the write port has occurred.
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This message is sent to the debugger (if support exists).
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@param address The write port address where the read occurred
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*/
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void triggerReadFromWritePort(uInt16 address);
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private:
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private:
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/**
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/**
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Get an image pointer and size for a ROM that is part of a larger,
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Get an image pointer and size for a ROM that is part of a larger,
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bool myBankLocked;
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bool myBankLocked;
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private:
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private:
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#ifdef DEBUGGER_SUPPORT
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// Contains RamArea entries for those carts with accessible RAM.
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// Contains RamArea entries for those carts with accessible RAM.
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RamAreaList myRamAreaList;
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RamAreaList myRamAreaList;
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#endif
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// Contains info about this cartridge in string format
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// Contains info about this cartridge in string format
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static string myAboutString;
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static string myAboutString;
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// Reading from the write port triggers an unwanted write
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// Reading from the write port triggers an unwanted write
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uInt8 value = mySystem->getDataBusState(0xFF);
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uInt8 value = mySystem->getDataBusState(0xFF);
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if(myBankLocked)
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if(myBankLocked) return value;
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return value;
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else return myRam[(address & 0x03FF) + ((myCurrentBank - 256) << 10)] = value;
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else
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{
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triggerReadFromWritePort(address);
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return myRam[(address & 0x03FF) + ((myCurrentBank - 256) << 10)] = value;
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}
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}
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}
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}
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}
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}
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}
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@ -113,13 +113,8 @@ uInt8 CartridgeCV::peek(uInt16 address)
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// Reading from the write port triggers an unwanted write
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// Reading from the write port triggers an unwanted write
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uInt8 value = mySystem->getDataBusState(0xFF);
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uInt8 value = mySystem->getDataBusState(0xFF);
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if(myBankLocked)
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if(myBankLocked) return value;
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return value;
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else return myRAM[address & 0x03FF] = value;
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else
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{
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triggerReadFromWritePort(address);
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return myRAM[address & 0x03FF] = value;
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}
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}
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}
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else
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else
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{
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{
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@ -111,13 +111,8 @@ uInt8 CartridgeE7::peek(uInt16 address)
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// Reading from the write port triggers an unwanted write
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// Reading from the write port triggers an unwanted write
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uInt8 value = mySystem->getDataBusState(0xFF);
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uInt8 value = mySystem->getDataBusState(0xFF);
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if(myBankLocked)
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if(myBankLocked) return value;
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return value;
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else return myImage[(myCurrentSlice[address >> 11] << 11) + (address & 0x07FF)] = value;
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else
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{
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triggerReadFromWritePort(address);
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return myImage[(myCurrentSlice[address >> 11] << 11) + (address & 0x07FF)] = value;
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}
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}
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}
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else
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else
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return myImage[(myCurrentSlice[address >> 11] << 11) + (address & 0x07FF)];
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return myImage[(myCurrentSlice[address >> 11] << 11) + (address & 0x07FF)];
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@ -104,13 +104,8 @@ uInt8 CartridgeEFSC::peek(uInt16 address)
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// Reading from the write port triggers an unwanted write
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// Reading from the write port triggers an unwanted write
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uInt8 value = mySystem->getDataBusState(0xFF);
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uInt8 value = mySystem->getDataBusState(0xFF);
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if(myBankLocked)
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if(myBankLocked) return value;
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return value;
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else return myRAM[address] = value;
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else
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{
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triggerReadFromWritePort(address);
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return myRAM[address] = value;
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}
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}
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}
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else
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else
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return myImage[(myCurrentBank << 12) + address];
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return myImage[(myCurrentBank << 12) + address];
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@ -104,13 +104,8 @@ uInt8 CartridgeF4SC::peek(uInt16 address)
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// Reading from the write port triggers an unwanted write
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// Reading from the write port triggers an unwanted write
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uInt8 value = mySystem->getDataBusState(0xFF);
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uInt8 value = mySystem->getDataBusState(0xFF);
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if(myBankLocked)
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if(myBankLocked) return value;
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return value;
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else return myRAM[address] = value;
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else
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{
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triggerReadFromWritePort(address);
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return myRAM[address] = value;
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}
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}
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}
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else
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else
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return myImage[(myCurrentBank << 12) + address];
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return myImage[(myCurrentBank << 12) + address];
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@ -127,13 +127,8 @@ uInt8 CartridgeF6SC::peek(uInt16 address)
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// Reading from the write port triggers an unwanted write
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// Reading from the write port triggers an unwanted write
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uInt8 value = mySystem->getDataBusState(0xFF);
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uInt8 value = mySystem->getDataBusState(0xFF);
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if(myBankLocked)
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if(myBankLocked) return value;
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return value;
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else return myRAM[address] = value;
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else
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{
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triggerReadFromWritePort(address);
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return myRAM[address] = value;
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}
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}
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}
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else
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else
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return myImage[(myCurrentBank << 12) + address];
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return myImage[(myCurrentBank << 12) + address];
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@ -117,13 +117,8 @@ uInt8 CartridgeF8SC::peek(uInt16 address)
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// Reading from the write port triggers an unwanted write
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// Reading from the write port triggers an unwanted write
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uInt8 value = mySystem->getDataBusState(0xFF);
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uInt8 value = mySystem->getDataBusState(0xFF);
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if(myBankLocked)
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if(myBankLocked) return value;
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return value;
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else return myRAM[address] = value;
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else
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{
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triggerReadFromWritePort(address);
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return myRAM[address] = value;
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}
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}
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}
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else
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else
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return myImage[(myCurrentBank << 12) + address];
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return myImage[(myCurrentBank << 12) + address];
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@ -122,13 +122,8 @@ uInt8 CartridgeFA::peek(uInt16 address)
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// Reading from the write port triggers an unwanted write
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// Reading from the write port triggers an unwanted write
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uInt8 value = mySystem->getDataBusState(0xFF);
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uInt8 value = mySystem->getDataBusState(0xFF);
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if(myBankLocked)
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if(myBankLocked) return value;
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return value;
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else return myRAM[address] = value;
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else
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{
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triggerReadFromWritePort(address);
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return myRAM[address] = value;
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}
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}
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}
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else
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else
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return myImage[(myCurrentBank << 12) + address];
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return myImage[(myCurrentBank << 12) + address];
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@ -146,13 +146,8 @@ uInt8 CartridgeMC::peek(uInt16 address)
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// Reading from the write port triggers an unwanted write
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// Reading from the write port triggers an unwanted write
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uInt8 value = mySystem->getDataBusState(0xFF);
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uInt8 value = mySystem->getDataBusState(0xFF);
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||||||
if(myBankLocked)
|
if(myBankLocked) return value;
|
||||||
return value;
|
else return myRAM[(uInt32)((block & 0x3F) << 9) + (address & 0x01FF)] = value;
|
||||||
else
|
|
||||||
{
|
|
||||||
triggerReadFromWritePort(address);
|
|
||||||
return myRAM[(uInt32)((block & 0x3F) << 9) + (address & 0x01FF)] = value;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
@ -19,7 +19,6 @@
|
||||||
#ifndef CONSOLE_HXX
|
#ifndef CONSOLE_HXX
|
||||||
#define CONSOLE_HXX
|
#define CONSOLE_HXX
|
||||||
|
|
||||||
class Console;
|
|
||||||
class Controller;
|
class Controller;
|
||||||
class Event;
|
class Event;
|
||||||
class Switches;
|
class Switches;
|
||||||
|
|
|
@ -34,7 +34,9 @@ M6502::M6502(uInt32 systemCyclesPerProcessorCycle)
|
||||||
myLastAccessWasRead(true),
|
myLastAccessWasRead(true),
|
||||||
myTotalInstructionCount(0),
|
myTotalInstructionCount(0),
|
||||||
myNumberOfDistinctAccesses(0),
|
myNumberOfDistinctAccesses(0),
|
||||||
myLastAddress(0)
|
myLastAddress(0),
|
||||||
|
myLastPeekAddress(0),
|
||||||
|
myLastPokeAddress(0)
|
||||||
{
|
{
|
||||||
#ifdef DEBUGGER_SUPPORT
|
#ifdef DEBUGGER_SUPPORT
|
||||||
myDebugger = NULL;
|
myDebugger = NULL;
|
||||||
|
@ -169,6 +171,7 @@ inline uInt8 M6502::peek(uInt16 address)
|
||||||
|
|
||||||
uInt8 result = mySystem->peek(address);
|
uInt8 result = mySystem->peek(address);
|
||||||
myLastAccessWasRead = true;
|
myLastAccessWasRead = true;
|
||||||
|
myLastPeekAddress = address;
|
||||||
return result;
|
return result;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -193,6 +196,7 @@ inline void M6502::poke(uInt16 address, uInt8 value)
|
||||||
|
|
||||||
mySystem->poke(address, value);
|
mySystem->poke(address, value);
|
||||||
myLastAccessWasRead = false;
|
myLastAccessWasRead = false;
|
||||||
|
myLastPokeAddress = address;
|
||||||
}
|
}
|
||||||
|
|
||||||
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
||||||
|
@ -206,9 +210,6 @@ bool M6502::execute(uInt32 number)
|
||||||
{
|
{
|
||||||
for(; !myExecutionStatus && (number != 0); --number)
|
for(; !myExecutionStatus && (number != 0); --number)
|
||||||
{
|
{
|
||||||
uInt16 operandAddress = 0;
|
|
||||||
uInt8 operand = 0;
|
|
||||||
|
|
||||||
#ifdef DEBUGGER_SUPPORT
|
#ifdef DEBUGGER_SUPPORT
|
||||||
if(myJustHitTrapFlag)
|
if(myJustHitTrapFlag)
|
||||||
{
|
{
|
||||||
|
@ -236,6 +237,11 @@ bool M6502::execute(uInt32 number)
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
uInt16 operandAddress = 0;
|
||||||
|
uInt8 operand = 0;
|
||||||
|
|
||||||
|
// Reset the peek/poke address pointers
|
||||||
|
myLastPeekAddress = myLastPokeAddress = 0;
|
||||||
|
|
||||||
// Fetch instruction at the program counter
|
// Fetch instruction at the program counter
|
||||||
IR = peek(PC++);
|
IR = peek(PC++);
|
||||||
|
|
|
@ -154,6 +154,20 @@ class M6502 : public Serializable
|
||||||
*/
|
*/
|
||||||
bool lastAccessWasRead() const { return myLastAccessWasRead; }
|
bool lastAccessWasRead() const { return myLastAccessWasRead; }
|
||||||
|
|
||||||
|
/**
|
||||||
|
Return the last address that was part of a read/peek. Note that
|
||||||
|
reads which are part of a write are not considered here, unless
|
||||||
|
they're not the same as the last write address. This eliminates
|
||||||
|
accesses that are part of a normal read/write cycle.
|
||||||
|
|
||||||
|
@return The address of the last read
|
||||||
|
*/
|
||||||
|
uInt16 lastReadAddress() const {
|
||||||
|
return myLastPokeAddress ?
|
||||||
|
(myLastPokeAddress != myLastPeekAddress ? myLastPeekAddress : 0) :
|
||||||
|
myLastPeekAddress;
|
||||||
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
Get the total number of instructions executed so far.
|
Get the total number of instructions executed so far.
|
||||||
|
|
||||||
|
@ -325,6 +339,10 @@ class M6502 : public Serializable
|
||||||
/// Indicates the last address which was accessed
|
/// Indicates the last address which was accessed
|
||||||
uInt16 myLastAddress;
|
uInt16 myLastAddress;
|
||||||
|
|
||||||
|
/// Indicates the last address which was accessed specifically
|
||||||
|
/// by a peek or poke command
|
||||||
|
uInt16 myLastPeekAddress, myLastPokeAddress;
|
||||||
|
|
||||||
#ifdef DEBUGGER_SUPPORT
|
#ifdef DEBUGGER_SUPPORT
|
||||||
/// Pointer to the debugger for this processor or the null pointer
|
/// Pointer to the debugger for this processor or the null pointer
|
||||||
Debugger* myDebugger;
|
Debugger* myDebugger;
|
||||||
|
|
|
@ -28,7 +28,7 @@
|
||||||
|
|
||||||
namespace GUI {
|
namespace GUI {
|
||||||
|
|
||||||
/*! @brief simple class for handling both 2D position and size
|
/*! @brief simple class for handling both 2D position and size
|
||||||
|
|
||||||
This small class is an helper for position and size values.
|
This small class is an helper for position and size values.
|
||||||
*/
|
*/
|
||||||
|
|
Loading…
Reference in New Issue