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fix M6532 access counters 

make stack pops result into DATA access
This commit is contained in:
thrust26 2020-04-02 17:59:04 +02:00
parent 541a40c44b
commit 17835be278
3 changed files with 13 additions and 13 deletions
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10
src/emucore/M6502.ins
View File

@ -3770,9 +3770,9 @@ case 0x40:
} }
{ {
peek(0x0100 + SP++, DISASM_NONE); peek(0x0100 + SP++, DISASM_NONE);
PS(peek(0x0100 + SP++, DISASM_NONE)); PS(peek(0x0100 + SP++, DISASM_DATA));
PC = peek(0x0100 + SP++, DISASM_NONE); PC = peek(0x0100 + SP++, DISASM_DATA);
PC |= (uInt16(peek(0x0100 + SP, DISASM_NONE)) << 8); PC |= (uInt16(peek(0x0100 + SP, DISASM_DATA)) << 8);
} }
break; break;
@ -3784,8 +3784,8 @@ case 0x60:
} }
{ {
peek(0x0100 + SP++, DISASM_NONE); peek(0x0100 + SP++, DISASM_NONE);
PC = peek(0x0100 + SP++, DISASM_NONE); PC = peek(0x0100 + SP++, DISASM_DATA);
PC |= (uInt16(peek(0x0100 + SP, DISASM_NONE)) << 8); PC |= (uInt16(peek(0x0100 + SP, DISASM_DATA)) << 8);
peek(PC++, DISASM_NONE); peek(PC++, DISASM_NONE);
} }
break; break;

10
src/emucore/M6502.m4
View File

@ -885,15 +885,15 @@ define(M6502_RRA, `{
define(M6502_RTI, `{ define(M6502_RTI, `{
peek(0x0100 + SP++, DISASM_NONE); peek(0x0100 + SP++, DISASM_NONE);
PS(peek(0x0100 + SP++, DISASM_NONE)); PS(peek(0x0100 + SP++, DISASM_DATA));
PC = peek(0x0100 + SP++, DISASM_NONE); PC = peek(0x0100 + SP++, DISASM_DATA);
PC |= (uInt16(peek(0x0100 + SP, DISASM_NONE)) << 8); PC |= (uInt16(peek(0x0100 + SP, DISASM_DATA)) << 8);
}') }')
define(M6502_RTS, `{ define(M6502_RTS, `{
peek(0x0100 + SP++, DISASM_NONE); peek(0x0100 + SP++, DISASM_NONE);
PC = peek(0x0100 + SP++, DISASM_NONE); PC = peek(0x0100 + SP++, DISASM_DATA);
PC |= (uInt16(peek(0x0100 + SP, DISASM_NONE)) << 8); PC |= (uInt16(peek(0x0100 + SP, DISASM_DATA)) << 8);
peek(PC++, DISASM_NONE); peek(PC++, DISASM_NONE);
}') }')

6
src/emucore/M6532.cxx
View File

@ -501,15 +501,15 @@ void M6532::setAccessFlags(uInt16 address, Device::AccessFlags flags)
void M6532::increaseAccessCounter(uInt16 address, bool isWrite) void M6532::increaseAccessCounter(uInt16 address, bool isWrite)
{ {
if (address & IO_BIT) if (address & IO_BIT)
myIOAccessCounter[isWrite ? 0 : IO_SIZE + (address & IO_MASK)]++; myIOAccessCounter[(isWrite ? IO_SIZE : 0) + (address & IO_MASK)]++;
else { else {
// the first access, either by direct RAM or stack access is assumed as initialization // the first access, either by direct RAM or stack access is assumed as initialization
if (myZPAccessDelay[address & RAM_MASK]) if (myZPAccessDelay[address & RAM_MASK])
myZPAccessDelay[address & RAM_MASK]--; myZPAccessDelay[address & RAM_MASK]--;
else if (address & STACK_BIT) else if (address & STACK_BIT)
myStackAccessCounter[isWrite ? 0 : STACK_SIZE + (address & STACK_MASK)]++; myStackAccessCounter[(isWrite ? STACK_SIZE : 0) + (address & STACK_MASK)]++;
else else
myRAMAccessCounter[isWrite ? 0 : RAM_SIZE + (address & RAM_MASK)]++; myRAMAccessCounter[(isWrite ? RAM_SIZE : 0) + (address & RAM_MASK)]++;
} }
} }