mirror of https://github.com/stella-emu/stella.git
refactored CartWD
fixed CartEnhanced for multi-segment ROMs with extra RAM improved CartEnhanced by enabling directPoke for extra RAM
This commit is contained in:
thrust26
parent
0851a445e5
commit
0bf12045d8
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@ -29,44 +29,17 @@ Cartridge3EPlus::Cartridge3EPlus(const ByteBuffer& image, size_t size,
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myRamSize = RAM_SIZE;
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myRamBankCount = RAM_BANKS;
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myRamWpHigh = RAM_HIGH_WP;
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//// Allocate array for the ROM image
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//myImage = make_unique<uInt8[]>(mySize);
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//// Copy the ROM image into my buffer
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//std::copy_n(image.get(), mySize, myImage.get());
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//createRomAccessArrays(mySize + myRAM.size());
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}
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//// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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//void Cartridge3EPlus::reset()
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//{
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// initializeRAM(myRAM.data(), myRAM.size());
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//
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// // Remember startup bank (0 per spec, rather than last per 3E scheme).
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// // Set this to go to 3rd 1K Bank.
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// initializeStartBank(0);
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//
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// // Initialise bank values for all ROM/RAM access
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// // This is used to reverse-lookup from address to bank location
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// for(auto& b: bankInUse)
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// b = BANK_UNDEFINED; // bank is undefined and inaccessible!
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//
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// initializeBankState();
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//
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// // We'll map the startup banks 0 and 3 from the image into the third 1K bank upon reset
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// bankROM((0 << BANK_BITS) | 0);
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// bankROM((3 << BANK_BITS) | 0);
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//}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void Cartridge3EPlus::reset()
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{
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CartridgeEnhanced::reset();
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// 1st segment in mapped to start bank in CartridgeEnhanced
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bank(mySystem->randGenerator().next() % romBankCount(), 1);
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bank(mySystem->randGenerator().next() % romBankCount(), 2);
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bank(startBank(), 3); // Stella reads the PC vector always from here (TODO?)
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bank(startBank(), 3);
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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@ -68,6 +68,8 @@ void CartridgeEnhanced::install(System& system)
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for(uInt16 addr = ROM_OFFSET + myWriteOffset; addr < ROM_OFFSET + myWriteOffset + myRamSize; addr += System::PAGE_SIZE)
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{
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uInt16 offset = addr & myRamMask;
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access.directPokeBase = &myRAM[offset];
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access.romAccessBase = &myRomAccessBase[myWriteOffset + offset];
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access.romPeekCounter = &myRomAccessCounter[myWriteOffset + offset];
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access.romPokeCounter = &myRomAccessCounter[myWriteOffset + offset + myAccessSize];
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@ -76,6 +78,7 @@ void CartridgeEnhanced::install(System& system)
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// Set the page accessing method for the RAM reading pages
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access.type = System::PageAccessType::READ;
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access.directPokeBase = nullptr;
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for(uInt16 addr = ROM_OFFSET + myReadOffset; addr < ROM_OFFSET + myReadOffset + myRamSize; addr += System::PAGE_SIZE)
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{
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uInt16 offset = addr & myRamMask;
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@ -125,7 +128,7 @@ uInt8 CartridgeEnhanced::peek(uInt16 address)
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}
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else
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{
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address &= myBankMask;
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address &= ROM_MASK;
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// Write port is e.g. at 0xF000 - 0xF07F (128 bytes)
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if(address < myReadOffset + myRamSize && address >= myReadOffset)
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@ -133,7 +136,8 @@ uInt8 CartridgeEnhanced::peek(uInt16 address)
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// Reading from the write port triggers an unwanted write
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return peekRAM(myRAM[address], peekAddress);
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else
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return myImage[myCurrentSegOffset[(peekAddress & ROM_MASK) >> myBankShift] + address];
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return myImage[myCurrentSegOffset[(peekAddress & ROM_MASK) >> myBankShift]
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+ (peekAddress & myBankMask)];
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}
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}
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@ -206,7 +210,8 @@ bool CartridgeEnhanced::bank(uInt16 bank, uInt16 segment)
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uInt32 bankOffset = myCurrentSegOffset[segment] = romBank << myBankShift;
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uInt16 hotspot = this->hotspot();
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uInt16 hotSpotAddr;
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uInt16 fromAddr = (ROM_OFFSET + segmentOffset + myRomOffset) & ~System::PAGE_MASK;
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// Skip extra RAM; if existing it is only mapped into first segment
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uInt16 fromAddr = (ROM_OFFSET + segmentOffset + (segment == 0 ? myRomOffset : 0)) & ~System::PAGE_MASK;
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// for ROMs < 4_KB, the whole address space will be mapped.
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uInt16 toAddr = (ROM_OFFSET + segmentOffset + (mySize < 4_KB ? 4_KB : myBankSize)) & ~System::PAGE_MASK;
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@ -65,7 +65,7 @@ class CartridgeEnhanced : public Cartridge
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@return true, if bank has changed
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*/
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bool bank(uInt16 bank, uInt16 segment);
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virtual bool bank(uInt16 bank, uInt16 segment);
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/**
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Install pages for the specified bank in the system.
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@ -23,70 +23,46 @@
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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CartridgeWD::CartridgeWD(const ByteBuffer& image, size_t size,
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const string& md5, const Settings& settings)
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: Cartridge(settings, md5),
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mySize(std::min<size_t>(8_KB + 3, size))
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: CartridgeEnhanced(image, size, md5, settings)
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{
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// Copy the ROM image into my buffer
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if (mySize == 8_KB + 3)
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{
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// swap slices 2 & 3
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std::copy_n(image.get(), 1_KB * 2, myImage.begin());
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std::copy_n(image.get() + 1_KB * 3, 1_KB * 1, myImage.begin() + 1_KB * 2);
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std::copy_n(image.get() + 1_KB * 2, 1_KB * 1, myImage.begin() + 1_KB * 3);
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std::copy_n(image.get() + 1_KB * 4, 1_KB * 4, myImage.begin() + 1_KB * 4);
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// swap slices 2 & 3 of bad dump and correct size
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std::copy_n(image.get() + 1_KB * 3, 1_KB * 1, myImage.get() + 1_KB * 2);
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std::copy_n(image.get() + 1_KB * 2, 1_KB * 1, myImage.get() + 1_KB * 3);
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mySize = 8_KB;
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}
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else
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std::copy_n(image.get(), mySize, myImage.begin());
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createRomAccessArrays(8_KB);
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myDirectPeek = false;
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myBankShift = BANK_SHIFT;
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myRamSize = RAM_SIZE;
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myRamWpHigh = RAM_HIGH_WP;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void CartridgeWD::reset()
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{
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initializeRAM(myRAM.data(), myRAM.size());
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initializeStartBank(0);
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CartridgeEnhanced::reset();
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myCyclesAtBankswitchInit = 0;
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myPendingBank = 0xF0; // one more than the allowable bank #
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// Setup segments to some default slices
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bank(startBank());
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void CartridgeWD::install(System& system)
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{
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mySystem = &system;
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CartridgeEnhanced::install(system);
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// Set the page accessing method for the RAM reading pages
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System::PageAccess read(this, System::PageAccessType::READ);
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for(uInt16 addr = 0x1000; addr < 0x1040; addr += System::PAGE_SIZE)
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{
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read.directPeekBase = &myRAM[addr & 0x003F];
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read.romAccessBase = &myRomAccessBase[addr & 0x003F];
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read.romPeekCounter = &myRomAccessCounter[addr & 0x003F];
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read.romPokeCounter = &myRomAccessCounter[(addr & 0x003F) + 8_KB];
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mySystem->setPageAccess(addr, read);
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}
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System::PageAccess access(this, System::PageAccessType::READ);
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// Set the page accessing method for the RAM writing pages
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// Map access to this class, since we need to inspect all accesses to
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// check if RWP happens
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System::PageAccess write(this, System::PageAccessType::WRITE);
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for(uInt16 addr = 0x1040; addr < 0x1080; addr += System::PAGE_SIZE)
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{
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write.romAccessBase = &myRomAccessBase[addr & 0x003F];
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write.romPeekCounter = &myRomAccessCounter[addr & 0x003F];
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write.romPokeCounter = &myRomAccessCounter[(addr & 0x003F) + 8_KB];
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mySystem->setPageAccess(addr, write);
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}
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// The hotspots are in TIA address space, so we claim it here
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for(uInt16 addr = 0x00; addr < 0x40; addr += System::PAGE_SIZE)
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mySystem->setPageAccess(addr, access);
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// Mirror all access in TIA; by doing so we're taking responsibility
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// for that address space in peek and poke below.
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mySystem->tia().installDelegate(system, *this);
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// Setup segments to some default slices
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bank(startBank());
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//mySystem->tia().installDelegate(system, *this);
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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@ -113,134 +89,31 @@ uInt8 CartridgeWD::peek(uInt16 address)
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return mySystem->tia().peek(address);
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}
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else
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{
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uInt16 peekAddress = address;
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address &= 0x0FFF;
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if(address < 0x0040) // RAM read port
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return myRAM[address];
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else if(address < 0x0080) // RAM write port
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// Reading from the write port @ $1040 - $107F triggers an unwanted write
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return peekRAM(myRAM[address & 0x003F], peekAddress);
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else if(address < 0x0400)
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return myImage[myOffset[0] + (address & 0x03FF)];
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else if(address < 0x0800)
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return myImage[myOffset[1] + (address & 0x03FF)];
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else if(address < 0x0C00)
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return myImage[myOffset[2] + (address & 0x03FF)];
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else
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return mySegment3[address & 0x03FF];
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}
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return CartridgeEnhanced::peek(address);
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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bool CartridgeWD::poke(uInt16 address, uInt8 value)
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{
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if(!(address & 0x1000)) // TIA addresses
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if(address < 0x40)
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return mySystem->tia().poke(address, value);
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else
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{
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if(address & 0x040)
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{
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pokeRAM(myRAM[address & 0x003F], address, value);
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return true;
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}
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else
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{
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// Writing to the read port should be ignored, but trigger a break if option enabled
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uInt8 dummy;
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pokeRAM(dummy, address, value);
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myRamWriteAccess = address;
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return false;
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}
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}
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return CartridgeEnhanced::poke(address, value);
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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bool CartridgeWD::bank(uInt16 bank)
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bool CartridgeWD::bank(uInt16 bank, uInt16)
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{
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if(bankLocked() || bank > 15) return false;
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if(bankLocked()) return false;
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myCurrentBank = bank;
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myCurrentBank = bank % romBankCount();
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segmentZero(ourBankOrg[bank & 0x7].zero);
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segmentOne(ourBankOrg[bank & 0x7].one);
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segmentTwo(ourBankOrg[bank & 0x7].two);
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segmentThree(ourBankOrg[bank & 0x7].three);
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CartridgeEnhanced::bank(ourBankOrg[myCurrentBank].zero, 0);
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CartridgeEnhanced::bank(ourBankOrg[myCurrentBank].one, 1);
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CartridgeEnhanced::bank(ourBankOrg[myCurrentBank].two, 2);
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CartridgeEnhanced::bank(ourBankOrg[myCurrentBank].three, 3);
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return myBankChanged = true;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void CartridgeWD::segmentZero(uInt8 slice)
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{
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uInt16 offset = slice << 10;
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System::PageAccess access(this, System::PageAccessType::READ);
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// Skip first 128 bytes; it is always RAM
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for(uInt16 addr = 0x1080; addr < 0x1400; addr += System::PAGE_SIZE)
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{
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access.romAccessBase = &myRomAccessBase[offset + (addr & 0x03FF)];
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access.romPeekCounter = &myRomAccessCounter[offset + (addr & 0x03FF)];
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access.romPokeCounter = &myRomAccessCounter[offset + (addr & 0x03FF) + 8_KB];
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mySystem->setPageAccess(addr, access);
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}
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myOffset[0] = offset;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void CartridgeWD::segmentOne(uInt8 slice)
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{
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uInt16 offset = slice << 10;
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System::PageAccess access(this, System::PageAccessType::READ);
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for(uInt16 addr = 0x1400; addr < 0x1800; addr += System::PAGE_SIZE)
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{
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access.romAccessBase = &myRomAccessBase[offset + (addr & 0x03FF)];
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access.romPeekCounter = &myRomAccessCounter[offset + (addr & 0x03FF)];
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access.romPokeCounter = &myRomAccessCounter[offset + (addr & 0x03FF) + 8_KB];
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mySystem->setPageAccess(addr, access);
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}
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myOffset[1] = offset;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void CartridgeWD::segmentTwo(uInt8 slice)
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{
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uInt16 offset = slice << 10;
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System::PageAccess access(this, System::PageAccessType::READ);
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for(uInt16 addr = 0x1800; addr < 0x1C00; addr += System::PAGE_SIZE)
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{
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access.romAccessBase = &myRomAccessBase[offset + (addr & 0x03FF)];
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access.romPeekCounter = &myRomAccessCounter[offset + (addr & 0x03FF)];
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access.romPokeCounter = &myRomAccessCounter[offset + (addr & 0x03FF) + 8_KB];
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mySystem->setPageAccess(addr, access);
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}
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myOffset[2] = offset;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void CartridgeWD::segmentThree(uInt8 slice)
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{
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uInt16 offset = slice << 10;
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// Make a copy of the address space pointed to by the slice
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// Then overwrite one byte with 0
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std::copy_n(myImage.begin()+offset, mySegment3.size(), mySegment3.begin());
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mySegment3[0x3FC] = 0;
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System::PageAccess access(this, System::PageAccessType::READ);
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for(uInt16 addr = 0x1C00; addr < 0x2000; addr += System::PAGE_SIZE)
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{
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access.romAccessBase = &myRomAccessBase[offset + (addr & 0x03FF)];
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access.romPeekCounter = &myRomAccessCounter[offset + (addr & 0x03FF)];
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access.romPokeCounter = &myRomAccessCounter[offset + (addr & 0x03FF) + 8_KB];
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mySystem->setPageAccess(addr, access);
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}
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myOffset[3] = offset;
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return true;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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@ -249,41 +122,13 @@ uInt16 CartridgeWD::getBank(uInt16) const
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return myCurrentBank;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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uInt16 CartridgeWD::romBankCount() const
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{
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return 16;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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bool CartridgeWD::patch(uInt16 address, uInt8 value)
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{
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address &= 0x0FFF;
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uInt16 idx = address >> 10;
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myImage[myOffset[idx] + (address & 0x03FF)] = value;
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// The upper segment is mirrored, so we need to patch its buffer too
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if(idx == 3)
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mySegment3[(address & 0x03FF)] = value;
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return true;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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const uInt8* CartridgeWD::getImage(size_t& size) const
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{
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size = mySize;
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return myImage.data();
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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bool CartridgeWD::save(Serializer& out) const
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{
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CartridgeEnhanced::save(out);
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try
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{
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out.putShort(myCurrentBank);
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out.putByteArray(myRAM.data(), myRAM.size());
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out.putLong(myCyclesAtBankswitchInit);
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out.putShort(myPendingBank);
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}
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@ -299,10 +144,10 @@ bool CartridgeWD::save(Serializer& out) const
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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bool CartridgeWD::load(Serializer& in)
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{
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CartridgeEnhanced::load(in);
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try
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{
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myCurrentBank = in.getShort();
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in.getByteArray(myRAM.data(), myRAM.size());
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myCyclesAtBankswitchInit = in.getLong();
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myPendingBank = in.getShort();
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@ -319,9 +164,9 @@ bool CartridgeWD::load(Serializer& in)
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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const std::array<CartridgeWD::BankOrg, 8> CartridgeWD::ourBankOrg = {{
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// 0 1 2 3 4 5 6 7
|
||||
{ 0, 0, 1, 3 }, // Bank 0, 8 2 1 - 1 - - - -
|
||||
{ 0, 1, 2, 3 }, // Bank 1, 9 1 1 1 1 - - - -
|
||||
// 0 1 2 3 4 5 6 7
|
||||
{ 0, 0, 1, 3 }, // Bank 0, 8 2 1 - 1 - - - -
|
||||
{ 0, 1, 2, 3 }, // Bank 1, 9 1 1 1 1 - - - -
|
||||
{ 4, 5, 6, 7 }, // Bank 2, 10 - - - - 1 1 1 1
|
||||
{ 7, 4, 2, 3 }, // Bank 3, 11 - - 1 1 1 - - 1
|
||||
{ 0, 0, 6, 7 }, // Bank 4, 12 2 - - - - - 1 1
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
class System;
|
||||
|
||||
#include "bspf.hxx"
|
||||
#include "Cart.hxx"
|
||||
#include "CartEnhanced.hxx"
|
||||
#ifdef DEBUGGER_SUPPORT
|
||||
#include "CartWDWidget.hxx"
|
||||
#endif
|
||||
|
|
@ -45,15 +45,15 @@ class System;
|
|||
$0037, $003F: 6,0,5,1
|
||||
|
||||
|
||||
In the uppermost (third) segment, the byte at $3FC is overwritten by 0.
|
||||
(Removed: In the uppermost (third) segment, the byte at $3FC is overwritten by 0.)
|
||||
|
||||
The 64 bytes of RAM are accessible at $1000 - $103F (read port) and
|
||||
$1040 - $107F (write port). Because the RAM takes 128 bytes of address
|
||||
space, the range $1000 - $107F of segment 0 ROM will never be available.
|
||||
|
||||
@author Stephen Anthony
|
||||
@author Stephen Anthony, Thomas Jentzsch
|
||||
*/
|
||||
class CartridgeWD : public Cartridge
|
||||
class CartridgeWD : public CartridgeEnhanced
|
||||
{
|
||||
friend class CartridgeWDWidget;
|
||||
|
||||
|
|
@ -89,7 +89,7 @@ class CartridgeWD : public Cartridge
|
|||
|
||||
@param bank The bank that should be installed in the system
|
||||
*/
|
||||
bool bank(uInt16 bank) override;
|
||||
bool bank(uInt16 bank, uInt16 = 0) override;
|
||||
|
||||
/**
|
||||
Get the current bank.
|
||||
|
|
@ -98,28 +98,6 @@ class CartridgeWD : public Cartridge
|
|||
*/
|
||||
uInt16 getBank(uInt16 address = 0) const override;
|
||||
|
||||
/**
|
||||
Query the number of banks supported by the cartridge.
|
||||
*/
|
||||
uInt16 romBankCount() const override;
|
||||
|
||||
/**
|
||||
Patch the cartridge ROM.
|
||||
|
||||
@param address The ROM address to patch
|
||||
@param value The value to place into the address
|
||||
@return Success or failure of the patch operation
|
||||
*/
|
||||
bool patch(uInt16 address, uInt8 value) override;
|
||||
|
||||
/**
|
||||
Access the internal ROM image for this cartridge.
|
||||
|
||||
@param size Set to the size of the internal ROM image data
|
||||
@return A pointer to the internal ROM image data
|
||||
*/
|
||||
const uInt8* getImage(size_t& size) const override;
|
||||
|
||||
/**
|
||||
Save the current state of this cart to the given Serializer.
|
||||
|
||||
|
|
@ -173,51 +151,9 @@ class CartridgeWD : public Cartridge
|
|||
bool poke(uInt16 address, uInt8 value) override;
|
||||
|
||||
private:
|
||||
/**
|
||||
Install the specified slice for segment zero.
|
||||
|
||||
@param slice The slice to map into the segment
|
||||
*/
|
||||
void segmentZero(uInt8 slice);
|
||||
|
||||
/**
|
||||
Install the specified slice for segment one.
|
||||
|
||||
@param slice The slice to map into the segment
|
||||
*/
|
||||
void segmentOne(uInt8 slice);
|
||||
|
||||
/**
|
||||
Install the specified slice for segment two.
|
||||
|
||||
@param slice The slice to map into the segment
|
||||
*/
|
||||
void segmentTwo(uInt8 slice);
|
||||
|
||||
/**
|
||||
Install the specified slice for segment three.
|
||||
Note that this method also takes care of setting one byte to 0.
|
||||
|
||||
@param slice The slice to map into the segment
|
||||
*/
|
||||
void segmentThree(uInt8 slice);
|
||||
bool checkSwitchBank(uInt16, uInt8 = 0) override { return false; };
|
||||
|
||||
private:
|
||||
// The 8K ROM image of the cartridge
|
||||
std::array<uInt8, 8_KB> myImage;
|
||||
|
||||
// Indicates the actual size of the ROM image (either 8K or 8K + 3)
|
||||
size_t mySize{0};
|
||||
|
||||
// The 64 bytes RAM of the cartridge
|
||||
std::array<uInt8, 64> myRAM;
|
||||
|
||||
// The 1K ROM mirror of segment 3 (sometimes contains extra 3 bytes)
|
||||
std::array<uInt8, 1_KB> mySegment3;
|
||||
|
||||
// Indicates the offset for each of the four segments
|
||||
std::array<uInt16, 4> myOffset;
|
||||
|
||||
// Indicates the cycle at which a bankswitch was initiated
|
||||
uInt64 myCyclesAtBankswitchInit{0};
|
||||
|
||||
|
|
@ -233,6 +169,16 @@ class CartridgeWD : public Cartridge
|
|||
};
|
||||
static const std::array<BankOrg, 8> ourBankOrg;
|
||||
|
||||
private:
|
||||
// log(ROM bank segment size) / log(2)
|
||||
static constexpr uInt16 BANK_SHIFT = 10; // = 1K = 0x0400
|
||||
|
||||
// RAM size
|
||||
static constexpr uInt16 RAM_SIZE = 0x40;
|
||||
|
||||
// Write port for extra RAM is at low address by default
|
||||
static constexpr bool RAM_HIGH_WP = true;
|
||||
|
||||
private:
|
||||
// Following constructors and assignment operators not supported
|
||||
CartridgeWD() = delete;
|
||||
|
|
|
|||
Loading…
Reference in New Issue