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fixed a bug in branch cycle counting (now the test value is less than 0.1% off)

This commit is contained in:
Thomas Jentzsch 2021-06-27 13:04:35 +02:00
parent 6175176a6a
commit 06c6c1ccaa
4 changed files with 8 additions and 7 deletions
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2
src/debugger/gui/CartARMWidget.cxx
View File

@ -49,7 +49,7 @@ void CartridgeARMWidget::addCycleWidgets(int xpos, int ypos)
myCycleFactor = new SliderWidget(_boss, _font, myIncCycles->getRight() + _fontWidth * 2, ypos - 1,
_fontWidth * 10, _lineHeight, "Cycle factor", _fontWidth * 14,
kFactorChanged, _fontWidth * 4, "%");
myCycleFactor->setMinValue(80); myCycleFactor->setMaxValue(100);
myCycleFactor->setMinValue(90); myCycleFactor->setMaxValue(110);
myCycleFactor->setTickmarkIntervals(4);
myCycleFactor->setToolTip("Correct approximated ARM cycles by factor.");
myCycleFactor->setTarget(this);

2
src/emucore/Settings.cxx
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@ -248,7 +248,7 @@ Settings::Settings()
setPermanent("dev.thumb.trapfatal", "true");
#ifdef DEBUGGER_SUPPORT
setPermanent("dev.thumb.inccycles", "true");
setPermanent("dev.thumb.cyclefactor", "0.95");
setPermanent("dev.thumb.cyclefactor", "1.05");
setPermanent("dev.thumb.chiptype", "0"); // = LPC2103
setPermanent("dev.thumb.mammode", "2");
#endif

9
src/emucore/Thumbulator.cxx
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@ -629,8 +629,8 @@ void Thumbulator::write_register(uInt32 reg, uInt32 data, bool isFlowBreak)
if(isFlowBreak)
{
// dummy fetch + fill the pipeline
INC_N_CYCLES(reg_norm[15] + 4, AccessType::data);
INC_S_CYCLES(data, AccessType::branch);
INC_N_CYCLES(reg_norm[15] - 2, AccessType::prefetch);
INC_S_CYCLES(data - 2, AccessType::branch);
}
}
//#endif
@ -1176,13 +1176,14 @@ int Thumbulator::execute()
//B(1) conditional branch
case Op::b1: {
rb = (inst >> 0) & 0xFF;
rb = inst & 0xFF;
if(rb & 0x80)
rb |= (~0U) << 8;
op=(inst >> 8) & 0xF;
rb <<= 1;
rb += pc;
rb += 2;
op = (inst >> 8) & 0xF;
switch(op)
{
case 0x0: //b eq z set

2
src/emucore/Thumbulator.hxx
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@ -300,7 +300,7 @@ class Thumbulator
bool _lockMamcr{false};
#ifdef THUMB_CYCLE_COUNT
double _armCyclesFactor{0.90};
double _armCyclesFactor{1.05};
CycleType _fetchCycleType{CycleType::S};
#ifdef EMULATE_PIPELINE
uInt32 _fetchPipeline{0}; // reserve fetch cycles resulting from pipelining (execution stage)