mirror of https://github.com/stella-emu/stella.git
Start to adapt thumbulator.
This commit is contained in:
Christian Speckner
parent
1e4ab23283
commit
061b0124a4
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@ -14,6 +14,7 @@
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"C_Cpp.intelliSenseEngine": "Default",
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"files.insertFinalNewline": true,
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"files.associations": {
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"*.h": "cpp",
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"__functional_base": "cpp",
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"array": "cpp",
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"istream": "cpp",
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@ -103,6 +104,18 @@
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"version": "cpp",
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"shared_mutex": "cpp",
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"compare": "cpp",
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"concepts": "cpp"
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"concepts": "cpp",
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"__verbose_abort": "cpp",
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"any": "cpp",
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"charconv": "cpp",
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"csignal": "cpp",
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"execution": "cpp",
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"numbers": "cpp",
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"span": "cpp",
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"unordered_set": "cpp",
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"variant": "cpp",
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"hash_map": "cpp",
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"format": "cpp",
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"*.inc": "cpp"
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}
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}
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@ -0,0 +1,623 @@
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//============================================================================
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//
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// SSSS tt lll lll
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// SS SS tt ll ll
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// SS tttttt eeee ll ll aaaa
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// SSSS tt ee ee ll ll aa
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// SS tt eeeeee ll ll aaaaa -- "An Atari 2600 VCS Emulator"
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// SS SS tt ee ll ll aa aa
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// SSSS ttt eeeee llll llll aaaaa
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//
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// Copyright (c) 1995-2024 by Bradford W. Mott, Stephen Anthony
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// and the Stella Team
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//
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// See the file "License.txt" for information on usage and redistribution of
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// this file, and for a DISCLAIMER OF ALL WARRANTIES.
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//============================================================================
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//============================================================================
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// This code is based on the "Thumbulator" by David Welch (dwelch@dwelch.com)
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// Code is public domain and used with the author's consent
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//============================================================================
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#include "CortexM0.hxx"
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#ifdef __BIG_ENDIAN__
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#define READ32(data, addr) ( \
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(((uInt8*)(data))[(addr)]) | \
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(((uInt8*)(data))[(addr) + 1] << 8) | \
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(((uInt8*)(data))[(addr) + 2] << 16) | \
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(((uInt8*)(data))[(addr) + 3] << 24) \
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)
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#define READ16(data, addr) ( \
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(((uInt8*)(data))[(addr)]) | \
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(((uInt8*)(data))[(addr) + 1] << 8) \
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)
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#define WRITE32(data, addr, value) \
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((uInt8*)(data))[(addr)] = (value); \
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((uInt8*)(data))[(addr) + 1] = (value) >> 8; \
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((uInt8*)(data))[(addr) + 2] = (value) >> 16; \
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((uInt8*)(data))[(addr) + 3] = (value) >> 24;
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#define WRITE16(data, addr, value) \
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((uInt8*)(data))[(addr)] = value; \
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((uInt8*)(data))[(addr) + 1] = (value) >> 8;
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#else
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#define READ32(data, addr) (((uInt32*)(data))[(addr) >> 2])
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#define READ16(data, addr) (((uInt16*)(data))[(addr) >> 1])
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#define WRITE32(data, addr, value) ((uInt32*)(data))[(addr) >> 2] = value;
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#define WRITE16(data, addr, value) ((uInt16*)(data))[(addr) >> 1] = value;
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#endif
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#define read_register(reg) reg_norm[reg]
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#define write_register(reg, data) reg_norm[reg]=(data)
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namespace {
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constexpr uInt32 PAGEMAP_SIZE = 0x100000000 / 4096;
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enum class Op : uInt8 {
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adc,
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add1, add2, add3, add4, add5, add6, add7,
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and_,
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asr1, asr2,
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// b1 variants:
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beq, bne, bcs, bcc, bmi, bpl, bvs, bvc, bhi, bls, bge, blt, bgt, ble,
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b2,
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bic,
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bkpt,
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// blx1 variants:
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bl, blx_thumb, blx_arm,
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blx2,
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bx,
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cmn,
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cmp1, cmp2, cmp3,
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cps,
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cpy,
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eor,
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ldmia,
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ldr1, ldr2, ldr3, ldr4,
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ldrb1, ldrb2,
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ldrh1, ldrh2,
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ldrsb,
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ldrsh,
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lsl1, lsl2,
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lsr1, lsr2,
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mov1, mov2, mov3,
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mul,
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mvn,
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neg,
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orr,
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pop,
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push,
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rev,
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rev16,
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revsh,
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ror,
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sbc,
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setend,
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stmia,
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str1, str2, str3,
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strb1, strb2,
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strh1, strh2,
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sub1, sub2, sub3, sub4,
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swi,
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sxtb,
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sxth,
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tst,
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uxtb,
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uxth,
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numOps,
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invalid,
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};
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inline Op decodeInstructionWord(uInt16 inst)
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{
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//ADC add with carry
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if((inst & 0xFFC0) == 0x4140) return Op::adc;
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//ADD(1) small immediate two registers
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if((inst & 0xFE00) == 0x1C00 && (inst >> 6) & 0x7) return Op::add1;
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//ADD(2) big immediate one register
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if((inst & 0xF800) == 0x3000) return Op::add2;
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//ADD(3) three registers
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if((inst & 0xFE00) == 0x1800) return Op::add3;
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//ADD(4) two registers one or both high no flags
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if((inst & 0xFF00) == 0x4400) return Op::add4;
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//ADD(5) rd = pc plus immediate
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if((inst & 0xF800) == 0xA000) return Op::add5;
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//ADD(6) rd = sp plus immediate
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if((inst & 0xF800) == 0xA800) return Op::add6;
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//ADD(7) sp plus immediate
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if((inst & 0xFF80) == 0xB000) return Op::add7;
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//AND
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if((inst & 0xFFC0) == 0x4000) return Op::and_;
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//ASR(1) two register immediate
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if((inst & 0xF800) == 0x1000) return Op::asr1;
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//ASR(2) two register
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if((inst & 0xFFC0) == 0x4100) return Op::asr2;
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//B(1) conditional branch, decoded into its variants
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if((inst & 0xF000) == 0xD000)
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{
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switch((inst >> 8) & 0xF)
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{
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case 0x0: //b eq z set
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return Op::beq;
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case 0x1: //b ne z clear
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return Op::bne;
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case 0x2: //b cs c set
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return Op::bcs;
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case 0x3: //b cc c clear
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return Op::bcc;
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case 0x4: //b mi n set
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return Op::bmi;
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case 0x5: //b pl n clear
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return Op::bpl;
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case 0x6: //b vs v set
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return Op::bvs;
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case 0x7: //b vc v clear
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return Op::bvc;
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case 0x8: //b hi c set z clear
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return Op::bhi;
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case 0x9: //b ls c clear or z set
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return Op::bls;
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case 0xA: //b ge N == V
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return Op::bge;
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case 0xB: //b lt N != V
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return Op::blt;
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case 0xC: //b gt Z==0 and N == V
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return Op::bgt;
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case 0xD: //b le Z==1 or N != V
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return Op::ble;
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default:
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return Op::invalid;
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}
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}
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//B(2) unconditional branch
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if((inst & 0xF800) == 0xE000) return Op::b2;
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//BIC
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if((inst & 0xFFC0) == 0x4380) return Op::bic;
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//BKPT
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if((inst & 0xFF00) == 0xBE00) return Op::bkpt;
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//BL/BLX(1) decoded into its variants
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if((inst & 0xE000) == 0xE000)
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{
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if((inst & 0x1800) == 0x1000) return Op::bl;
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else if((inst & 0x1800) == 0x1800) return Op::blx_thumb;
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else if((inst & 0x1800) == 0x0800) return Op::blx_arm;
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return Op::invalid;
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}
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//BLX(2)
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if((inst & 0xFF87) == 0x4780) return Op::blx2;
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//BX
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if((inst & 0xFF87) == 0x4700) return Op::bx;
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//CMN
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if((inst & 0xFFC0) == 0x42C0) return Op::cmn;
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//CMP(1) compare immediate
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if((inst & 0xF800) == 0x2800) return Op::cmp1;
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//CMP(2) compare register
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if((inst & 0xFFC0) == 0x4280) return Op::cmp2;
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//CMP(3) compare high register
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if((inst & 0xFF00) == 0x4500) return Op::cmp3;
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//CPS
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if((inst & 0xFFE8) == 0xB660) return Op::cps;
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//CPY copy high register
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if((inst & 0xFFC0) == 0x4600) return Op::cpy;
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//EOR
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if((inst & 0xFFC0) == 0x4040) return Op::eor;
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//LDMIA
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if((inst & 0xF800) == 0xC800) return Op::ldmia;
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//LDR(1) two register immediate
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if((inst & 0xF800) == 0x6800) return Op::ldr1;
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//LDR(2) three register
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if((inst & 0xFE00) == 0x5800) return Op::ldr2;
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//LDR(3)
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if((inst & 0xF800) == 0x4800) return Op::ldr3;
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//LDR(4)
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if((inst & 0xF800) == 0x9800) return Op::ldr4;
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//LDRB(1)
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if((inst & 0xF800) == 0x7800) return Op::ldrb1;
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//LDRB(2)
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if((inst & 0xFE00) == 0x5C00) return Op::ldrb2;
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//LDRH(1)
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if((inst & 0xF800) == 0x8800) return Op::ldrh1;
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//LDRH(2)
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if((inst & 0xFE00) == 0x5A00) return Op::ldrh2;
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//LDRSB
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if((inst & 0xFE00) == 0x5600) return Op::ldrsb;
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//LDRSH
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if((inst & 0xFE00) == 0x5E00) return Op::ldrsh;
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//LSL(1)
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if((inst & 0xF800) == 0x0000) return Op::lsl1;
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//LSL(2) two register
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if((inst & 0xFFC0) == 0x4080) return Op::lsl2;
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//LSR(1) two register immediate
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if((inst & 0xF800) == 0x0800) return Op::lsr1;
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//LSR(2) two register
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if((inst & 0xFFC0) == 0x40C0) return Op::lsr2;
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//MOV(1) immediate
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if((inst & 0xF800) == 0x2000) return Op::mov1;
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//MOV(2) two low registers
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if((inst & 0xFFC0) == 0x1C00) return Op::mov2;
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//MOV(3)
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if((inst & 0xFF00) == 0x4600) return Op::mov3;
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//MUL
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if((inst & 0xFFC0) == 0x4340) return Op::mul;
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//MVN
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if((inst & 0xFFC0) == 0x43C0) return Op::mvn;
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//NEG
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if((inst & 0xFFC0) == 0x4240) return Op::neg;
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//ORR
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if((inst & 0xFFC0) == 0x4300) return Op::orr;
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//POP
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if((inst & 0xFE00) == 0xBC00) return Op::pop;
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//PUSH
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if((inst & 0xFE00) == 0xB400) return Op::push;
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//REV
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if((inst & 0xFFC0) == 0xBA00) return Op::rev;
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//REV16
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if((inst & 0xFFC0) == 0xBA40) return Op::rev16;
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//REVSH
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if((inst & 0xFFC0) == 0xBAC0) return Op::revsh;
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//ROR
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if((inst & 0xFFC0) == 0x41C0) return Op::ror;
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//SBC
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if((inst & 0xFFC0) == 0x4180) return Op::sbc;
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//SETEND
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if((inst & 0xFFF7) == 0xB650) return Op::setend;
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//STMIA
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if((inst & 0xF800) == 0xC000) return Op::stmia;
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//STR(1)
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if((inst & 0xF800) == 0x6000) return Op::str1;
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//STR(2)
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if((inst & 0xFE00) == 0x5000) return Op::str2;
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//STR(3)
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if((inst & 0xF800) == 0x9000) return Op::str3;
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//STRB(1)
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if((inst & 0xF800) == 0x7000) return Op::strb1;
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//STRB(2)
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if((inst & 0xFE00) == 0x5400) return Op::strb2;
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//STRH(1)
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if((inst & 0xF800) == 0x8000) return Op::strh1;
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//STRH(2)
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if((inst & 0xFE00) == 0x5200) return Op::strh2;
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//SUB(1)
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if((inst & 0xFE00) == 0x1E00) return Op::sub1;
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//SUB(2)
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if((inst & 0xF800) == 0x3800) return Op::sub2;
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//SUB(3)
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if((inst & 0xFE00) == 0x1A00) return Op::sub3;
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//SUB(4)
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if((inst & 0xFF80) == 0xB080) return Op::sub4;
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//SWI SoftWare Interupt
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if((inst & 0xFF00) == 0xDF00) return Op::swi;
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//SXTB
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if((inst & 0xFFC0) == 0xB240) return Op::sxtb;
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//SXTH
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if((inst & 0xFFC0) == 0xB200) return Op::sxth;
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//TST
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if((inst & 0xFFC0) == 0x4200) return Op::tst;
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//UXTB
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if((inst & 0xFFC0) == 0xB2C0) return Op::uxtb;
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//UXTH Zero extend Halfword
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if((inst & 0xFFC0) == 0xB280) return Op::uxth;
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return Op::invalid;
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}
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}
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CortexM0::CortexM0()
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{
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myPageMap = make_unique<uInt8[]>(PAGEMAP_SIZE);
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std::memset(myPageMap.get(), 0xff, PAGEMAP_SIZE);
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reset();
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}
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CortexM0& CortexM0::mapRegionData(uInt32 pageBase,
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uInt32 pageCount, bool readOnly, uInt8* backingStore)
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{
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MemoryRegion& region =
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setupMapping(pageBase, pageCount, readOnly, MemoryRegionType::directData);
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region.access.accessData.backingStore = backingStore;
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return *this;
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}
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CortexM0& CortexM0::mapRegionCode(uInt32 pageBase,
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uInt32 pageCount, bool readOnly, uInt8* backingStore)
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{
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MemoryRegion& region =
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setupMapping(pageBase, pageCount, readOnly, MemoryRegionType::directCode);
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region.access.accessCode.backingStore = backingStore;
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region.access.accessCode.ops = static_cast<uInt8*>(std::malloc((pageCount * PAGE_SIZE) >> 1));
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for (size_t i = 0; i < pageCount * PAGE_SIZE; i += 2)
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region.access.accessCode.ops[i >> 1] =
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decodeInstructionWord(READ16(backingStore, i));
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return *this;
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}
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CortexM0& CortexM0::mapRegionDelegate(uInt32 pageBase, uInt32 pageCount, bool readOnly,
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CortexM0::BusTransactionDelegate* delegate)
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{
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MemoryRegion& region =
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setupMapping(pageBase, pageCount, readOnly, MemoryRegionType::delegate);
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region.access.delegate = delegate;
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return *this;
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}
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CortexM0& CortexM0::mapDefault(CortexM0::BusTransactionDelegate* delegate)
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{
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myDefaultDelegate = delegate;
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return *this;
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}
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CortexM0& CortexM0::reset()
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{
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reg_norm.fill(0);
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znFlags = cFlag = vFlag = 0;
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return *this;
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}
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CortexM0& CortexM0::setRegister(uInt8 regno, uInt32 value)
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{
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write_register(regno, value);
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||||
return *this;
|
||||
}
|
||||
|
||||
uInt8 CortexM0::decodeInstructionWord(uInt16 instructionWord)
|
||||
{
|
||||
return static_cast<uInt8>(::decodeInstructionWord(instructionWord));
|
||||
}
|
||||
|
||||
CortexM0::MemoryRegion& CortexM0::setupMapping(uInt32 pageBase, uInt32 pageCount,
|
||||
bool readOnly, CortexM0::MemoryRegionType type)
|
||||
{
|
||||
if (myNextRegionIndex == 0xff) throw runtime_error("no free memory region");
|
||||
const uInt8 regionIndex = myNextRegionIndex++;
|
||||
|
||||
MemoryRegion& region = myRegions[regionIndex];
|
||||
|
||||
region.type = type;
|
||||
region.base = pageBase * PAGE_SIZE;
|
||||
region.size = pageCount * PAGE_SIZE;
|
||||
region.readOnly = readOnly;
|
||||
|
||||
for (uInt32 page = pageBase; page < pageBase + pageCount; page++)
|
||||
myPageMap[page] = regionIndex;
|
||||
|
||||
return region;
|
||||
}
|
||||
|
||||
CortexM0::BusTransactionResult CortexM0::read32(uInt32 address, uInt32& value)
|
||||
{
|
||||
MemoryRegion& region = myRegions[myPageMap[address / PAGE_SIZE]];
|
||||
|
||||
switch (region.type) {
|
||||
case MemoryRegionType::delegate:
|
||||
return region.access.delegate->read32(address, value);
|
||||
|
||||
case MemoryRegionType::directCode:
|
||||
value = READ32(region.access.accessCode.backingStore, address - region.base);
|
||||
return BusTransactionResult::ok;
|
||||
|
||||
case MemoryRegionType::directData:
|
||||
value = READ32(region.access.accessData.backingStore, address - region.base);
|
||||
return BusTransactionResult::ok;
|
||||
|
||||
default:
|
||||
return myDefaultDelegate ?
|
||||
myDefaultDelegate->read32(address, value) : BusTransactionResult::fail;
|
||||
}
|
||||
}
|
||||
|
||||
CortexM0::BusTransactionResult CortexM0::read16(uInt32 address, uInt16& value)
|
||||
{
|
||||
MemoryRegion& region = myRegions[myPageMap[address / PAGE_SIZE]];
|
||||
|
||||
switch (region.type) {
|
||||
case MemoryRegionType::delegate:
|
||||
return region.access.delegate->read16(address, value);
|
||||
|
||||
case MemoryRegionType::directCode:
|
||||
value = READ16(region.access.accessCode.backingStore, address - region.base);
|
||||
return BusTransactionResult::ok;
|
||||
|
||||
case MemoryRegionType::directData:
|
||||
value = READ16(region.access.accessData.backingStore, address - region.base);
|
||||
return BusTransactionResult::ok;
|
||||
|
||||
default:
|
||||
return myDefaultDelegate ?
|
||||
myDefaultDelegate->read16(address, value) : BusTransactionResult::fail;
|
||||
}
|
||||
}
|
||||
|
||||
CortexM0::BusTransactionResult CortexM0::write32(uInt32 address, uInt32 value)
|
||||
{
|
||||
MemoryRegion& region = myRegions[myPageMap[address / PAGE_SIZE]];
|
||||
|
||||
switch (region.type) {
|
||||
case MemoryRegionType::delegate:
|
||||
return region.access.delegate->write32(address, value);
|
||||
|
||||
case MemoryRegionType::directCode:
|
||||
WRITE32(region.access.accessCode.backingStore, address - region.base, value);
|
||||
return BusTransactionResult::ok;
|
||||
|
||||
case MemoryRegionType::directData:
|
||||
WRITE32(region.access.accessData.backingStore, address - region.base, value);
|
||||
return BusTransactionResult::ok;
|
||||
|
||||
default:
|
||||
return myDefaultDelegate ?
|
||||
myDefaultDelegate->write32(address, value) : BusTransactionResult::fail;
|
||||
}
|
||||
}
|
||||
|
||||
CortexM0::BusTransactionResult CortexM0::write16(uInt32 address, uInt16 value)
|
||||
{
|
||||
MemoryRegion& region = myRegions[myPageMap[address / PAGE_SIZE]];
|
||||
|
||||
switch (region.type) {
|
||||
case MemoryRegionType::delegate:
|
||||
return region.access.delegate->write16(address, value);
|
||||
|
||||
case MemoryRegionType::directCode: {
|
||||
const uInt32 offset = address - region.base;
|
||||
|
||||
WRITE16(region.access.accessCode.backingStore, offset, value);
|
||||
region.access.accessCode.ops[offset >> 1] = decodeInstructionWord(value);
|
||||
|
||||
return BusTransactionResult::ok;
|
||||
}
|
||||
|
||||
case MemoryRegionType::directData:
|
||||
WRITE16(region.access.accessData.backingStore, address - region.base, value);
|
||||
return BusTransactionResult::ok;
|
||||
|
||||
default:
|
||||
return myDefaultDelegate ?
|
||||
myDefaultDelegate->write16(address, value) : BusTransactionResult::fail;
|
||||
}
|
||||
}
|
||||
|
||||
CortexM0::BusTransactionResult CortexM0::fetch16(uInt32 address, uInt16& value, uInt8& op)
|
||||
{
|
||||
MemoryRegion& region = myRegions[myPageMap[address / PAGE_SIZE]];
|
||||
|
||||
switch (region.type) {
|
||||
case MemoryRegionType::delegate:
|
||||
return region.access.delegate->fetch16(address, value, op);
|
||||
|
||||
case MemoryRegionType::directCode: {
|
||||
const uInt32 offset = address - region.base;
|
||||
|
||||
value = READ16(region.access.accessCode.backingStore, offset);
|
||||
op = region.access.accessCode.ops[offset >> 1];
|
||||
|
||||
return BusTransactionResult::ok;
|
||||
}
|
||||
|
||||
case MemoryRegionType::directData:
|
||||
value = READ16(region.access.accessCode.backingStore, address - region.base);
|
||||
op = decodeInstructionWord(value);
|
||||
|
||||
return BusTransactionResult::ok;
|
||||
|
||||
default:
|
||||
return myDefaultDelegate ?
|
||||
myDefaultDelegate->fetch16(address, value, op) : BusTransactionResult::fail;
|
||||
}
|
||||
}
|
||||
|
||||
void CortexM0::do_cvflag(uInt32 a, uInt32 b, uInt32 c)
|
||||
{
|
||||
uInt32 rc = (a & 0x7FFFFFFF) + (b & 0x7FFFFFFF) + c; //carry in
|
||||
rc >>= 31; //carry in in lsbit
|
||||
a >>= 31;
|
||||
b >>= 31;
|
||||
uInt32 rd = (rc & 1) + (a & 1) + (b & 1); //carry out
|
||||
rd >>= 1; //carry out in lsbit
|
||||
|
||||
vFlag = (rc ^ rd) & 1; //if carry in != carry out then signed overflow
|
||||
|
||||
rc += a + b; //carry out
|
||||
cFlag = rc & 2;
|
||||
}
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
//============================================================================
|
||||
//
|
||||
// SSSS tt lll lll
|
||||
// SS SS tt ll ll
|
||||
// SS tttttt eeee ll ll aaaa
|
||||
// SSSS tt ee ee ll ll aa
|
||||
// SS tt eeeeee ll ll aaaaa -- "An Atari 2600 VCS Emulator"
|
||||
// SS SS tt ee ll ll aa aa
|
||||
// SSSS ttt eeeee llll llll aaaaa
|
||||
//
|
||||
// Copyright (c) 1995-2024 by Bradford W. Mott, Stephen Anthony
|
||||
// and the Stella Team
|
||||
//
|
||||
// See the file "License.txt" for information on usage and redistribution of
|
||||
// this file, and for a DISCLAIMER OF ALL WARRANTIES.
|
||||
//============================================================================
|
||||
|
||||
//============================================================================
|
||||
// This code is based on the "Thumbulator" by David Welch (dwelch@dwelch.com)
|
||||
// Code is public domain and used with the author's consent
|
||||
//============================================================================
|
||||
|
||||
#ifndef CORTEX_M0
|
||||
#define CORTEX_M0
|
||||
|
||||
#include "bspf.hxx"
|
||||
|
||||
class CortexM0
|
||||
{
|
||||
public:
|
||||
enum class BusTransactionResult : uInt8 {
|
||||
ok,
|
||||
stopAndRollback,
|
||||
stop,
|
||||
fail
|
||||
};
|
||||
|
||||
class BusTransactionDelegate {
|
||||
public:
|
||||
virtual ~BusTransactionDelegate() = default;
|
||||
|
||||
virtual BusTransactionResult read32(uInt32 address, uInt32& value) = 0;
|
||||
virtual BusTransactionResult read16(uInt32 address, uInt16& value) = 0;
|
||||
|
||||
virtual BusTransactionResult write32(uInt32 address, uInt32 value) = 0;
|
||||
virtual BusTransactionResult write16(uInt32 address, uInt16 value) = 0;
|
||||
|
||||
virtual BusTransactionResult fetch16(uInt32 address, uInt16& value, uInt8& op) = 0;
|
||||
};
|
||||
|
||||
static constexpr uInt32 PAGE_SIZE = 4096;
|
||||
|
||||
public:
|
||||
CortexM0();
|
||||
|
||||
CortexM0& mapRegionData(uInt32 pageBase, uInt32 pageCount,
|
||||
bool readOnly, uInt8* backingStore);
|
||||
|
||||
CortexM0& mapRegionCode(uInt32 pageBase, uInt32 pageCount,
|
||||
bool readOnly, uInt8* backingStore);
|
||||
|
||||
CortexM0& mapRegionDelegate(uInt32 pageBase, uInt32 pageCount,
|
||||
bool readOnly, BusTransactionDelegate* delegate);
|
||||
|
||||
CortexM0& mapDefault(BusTransactionDelegate* delegate);
|
||||
|
||||
CortexM0& reset();
|
||||
CortexM0& setRegister(uInt8 regno, uInt32 value);
|
||||
|
||||
static uInt8 decodeInstructionWord(uInt16 instructionWord);
|
||||
|
||||
BusTransactionResult run(uInt32 maxCycles, uInt32& cycles);
|
||||
|
||||
private:
|
||||
|
||||
enum class MemoryRegionType : uInt8 {
|
||||
directData,
|
||||
directCode,
|
||||
delegate,
|
||||
unmapped
|
||||
};
|
||||
|
||||
struct MemoryRegionAccessData {
|
||||
uInt8* backingStore;
|
||||
};
|
||||
|
||||
struct MemoryRegionAccessCode {
|
||||
uInt8* backingStore;
|
||||
uInt8* ops;
|
||||
};
|
||||
|
||||
struct MemoryRegion {
|
||||
~MemoryRegion() {
|
||||
if (type == MemoryRegionType::directCode)
|
||||
std::free(access.accessCode.ops);
|
||||
}
|
||||
|
||||
MemoryRegionType type{MemoryRegionType::unmapped};
|
||||
|
||||
uInt32 base;
|
||||
uInt32 size;
|
||||
bool readOnly;
|
||||
|
||||
union {
|
||||
MemoryRegionAccessData accessData;
|
||||
MemoryRegionAccessCode accessCode;
|
||||
BusTransactionDelegate* delegate;
|
||||
} access;
|
||||
};
|
||||
|
||||
private:
|
||||
MemoryRegion& setupMapping(uInt32 pageBase, uInt32 pageCount,
|
||||
bool readOnly, MemoryRegionType type);
|
||||
|
||||
BusTransactionResult read32(uInt32 address, uInt32& value);
|
||||
BusTransactionResult read16(uInt32 address, uInt16& value);
|
||||
|
||||
BusTransactionResult write32(uInt32 address, uInt32 value);
|
||||
BusTransactionResult write16(uInt32 address, uInt16 value);
|
||||
|
||||
BusTransactionResult fetch16(uInt32 address, uInt16& value, uInt8& op);
|
||||
|
||||
void do_cvflag(uInt32 a, uInt32 b, uInt32 c);
|
||||
|
||||
int execute();
|
||||
|
||||
private:
|
||||
std::array<uInt32, 16> reg_norm; // normal execution mode, do not have a thread mode
|
||||
uInt32 znFlags{0};
|
||||
uInt32 cFlag{0};
|
||||
uInt32 vFlag{0};
|
||||
|
||||
std::array<MemoryRegion, 0x100> myRegions;
|
||||
unique_ptr<uInt8[]> myPageMap;
|
||||
uInt8 myNextRegionIndex{0};
|
||||
BusTransactionDelegate* myDefaultDelegate{nullptr};
|
||||
|
||||
static constexpr uInt32
|
||||
CPSR_N = 1u << 31,
|
||||
CPSR_Z = 1u << 30,
|
||||
CPSR_C = 1u << 29,
|
||||
CPSR_V = 1u << 28;
|
||||
|
||||
private:
|
||||
// Following constructors and assignment operators not supported
|
||||
CortexM0(const CortexM0&) = delete;
|
||||
CortexM0(CortexM0&&) = delete;
|
||||
CortexM0& operator=(const CortexM0&) = delete;
|
||||
CortexM0& operator=(CortexM0&&) = delete;
|
||||
};
|
||||
|
||||
#endif // CORTEX_M0
|
||||
|
|
@ -62,6 +62,7 @@ MODULE_OBJS := \
|
|||
src/emucore/Console.o \
|
||||
src/emucore/Control.o \
|
||||
src/emucore/ControllerDetector.o \
|
||||
src/emucore/CortexM0.o \
|
||||
src/emucore/DispatchResult.o \
|
||||
src/emucore/Driving.o \
|
||||
src/emucore/EventHandler.o \
|
||||
|
|
|
|||
|
|
@ -695,6 +695,7 @@
|
|||
<ClCompile Include="..\..\emucore\elf\ElfLinker.cxx" />
|
||||
<ClCompile Include="..\..\emucore\elf\ElfUtil.cxx" />
|
||||
<ClCompile Include="..\..\emucore\elf\ElfEnvironment.cxx" />
|
||||
<ClCompile Include="..\..\emucore\CortexM0.cxx" />
|
||||
<ClCompile Include="..\..\emucore\EmulationTiming.cxx" />
|
||||
<ClCompile Include="..\..\emucore\EmulationWorker.cxx" />
|
||||
<ClCompile Include="..\..\emucore\FBSurface.cxx" />
|
||||
|
|
@ -1670,6 +1671,7 @@
|
|||
<ClInclude Include="..\..\emucore\elf\ElfLinker.hxx" />
|
||||
<ClInclude Include="..\..\emucore\elf\ElfUtil.hxx" />
|
||||
<ClInclude Include="..\..\emucore\elf\ElfEnvironment.hxx" />
|
||||
<ClInclude Include="..\..\emucore\CortexM0.hxx" />
|
||||
<ClInclude Include="..\..\emucore\EmulationTiming.hxx" />
|
||||
<ClInclude Include="..\..\emucore\EmulationWorker.hxx" />
|
||||
<ClInclude Include="..\..\emucore\EventHandlerConstants.hxx" />
|
||||
|
|
|
|||
|
|
@ -1242,6 +1242,9 @@
|
|||
<ClCompile Include="..\..\emucore\CartJANE.cxx">
|
||||
<Filter>Source Files\emucore</Filter>
|
||||
</ClCompile>
|
||||
<ClCompile Include="..\..\emucore\CortexMß.cxx">
|
||||
<Filter>Source Files\emucore</Filter>
|
||||
</ClCompile>
|
||||
<ClCompile Include="..\..\debugger\gui\CartJANEWidget.cxx">
|
||||
<Filter>Source Files\debugger\gui</Filter>
|
||||
</ClCompile>
|
||||
|
|
@ -2528,6 +2531,9 @@
|
|||
<ClInclude Include="..\..\emucore\CartJANE.hxx">
|
||||
<Filter>Header Files\emucore</Filter>
|
||||
</ClInclude>
|
||||
<ClInclude Include="..\..\emucore\CortexM0.hxx">
|
||||
<Filter>Header Files\emucore</Filter>
|
||||
</ClInclude>
|
||||
<ClInclude Include="..\..\debugger\gui\CartJANEWidget.hxx">
|
||||
<Filter>Header Files\debugger\gui</Filter>
|
||||
</ClInclude>
|
||||
|
|
|
|||
Loading…
Reference in New Issue