From 03cd7ea2913be78ce6324f4c8e82e3e9ab5815c8 Mon Sep 17 00:00:00 2001
From: stephena <stephena@8b62c5a3-ac7e-4cc8-8f21-d9a121418aba>
Date: Thu, 21 Feb 2008 16:11:15 +0000
Subject: [PATCH] Fix comments in zero-page bankswitching code in 4A50 cart
 format.

git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1399 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
---
 stella/src/emucore/Cart4A50.cxx | 29 ++++++++++++++++++-----------
 1 file changed, 18 insertions(+), 11 deletions(-)

diff --git a/stella/src/emucore/Cart4A50.cxx b/stella/src/emucore/Cart4A50.cxx
index 6e405d4f0..c968f2e12 100644
--- a/stella/src/emucore/Cart4A50.cxx
+++ b/stella/src/emucore/Cart4A50.cxx
@@ -13,7 +13,7 @@
 // See the file "license" for information on usage and redistribution of
 // this file, and for a DISCLAIMER OF ALL WARRANTIES.
 //
-// $Id: Cart4A50.cxx,v 1.10 2008-02-19 12:33:03 stephena Exp $
+// $Id: Cart4A50.cxx,v 1.11 2008-02-21 16:11:15 stephena Exp $
 //============================================================================
 
 #include <cassert>
@@ -88,7 +88,7 @@ void Cartridge4A50::install(System& system)
 // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 uInt8 Cartridge4A50::peek(uInt16 address)
 {
-  uInt8 value = 0;//mySystem->getDataBusState();
+  uInt8 value = 0;
 
   if(!(address & 0x1000))                      // Hotspots below 0x1000
   {
@@ -182,8 +182,6 @@ void Cartridge4A50::poke(uInt16 address, uInt8 value)
 // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 void Cartridge4A50::checkBankSwitch(uInt16 address)
 {
-  uInt8 databus = mySystem->getDataBusState();
-
   // This scheme contains so many hotspots that it's easier to just check
   // all of them
   if(((myLastData & 0xe0) == 0x60) &&      // Switch lower/middle/upper bank
@@ -239,34 +237,43 @@ void Cartridge4A50::checkBankSwitch(uInt16 address)
     }
   }
 
-  if((address & 0xf75) == 0x74)         // 
+  uInt8 databus = mySystem->getDataBusState();
+
+  // Zero-page hotspots for upper page
+  //   0xf4, 0xf6, 0xfc, 0xfe for ROM
+  //   0xf5, 0xf7, 0xfd, 0xff for RAM
+  //   0x74 - 0x7f (0x80 bytes lower)
+  if((address & 0xf75) == 0x74)         // Enable 256B of ROM at 0x1e00 - 0x1eff
   {
     myIsRomHigh = true;
     mySliceHigh = databus << 8;
   }
-  else if((address & 0xf75) == 0x75)    // 
+  else if((address & 0xf75) == 0x75)    // Enable 256B of RAM at 0x1e00 - 0x1eff
   {
     myIsRomHigh = false;
     mySliceHigh = (databus & 0x7f) << 8;
   }
-  else if((address & 0xf7c) == 0x78)    
+  // Zero-page hotspots for lower and middle blocks
+  //   0xf8, 0xf9, 0xfa, 0xfb
+  //   0x78, 0x79, 0x7a, 0x7b (0x80 bytes lower)
+  else if((address & 0xf7c) == 0x78)
   {
-    if((databus & 0xf0) == 0)           // Zero page 0xf8 (lower block address of ROM)
+    if((databus & 0xf0) == 0)           // Enable 2K of ROM at 0x1000 - 0x17ff
     {
       myIsRomLow = true;
       mySliceLow = (databus & 0xf) << 11;
     }
-    else if((databus & 0xf0) == 0x40)   // Zero page 0xf9 (lower block address of RAM)
+    else if((databus & 0xf0) == 0x40)   // Enable 2K of RAM at 0x1000 - 0x17ff
     {
       myIsRomLow = false;
       mySliceLow = (databus & 0xf) << 11;
     }
-    else if((databus & 0xf0) == 0x90)   // Zero page 0xfa (middle block address of ROM)
+    else if((databus & 0xf0) == 0x90)   // Enable 1.5K of ROM at 0x1800 - 0x1dff
     {
       myIsRomMiddle = true;
       mySliceMiddle = ((databus & 0xf) | 0x10) << 11;
     }
-    else if((databus & 0xf0) == 0xc0)   // Zero page 0xfb (middle block address of RAM)
+    else if((databus & 0xf0) == 0xc0)   // Enable 1.5K of RAM at 0x1800 - 0x1dff
     {
       myIsRomMiddle = false;
       mySliceMiddle = (databus & 0xf) << 11;