2001-12-27 19:54:36 +00:00
|
|
|
//============================================================================
|
|
|
|
//
|
|
|
|
// SSSS tt lll lll
|
|
|
|
// SS SS tt ll ll
|
|
|
|
// SS tttttt eeee ll ll aaaa
|
|
|
|
// SSSS tt ee ee ll ll aa
|
|
|
|
// SS tt eeeeee ll ll aaaaa -- "An Atari 2600 VCS Emulator"
|
|
|
|
// SS SS tt ee ll ll aa aa
|
|
|
|
// SSSS ttt eeeee llll llll aaaaa
|
|
|
|
//
|
2015-01-01 03:49:32 +00:00
|
|
|
// Copyright (c) 1995-2015 by Bradford W. Mott, Stephen Anthony
|
2010-04-10 21:37:23 +00:00
|
|
|
// and the Stella Team
|
2001-12-27 19:54:36 +00:00
|
|
|
//
|
2010-01-10 03:23:32 +00:00
|
|
|
// See the file "License.txt" for information on usage and redistribution of
|
2001-12-27 19:54:36 +00:00
|
|
|
// this file, and for a DISCLAIMER OF ALL WARRANTIES.
|
|
|
|
//
|
2009-05-13 13:55:40 +00:00
|
|
|
// $Id$
|
2001-12-27 19:54:36 +00:00
|
|
|
//============================================================================
|
|
|
|
|
2009-01-26 21:08:07 +00:00
|
|
|
#include <cassert>
|
|
|
|
#include <iostream>
|
|
|
|
|
2001-12-27 19:54:36 +00:00
|
|
|
#include "Console.hxx"
|
2010-08-19 21:48:28 +00:00
|
|
|
#include "Settings.hxx"
|
2001-12-27 19:54:36 +00:00
|
|
|
#include "Switches.hxx"
|
|
|
|
#include "System.hxx"
|
2009-01-26 21:08:07 +00:00
|
|
|
|
|
|
|
#include "M6532.hxx"
|
2001-12-27 19:54:36 +00:00
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2010-08-19 21:48:28 +00:00
|
|
|
M6532::M6532(const Console& console, const Settings& settings)
|
|
|
|
: myConsole(console),
|
2014-10-27 14:41:46 +00:00
|
|
|
mySettings(settings),
|
|
|
|
myTimerFlagValid(false),
|
|
|
|
myEdgeDetectPositive(false)
|
2001-12-27 19:54:36 +00:00
|
|
|
{
|
|
|
|
}
|
2015-12-04 19:08:14 +00:00
|
|
|
|
2001-12-27 19:54:36 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
M6532::~M6532()
|
|
|
|
{
|
|
|
|
}
|
2015-12-04 19:08:14 +00:00
|
|
|
|
2001-12-27 19:54:36 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
void M6532::reset()
|
|
|
|
{
|
2010-08-19 21:48:28 +00:00
|
|
|
// Initialize the 128 bytes of memory
|
|
|
|
if(mySettings.getBool("ramrandom"))
|
|
|
|
for(uInt32 t = 0; t < 128; ++t)
|
|
|
|
myRAM[t] = mySystem->randGenerator().next();
|
|
|
|
else
|
|
|
|
memset(myRAM, 0, 128);
|
2008-08-01 12:16:00 +00:00
|
|
|
|
2008-05-16 23:56:31 +00:00
|
|
|
// The timer absolutely cannot be initialized to zero; some games will
|
|
|
|
// loop or hang (notably Solaris and H.E.R.O.)
|
2009-11-08 01:39:05 +00:00
|
|
|
myTimer = (0xff - (mySystem->randGenerator().next() % 0xfe)) << 10;
|
2008-05-16 23:56:31 +00:00
|
|
|
myIntervalShift = 10;
|
2001-12-27 19:54:36 +00:00
|
|
|
myCyclesWhenTimerSet = 0;
|
|
|
|
|
|
|
|
// Zero the I/O registers
|
2010-08-08 12:32:02 +00:00
|
|
|
myDDRA = myDDRB = myOutA = myOutB = 0x00;
|
Added RiotDebug class, which for now only duplicates the previous
functionality of the Debugger::riotState() method. It will become
more useful when I add a RIOT tab to the debugger. Also, added
change tracking infrastructure.
Fixed long-standing bug with viewing the contents of TIM{1, 8, 64, 1024}T
registers. Apparently, the output generated by the 'riot' debugger
command showed either INTIM or TIMINT for those registers, and not the
actual value written to those registers.
Added INTIM, TIMINT, and TIMCLKS to the riot output, which show the
current values of the timer, the timer interrupt, and the number of
'timer clocks' resulting from writing to a timer register.
Cleaned up some of the debugger API, removing pointers and using
references instead.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1479 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2008-04-19 21:11:52 +00:00
|
|
|
|
|
|
|
// Zero the timer registers
|
2008-04-23 16:51:11 +00:00
|
|
|
myOutTimer[0] = myOutTimer[1] = myOutTimer[2] = myOutTimer[3] = 0x00;
|
2012-09-11 21:16:21 +00:00
|
|
|
|
2012-09-15 12:44:24 +00:00
|
|
|
// Zero the interrupt flag register and mark D7 as invalid
|
2012-09-11 21:16:21 +00:00
|
|
|
myInterruptFlag = 0x00;
|
2012-09-15 12:44:24 +00:00
|
|
|
myTimerFlagValid = false;
|
2012-09-16 17:32:45 +00:00
|
|
|
|
|
|
|
// Edge-detect set to negative (high to low)
|
|
|
|
myEdgeDetectPositive = false;
|
2001-12-27 19:54:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
void M6532::systemCyclesReset()
|
|
|
|
{
|
|
|
|
// System cycles are being reset to zero so we need to adjust
|
|
|
|
// the cycle count we remembered when the timer was last set
|
|
|
|
myCyclesWhenTimerSet -= mySystem->cycles();
|
2008-05-19 02:53:58 +00:00
|
|
|
|
|
|
|
// We should also inform any 'smart' controllers as well
|
2014-11-04 00:34:56 +00:00
|
|
|
myConsole.leftController().systemCyclesReset();
|
|
|
|
myConsole.rightController().systemCyclesReset();
|
2001-12-27 19:54:36 +00:00
|
|
|
}
|
|
|
|
|
2012-09-16 17:32:45 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
void M6532::update()
|
|
|
|
{
|
2014-11-04 00:34:56 +00:00
|
|
|
Controller& port0 = myConsole.leftController();
|
|
|
|
Controller& port1 = myConsole.rightController();
|
2012-09-16 17:32:45 +00:00
|
|
|
|
|
|
|
// Get current PA7 state
|
|
|
|
bool prevPA7 = port0.myDigitalPinState[Controller::Four];
|
|
|
|
|
|
|
|
// Update entire port state
|
|
|
|
port0.update();
|
|
|
|
port1.update();
|
|
|
|
myConsole.switches().update();
|
|
|
|
|
|
|
|
// Get new PA7 state
|
|
|
|
bool currPA7 = port0.myDigitalPinState[Controller::Four];
|
|
|
|
|
|
|
|
// PA7 Flag is set on active transition in appropriate direction
|
|
|
|
if((!myEdgeDetectPositive && prevPA7 && !currPA7) ||
|
|
|
|
(myEdgeDetectPositive && !prevPA7 && currPA7))
|
|
|
|
myInterruptFlag |= PA7Bit;
|
|
|
|
}
|
|
|
|
|
2001-12-27 19:54:36 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
void M6532::install(System& system)
|
2008-02-19 12:33:07 +00:00
|
|
|
{
|
|
|
|
install(system, *this);
|
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
void M6532::install(System& system, Device& device)
|
2001-12-27 19:54:36 +00:00
|
|
|
{
|
|
|
|
// Remember which system I'm installed in
|
|
|
|
mySystem = &system;
|
|
|
|
|
2008-02-19 12:33:07 +00:00
|
|
|
// All accesses are to the given device
|
2014-07-24 16:24:27 +00:00
|
|
|
System::PageAccess access(&device, System::PA_READWRITE);
|
2001-12-27 19:54:36 +00:00
|
|
|
|
|
|
|
// We're installing in a 2600 system
|
2014-10-26 00:40:27 +00:00
|
|
|
for(int address = 0; address < 8192; address += (1 << System::PAGE_SHIFT))
|
2001-12-27 19:54:36 +00:00
|
|
|
if((address & 0x1080) == 0x0080)
|
2014-10-26 00:40:27 +00:00
|
|
|
mySystem->setPageAccess(address >> System::PAGE_SHIFT, access);
|
2001-12-27 19:54:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
uInt8 M6532::peek(uInt16 addr)
|
|
|
|
{
|
2008-02-19 12:33:07 +00:00
|
|
|
// Access RAM directly. Originally, accesses to RAM could bypass
|
|
|
|
// this method and its pages could be installed directly into the
|
|
|
|
// system. However, certain cartridges (notably 4A50) can mirror
|
|
|
|
// the RAM address space, making it necessary to chain accesses.
|
|
|
|
if((addr & 0x1080) == 0x0080 && (addr & 0x0200) == 0x0000)
|
|
|
|
{
|
|
|
|
return myRAM[addr & 0x007f];
|
|
|
|
}
|
|
|
|
|
2001-12-27 19:54:36 +00:00
|
|
|
switch(addr & 0x07)
|
|
|
|
{
|
2010-08-08 19:14:37 +00:00
|
|
|
case 0x00: // SWCHA - Port A I/O Register (Joystick)
|
2001-12-27 19:54:36 +00:00
|
|
|
{
|
2014-11-04 00:34:56 +00:00
|
|
|
uInt8 value = (myConsole.leftController().read() << 4) |
|
|
|
|
myConsole.rightController().read();
|
2001-12-27 19:54:36 +00:00
|
|
|
|
2008-05-06 16:39:12 +00:00
|
|
|
// Each pin is high (1) by default and will only go low (0) if either
|
|
|
|
// (a) External device drives the pin low
|
|
|
|
// (b) Corresponding bit in SWACNT = 1 and SWCHA = 0
|
|
|
|
// Thanks to A. Herbert for this info
|
|
|
|
return (myOutA | ~myDDRA) & value;
|
2001-12-27 19:54:36 +00:00
|
|
|
}
|
|
|
|
|
2010-08-08 19:14:37 +00:00
|
|
|
case 0x01: // SWACNT - Port A Data Direction Register
|
2001-12-27 19:54:36 +00:00
|
|
|
{
|
|
|
|
return myDDRA;
|
|
|
|
}
|
|
|
|
|
2010-08-08 19:14:37 +00:00
|
|
|
case 0x02: // SWCHB - Port B I/O Register (Console switches)
|
2001-12-27 19:54:36 +00:00
|
|
|
{
|
2010-08-08 19:14:37 +00:00
|
|
|
return (myOutB | ~myDDRB) & (myConsole.switches().read() | myDDRB);
|
2001-12-27 19:54:36 +00:00
|
|
|
}
|
|
|
|
|
2010-08-08 19:14:37 +00:00
|
|
|
case 0x03: // SWBCNT - Port B Data Direction Register
|
2001-12-27 19:54:36 +00:00
|
|
|
{
|
|
|
|
return myDDRB;
|
|
|
|
}
|
|
|
|
|
2012-09-15 12:44:24 +00:00
|
|
|
case 0x04: // INTIM - Timer Output
|
2001-12-27 19:54:36 +00:00
|
|
|
case 0x06:
|
|
|
|
{
|
2012-09-15 12:44:24 +00:00
|
|
|
// Timer Flag is always cleared when accessing INTIM
|
|
|
|
myInterruptFlag &= ~TimerBit;
|
|
|
|
|
|
|
|
// Get number of clocks since timer was set
|
2013-07-21 00:27:52 +00:00
|
|
|
Int32 timer = timerClocks();
|
2013-01-26 21:17:38 +00:00
|
|
|
|
|
|
|
// Note that this constant comes from z26, and corresponds to
|
|
|
|
// 256 intervals of T1024T (ie, the maximum that the timer should hold)
|
|
|
|
// I'm not sure why this is required, but quite a few ROMs fail
|
|
|
|
// if we just check >= 0.
|
|
|
|
if(!(timer & 0x40000))
|
2012-09-15 12:44:24 +00:00
|
|
|
{
|
|
|
|
// Return at 'divide by TIMxT' interval rate
|
|
|
|
return (timer >> myIntervalShift) & 0xff;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
// Return at 'divide by 1' rate
|
|
|
|
uInt8 divByOne = timer & 0xff;
|
|
|
|
|
|
|
|
// Timer flag has been updated; don't update it again on TIMINT read
|
|
|
|
if(divByOne != 0 && divByOne != 255)
|
|
|
|
myTimerFlagValid = true;
|
|
|
|
|
|
|
|
return divByOne;
|
|
|
|
}
|
2001-12-27 19:54:36 +00:00
|
|
|
}
|
|
|
|
|
2012-09-15 12:44:24 +00:00
|
|
|
case 0x05: // TIMINT/INSTAT - Interrupt Flag
|
2001-12-27 19:54:36 +00:00
|
|
|
case 0x07:
|
|
|
|
{
|
2012-09-15 12:44:24 +00:00
|
|
|
// Update timer flag if it is invalid and timer has expired
|
|
|
|
if(!myTimerFlagValid && timerClocks() < 0)
|
|
|
|
{
|
|
|
|
myInterruptFlag |= TimerBit;
|
|
|
|
myTimerFlagValid = true;
|
|
|
|
}
|
2012-09-16 17:32:45 +00:00
|
|
|
// PA7 Flag is always cleared after accessing TIMINT
|
|
|
|
uInt8 result = myInterruptFlag;
|
|
|
|
myInterruptFlag &= ~PA7Bit;
|
|
|
|
return result;
|
2001-12-27 19:54:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
default:
|
|
|
|
{
|
|
|
|
#ifdef DEBUG_ACCESSES
|
|
|
|
cerr << "BAD M6532 Peek: " << hex << addr << endl;
|
|
|
|
#endif
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2010-03-28 03:13:10 +00:00
|
|
|
bool M6532::poke(uInt16 addr, uInt8 value)
|
2001-12-27 19:54:36 +00:00
|
|
|
{
|
2008-02-19 12:33:07 +00:00
|
|
|
// Access RAM directly. Originally, accesses to RAM could bypass
|
|
|
|
// this method and its pages could be installed directly into the
|
|
|
|
// system. However, certain cartridges (notably 4A50) can mirror
|
|
|
|
// the RAM address space, making it necessary to chain accesses.
|
|
|
|
if((addr & 0x1080) == 0x0080 && (addr & 0x0200) == 0x0000)
|
|
|
|
{
|
|
|
|
myRAM[addr & 0x007f] = value;
|
2010-03-28 03:13:10 +00:00
|
|
|
return true;
|
2008-02-19 12:33:07 +00:00
|
|
|
}
|
2008-04-23 16:51:11 +00:00
|
|
|
|
2008-04-28 21:31:40 +00:00
|
|
|
// A2 distinguishes I/O registers from the timer
|
2012-09-16 17:32:45 +00:00
|
|
|
// A2 = 1 is write to timer
|
|
|
|
// A2 = 0 is write to I/O
|
2008-04-23 16:51:11 +00:00
|
|
|
if((addr & 0x04) != 0)
|
2001-12-27 19:54:36 +00:00
|
|
|
{
|
2012-09-16 17:32:45 +00:00
|
|
|
// A4 = 1 is write to TIMxT (x = 1, 8, 64, 1024)
|
|
|
|
// A4 = 0 is write to edge detect control
|
|
|
|
if((addr & 0x10) != 0)
|
|
|
|
setTimerRegister(value, addr & 0x03); // A1A0 determines interval
|
2012-09-27 22:17:27 +00:00
|
|
|
else
|
2012-09-16 17:32:45 +00:00
|
|
|
myEdgeDetectPositive = addr & 0x01; // A0 determines direction
|
2001-12-27 19:54:36 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2008-04-23 16:51:11 +00:00
|
|
|
switch(addr & 0x03)
|
|
|
|
{
|
2010-08-08 19:14:37 +00:00
|
|
|
case 0: // SWCHA - Port A I/O Register (Joystick)
|
2008-04-23 16:51:11 +00:00
|
|
|
{
|
|
|
|
myOutA = value;
|
2012-01-02 16:37:17 +00:00
|
|
|
setPinState(true);
|
2008-04-23 16:51:11 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2010-08-08 19:14:37 +00:00
|
|
|
case 1: // SWACNT - Port A Data Direction Register
|
2008-04-23 16:51:11 +00:00
|
|
|
{
|
|
|
|
myDDRA = value;
|
2012-01-02 16:37:17 +00:00
|
|
|
setPinState(false);
|
2008-04-23 16:51:11 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2010-08-08 19:14:37 +00:00
|
|
|
case 2: // SWCHB - Port B I/O Register (Console switches)
|
2010-08-08 12:32:02 +00:00
|
|
|
{
|
2010-08-08 19:14:37 +00:00
|
|
|
myOutB = value;
|
2010-08-08 12:32:02 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2010-08-08 19:14:37 +00:00
|
|
|
case 3: // SWBCNT - Port B Data Direction Register
|
2010-08-08 12:32:02 +00:00
|
|
|
{
|
2010-08-08 19:14:37 +00:00
|
|
|
myDDRB = value;
|
2010-08-08 12:32:02 +00:00
|
|
|
break;
|
|
|
|
}
|
2008-05-06 16:39:12 +00:00
|
|
|
}
|
2001-12-27 19:54:36 +00:00
|
|
|
}
|
2010-03-28 03:13:10 +00:00
|
|
|
return true;
|
2001-12-27 19:54:36 +00:00
|
|
|
}
|
|
|
|
|
2008-04-23 16:51:11 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
void M6532::setTimerRegister(uInt8 value, uInt8 interval)
|
|
|
|
{
|
|
|
|
static const uInt8 shift[] = { 0, 3, 6, 10 };
|
|
|
|
|
|
|
|
myIntervalShift = shift[interval];
|
|
|
|
myOutTimer[interval] = value;
|
|
|
|
myTimer = value << myIntervalShift;
|
|
|
|
myCyclesWhenTimerSet = mySystem->cycles();
|
2012-09-11 21:16:21 +00:00
|
|
|
|
2012-09-15 12:44:24 +00:00
|
|
|
// Interrupt timer flag is cleared (and invalid) when writing to the timer
|
|
|
|
myInterruptFlag &= ~TimerBit;
|
|
|
|
myTimerFlagValid = false;
|
2008-04-23 16:51:11 +00:00
|
|
|
}
|
|
|
|
|
2008-05-06 16:39:12 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
2012-01-02 16:37:17 +00:00
|
|
|
void M6532::setPinState(bool swcha)
|
2008-05-06 16:39:12 +00:00
|
|
|
{
|
|
|
|
/*
|
|
|
|
When a bit in the DDR is set as input, +5V is placed on its output
|
|
|
|
pin. When it's set as output, either +5V or 0V (depending on the
|
|
|
|
contents of SWCHA) will be placed on the output pin.
|
2008-05-16 23:56:31 +00:00
|
|
|
The standard macros for the AtariVox and SaveKey use this fact to
|
|
|
|
send data to the port. This is represented by the following algorithm:
|
2008-05-06 16:39:12 +00:00
|
|
|
|
|
|
|
if(DDR bit is input) set output as 1
|
|
|
|
else if(DDR bit is output) set output as bit in ORA
|
|
|
|
*/
|
2014-11-04 00:34:56 +00:00
|
|
|
Controller& port0 = myConsole.leftController();
|
|
|
|
Controller& port1 = myConsole.rightController();
|
2012-03-25 14:42:09 +00:00
|
|
|
|
|
|
|
uInt8 ioport = myOutA | ~myDDRA;
|
|
|
|
|
|
|
|
port0.write(Controller::One, ioport & 0x10);
|
|
|
|
port0.write(Controller::Two, ioport & 0x20);
|
|
|
|
port0.write(Controller::Three, ioport & 0x40);
|
|
|
|
port0.write(Controller::Four, ioport & 0x80);
|
|
|
|
port1.write(Controller::One, ioport & 0x01);
|
|
|
|
port1.write(Controller::Two, ioport & 0x02);
|
|
|
|
port1.write(Controller::Three, ioport & 0x04);
|
|
|
|
port1.write(Controller::Four, ioport & 0x08);
|
2012-03-14 01:19:23 +00:00
|
|
|
|
|
|
|
if(swcha)
|
|
|
|
{
|
2012-03-25 14:42:09 +00:00
|
|
|
port0.controlWrite(ioport);
|
|
|
|
port1.controlWrite(ioport);
|
2012-03-14 01:19:23 +00:00
|
|
|
}
|
2008-05-06 16:39:12 +00:00
|
|
|
}
|
|
|
|
|
2002-05-13 19:17:32 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
OK, another huge commit. I need to commit this now, because things are
starting to go out of sync on my development machines. OK, where to
begin ...
Changed state file format, so older state files will no longer work. The
changes aren't finalized yet, so expect more breakage.
Added getByte() and putByte() methods to serialized data, resulting in
smaller state files (previously, 1-byte values were stored as 4-byte ints).
Totally reworked controller handling code. Controller state is now
explicitly set with an ::update() method, making it easier to serialize.
Some work is still required on the serialization stuff for more advanced
controllers.
Added a 'Serializable' interface to all carts, device, controllers, etc
that can be (de)serialized. This fixes a long-standing design issue
which I personally caused many years ago.
Console switches state (SWCHB register) is now saved to state files.
Added beginnings of movie support. Basically, this saves an initial
state file, and thereafter continuously saves controller and console
switches state. Support is still somewhat rough and there's no UI for
it, but it does successfully save and later load/play state movies.
Removed specific events for driving controllers, and have them use
joystick events instead. This has the nice side effect that
joystick direction remapping 'just works' for driving controllers too.
Fixed issues with paddle emulation seen in 'Night Driver' ROM. Related
to this, removed a hack wrt paddles when grabmouse is enabled. There's
still some work to do when using the mouse to emulate paddles, but the
Stelladaptor and real paddles work fine.
Added beginnings of TrackBall CX-22 controller emulation. It doesn't
actually do anything yet, but the class is there :)
Probably some other stuff that I'm forgetting ...
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1385 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2007-10-03 21:41:19 +00:00
|
|
|
bool M6532::save(Serializer& out) const
|
2002-05-13 19:17:32 +00:00
|
|
|
{
|
|
|
|
try
|
|
|
|
{
|
2010-08-08 19:14:37 +00:00
|
|
|
out.putString(name());
|
2002-05-13 19:17:32 +00:00
|
|
|
|
2012-05-20 14:23:48 +00:00
|
|
|
out.putByteArray(myRAM, 128);
|
2002-05-13 19:17:32 +00:00
|
|
|
|
2005-12-17 01:23:07 +00:00
|
|
|
out.putInt(myTimer);
|
|
|
|
out.putInt(myIntervalShift);
|
|
|
|
out.putInt(myCyclesWhenTimerSet);
|
2008-04-23 16:51:11 +00:00
|
|
|
|
2012-05-20 14:23:48 +00:00
|
|
|
out.putByte(myDDRA);
|
|
|
|
out.putByte(myDDRB);
|
|
|
|
out.putByte(myOutA);
|
|
|
|
out.putByte(myOutB);
|
2012-09-16 17:32:45 +00:00
|
|
|
|
2012-09-11 21:16:21 +00:00
|
|
|
out.putByte(myInterruptFlag);
|
2012-09-15 12:44:24 +00:00
|
|
|
out.putBool(myTimerFlagValid);
|
2012-09-16 17:32:45 +00:00
|
|
|
out.putBool(myEdgeDetectPositive);
|
2012-05-20 14:23:48 +00:00
|
|
|
out.putByteArray(myOutTimer, 4);
|
2002-05-13 19:17:32 +00:00
|
|
|
}
|
2012-05-25 12:41:19 +00:00
|
|
|
catch(...)
|
2002-05-13 19:17:32 +00:00
|
|
|
{
|
2012-05-25 12:41:19 +00:00
|
|
|
cerr << "ERROR: M6532::save" << endl;
|
2002-05-13 19:17:32 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
OK, this looks like a huge update, but it's only because of some Serializer
class reworking. Serializer class now handles read/write of state from
files as well as in-memory streams. As a result, Deserializer class has
been removed.
Added state rewinding to the debugger. For now, this is limited to 100
levels of undo, with a new state generated each time a step/trace/frame/
scanline advance is performed. The undo level is 'rolling', in that it
remembers the last 100 levels (so you lose the oldest states when you
start adding more than 100). For now, this is tied to the 'Alt-r' key
in the debugger. Still TODO is add a button for it, and clean up some
TIA output issues when rewinding.
Added support for 6K version of Supercharger ROMs (this fixes issues
with the 6K version of Cubis).
Cleaned up the Serializable infrastructure, making sure that all
classes that need to implement it actually do so now.
Fixed issue with editable widgets in the UI, where pressing Enter
on the keypad wasn't actually being registered.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1849 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2009-08-05 16:05:34 +00:00
|
|
|
bool M6532::load(Serializer& in)
|
2002-05-13 19:17:32 +00:00
|
|
|
{
|
|
|
|
try
|
|
|
|
{
|
2010-08-08 19:14:37 +00:00
|
|
|
if(in.getString() != name())
|
2002-05-13 19:17:32 +00:00
|
|
|
return false;
|
|
|
|
|
2012-05-20 14:23:48 +00:00
|
|
|
in.getByteArray(myRAM, 128);
|
2002-05-13 19:17:32 +00:00
|
|
|
|
2012-05-20 14:23:48 +00:00
|
|
|
myTimer = in.getInt();
|
|
|
|
myIntervalShift = in.getInt();
|
|
|
|
myCyclesWhenTimerSet = in.getInt();
|
2002-05-13 19:17:32 +00:00
|
|
|
|
2012-05-20 14:23:48 +00:00
|
|
|
myDDRA = in.getByte();
|
|
|
|
myDDRB = in.getByte();
|
|
|
|
myOutA = in.getByte();
|
|
|
|
myOutB = in.getByte();
|
2012-09-16 17:32:45 +00:00
|
|
|
|
2012-09-11 21:16:21 +00:00
|
|
|
myInterruptFlag = in.getByte();
|
2012-09-15 12:44:24 +00:00
|
|
|
myTimerFlagValid = in.getBool();
|
2012-09-16 17:32:45 +00:00
|
|
|
myEdgeDetectPositive = in.getBool();
|
2012-05-20 14:23:48 +00:00
|
|
|
in.getByteArray(myOutTimer, 4);
|
2002-05-13 19:17:32 +00:00
|
|
|
}
|
2012-05-25 12:41:19 +00:00
|
|
|
catch(...)
|
2002-05-13 19:17:32 +00:00
|
|
|
{
|
2012-05-25 12:41:19 +00:00
|
|
|
cerr << "ERROR: M6532::load" << endl;
|
2002-05-13 19:17:32 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-02-17 22:33:53 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
uInt8 M6532::intim() const
|
|
|
|
{
|
|
|
|
// This method is documented in ::peek(0x284), and exists so that the
|
|
|
|
// debugger can read INTIM without changing the state of the system
|
|
|
|
|
|
|
|
// Get number of clocks since timer was set
|
|
|
|
Int32 timer = timerClocks();
|
|
|
|
if(!(timer & 0x40000))
|
|
|
|
return (timer >> myIntervalShift) & 0xff;
|
|
|
|
else
|
|
|
|
return timer & 0xff;
|
|
|
|
}
|
|
|
|
|
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
uInt8 M6532::timint() const
|
|
|
|
{
|
|
|
|
// This method is documented in ::peek(0x285), and exists so that the
|
|
|
|
// debugger can read TIMINT without changing the state of the system
|
|
|
|
|
|
|
|
// Update timer flag if it is invalid and timer has expired
|
|
|
|
uInt8 interrupt = myInterruptFlag;
|
|
|
|
if(timerClocks() < 0)
|
|
|
|
interrupt |= TimerBit;
|
|
|
|
|
|
|
|
return interrupt;
|
|
|
|
}
|
|
|
|
|
2013-07-21 00:27:52 +00:00
|
|
|
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
|
|
|
Int32 M6532::intimClocks() const
|
|
|
|
{
|
|
|
|
// This method is similar to intim(), except instead of giving the actual
|
|
|
|
// INTIM value, it will give the current number of clocks between one
|
|
|
|
// INTIM value and the next
|
|
|
|
|
|
|
|
// Get number of clocks since timer was set
|
|
|
|
Int32 timer = timerClocks();
|
|
|
|
if(!(timer & 0x40000))
|
|
|
|
return timerClocks() & ((1 << myIntervalShift) - 1);
|
|
|
|
else
|
|
|
|
return timer & 0xff;
|
|
|
|
}
|