mirror of https://github.com/snes9xgit/snes9x.git
Increment VRAM pointer even if we don't write to it.
This commit is contained in:
parent
a911503d4a
commit
c29ca215d0
|
@ -3856,9 +3856,7 @@ void CMemory::ApplyROMFixes (void)
|
|||
if (!Settings.DisableGameSpecificHacks)
|
||||
{
|
||||
// XXX: What's happening?
|
||||
if (match_na("X-MEN") || // Spider-Man and the X-Men
|
||||
match_na("KICK OFF") ||
|
||||
match_na("SUPER FAMICOM JOJO"))
|
||||
if (match_na("X-MEN")) // Spider-Man and the X-Men
|
||||
{
|
||||
Settings.BlockInvalidVRAMAccess = FALSE;
|
||||
printf("Invalid VRAM access hack\n");
|
||||
|
|
129
ppu.h
129
ppu.h
|
@ -517,12 +517,18 @@ static inline void REGISTER_2104 (uint8 Byte)
|
|||
{ \
|
||||
printf("Invalid VRAM acess at (%04d, %04d) blank:%d\n", CPU.Cycles, CPU.V_Counter, PPU.ForcedBlanking); \
|
||||
if (Settings.BlockInvalidVRAMAccess) \
|
||||
{ \
|
||||
PPU.VMA.Address += !PPU.VMA.High ? PPU.VMA.Increment : 0; \
|
||||
return; \
|
||||
} \
|
||||
}
|
||||
#else
|
||||
#define CHECK_INBLANK() \
|
||||
if (Settings.BlockInvalidVRAMAccess && !PPU.ForcedBlanking && CPU.V_Counter < PPU.ScreenHeight + FIRST_VISIBLE_LINE) \
|
||||
return;
|
||||
{ \
|
||||
PPU.VMA.Address += !PPU.VMA.High ? PPU.VMA.Increment : 0; \
|
||||
return; \
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline void REGISTER_2118 (uint8 Byte)
|
||||
|
@ -562,10 +568,80 @@ static inline void REGISTER_2118 (uint8 Byte)
|
|||
}
|
||||
}
|
||||
|
||||
static inline void REGISTER_2119 (uint8 Byte)
|
||||
static inline void REGISTER_2118_tile (uint8 Byte)
|
||||
{
|
||||
CHECK_INBLANK();
|
||||
|
||||
uint32 rem = PPU.VMA.Address & PPU.VMA.Mask1;
|
||||
uint32 address = (((PPU.VMA.Address & ~PPU.VMA.Mask1) + (rem >> PPU.VMA.Shift) + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) & 0xffff;
|
||||
|
||||
Memory.VRAM[address] = Byte;
|
||||
|
||||
IPPU.TileCached[TILE_2BIT][address >> 4] = FALSE;
|
||||
IPPU.TileCached[TILE_4BIT][address >> 5] = FALSE;
|
||||
IPPU.TileCached[TILE_8BIT][address >> 6] = FALSE;
|
||||
IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = FALSE;
|
||||
IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = FALSE;
|
||||
IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = FALSE;
|
||||
IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = FALSE;
|
||||
IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = FALSE;
|
||||
IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = FALSE;
|
||||
IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = FALSE;
|
||||
IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = FALSE;
|
||||
|
||||
if (!PPU.VMA.High)
|
||||
PPU.VMA.Address += PPU.VMA.Increment;
|
||||
}
|
||||
|
||||
static inline void REGISTER_2118_linear (uint8 Byte)
|
||||
{
|
||||
CHECK_INBLANK();
|
||||
|
||||
uint32 address;
|
||||
|
||||
Memory.VRAM[address = (PPU.VMA.Address << 1) & 0xffff] = Byte;
|
||||
|
||||
IPPU.TileCached[TILE_2BIT][address >> 4] = FALSE;
|
||||
IPPU.TileCached[TILE_4BIT][address >> 5] = FALSE;
|
||||
IPPU.TileCached[TILE_8BIT][address >> 6] = FALSE;
|
||||
IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = FALSE;
|
||||
IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = FALSE;
|
||||
IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = FALSE;
|
||||
IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = FALSE;
|
||||
IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = FALSE;
|
||||
IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = FALSE;
|
||||
IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = FALSE;
|
||||
IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = FALSE;
|
||||
|
||||
if (!PPU.VMA.High)
|
||||
PPU.VMA.Address += PPU.VMA.Increment;
|
||||
}
|
||||
|
||||
#undef CHECK_INBLANK
|
||||
#ifdef DEBUGGER
|
||||
#define CHECK_INBLANK() \
|
||||
if (!PPU.ForcedBlanking && CPU.V_Counter < PPU.ScreenHeight + FIRST_VISIBLE_LINE) \
|
||||
{ \
|
||||
printf("Invalid VRAM acess at (%04d, %04d) blank:%d\n", CPU.Cycles, CPU.V_Counter, PPU.ForcedBlanking); \
|
||||
if (Settings.BlockInvalidVRAMAccess) \
|
||||
{ \
|
||||
PPU.VMA.Address += PPU.VMA.High ? PPU.VMA.Increment : 0; \
|
||||
return; \
|
||||
} \
|
||||
}
|
||||
#else
|
||||
#define CHECK_INBLANK() \
|
||||
if (Settings.BlockInvalidVRAMAccess && !PPU.ForcedBlanking && CPU.V_Counter < PPU.ScreenHeight + FIRST_VISIBLE_LINE) \
|
||||
{ \
|
||||
PPU.VMA.Address += PPU.VMA.High ? PPU.VMA.Increment : 0; \
|
||||
return; \
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
static inline void REGISTER_2119 (uint8 Byte)
|
||||
{
|
||||
CHECK_INBLANK();
|
||||
uint32 address;
|
||||
|
||||
if (PPU.VMA.FullGraphicCount)
|
||||
|
@ -599,31 +675,6 @@ static inline void REGISTER_2119 (uint8 Byte)
|
|||
}
|
||||
}
|
||||
|
||||
static inline void REGISTER_2118_tile (uint8 Byte)
|
||||
{
|
||||
CHECK_INBLANK();
|
||||
|
||||
uint32 rem = PPU.VMA.Address & PPU.VMA.Mask1;
|
||||
uint32 address = (((PPU.VMA.Address & ~PPU.VMA.Mask1) + (rem >> PPU.VMA.Shift) + ((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) & 0xffff;
|
||||
|
||||
Memory.VRAM[address] = Byte;
|
||||
|
||||
IPPU.TileCached[TILE_2BIT][address >> 4] = FALSE;
|
||||
IPPU.TileCached[TILE_4BIT][address >> 5] = FALSE;
|
||||
IPPU.TileCached[TILE_8BIT][address >> 6] = FALSE;
|
||||
IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = FALSE;
|
||||
IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = FALSE;
|
||||
IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = FALSE;
|
||||
IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = FALSE;
|
||||
IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = FALSE;
|
||||
IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = FALSE;
|
||||
IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = FALSE;
|
||||
IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = FALSE;
|
||||
|
||||
if (!PPU.VMA.High)
|
||||
PPU.VMA.Address += PPU.VMA.Increment;
|
||||
}
|
||||
|
||||
static inline void REGISTER_2119_tile (uint8 Byte)
|
||||
{
|
||||
CHECK_INBLANK();
|
||||
|
@ -649,30 +700,6 @@ static inline void REGISTER_2119_tile (uint8 Byte)
|
|||
PPU.VMA.Address += PPU.VMA.Increment;
|
||||
}
|
||||
|
||||
static inline void REGISTER_2118_linear (uint8 Byte)
|
||||
{
|
||||
CHECK_INBLANK();
|
||||
|
||||
uint32 address;
|
||||
|
||||
Memory.VRAM[address = (PPU.VMA.Address << 1) & 0xffff] = Byte;
|
||||
|
||||
IPPU.TileCached[TILE_2BIT][address >> 4] = FALSE;
|
||||
IPPU.TileCached[TILE_4BIT][address >> 5] = FALSE;
|
||||
IPPU.TileCached[TILE_8BIT][address >> 6] = FALSE;
|
||||
IPPU.TileCached[TILE_2BIT_EVEN][address >> 4] = FALSE;
|
||||
IPPU.TileCached[TILE_2BIT_EVEN][((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = FALSE;
|
||||
IPPU.TileCached[TILE_2BIT_ODD] [address >> 4] = FALSE;
|
||||
IPPU.TileCached[TILE_2BIT_ODD] [((address >> 4) - 1) & (MAX_2BIT_TILES - 1)] = FALSE;
|
||||
IPPU.TileCached[TILE_4BIT_EVEN][address >> 5] = FALSE;
|
||||
IPPU.TileCached[TILE_4BIT_EVEN][((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = FALSE;
|
||||
IPPU.TileCached[TILE_4BIT_ODD] [address >> 5] = FALSE;
|
||||
IPPU.TileCached[TILE_4BIT_ODD] [((address >> 5) - 1) & (MAX_4BIT_TILES - 1)] = FALSE;
|
||||
|
||||
if (!PPU.VMA.High)
|
||||
PPU.VMA.Address += PPU.VMA.Increment;
|
||||
}
|
||||
|
||||
static inline void REGISTER_2119_linear (uint8 Byte)
|
||||
{
|
||||
CHECK_INBLANK();
|
||||
|
|
Loading…
Reference in New Issue