Proper for Marko AND Super Ghouls and Ghosts.

This commit is contained in:
Brandon Wright 2018-05-31 15:02:42 -05:00
parent f9a659d951
commit 85b0cf0191
5 changed files with 28 additions and 5 deletions

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@ -267,6 +267,8 @@ static void S9xSoftResetCPU (void)
Timings.V_Max = Timings.V_Max_Master; Timings.V_Max = Timings.V_Max_Master;
Timings.NMITriggerPos = 0xffff; Timings.NMITriggerPos = 0xffff;
Timings.NextIRQTimer = 0x0fffffff; Timings.NextIRQTimer = 0x0fffffff;
Timings.IRQFlagChanging = IRQ_NONE;
if (Model->_5A22 == 2) if (Model->_5A22 == 2)
Timings.WRAMRefreshPos = SNES_WRAM_REFRESH_HC_v2; Timings.WRAMRefreshPos = SNES_WRAM_REFRESH_HC_v2;
else else

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@ -260,6 +260,17 @@ void S9xMainLoop (void)
if ((CPU.IRQLine || CPU.IRQExternal) && !CheckFlag(IRQ)) if ((CPU.IRQLine || CPU.IRQExternal) && !CheckFlag(IRQ))
S9xOpcode_IRQ(); S9xOpcode_IRQ();
/* Change IRQ flag for instructions that set it only on last cycle */
if (Timings.IRQFlagChanging)
{
if (Timings.IRQFlagChanging == IRQ_CLEAR_FLAG)
ClearIRQ();
else if (Timings.IRQFlagChanging == IRQ_SET_FLAG)
SetIRQ();
Timings.IRQFlagChanging = IRQ_NONE;
}
#ifdef DEBUGGER #ifdef DEBUGGER
if ((CPU.Flags & BREAK_FLAG) && !(CPU.Flags & SINGLE_STEP_FLAG)) if ((CPU.Flags & BREAK_FLAG) && !(CPU.Flags & SINGLE_STEP_FLAG))
{ {

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@ -1635,19 +1635,22 @@ static void OpF8 (void)
// CLI // CLI
static void Op58 (void) static void Op58 (void)
{ {
ClearIRQ(); // ClearIRQ();
AddCycles(ONE_CYCLE); AddCycles(ONE_CYCLE);
#ifndef SA1_OPCODES #ifndef SA1_OPCODES
CPU.IRQLine = FALSE; Timings.IRQFlagChanging = IRQ_CLEAR_FLAG;
#endif #endif
} }
// SEI // SEI
static void Op78 (void) static void Op78 (void)
{ {
SetIRQ();
AddCycles(ONE_CYCLE); AddCycles(ONE_CYCLE);
#ifndef SA1_OPCODES
Timings.IRQFlagChanging = IRQ_SET_FLAG;
#endif
} }
// CLV // CLV

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@ -595,7 +595,7 @@ static FreezeData SnapTimings[] =
INT_ENTRY(6, InterlaceField), INT_ENTRY(6, InterlaceField),
INT_ENTRY(6, DMACPUSync), INT_ENTRY(6, DMACPUSync),
INT_ENTRY(6, NMIDMADelay), INT_ENTRY(6, NMIDMADelay),
INT_ENTRY(6, IRQPendCount), INT_ENTRY(6, IRQFlagChanging),
INT_ENTRY(6, APUSpeedup), INT_ENTRY(6, APUSpeedup),
INT_ENTRY(7, IRQTriggerCycles), INT_ENTRY(7, IRQTriggerCycles),
INT_ENTRY(7, APUAllowTimeOverflow) INT_ENTRY(7, APUAllowTimeOverflow)

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@ -335,6 +335,13 @@ enum
HC_WRAM_REFRESH_EVENT = 6 HC_WRAM_REFRESH_EVENT = 6
}; };
enum
{
IRQ_NONE = 0,
IRQ_SET_FLAG = 1,
IRQ_CLEAR_FLAG = 2
};
struct STimings struct STimings
{ {
int32 H_Max_Master; int32 H_Max_Master;
@ -353,7 +360,7 @@ struct STimings
bool8 InterlaceField; bool8 InterlaceField;
int32 DMACPUSync; // The cycles to synchronize DMA and CPU. Snes9x cannot emulate correctly. int32 DMACPUSync; // The cycles to synchronize DMA and CPU. Snes9x cannot emulate correctly.
int32 NMIDMADelay; // The delay of NMI trigger after DMA transfers. Snes9x cannot emulate correctly. int32 NMIDMADelay; // The delay of NMI trigger after DMA transfers. Snes9x cannot emulate correctly.
int32 IRQPendCount; // This value is just a hack. int32 IRQFlagChanging; // This value is just a hack.
int32 APUSpeedup; int32 APUSpeedup;
bool8 APUAllowTimeOverflow; bool8 APUAllowTimeOverflow;
}; };