2011-06-12 06:25:22 +00:00
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void SMP::tick() {
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timer0.tick();
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timer1.tick();
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timer2.tick();
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2011-06-23 10:24:13 +00:00
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#ifndef SNES9X
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2011-06-12 06:25:22 +00:00
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clock += cycle_step_cpu;
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2011-06-23 11:14:14 +00:00
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dsp.clock -= 24;
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synchronize_dsp();
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2011-06-22 11:03:29 +00:00
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#else
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clock++;
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2011-06-27 20:41:17 +00:00
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dsp.clock++;
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2011-06-22 11:03:29 +00:00
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#endif
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2011-06-12 06:25:22 +00:00
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}
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2011-09-14 17:54:51 +00:00
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void SMP::tick(unsigned clocks) {
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timer0.tick(clocks);
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timer1.tick(clocks);
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timer2.tick(clocks);
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clock += clocks;
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dsp.clock += clocks;
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}
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2011-06-12 06:25:22 +00:00
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void SMP::op_io() {
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#if defined(CYCLE_ACCURATE)
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tick();
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#endif
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}
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2011-09-14 17:54:51 +00:00
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void SMP::op_io(unsigned clocks) {
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tick(clocks);
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}
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2011-06-12 06:25:22 +00:00
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uint8 SMP::op_read(uint16 addr) {
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#if defined(CYCLE_ACCURATE)
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tick();
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#endif
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if((addr & 0xfff0) == 0x00f0) return mmio_read(addr);
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if(addr >= 0xffc0 && status.iplrom_enable) return iplrom[addr & 0x3f];
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return apuram[addr];
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}
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void SMP::op_write(uint16 addr, uint8 data) {
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#if defined(CYCLE_ACCURATE)
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tick();
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#endif
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if((addr & 0xfff0) == 0x00f0) mmio_write(addr, data);
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apuram[addr] = data; //all writes go to RAM, even MMIO writes
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}
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void SMP::op_step() {
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#define op_readpc() op_read(regs.pc++)
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#define op_readdp(addr) op_read((regs.p.p << 8) + addr)
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#define op_writedp(addr, data) op_write((regs.p.p << 8) + addr, data)
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#define op_readaddr(addr) op_read(addr)
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#define op_writeaddr(addr, data) op_write(addr, data)
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#define op_readstack() op_read(0x0100 | ++regs.sp)
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#define op_writestack(data) op_write(0x0100 | regs.sp--, data)
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#if defined(CYCLE_ACCURATE)
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2011-10-18 18:10:06 +00:00
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#if defined(PSEUDO_CYCLE)
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2011-06-12 06:25:22 +00:00
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2011-09-19 20:15:19 +00:00
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if(opcode_cycle == 0)
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2011-06-12 06:25:22 +00:00
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opcode_number = op_readpc();
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2011-09-19 20:15:19 +00:00
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switch(opcode_number) {
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2011-10-18 18:10:06 +00:00
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#include "core/oppseudo_misc.cpp"
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#include "core/oppseudo_mov.cpp"
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#include "core/oppseudo_pc.cpp"
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#include "core/oppseudo_read.cpp"
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#include "core/oppseudo_rmw.cpp"
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}
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#else
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if(opcode_cycle == 0) {
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opcode_number = op_readpc();
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opcode_cycle++;
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} else switch(opcode_number) {
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2011-06-12 06:25:22 +00:00
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#include "core/opcycle_misc.cpp"
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#include "core/opcycle_mov.cpp"
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#include "core/opcycle_pc.cpp"
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#include "core/opcycle_read.cpp"
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#include "core/opcycle_rmw.cpp"
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}
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2011-10-18 18:10:06 +00:00
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#endif // defined(PSEUDO_CYCLE)
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2011-06-12 06:25:22 +00:00
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#else
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unsigned opcode = op_readpc();
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switch(opcode) {
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#include "core/op_misc.cpp"
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#include "core/op_mov.cpp"
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#include "core/op_pc.cpp"
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#include "core/op_read.cpp"
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#include "core/op_rmw.cpp"
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}
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//TODO: untaken branches should consume less cycles
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timer0.tick(cycle_count_table[opcode]);
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timer1.tick(cycle_count_table[opcode]);
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timer2.tick(cycle_count_table[opcode]);
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2011-06-23 10:24:13 +00:00
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#ifndef SNES9X
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2011-06-12 06:25:22 +00:00
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clock += cycle_table_cpu[opcode];
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2011-06-23 11:14:14 +00:00
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dsp.clock -= cycle_table_dsp[opcode];
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synchronize_dsp();
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2011-06-22 11:03:29 +00:00
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#else
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clock += cycle_count_table[opcode];
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2011-06-27 20:41:17 +00:00
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dsp.clock += cycle_count_table[opcode];
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2011-06-22 11:03:29 +00:00
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#endif
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2011-06-23 11:14:14 +00:00
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2011-10-18 18:10:06 +00:00
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#endif // defined(CYCLE_ACCURATE)
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2011-06-12 06:25:22 +00:00
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}
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const unsigned SMP::cycle_count_table[256] = {
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#define c 12
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//0 1 2 3 4 5 6 7 8 9 A B C D E F
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2,8,4,7, 3,4,3,6, 2,6,5,4, 5,4,6,8, //0
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4,8,4,7, 4,5,5,6, 5,5,6,5, 2,2,4,6, //1
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2,8,4,7, 3,4,3,6, 2,6,5,4, 5,4,7,4, //2
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4,8,4,7, 4,5,5,6, 5,5,6,5, 2,2,3,8, //3
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2,8,4,7, 3,4,3,6, 2,6,4,4, 5,4,6,6, //4
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4,8,4,7, 4,5,5,6, 5,5,4,5, 2,2,4,3, //5
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2,8,4,7, 3,4,3,6, 2,6,4,4, 5,4,7,5, //6
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4,8,4,7, 4,5,5,6, 5,5,5,5, 2,2,3,6, //7
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2,8,4,7, 3,4,3,6, 2,6,5,4, 5,2,4,5, //8
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4,8,4,7, 4,5,5,6, 5,5,5,5, 2,2,c,5, //9
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3,8,4,7, 3,4,3,6, 2,6,4,4, 5,2,4,4, //A
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4,8,4,7, 4,5,5,6, 5,5,5,5, 2,2,3,4, //B
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3,8,4,7, 4,5,4,7, 2,5,6,4, 5,2,4,9, //C
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4,8,4,7, 5,6,6,7, 4,5,5,5, 2,2,8,3, //D
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2,8,4,7, 3,4,3,6, 2,4,5,3, 4,3,4,1, //E
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4,8,4,7, 4,5,5,6, 3,4,5,4, 2,2,6,1, //F
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#undef c
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};
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