diff --git a/rpcs3/Emu/Cell/PPUAnalyser.cpp b/rpcs3/Emu/Cell/PPUAnalyser.cpp
index cdc9b02139..b5d7ad6520 100644
--- a/rpcs3/Emu/Cell/PPUAnalyser.cpp
+++ b/rpcs3/Emu/Cell/PPUAnalyser.cpp
@@ -23,9 +23,6 @@ void fmt_class_string<ppu_attr>::format(std::string& out, u64 arg)
 		case ppu_attr::known_size: return "known_size";
 		case ppu_attr::no_return: return "no_return";
 		case ppu_attr::no_size: return "no_size";
-		case ppu_attr::uses_r0: return "uses_r0";
-		case ppu_attr::entry_point: return "entry_point";
-		case ppu_attr::complex_stack: return "complex_stack";
 		case ppu_attr::__bitset_enum_max: break;
 		}
 
@@ -1037,15 +1034,6 @@ std::vector<ppu_function> ppu_analyse(const std::vector<std::pair<u32, u32>>& se
 				func.size = len;
 			}
 
-			if (ptr + 3 <= fend &&
-				(ptr[0] & 0xffff0000) == LI(r0, 0) &&
-				(ptr[1] & 0xffff0000) == ORIS(r0, r0, 0) &&
-				(ptr[2] & 0xfc000003) == B({}, {}, {}))
-			{
-				// Import stub with r0 usage
-				func.attr += ppu_attr::uses_r0;
-			}
-
 			// TODO: detect no_return, scribe more TODOs
 
 			// Acknowledge completion
diff --git a/rpcs3/Emu/Cell/PPUAnalyser.h b/rpcs3/Emu/Cell/PPUAnalyser.h
index 69cf38913c..1e2a1e9513 100644
--- a/rpcs3/Emu/Cell/PPUAnalyser.h
+++ b/rpcs3/Emu/Cell/PPUAnalyser.h
@@ -14,12 +14,6 @@ enum class ppu_attr : u32
 	known_size,
 	no_return,
 	no_size,
-	uses_r0,
-	entry_point,
-	complex_stack,
-	special,
-	//call_use_context,
-	//call_trace,
 
 	__bitset_enum_max
 };
@@ -536,422 +530,6 @@ struct ppu_itype
 	}
 };
 
-// PPU Instruction Flags
-struct ppu_iflag
-{
-	// Various flags (TODO)
-	enum : u32
-	{
-		write_rd  = 1 << 0,
-		write_ra  = 1 << 1,
-		read_ra   = 1 << 2,
-		read_rb   = 1 << 3,
-		read_rs   = 1 << 4,
-		write_vd  = 1 << 5,
-		read_va   = 1 << 6,
-		read_vb   = 1 << 7,
-		read_vc   = 1 << 8,
-		read_vs   = 1 << 9,
-		write_frd = 1 << 10,
-		read_fra  = 1 << 11,
-		read_frb  = 1 << 12,
-		read_frc  = 1 << 13,
-		read_frs  = 1 << 14,
-		rw_all    = 1 << 15,
-	};
-
-	enum flags : u32
-	{
-		UNK        = 0,
-
-		MFVSCR     = 0,
-		MTVSCR     = 0,
-		VADDCUW    = 0,
-		VADDFP     = 0,
-		VADDSBS    = 0,
-		VADDSHS    = 0,
-		VADDSWS    = 0,
-		VADDUBM    = 0,
-		VADDUBS    = 0,
-		VADDUHM    = 0,
-		VADDUHS    = 0,
-		VADDUWM    = 0,
-		VADDUWS    = 0,
-		VAND       = 0,
-		VANDC      = 0,
-		VAVGSB     = 0,
-		VAVGSH     = 0,
-		VAVGSW     = 0,
-		VAVGUB     = 0,
-		VAVGUH     = 0,
-		VAVGUW     = 0,
-		VCFSX      = 0,
-		VCFUX      = 0,
-		VCMPBFP    = 0,
-		VCMPEQFP   = 0,
-		VCMPEQUB   = 0,
-		VCMPEQUH   = 0,
-		VCMPEQUW   = 0,
-		VCMPGEFP   = 0,
-		VCMPGTFP   = 0,
-		VCMPGTSB   = 0,
-		VCMPGTSH   = 0,
-		VCMPGTSW   = 0,
-		VCMPGTUB   = 0,
-		VCMPGTUH   = 0,
-		VCMPGTUW   = 0,
-		VCTSXS     = 0,
-		VCTUXS     = 0,
-		VEXPTEFP   = 0,
-		VLOGEFP    = 0,
-		VMADDFP    = 0,
-		VMAXFP     = 0,
-		VMAXSB     = 0,
-		VMAXSH     = 0,
-		VMAXSW     = 0,
-		VMAXUB     = 0,
-		VMAXUH     = 0,
-		VMAXUW     = 0,
-		VMHADDSHS  = 0,
-		VMHRADDSHS = 0,
-		VMINFP     = 0,
-		VMINSB     = 0,
-		VMINSH     = 0,
-		VMINSW     = 0,
-		VMINUB     = 0,
-		VMINUH     = 0,
-		VMINUW     = 0,
-		VMLADDUHM  = 0,
-		VMRGHB     = 0,
-		VMRGHH     = 0,
-		VMRGHW     = 0,
-		VMRGLB     = 0,
-		VMRGLH     = 0,
-		VMRGLW     = 0,
-		VMSUMMBM   = 0,
-		VMSUMSHM   = 0,
-		VMSUMSHS   = 0,
-		VMSUMUBM   = 0,
-		VMSUMUHM   = 0,
-		VMSUMUHS   = 0,
-		VMULESB    = 0,
-		VMULESH    = 0,
-		VMULEUB    = 0,
-		VMULEUH    = 0,
-		VMULOSB    = 0,
-		VMULOSH    = 0,
-		VMULOUB    = 0,
-		VMULOUH    = 0,
-		VNMSUBFP   = 0,
-		VNOR       = 0,
-		VOR        = 0,
-		VPERM      = 0,
-		VPKPX      = 0,
-		VPKSHSS    = 0,
-		VPKSHUS    = 0,
-		VPKSWSS    = 0,
-		VPKSWUS    = 0,
-		VPKUHUM    = 0,
-		VPKUHUS    = 0,
-		VPKUWUM    = 0,
-		VPKUWUS    = 0,
-		VREFP      = 0,
-		VRFIM      = 0,
-		VRFIN      = 0,
-		VRFIP      = 0,
-		VRFIZ      = 0,
-		VRLB       = 0,
-		VRLH       = 0,
-		VRLW       = 0,
-		VRSQRTEFP  = 0,
-		VSEL       = 0,
-		VSL        = 0,
-		VSLB       = 0,
-		VSLDOI     = 0,
-		VSLH       = 0,
-		VSLO       = 0,
-		VSLW       = 0,
-		VSPLTB     = 0,
-		VSPLTH     = 0,
-		VSPLTISB   = 0,
-		VSPLTISH   = 0,
-		VSPLTISW   = 0,
-		VSPLTW     = 0,
-		VSR        = 0,
-		VSRAB      = 0,
-		VSRAH      = 0,
-		VSRAW      = 0,
-		VSRB       = 0,
-		VSRH       = 0,
-		VSRO       = 0,
-		VSRW       = 0,
-		VSUBCUW    = 0,
-		VSUBFP     = 0,
-		VSUBSBS    = 0,
-		VSUBSHS    = 0,
-		VSUBSWS    = 0,
-		VSUBUBM    = 0,
-		VSUBUBS    = 0,
-		VSUBUHM    = 0,
-		VSUBUHS    = 0,
-		VSUBUWM    = 0,
-		VSUBUWS    = 0,
-		VSUMSWS    = 0,
-		VSUM2SWS   = 0,
-		VSUM4SBS   = 0,
-		VSUM4SHS   = 0,
-		VSUM4UBS   = 0,
-		VUPKHPX    = 0,
-		VUPKHSB    = 0,
-		VUPKHSH    = 0,
-		VUPKLPX    = 0,
-		VUPKLSB    = 0,
-		VUPKLSH    = 0,
-		VXOR       = 0,
-		TDI        = read_ra,
-		TWI        = read_ra,
-		MULLI      = read_ra,
-		SUBFIC     = read_ra,
-		CMPLI      = read_ra,
-		CMPI       = read_ra,
-		ADDIC      = read_ra,
-		ADDI       = read_ra,
-		ADDIS      = read_ra,
-		BC         = 0,
-		SC         = 0,
-		B          = 0,
-		MCRF       = 0,
-		BCLR       = 0,
-		CRNOR      = 0,
-		CRANDC     = 0,
-		ISYNC      = 0,
-		CRXOR      = 0,
-		CRNAND     = 0,
-		CRAND      = 0,
-		CREQV      = 0,
-		CRORC      = 0,
-		CROR       = 0,
-		BCCTR      = 0,
-		RLWIMI     = read_ra | read_rs,
-		RLWINM     = read_rs,
-		RLWNM      = read_rs | read_rb,
-		ORI        = read_rs,
-		ORIS       = read_rs,
-		XORI       = read_rs,
-		XORIS      = read_rs,
-		ANDI       = read_rs,
-		ANDIS      = read_rs,
-		RLDICL     = read_rs,
-		RLDICR     = read_rs,
-		RLDIC      = read_rs,
-		RLDIMI     = read_ra | read_rs,
-		RLDCL      = read_rs | read_rb,
-		RLDCR      = read_rs | read_rb,
-		CMP        = read_ra | read_rb,
-		TW         = read_ra | read_rb,
-		LVSL       = read_ra | read_rb,
-		LVEBX      = read_ra | read_rb,
-		SUBFC      = read_ra | read_rb,
-		ADDC       = read_ra | read_rb,
-		MULHDU     = read_ra | read_rb,
-		MULHWU     = read_ra | read_rb,
-		MFOCRF     = 0,
-		LWARX      = read_ra | read_rb,
-		LDX        = read_ra | read_rb,
-		LWZX       = read_ra | read_rb,
-		SLW        = read_rs | read_rb,
-		CNTLZW     = read_rs,
-		SLD        = read_rs | read_rb,
-		AND        = read_rs | read_rb,
-		CMPL       = read_ra | read_rb,
-		LVSR       = read_ra | read_rb,
-		LVEHX      = read_ra | read_rb,
-		SUBF       = read_ra | read_rb,
-		LDUX       = read_ra | read_rb,
-		DCBST      = 0,
-		LWZUX      = read_ra | read_rb,
-		CNTLZD     = read_rs,
-		ANDC       = read_rs | read_rb,
-		TD         = read_ra | read_rb,
-		LVEWX      = read_ra | read_rb,
-		MULHD      = read_ra | read_rb,
-		MULHW      = read_ra | read_rb,
-		LDARX      = read_ra | read_rb,
-		DCBF       = 0,
-		LBZX       = read_ra | read_rb,
-		LVX        = read_ra | read_rb,
-		NEG        = read_ra,
-		LBZUX      = read_ra | read_rb,
-		NOR        = read_rs | read_rb,
-		STVEBX     = read_ra | read_rb,
-		SUBFE      = read_ra | read_rb,
-		ADDE       = read_ra | read_rb,
-		MTOCRF     = read_rs,
-		STDX       = read_rs | read_ra | read_rb,
-		STWCX      = read_rs | read_ra | read_rb,
-		STWX       = read_rs | read_ra | read_rb,
-		STVEHX     = read_ra | read_rb,
-		STDUX      = read_rs | read_ra | read_rb,
-		STWUX      = read_rs | read_ra | read_rb,
-		STVEWX     = read_ra | read_rb,
-		SUBFZE     = read_ra,
-		ADDZE      = read_ra,
-		STDCX      = read_rs | read_ra | read_rb,
-		STBX       = read_rs | read_ra | read_rb,
-		STVX       = read_ra | read_rb,
-		SUBFME     = read_ra,
-		MULLD      = read_ra | read_rb,
-		ADDME      = read_ra | read_rb,
-		MULLW      = read_ra | read_rb,
-		DCBTST     = 0,
-		STBUX      = read_rs | read_ra | read_rb,
-		ADD        = read_ra | read_rb,
-		DCBT       = 0,
-		LHZX       = read_ra | read_rb,
-		EQV        = read_rs | read_rb,
-		ECIWX      = read_ra | read_rb,
-		LHZUX      = read_ra | read_rb,
-		XOR        = read_rs | read_rb,
-		MFSPR      = 0,
-		LWAX       = read_ra | read_rb,
-		DST        = 0,
-		LHAX       = read_ra | read_rb,
-		LVXL       = LVX,
-		MFTB       = MFSPR,
-		LWAUX      = read_ra | read_rb,
-		DSTST      = 0,
-		LHAUX      = read_ra | read_rb,
-		STHX       = read_rs | read_ra | read_rb,
-		ORC        = read_rs | read_rb,
-		ECOWX      = read_rs | read_ra | read_rb,
-		STHUX      = read_rs | read_ra | read_rb,
-		OR         = read_rs | read_rb,
-		DIVDU      = read_ra | read_rb,
-		DIVWU      = read_ra | read_rb,
-		MTSPR      = read_rs,
-		DCBI       = 0,
-		NAND       = read_rs | read_rb,
-		STVXL      = STVX,
-		DIVD       = read_ra | read_rb,
-		DIVW       = read_ra | read_rb,
-		LVLX       = read_ra | read_rb,
-		LDBRX      = read_ra | read_rb,
-		LSWX       = read_ra | read_rb | rw_all,
-		LWBRX      = read_ra | read_rb,
-		LFSX       = read_ra | read_rb,
-		SRW        = read_rs | read_rb,
-		SRD        = read_rs | read_rb,
-		LVRX       = read_ra | read_rb,
-		LSWI       = rw_all,
-		LFSUX      = read_ra | read_rb,
-		SYNC       = 0,
-		LFDX       = read_ra | read_rb,
-		LFDUX      = read_ra | read_rb,
-		STVLX      = read_ra | read_rb,
-		STDBRX     = read_rs | read_ra | read_rb,
-		STSWX      = rw_all,
-		STWBRX     = read_rs | read_ra | read_rb,
-		STFSX      = read_ra | read_rb,
-		STVRX      = read_ra | read_rb,
-		STFSUX     = read_ra | read_rb,
-		STSWI      = rw_all,
-		STFDX      = read_ra | read_rb,
-		STFDUX     = read_ra | read_rb,
-		LVLXL      = LVLX,
-		LHBRX      = read_ra | read_rb,
-		SRAW       = read_rs | read_rb,
-		SRAD       = read_rs | read_rb,
-		LVRXL      = LVRX,
-		DSS        = 0,
-		SRAWI      = read_rs,
-		SRADI      = read_rs,
-		EIEIO      = 0,
-		STVLXL     = STVLX,
-		STHBRX     = read_rs | read_ra | read_rb,
-		EXTSH      = read_rs,
-		STVRXL     = STVRX,
-		EXTSB      = read_rs,
-		STFIWX     = read_ra | read_rb,
-		EXTSW      = read_rs,
-		ICBI       = 0,
-		DCBZ       = read_ra | read_rb,
-		LWZ        = read_ra,
-		LWZU       = read_ra,
-		LBZ        = read_ra,
-		LBZU       = read_ra,
-		STW        = read_rs | read_ra,
-		STWU       = read_rs | read_ra,
-		STB        = read_rs | read_ra,
-		STBU       = read_rs | read_ra,
-		LHZ        = read_ra,
-		LHZU       = read_ra,
-		LHA        = read_ra,
-		LHAU       = read_ra,
-		STH        = read_rs | read_ra,
-		STHU       = read_rs | read_ra,
-		LMW        = rw_all,
-		STMW       = rw_all,
-		LFS        = read_ra,
-		LFSU       = read_ra,
-		LFD        = read_ra,
-		LFDU       = read_ra,
-		STFS       = read_ra,
-		STFSU      = read_ra,
-		STFD       = read_ra,
-		STFDU      = read_ra,
-		LD         = read_ra,
-		LDU        = read_ra,
-		LWA        = read_ra,
-		STD        = read_rs | read_ra,
-		STDU       = read_rs | read_ra,
-		FDIVS      = 0,
-		FSUBS      = 0,
-		FADDS      = 0,
-		FSQRTS     = 0,
-		FRES       = 0,
-		FMULS      = 0,
-		FMADDS     = 0,
-		FMSUBS     = 0,
-		FNMSUBS    = 0,
-		FNMADDS    = 0,
-		MTFSB1     = 0,
-		MCRFS      = 0,
-		MTFSB0     = 0,
-		MTFSFI     = 0,
-		MFFS       = 0,
-		MTFSF      = 0,
-		FCMPU      = 0,
-		FRSP       = 0,
-		FCTIW      = 0,
-		FCTIWZ     = 0,
-		FDIV       = 0,
-		FSUB       = 0,
-		FADD       = 0,
-		FSQRT      = 0,
-		FSEL       = 0,
-		FMUL       = 0,
-		FRSQRTE    = 0,
-		FMSUB      = 0,
-		FMADD      = 0,
-		FNMSUB     = 0,
-		FNMADD     = 0,
-		FCMPO      = 0,
-		FNEG       = 0,
-		FMR        = 0,
-		FNABS      = 0,
-		FABS       = 0,
-		FCTID      = 0,
-		FCTIDZ     = 0,
-		FCFID      = 0,
-	};
-
-	// Enable address-of operator for ppu_decoder<>
-	friend constexpr flags operator &(flags value)
-	{
-		return value;
-	}
-};
-
 // Encode instruction name: 6 bits per character (0x20..0x5f), max 10
 static constexpr u64 ppu_iname_encode(const char* ptr, u64 value = 0)
 {
diff --git a/rpcs3/Emu/Cell/PPUInterpreter.cpp b/rpcs3/Emu/Cell/PPUInterpreter.cpp
index 6596b27ea6..6718af0f20 100644
--- a/rpcs3/Emu/Cell/PPUInterpreter.cpp
+++ b/rpcs3/Emu/Cell/PPUInterpreter.cpp
@@ -5,28 +5,7 @@
 
 #include <cmath>
 
-inline u64 dup32(const u32 x) { return x | static_cast<u64>(x) << 32; }
-
-#if defined(__GNUG__)
-inline u64 UMULH64(u64 a, u64 b)
-{
-	u64 result;
-	__asm__("mulq %[b]" : "=d" (result) : [a] "a" (a), [b] "rm" (b));
-	return result;
-}
-
-inline s64 MULH64(s64 a, s64 b)
-{
-	s64 result;
-	__asm__("imulq %[b]" : "=d" (result) : [a] "a" (a), [b] "rm" (b));
-	return result;
-}
-#endif
-
-#if defined(_MSC_VER)
-#define UMULH64 __umulh
-#define MULH64 __mulh
-#endif
+inline u64 dup32(u32 x) { return x | static_cast<u64>(x) << 32; }
 
 // Write values to CR field
 inline void ppu_cr_set(ppu_thread& ppu, u32 field, bool le, bool gt, bool eq, bool so)
@@ -3145,7 +3124,7 @@ bool ppu_interpreter::SUBFC(ppu_thread& ppu, ppu_opcode_t op)
 
 bool ppu_interpreter::MULHDU(ppu_thread& ppu, ppu_opcode_t op)
 {
-	ppu.gpr[op.rd] = UMULH64(ppu.gpr[op.ra], ppu.gpr[op.rb]);
+	ppu.gpr[op.rd] = umulh64(ppu.gpr[op.ra], ppu.gpr[op.rb]);
 	if (UNLIKELY(op.rc)) ppu_cr_set<s64>(ppu, 0, ppu.gpr[op.rd], 0);
 	return true;
 }
@@ -3343,7 +3322,7 @@ bool ppu_interpreter::LVEWX(ppu_thread& ppu, ppu_opcode_t op)
 
 bool ppu_interpreter::MULHD(ppu_thread& ppu, ppu_opcode_t op)
 {
-	ppu.gpr[op.rd] = MULH64(ppu.gpr[op.ra], ppu.gpr[op.rb]);
+	ppu.gpr[op.rd] = mulh64(ppu.gpr[op.ra], ppu.gpr[op.rb]);
 	if (UNLIKELY(op.rc)) ppu_cr_set<s64>(ppu, 0, ppu.gpr[op.rd], 0);
 	return true;
 }
@@ -3579,7 +3558,7 @@ bool ppu_interpreter::MULLD(ppu_thread& ppu, ppu_opcode_t op)
 	ppu.gpr[op.rd] = (s64)(RA * RB);
 	if (UNLIKELY(op.oe))
 	{
-		const s64 high = MULH64(RA, RB);
+		const s64 high = mulh64(RA, RB);
 		ppu_ov_set(ppu, high != s64(ppu.gpr[op.rd]) >> 63);
 	}
 	if (UNLIKELY(op.rc)) ppu_cr_set<s64>(ppu, 0, ppu.gpr[op.rd], 0);
diff --git a/rpcs3/Emu/Cell/PPUThread.cpp b/rpcs3/Emu/Cell/PPUThread.cpp
index 5e00eabfa8..116dd83211 100644
--- a/rpcs3/Emu/Cell/PPUThread.cpp
+++ b/rpcs3/Emu/Cell/PPUThread.cpp
@@ -1229,7 +1229,7 @@ static void ppu_initialize2(jit_compiler& jit, const ppu_module& module_part, co
 				return;
 			}
 
-			if (module_part.funcs[fi].size && !test(module_part.funcs[fi].attr & ppu_attr::special))
+			if (module_part.funcs[fi].size)
 			{
 				// Update dialog		
 				Emu.CallAfter([=, max = module_part.funcs.size()]()
diff --git a/rpcs3/Emu/Cell/PPUTranslator.cpp b/rpcs3/Emu/Cell/PPUTranslator.cpp
index 2b1f516b19..c646370333 100644
--- a/rpcs3/Emu/Cell/PPUTranslator.cpp
+++ b/rpcs3/Emu/Cell/PPUTranslator.cpp
@@ -11,59 +11,6 @@ using namespace llvm;
 
 const ppu_decoder<PPUTranslator> s_ppu_decoder;
 
-/* Interpreter Call Macro (unused) */
-
-#define VEC3OP(name) SetVr(op.vd, Call(GetType<u32[4]>(), "__vec3op",\
-	m_ir->getInt64((u64)&ppu_interpreter_fast::name),\
-	GetVr(op.va, VrType::vi32),\
-	GetVr(op.vb, VrType::vi32),\
-	GetVr(op.vc, VrType::vi32)))
-
-#define VEC2OP(name) SetVr(op.vd, Call(GetType<u32[4]>(), "__vec3op",\
-	m_ir->getInt64((u64)&ppu_interpreter_fast::name),\
-	GetVr(op.va, VrType::vi32),\
-	GetVr(op.vb, VrType::vi32),\
-	GetUndef<u32[4]>()))
-
-#define VECIOP(name) SetVr(op.vd, Call(GetType<u32[4]>(), "__veciop",\
-	m_ir->getInt64((u64)&ppu_interpreter_fast::name),\
-	m_ir->getInt32(op.opcode),\
-	GetVr(op.vb, VrType::vi32)))
-
-#define FPOP(name) SetFpr(op.frd, Call(GetType<f64>(), "__fpop",\
-	m_ir->getInt64((u64)&ppu_interpreter_fast::name),\
-	GetFpr(op.fra),\
-	GetFpr(op.frb),\
-	GetFpr(op.frc)))
-
-#define AIMMOP(name) SetGpr(op.ra, Call(GetType<u64>(), "__aimmop",\
-	m_ir->getInt64((u64)&ppu_interpreter_fast::name),\
-	m_ir->getInt32(op.opcode),\
-	GetGpr(op.rs)))
-
-#define AIMMBOP(name) SetGpr(op.ra, Call(GetType<u64>(), "__aimmbop",\
-	m_ir->getInt64((u64)&ppu_interpreter_fast::name),\
-	m_ir->getInt32(op.opcode),\
-	GetGpr(op.rs),\
-	GetGpr(op.rb)))
-
-#define AAIMMOP(name) SetGpr(op.ra, Call(GetType<u64>(), "__aaimmop",\
-	m_ir->getInt64((u64)&ppu_interpreter_fast::name),\
-	m_ir->getInt32(op.opcode),\
-	GetGpr(op.rs),\
-	GetGpr(op.ra)))
-
-#define IMMAOP(name) SetGpr(op.rd, Call(GetType<u64>(), "__immaop",\
-	m_ir->getInt64((u64)&ppu_interpreter_fast::name),\
-	m_ir->getInt32(op.opcode),\
-	GetGpr(op.ra)))
-
-#define IMMABOP(name) SetGpr(op.rd, Call(GetType<u64>(), "__immabop",\
-	m_ir->getInt64((u64)&ppu_interpreter_fast::name),\
-	m_ir->getInt32(op.opcode),\
-	GetGpr(op.ra),\
-	GetGpr(op.rb)))
-
 PPUTranslator::PPUTranslator(LLVMContext& context, Module* module, const ppu_module& info)
 	: m_context(context)
 	, m_module(module)