From f9f2657c984a5e8b2dfeb4e51c47d3727bb9fb13 Mon Sep 17 00:00:00 2001 From: Eladash Date: Fri, 1 Sep 2023 15:48:43 +0300 Subject: [PATCH] SPU LLVM: Optimize spu_idisable --- rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp | 6 ++++++ rpcs3/Emu/Cell/SPURecompiler.cpp | 13 +++++++++++++ 2 files changed, 19 insertions(+) diff --git a/rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp b/rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp index c76aba5d4f..1b64c00530 100644 --- a/rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp +++ b/rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp @@ -2607,6 +2607,12 @@ void spu_recompiler::BI(spu_opcode_t op) { spu_log.error("[0x%x] BI: no targets", m_pos); } + else if (op.d && found->second.size() == 1 && found->second[0] == spu_branch_target(m_pos, 1)) + { + // Interrupts-disable pattern + c->mov(SPU_OFF_8(interrupts_enabled), 0); + return; + } c->mov(*addr, SPU_OFF_32(gpr, op.ra, &v128::_u32, 3)); c->and_(*addr, 0x3fffc); diff --git a/rpcs3/Emu/Cell/SPURecompiler.cpp b/rpcs3/Emu/Cell/SPURecompiler.cpp index 55b5e3c8dc..b9f70ffe31 100644 --- a/rpcs3/Emu/Cell/SPURecompiler.cpp +++ b/rpcs3/Emu/Cell/SPURecompiler.cpp @@ -2382,6 +2382,12 @@ spu_program spu_recompiler_base::analyse(const be_t* ls, u32 entry_point) spu_log.warning("[0x%x] At 0x%x: indirect branch to 0x%x%s", entry_point, pos, target, op.d ? " (D)" : op.e ? " (E)" : ""); + if (type == spu_itype::BI && target == pos + 4 && op.d) + { + // Disable interrupts idiom + break; + } + m_targets[pos].push_back(target); if (g_cfg.core.spu_block_size == spu_block_size_type::giga) @@ -10870,6 +10876,13 @@ public: // Create jump table if necessary (TODO) const auto tfound = m_targets.find(m_pos); + if (op.d && tfound != m_targets.end() && tfound->second.size() == 1 && tfound->second[0] == spu_branch_target(m_pos, 1)) + { + // Interrupts-disable pattern + m_ir->CreateStore(m_ir->getFalse(), spu_ptr(&spu_thread::interrupts_enabled)); + return; + } + if (!op.d && !op.e && tfound != m_targets.end() && tfound->second.size() > 1) { // Shift aligned address for switch