mirror of https://github.com/RPCS3/rpcs3.git
SPU LLVM: Simplify register origin discovery
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f6a9ac73b4
commit
cfa553df86
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@ -2680,12 +2680,13 @@ reg_state_t reg_state_t::merge(const reg_state_t& rhs, u32 current_pc) const
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res.tag = reg_state_t::alloc_tag();
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res.origin = current_pc;
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res.is_instruction = false;
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res.is_phi = true;
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return res;
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}
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}
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}
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return make_unknown(current_pc);
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return make_unknown(current_pc, current_pc, true);
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}
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reg_state_t reg_state_t::build_on_top_of(const reg_state_t& rhs) const
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@ -4190,23 +4191,6 @@ spu_program spu_recompiler_base::analyse(const be_t<u32>* ls, u32 entry_point, s
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for (u32 i = 0; i < s_reg_max; i++)
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{
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if (tb.chunk == block.chunk && tb.reg_origin[i] + 1)
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{
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const u32 expected = block.reg_mod[i] ? addr : block.reg_origin[i];
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if (tb.reg_origin[i] == 0x80000000)
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{
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tb.reg_origin[i] = expected;
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}
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else if (tb.reg_origin[i] != expected)
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{
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// Set -1 if multiple origins merged (requires PHI node)
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tb.reg_origin[i] = -1;
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must_repeat |= !tb.targets.empty();
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}
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}
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if (g_cfg.core.spu_block_size == spu_block_size_type::giga && tb.func == block.func && tb.reg_origin_abs[i] + 2)
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{
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const u32 expected = block.reg_mod[i] ? addr : block.reg_origin_abs[i];
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@ -5793,7 +5777,7 @@ spu_program spu_recompiler_base::analyse(const be_t<u32>* ls, u32 entry_point, s
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}
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case MFC_Cmd:
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{
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const auto [af, av, atagg, _3, _5, apc, ainst] = get_reg(op.rt);
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const auto [af, av, atagg, _3, _5, apc, ainst, aphi] = get_reg(op.rt);
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if (!is_pattern_match)
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{
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@ -6591,7 +6575,7 @@ spu_program spu_recompiler_base::analyse(const be_t<u32>* ls, u32 entry_point, s
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case spu_itype::HBR:
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{
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hbr_loc = spu_branch_target(pos, op.roh << 7 | op.rt);
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const auto [af, av, at, ao, az, apc, ainst] = get_reg(op.ra);
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const auto [af, av, at, ao, az, apc, ainst, aphi] = get_reg(op.ra);
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hbr_tg = af & vf::is_const && !op.c ? av & 0x3fffc : -1;
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break;
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}
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@ -6659,8 +6643,8 @@ spu_program spu_recompiler_base::analyse(const be_t<u32>* ls, u32 entry_point, s
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const auto ra = get_reg(op.ra);
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const auto rb = get_reg(op.rb);
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const auto [af, av, at, ao, az, apc, ainst] = ra;
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const auto [bf, bv, bt, bo, bz, bpc, binst] = rb;
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const auto [af, av, at, ao, az, apc, ainst, aphi] = ra;
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const auto [bf, bv, bt, bo, bz, bpc, binst, bphi] = rb;
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inherit_const_value(op.rt, ra, rb, av | bv, pos);
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break;
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@ -6675,7 +6659,7 @@ spu_program spu_recompiler_base::analyse(const be_t<u32>* ls, u32 entry_point, s
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const auto ra = get_reg(op.ra);
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const auto [af, av, at, ao, az, apc, ainst] = ra;
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const auto [af, av, at, ao, az, apc, ainst, aphi] = ra;
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inherit_const_value(op.rt, ra, ra, av ^ op.si10, pos);
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break;
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@ -6691,8 +6675,8 @@ spu_program spu_recompiler_base::analyse(const be_t<u32>* ls, u32 entry_point, s
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const auto ra = get_reg(op.ra);
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const auto rb = get_reg(op.rb);
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const auto [af, av, at, ao, az, apc, ainst] = ra;
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const auto [bf, bv, bt, bo, bz, bpc, binst] = rb;
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const auto [af, av, at, ao, az, apc, ainst, aphi] = ra;
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const auto [bf, bv, bt, bo, bz, bpc, binst, bphi] = rb;
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inherit_const_value(op.rt, ra, rb, bv ^ av, pos);
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break;
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@ -6702,8 +6686,8 @@ spu_program spu_recompiler_base::analyse(const be_t<u32>* ls, u32 entry_point, s
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const auto ra = get_reg(op.ra);
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const auto rb = get_reg(op.rb);
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const auto [af, av, at, ao, az, apc, ainst] = ra;
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const auto [bf, bv, bt, bo, bz, bpc, binst] = rb;
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const auto [af, av, at, ao, az, apc, ainst, aphi] = ra;
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const auto [bf, bv, bt, bo, bz, bpc, binst, bphi] = rb;
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inherit_const_value(op.rt, ra, rb, ~(bv | av), pos);
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break;
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@ -6725,8 +6709,8 @@ spu_program spu_recompiler_base::analyse(const be_t<u32>* ls, u32 entry_point, s
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const auto ra = get_reg(op.ra);
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const auto rb = get_reg(op.rb);
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const auto [af, av, at, ao, az, apc, ainst] = ra;
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const auto [bf, bv, bt, bo, bz, bpc, binst] = rb;
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const auto [af, av, at, ao, az, apc, ainst, aphi] = ra;
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const auto [bf, bv, bt, bo, bz, bpc, binst, bphi] = rb;
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inherit_const_value(op.rt, ra, rb, bv & av, pos);
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break;
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@ -6740,7 +6724,7 @@ spu_program spu_recompiler_base::analyse(const be_t<u32>* ls, u32 entry_point, s
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}
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const auto ra = get_reg(op.ra);
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const auto [af, av, at, ao, az, apc, ainst] = ra;
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const auto [af, av, at, ao, az, apc, ainst, aphi] = ra;
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inherit_const_value(op.rt, ra, ra, av + op.si10, pos);
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@ -6757,8 +6741,8 @@ spu_program spu_recompiler_base::analyse(const be_t<u32>* ls, u32 entry_point, s
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const auto ra = get_reg(op.ra);
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const auto rb = get_reg(op.rb);
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const auto [af, av, at, ao, az, apc, ainst] = ra;
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const auto [bf, bv, bt, bo, bz, bpc, binst] = rb;
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const auto [af, av, at, ao, az, apc, ainst, aphi] = ra;
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const auto [bf, bv, bt, bo, bz, bpc, binst, bphi] = rb;
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inherit_const_value(op.rt, ra, rb, bv + av, pos);
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@ -6773,7 +6757,7 @@ spu_program spu_recompiler_base::analyse(const be_t<u32>* ls, u32 entry_point, s
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case spu_itype::SFI:
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{
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const auto ra = get_reg(op.ra);
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const auto [af, av, at, ao, az, apc, ainst] = get_reg(op.ra);
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const auto [af, av, at, ao, az, apc, ainst, aphi] = get_reg(op.ra);
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inherit_const_value(op.rt, ra, ra, op.si10 - av, pos);
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break;
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@ -6783,8 +6767,8 @@ spu_program spu_recompiler_base::analyse(const be_t<u32>* ls, u32 entry_point, s
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const auto ra = get_reg(op.ra);
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const auto rb = get_reg(op.rb);
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const auto [af, av, at, ao, az, apc, ainst] = ra;
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const auto [bf, bv, bt, bo, bz, bpc, binst] = rb;
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const auto [af, av, at, ao, az, apc, ainst, aphi] = ra;
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const auto [bf, bv, bt, bo, bz, bpc, binst, bphi] = rb;
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inherit_const_value(op.rt, ra, rb, bv - av, pos);
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@ -6823,7 +6807,7 @@ spu_program spu_recompiler_base::analyse(const be_t<u32>* ls, u32 entry_point, s
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}
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const auto ra = get_reg(op.ra);
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const auto [af, av, at, ao, az, apc, ainst] = get_reg(op.ra);
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const auto [af, av, at, ao, az, apc, ainst, aphi] = get_reg(op.ra);
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inherit_const_value(op.rt, ra, ra, av >> ((0 - op.i7) & 0x1f), pos);
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break;
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@ -6843,7 +6827,7 @@ spu_program spu_recompiler_base::analyse(const be_t<u32>* ls, u32 entry_point, s
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}
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const auto ra = get_reg(op.ra);
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const auto [af, av, at, ao, az, apc, ainst] = ra;
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const auto [af, av, at, ao, az, apc, ainst, aphi] = ra;
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inherit_const_value(op.rt, ra, ra, av << (op.i7 & 0x1f), pos);
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break;
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@ -6860,7 +6844,7 @@ spu_program spu_recompiler_base::analyse(const be_t<u32>* ls, u32 entry_point, s
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case spu_itype::CEQI:
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{
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const auto ra = get_reg(op.ra);
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const auto [af, av, at, ao, az, apc, ainst] = ra;
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const auto [af, av, at, ao, az, apc, ainst, aphi] = ra;
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inherit_const_value(op.rt, ra, ra, av == op.si10 + 0u, pos);
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@ -6996,6 +6980,14 @@ spu_program spu_recompiler_base::analyse(const be_t<u32>* ls, u32 entry_point, s
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bb.reg_const[i] = true;
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bb.reg_val32[i] = reg.value;
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}
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else if (reg.is_instruction)
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{
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bb.reg_origin[i] = reg.origin;
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}
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else if (reg.is_phi)
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{
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bb.reg_origin[i] = -1;
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}
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}
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}
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@ -210,6 +210,7 @@ public:
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u32 known_zeroes{};
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u32 origin = SPU_LS_SIZE;
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bool is_instruction = false;
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bool is_phi = false;
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bool is_const() const;
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@ -243,7 +244,7 @@ public:
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void invalidate_if_created(u32 current_pc);
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template <usz Count = 1>
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static std::conditional_t<Count == 1, reg_state_t, std::array<reg_state_t, Count>> make_unknown(u32 pc, u32 current_pc = SPU_LS_SIZE) noexcept
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static std::conditional_t<Count == 1, reg_state_t, std::array<reg_state_t, Count>> make_unknown(u32 pc, u32 current_pc = SPU_LS_SIZE, bool is_phi = false) noexcept
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{
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if constexpr (Count == 1)
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{
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@ -252,6 +253,7 @@ public:
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v.flag = {};
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v.origin = pc;
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v.is_instruction = pc == current_pc;
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v.is_phi = is_phi;
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return v;
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}
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else
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@ -260,7 +262,7 @@ public:
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for (reg_state_t& state : result)
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{
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state = make_unknown<1>(pc, current_pc);
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state = make_unknown<1>(pc, current_pc, is_phi);
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}
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return result;
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