diff --git a/rpcs3/Emu/Cell/PPUInterpreter2.h b/rpcs3/Emu/Cell/PPUInterpreter2.h
index d5bb82a77a..9ad6989714 100644
--- a/rpcs3/Emu/Cell/PPUInterpreter2.h
+++ b/rpcs3/Emu/Cell/PPUInterpreter2.h
@@ -9,7 +9,7 @@ union ppu_opcode_t
 
 	struct
 	{
-		u32 rc    : 1; // 31
+		u32       : 1; // 31
 		u32 shh   : 1; // 30
 		u32       : 3; // 27..29
 		u32 mbmeh : 1; // 26
diff --git a/rpcs3/Emu/Cell/SPUInterpreter.cpp b/rpcs3/Emu/Cell/SPUInterpreter.cpp
index 618a06fda0..282df3963d 100644
--- a/rpcs3/Emu/Cell/SPUInterpreter.cpp
+++ b/rpcs3/Emu/Cell/SPUInterpreter.cpp
@@ -16,37 +16,36 @@ void spu_interpreter::DEFAULT(SPUThread& CPU, spu_opcode_t op)
 
 void spu_interpreter::STOP(SPUThread& CPU, spu_opcode_t op)
 {
-	DEFAULT(CPU, op);
+	CPU.stop_and_signal(op.opcode & 0x3fff);
 }
 
 void spu_interpreter::LNOP(SPUThread& CPU, spu_opcode_t op)
 {
-	DEFAULT(CPU, op);
 }
 
 void spu_interpreter::SYNC(SPUThread& CPU, spu_opcode_t op)
 {
-	DEFAULT(CPU, op);
+	_mm_mfence();
 }
 
 void spu_interpreter::DSYNC(SPUThread& CPU, spu_opcode_t op)
 {
-	DEFAULT(CPU, op);
+	_mm_mfence();
 }
 
 void spu_interpreter::MFSPR(SPUThread& CPU, spu_opcode_t op)
 {
-	DEFAULT(CPU, op);
+	CPU.GPR[op.rt].clear();
 }
 
 void spu_interpreter::RDCH(SPUThread& CPU, spu_opcode_t op)
 {
-	DEFAULT(CPU, op);
+	CPU.GPR[op.rt] = u128::from32r(CPU.get_ch_value(op.ra));
 }
 
 void spu_interpreter::RCHCNT(SPUThread& CPU, spu_opcode_t op)
 {
-	DEFAULT(CPU, op);
+	CPU.GPR[op.rt] = u128::from32r(CPU.get_ch_count(op.ra));
 }
 
 void spu_interpreter::SF(SPUThread& CPU, spu_opcode_t op)
@@ -191,12 +190,11 @@ void spu_interpreter::AVGB(SPUThread& CPU, spu_opcode_t op)
 
 void spu_interpreter::MTSPR(SPUThread& CPU, spu_opcode_t op)
 {
-	DEFAULT(CPU, op);
 }
 
 void spu_interpreter::WRCH(SPUThread& CPU, spu_opcode_t op)
 {
-	DEFAULT(CPU, op);
+	CPU.set_ch_value(op.ra, CPU.GPR[op.rt]._u32[3]);
 }
 
 void spu_interpreter::BIZ(SPUThread& CPU, spu_opcode_t op)
@@ -1019,4 +1017,3 @@ void spu_interpreter::UNK(SPUThread& CPU, spu_opcode_t op)
 {
 	DEFAULT(CPU, op);
 }
-
diff --git a/rpcs3/Emu/Cell/SPUInterpreter2.h b/rpcs3/Emu/Cell/SPUInterpreter2.h
index 48daf67b8e..68dcb860e2 100644
--- a/rpcs3/Emu/Cell/SPUInterpreter2.h
+++ b/rpcs3/Emu/Cell/SPUInterpreter2.h
@@ -6,7 +6,73 @@ union spu_opcode_t
 {
 	u32 opcode;
 
+	struct
+	{
+		u32 rt : 7; // 25..31
+		u32 ra : 7; // 18..24
+		u32 rb : 7; // 11..17
+		u32 rc : 7; // 4..10
+	};
 
+	struct
+	{
+		u32    : 14; // 18..31
+		u32 i7 : 7;  // 11..17
+	};
+
+	struct
+	{
+		u32    : 14; // 18..31
+		u32 i8 : 8;  // 10..17
+	};
+
+	struct
+	{
+		u32     : 14; // 18..31
+		u32 i10 : 10; // 8..17
+	};
+
+	struct
+	{
+		u32     : 7; // 25..31
+		u32 i16 : 16; // 9..24
+	};
+
+	struct
+	{
+		u32     : 7; // 25..31
+		u32 i18 : 18; // 7..24
+	};
+
+	struct
+	{
+		s32     : 14; // 18..31
+		s32 si7 : 7;  // 11..17
+	};
+
+	struct
+	{
+		s32     : 14; // 18..31
+		s32 si8 : 8;  // 10..17
+	};
+
+	struct
+	{
+		s32      : 14; // 18..31
+		s32 si10 : 10; // 8..17
+	};
+
+	struct
+	{
+		s32      : 7; // 25..31
+		s32 si16 : 16; // 9..24
+	};
+
+	struct
+	{
+		s32      : 7; // 25..31
+		s32 si18 : 18; // 7..24
+	};
 };
 
 using spu_inter_func_t = void(*)(SPUThread& CPU, spu_opcode_t opcode);