diff --git a/rpcs3/Emu/Cell/SPUInterpreter.h b/rpcs3/Emu/Cell/SPUInterpreter.h
index d903353991..7f88e6e3ec 100644
--- a/rpcs3/Emu/Cell/SPUInterpreter.h
+++ b/rpcs3/Emu/Cell/SPUInterpreter.h
@@ -251,10 +251,12 @@ private:
 	}
 	void BIZ(u32 intr, u32 rt, u32 ra)
 	{
-		if (intr)
+		switch (intr)
 		{
-			UNIMPLEMENTED();
-			return;
+		case 0: break;
+		case 0x10: break; // enable interrupts
+		case 0x20: break; // disable interrupts
+		default: UNIMPLEMENTED(); return;
 		}
 
 		u32 target = branchTarget(CPU.GPR[ra]._u32[3], 0);
@@ -270,10 +272,12 @@ private:
 	}
 	void BINZ(u32 intr, u32 rt, u32 ra)
 	{
-		if (intr)
+		switch (intr)
 		{
-			UNIMPLEMENTED();
-			return;
+		case 0: break;
+		case 0x10: break; // enable interrupts
+		case 0x20: break; // disable interrupts
+		default: UNIMPLEMENTED(); return;
 		}
 
 		u32 target = branchTarget(CPU.GPR[ra]._u32[3], 0);
@@ -289,10 +293,12 @@ private:
 	}
 	void BIHZ(u32 intr, u32 rt, u32 ra)
 	{
-		if (intr)
+		switch (intr)
 		{
-			UNIMPLEMENTED();
-			return;
+		case 0: break;
+		case 0x10: break; // enable interrupts
+		case 0x20: break; // disable interrupts
+		default: UNIMPLEMENTED(); return;
 		}
 
 		u32 target = branchTarget(CPU.GPR[ra]._u32[3], 0);
@@ -308,10 +314,12 @@ private:
 	}
 	void BIHNZ(u32 intr, u32 rt, u32 ra)
 	{
-		if (intr)
+		switch (intr)
 		{
-			UNIMPLEMENTED();
-			return;
+		case 0: break;
+		case 0x10: break; // enable interrupts
+		case 0x20: break; // disable interrupts
+		default: UNIMPLEMENTED(); return;
 		}
 
 		u32 target = branchTarget(CPU.GPR[ra]._u32[3], 0);
@@ -337,10 +345,12 @@ private:
 	}
 	void BI(u32 intr, u32 ra)
 	{
-		if (intr)
+		switch (intr)
 		{
-			UNIMPLEMENTED();
-			return;
+		case 0: break;
+		case 0x10: break; // enable interrupts
+		case 0x20: break; // disable interrupts
+		default: UNIMPLEMENTED(); return;
 		}
 
 		u32 target = branchTarget(CPU.GPR[ra]._u32[3], 0);
@@ -349,10 +359,12 @@ private:
 	}
 	void BISL(u32 intr, u32 rt, u32 ra)
 	{
-		if (intr)
+		switch (intr)
 		{
-			UNIMPLEMENTED();
-			return;
+		case 0: break;
+		case 0x10: break; // enable interrupts
+		case 0x20: break; // disable interrupts
+		default: UNIMPLEMENTED(); return;
 		}
 
 		u32 target = branchTarget(CPU.GPR[ra]._u32[3], 0);
diff --git a/rpcs3/Emu/Cell/SPURecompiler.h b/rpcs3/Emu/Cell/SPURecompiler.h
index 12930680a9..82c2c287f6 100644
--- a/rpcs3/Emu/Cell/SPURecompiler.h
+++ b/rpcs3/Emu/Cell/SPURecompiler.h
@@ -1074,10 +1074,12 @@ private:
 	}
 	void BIZ(u32 intr, u32 rt, u32 ra)
 	{
-		if (intr)
+		switch (intr)
 		{
-			UNIMPLEMENTED();
-			return;
+		case 0: break;
+		case 0x10: break; // enable interrupts
+		case 0x20: break; // disable interrupts
+		default: UNIMPLEMENTED(); return;
 		}
 
 		c.mov(cpu_dword(PC), CPU.PC);
@@ -1093,10 +1095,12 @@ private:
 	}
 	void BINZ(u32 intr, u32 rt, u32 ra)
 	{
-		if (intr)
+		switch (intr)
 		{
-			UNIMPLEMENTED();
-			return;
+		case 0: break;
+		case 0x10: break; // enable interrupts
+		case 0x20: break; // disable interrupts
+		default: UNIMPLEMENTED(); return;
 		}
 
 		c.mov(cpu_dword(PC), CPU.PC);
@@ -1112,10 +1116,12 @@ private:
 	}
 	void BIHZ(u32 intr, u32 rt, u32 ra)
 	{
-		if (intr)
+		switch (intr)
 		{
-			UNIMPLEMENTED();
-			return;
+		case 0: break;
+		case 0x10: break; // enable interrupts
+		case 0x20: break; // disable interrupts
+		default: UNIMPLEMENTED(); return;
 		}
 
 		c.mov(cpu_dword(PC), CPU.PC);
@@ -1131,10 +1137,12 @@ private:
 	}
 	void BIHNZ(u32 intr, u32 rt, u32 ra)
 	{
-		if (intr)
+		switch (intr)
 		{
-			UNIMPLEMENTED();
-			return;
+		case 0: break;
+		case 0x10: break; // enable interrupts
+		case 0x20: break; // disable interrupts
+		default: UNIMPLEMENTED(); return;
 		}
 
 		c.mov(cpu_dword(PC), CPU.PC);
@@ -1181,10 +1189,12 @@ private:
 	}
 	void BI(u32 intr, u32 ra)
 	{
-		if (intr)
+		switch (intr)
 		{
-			UNIMPLEMENTED();
-			return;
+		case 0: break;
+		case 0x10: break; // enable interrupts
+		case 0x20: break; // disable interrupts
+		default: UNIMPLEMENTED(); return;
 		}
 
 		c.mov(cpu_dword(PC), CPU.PC);
@@ -1197,10 +1207,12 @@ private:
 	}
 	void BISL(u32 intr, u32 rt, u32 ra)
 	{
-		if (intr)
+		switch (intr)
 		{
-			UNIMPLEMENTED();
-			return;
+		case 0: break;
+		case 0x10: break; // enable interrupts
+		case 0x20: break; // disable interrupts
+		default: UNIMPLEMENTED(); return;
 		}
 
 		XmmInvalidate(rt);
diff --git a/rpcs3/Emu/SysCalls/Modules/cellGcmSys.cpp b/rpcs3/Emu/SysCalls/Modules/cellGcmSys.cpp
index ce69c39c23..cafe9b7442 100644
--- a/rpcs3/Emu/SysCalls/Modules/cellGcmSys.cpp
+++ b/rpcs3/Emu/SysCalls/Modules/cellGcmSys.cpp
@@ -933,8 +933,8 @@ s32 cellGcmMapMainMemory(u32 ea, u32 size, vm::ptr<be_t<u32>> offset)
 		//fill the offset table
 		for (u32 i = 0; i<(size >> 20); i++)
 		{
-			offsetTable.ioAddress[(ea >> 20) + i] = (u16)(io >> 20) + i;
-			offsetTable.eaAddress[(io >> 20) + i] = (u16)(ea >> 20) + i;
+			offsetTable.ioAddress[(ea >> 20) + i] = (u16)((io >> 20) + i);
+			offsetTable.eaAddress[(io >> 20) + i] = (u16)((ea >> 20) + i);
 			Emu.GetGSManager().GetRender().m_strict_ordering[(io >> 20) + i] = false;
 		}