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SPU DisAsm: Print SPU floats

This commit is contained in:
Eladash 2021-10-29 16:46:34 +03:00 committed by Megamouse
parent aff7d8a994
commit a90376a7c4
3 changed files with 26 additions and 4 deletions
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22
rpcs3/Emu/Cell/PPUDisAsm.cpp
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@ -6,6 +6,8 @@
#include "util/asm.hpp" #include "util/asm.hpp"
#include <cmath>
const ppu_decoder<PPUDisAsm> s_ppu_disasm; const ppu_decoder<PPUDisAsm> s_ppu_disasm;
const ppu_decoder<ppu_itype> s_ppu_itype; const ppu_decoder<ppu_itype> s_ppu_itype;
@ -324,7 +326,7 @@ std::pair<PPUDisAsm::const_op, u64> PPUDisAsm::try_get_const_op_gpr_value(u32 re
enum CellError : u32; enum CellError : u32;
void comment_constant(std::string& last_opcode, u64 value) void comment_constant(std::string& last_opcode, u64 value, bool print_float = false)
{ {
// Test if potentially a CELL error // Test if potentially a CELL error
if ((value >> 28) == 0xf'ffff'fff8u || (value >> 28) == 0x8u) if ((value >> 28) == 0xf'ffff'fff8u || (value >> 28) == 0x8u)
@ -332,7 +334,7 @@ void comment_constant(std::string& last_opcode, u64 value)
const usz old_size = last_opcode.size(); const usz old_size = last_opcode.size();
// Comment as CELL error // Comment as CELL error
fmt::append(last_opcode, " #%s (0x%x)", CellError{static_cast<u32>(value)}, value); fmt::append(last_opcode, " #%s (0x%xh)", CellError{static_cast<u32>(value)}, value);
// Test if failed to format (appended " #0x8".. in such case) // Test if failed to format (appended " #0x8".. in such case)
if (last_opcode[old_size + 2] != '0') if (last_opcode[old_size + 2] != '0')
@ -346,7 +348,21 @@ void comment_constant(std::string& last_opcode, u64 value)
} }
// Comment constant formation // Comment constant formation
fmt::append(last_opcode, " #0x%x", value); fmt::append(last_opcode, " #0x%xh", value);
if (print_float && ((value >> 31) <= 1u || (value >> 31) == 0x1'ffff'ffffu))
{
const f32 float_val = std::bit_cast<f32>(static_cast<u32>(value));
if (std::isfinite(float_val))
{
fmt::append(last_opcode, " (%.6gf)", float_val);
}
else
{
fmt::append(last_opcode, " (%g)", float_val);
}
}
} }
constexpr std::pair<const char*, char> get_BC_info(u32 bo, u32 bi) constexpr std::pair<const char*, char> get_BC_info(u32 bo, u32 bi)

4
rpcs3/Emu/Cell/SPUDisAsm.cpp
View File

@ -121,6 +121,10 @@ std::pair<bool, v128> SPUDisAsm::try_get_const_value(u32 reg, u32 pc, u32 TTL) c
{ {
return { true, v128::from32p(op0.i16 << 16) }; return { true, v128::from32p(op0.i16 << 16) };
} }
case spu_itype::ILH:
{
return { true, v128::from16p(op0.i16) };
}
case spu_itype::CBD: case spu_itype::CBD:
case spu_itype::CHD: case spu_itype::CHD:
case spu_itype::CWD: case spu_itype::CWD:

4
rpcs3/Emu/Cell/SPUDisAsm.h
View File

@ -74,7 +74,7 @@ namespace utils
class shm; class shm;
} }
void comment_constant(std::string& last_opocde, u64 value); void comment_constant(std::string& last_opocde, u64 value, bool print_float = true);
class SPUDisAsm final : public PPCDisAsm class SPUDisAsm final : public PPCDisAsm
{ {
@ -872,10 +872,12 @@ public:
void ILHU(spu_opcode_t op) void ILHU(spu_opcode_t op)
{ {
DisAsm("ilhu", spu_reg_name[op.rt], op.i16); DisAsm("ilhu", spu_reg_name[op.rt], op.i16);
comment_constant(last_opcode, op.i16 << 16);
} }
void ILH(spu_opcode_t op) void ILH(spu_opcode_t op)
{ {
DisAsm("ilh", spu_reg_name[op.rt], op.i16); DisAsm("ilh", spu_reg_name[op.rt], op.i16);
comment_constant(last_opcode, (op.i16 << 16) | op.i16);
} }
void IOHL(spu_opcode_t op); void IOHL(spu_opcode_t op);