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Bugfix

This commit is contained in:
Nekotekina 2014-10-08 16:29:29 +04:00
parent fd7da9d61a
commit 9a02add930
3 changed files with 30 additions and 44 deletions
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3
rpcs3/Emu/CPU/CPUThread.cpp
View File

@ -338,8 +338,7 @@ void CPUThread::Task()
} }
Step(); Step();
//if (PC - 0x13ED4 < 0x288) trace.push_back(PC); //if (m_trace_enabled) trace.push_back(PC);
if (m_trace_enabled) trace.push_back(PC);
NextPc(m_dec->DecodeMemory(PC + m_offset)); NextPc(m_dec->DecodeMemory(PC + m_offset));
if (status == CPUThread_Step) if (status == CPUThread_Step)

2
rpcs3/Emu/Cell/SPUThread.cpp
View File

@ -1161,7 +1161,7 @@ void SPUThread::StopAndSignal(u32 code)
{ {
LOG_ERROR(Log::SPU, "Unknown STOP code: 0x%x (message=0x%x)", code, SPU.Out_MBox.GetValue()); LOG_ERROR(Log::SPU, "Unknown STOP code: 0x%x (message=0x%x)", code, SPU.Out_MBox.GetValue());
} }
Stop(); Emu.Pause();
break; break;
} }
} }

69
rpcs3/Emu/SysCalls/Modules/cellSpurs.cpp
View File

@ -170,9 +170,17 @@ s64 spursInit(
SPU.GPR[4]._u64[1] = spurs.addr(); SPU.GPR[4]._u64[1] = spurs.addr();
return SPU.FastCall(SPU.PC); return SPU.FastCall(SPU.PC);
#endif #endif
SPU.WriteLS32(SPU.ReadLS32(0x1e0), 2); // hack for cellSpursModuleExit // code replacement:
{
const u32 addr = /*SPU.ReadLS32(0x1e0) +*/ 8; //SPU.ReadLS32(0x1e4);
SPU.WriteLS32(addr + 0, 3); // hack for cellSpursModulePollStatus
SPU.WriteLS32(addr + 4, 0x35000000); // bi $0
SPU.WriteLS32(0x1e4, addr);
/*if (!isSecond)*/ SPU.m_code3_func = [spurs, num](SPUThread& SPU) -> u64 // first variant SPU.WriteLS32(SPU.ReadLS32(0x1e0), 2); // hack for cellSpursModuleExit
}
/*if (!isSecond)*/ SPU.m_code3_func = [spurs, num](SPUThread& SPU) -> u64 // first kernel
{ {
LV2_LOCK(0); LV2_LOCK(0);
@ -194,7 +202,7 @@ s64 spursInit(
if (spurs->m.x72.read_relaxed() & (1 << num)) if (spurs->m.x72.read_relaxed() & (1 << num))
{ {
SPU.WriteLS8(0x1eb, 0); // var4 SPU.WriteLS8(0x1eb, 0); // var4
if (arg1 && var1 != 0x20) if (arg1 == 0 || var1 == 0x20)
{ {
spurs->m.x72._and_not(1 << num); spurs->m.x72._and_not(1 << num);
} }
@ -219,7 +227,6 @@ s64 spursInit(
u128::leu8(wklMaxCnt, vAABB) | u128::leu8(wklMaxCnt, vAABB) |
u128::eq8(savedC, {}) | u128::eq8(savedC, {}) |
u128::fromV(g_imm_table.fsmb_table[(~var5) >> 16]); u128::fromV(g_imm_table.fsmb_table[(~var5) >> 16]);
cellSpurs->Notice("vCC = %s", vCC.to_hex().c_str());
u128 vCCH1 = u128::andnot(vCC, u128 vCCH1 = u128::andnot(vCC,
u128::from8p(0x80) & (vFMS1 | u128::gtu8(wklReadyCount0, vAABB)) | u128::from8p(0x80) & (vFMS1 | u128::gtu8(wklReadyCount0, vAABB)) |
u128::from8p(0x7f) & savedC); u128::from8p(0x7f) & savedC);
@ -283,18 +290,17 @@ s64 spursInit(
return vRES; return vRES;
}; };
//else SPU.m_code3_func = [spurs, num](SPUThread& SPU) -> u64 // second variant //else SPU.m_code3_func = [spurs, num](SPUThread& SPU) -> u64 // second kernel (TODO)
//{ //{
// //
//}; //};
SPU.m_code3_func = nullptr; //SPU.m_code3_func = [spurs, num](SPUThread& SPU) -> u64 // test
//{
if (SPU.m_code3_func) // LV2_LOCK(0);
{ // SPU.FastCall(0x290);
const u32 addr = SPU.ReadLS32(0x1e4); // u64 vRES = SPU.GPR[3]._u64[1];
SPU.WriteLS32(addr + 0, 3); // hack for cellSpursModulePollStatus // return vRES;
SPU.WriteLS32(addr + 4, 0x35000000); // bi $0 //};
}
SPU.WriteLS128(0x1c0, u128::from32r(0, spurs.addr(), num, 0x1f)); SPU.WriteLS128(0x1c0, u128::from32r(0, spurs.addr(), num, 0x1f));
@ -322,22 +328,11 @@ s64 spursInit(
if (!isSecond) SPU.WriteLS16(0x1e8, 0); if (!isSecond) SPU.WriteLS16(0x1e8, 0);
// run workload: // run workload:
if (wid <= 0x20) SPU.GPR[1]._u32[3] = 0x3FFB0;
{ SPU.GPR[3]._u32[3] = 0x100;
SPU.GPR[1]._u32[3] = 0x3FFB0; SPU.GPR[4]._u64[1] = wkl.data;
SPU.GPR[3]._u32[3] = 0x100; SPU.GPR[5]._u32[3] = stat;
SPU.GPR[4]._u64[1] = wkl.data; SPU.FastCall(0xa00);
SPU.GPR[5]._u32[3] = stat;
cellSpurs->Notice("In: [0x1e0] = %s", SPU.ReadLS128(0x1e0).to_hex().c_str());
//SPU.m_trace_enabled = (num == 0 && wid == 0x20);
SPU.FastCall(0xa00);
SPU.m_trace_enabled = false;
}
else
{
// hack
std::this_thread::sleep_for(std::chrono::milliseconds(1));
}
// check status: // check status:
auto status = SPU.SPU.Status.GetValue(); auto status = SPU.SPU.Status.GetValue();
@ -352,18 +347,10 @@ s64 spursInit(
// get workload id: // get workload id:
SPU.GPR[3].clear(); SPU.GPR[3].clear();
if (SPU.m_code3_func) assert(SPU.m_code3_func);
{ u64 res = SPU.m_code3_func(SPU);
u64 res = SPU.m_code3_func(SPU); stat = (u32)(res);
stat = (u32)(res); wid = (u32)(res >> 32);
wid = (u32)(res >> 32);
}
else
{
SPU.FastCall(0x290);
stat = SPU.GPR[3]._u32[2];
wid = SPU.GPR[3]._u32[3];
}
} }
})->GetId(); })->GetId();