diff --git a/rpcs3/Emu/Cell/PPCDecoder.h b/rpcs3/Emu/Cell/PPCDecoder.h index f315da01b3..053a30c2d1 100644 --- a/rpcs3/Emu/Cell/PPCDecoder.h +++ b/rpcs3/Emu/Cell/PPCDecoder.h @@ -1,6 +1,6 @@ #pragma once #include "PPCInstrTable.h" -#pragma warning( disable : 4800 ) +#pragma warning( disable : 4800 4554 ) template class InstrCaller @@ -481,22 +481,22 @@ static InstrList* connect_list(InstrList* parent, InstrL return child; } -template -static InstrList* new_list(const CodeFieldBase& func, InstrCaller* error_func = nullptr) +template +static InstrList<1 << (to - from + 1), TO>* new_list(const CodeField& func, InstrCaller* error_func = nullptr) { - return new InstrList(func, error_func); + return new InstrList<1 << (to - from + 1), TO>(func, error_func); } -template -static InstrList* new_list(InstrList* parent, int opcode, const CodeFieldBase& func, InstrCaller* error_func = nullptr) +template +static InstrList<1 << (to - from + 1), TO>* new_list(InstrList* parent, int opcode, const CodeField& func, InstrCaller* error_func = nullptr) { - return connect_list(parent, new InstrList(func, error_func), opcode); + return connect_list(parent, new InstrList<1 << (to - from + 1), TO>(func, error_func), opcode); } -template -static InstrList* new_list(InstrList* parent, const CodeFieldBase& func, InstrCaller* error_func = nullptr) +template +static InstrList<1 << (to - from + 1), TO>* new_list(InstrList* parent, const CodeField& func, InstrCaller* error_func = nullptr) { - return connect_list(parent, new InstrList(func, error_func)); + return connect_list(parent, new InstrList<1 << (to - from + 1), TO>(func, error_func)); } template diff --git a/rpcs3/Emu/Cell/PPCDisAsm.h b/rpcs3/Emu/Cell/PPCDisAsm.h index 14ca84246c..0c8ee7eb3b 100644 --- a/rpcs3/Emu/Cell/PPCDisAsm.h +++ b/rpcs3/Emu/Cell/PPCDisAsm.h @@ -76,83 +76,83 @@ protected: return op; } - void DisAsm_V4(const wxString& op, OP_REG v0, OP_REG v1, OP_REG v2, OP_REG v3) + void DisAsm_V4(const wxString& op, u32 v0, u32 v1, u32 v2, u32 v3) { Write(wxString::Format("%s v%d,v%d,v%d,v%d", FixOp(op), v0, v1, v2, v3)); } - void DisAsm_V3_UIMM(const wxString& op, OP_REG v0, OP_REG v1, OP_REG v2, OP_uIMM uimm) + void DisAsm_V3_UIMM(const wxString& op, u32 v0, u32 v1, u32 v2, u32 uimm) { Write(wxString::Format("%s v%d,v%d,v%d,%u #%x", FixOp(op), v0, v1, v2, uimm, uimm)); } - void DisAsm_V3(const wxString& op, OP_REG v0, OP_REG v1, OP_REG v2) + void DisAsm_V3(const wxString& op, u32 v0, u32 v1, u32 v2) { Write(wxString::Format("%s v%d,v%d,v%d", FixOp(op), v0, v1, v2)); } - void DisAsm_V2_UIMM(const wxString& op, OP_REG v0, OP_REG v1, OP_uIMM uimm) + void DisAsm_V2_UIMM(const wxString& op, u32 v0, u32 v1, u32 uimm) { Write(wxString::Format("%s v%d,v%d,%u #%x", FixOp(op), v0, v1, uimm, uimm)); } - void DisAsm_V2(const wxString& op, OP_REG v0, OP_REG v1) + void DisAsm_V2(const wxString& op, u32 v0, u32 v1) { Write(wxString::Format("%s v%d,v%d", FixOp(op), v0, v1)); } - void DisAsm_V1_SIMM(const wxString& op, OP_REG v0, OP_sIMM simm) + void DisAsm_V1_SIMM(const wxString& op, u32 v0, s32 simm) { Write(wxString::Format("%s v%d,%d #%x", FixOp(op), v0, simm, simm)); } - void DisAsm_V1(const wxString& op, OP_REG v0) + void DisAsm_V1(const wxString& op, u32 v0) { Write(wxString::Format("%s v%d", FixOp(op), v0)); } - void DisAsm_V1_R2(const wxString& op, OP_REG v0, OP_REG r1, OP_REG r2) + void DisAsm_V1_R2(const wxString& op, u32 v0, u32 r1, u32 r2) { Write(wxString::Format("%s v%d,r%d,r%d", FixOp(op), v0, r1, r2)); } - void DisAsm_CR1_F2_RC(const wxString& op, OP_REG cr0, OP_REG f0, OP_REG f1, bool rc) + void DisAsm_CR1_F2_RC(const wxString& op, u32 cr0, u32 f0, u32 f1, bool rc) { Write(wxString::Format("%s%s cr%d,f%d,f%d", FixOp(op), rc ? "." : "", cr0, f0, f1)); } - void DisAsm_CR1_F2(const wxString& op, OP_REG cr0, OP_REG f0, OP_REG f1) + void DisAsm_CR1_F2(const wxString& op, u32 cr0, u32 f0, u32 f1) { DisAsm_CR1_F2_RC(op, cr0, f0, f1, false); } - void DisAsm_INT1_R2(const wxString& op, OP_REG i0, OP_REG r0, OP_REG r1) + void DisAsm_INT1_R2(const wxString& op, u32 i0, u32 r0, u32 r1) { Write(wxString::Format("%s %d,r%d,r%d", FixOp(op), i0, r0, r1)); } - void DisAsm_INT1_R1_IMM(const wxString& op, OP_REG i0, OP_REG r0, OP_sIMM imm0) + void DisAsm_INT1_R1_IMM(const wxString& op, u32 i0, u32 r0, s32 imm0) { Write(wxString::Format("%s %d,r%d,%d #%x", FixOp(op), i0, r0, imm0, imm0)); } - void DisAsm_INT1_R1_RC(const wxString& op, OP_REG i0, OP_REG r0, bool rc) + void DisAsm_INT1_R1_RC(const wxString& op, u32 i0, u32 r0, bool rc) { Write(wxString::Format("%s%s %d,r%d", FixOp(op), rc ? "." : "", i0, r0)); } - void DisAsm_INT1_R1(const wxString& op, OP_REG i0, OP_REG r0) + void DisAsm_INT1_R1(const wxString& op, u32 i0, u32 r0) { DisAsm_INT1_R1_RC(op, i0, r0, false); } - void DisAsm_F4_RC(const wxString& op, OP_REG f0, OP_REG f1, OP_REG f2, OP_REG f3, bool rc) + void DisAsm_F4_RC(const wxString& op, u32 f0, u32 f1, u32 f2, u32 f3, bool rc) { Write(wxString::Format("%s%s f%d,f%d,f%d,f%d", FixOp(op), rc ? "." : "", f0, f1, f2, f3)); } - void DisAsm_F3_RC(const wxString& op, OP_REG f0, OP_REG f1, OP_REG f2, bool rc) + void DisAsm_F3_RC(const wxString& op, u32 f0, u32 f1, u32 f2, bool rc) { Write(wxString::Format("%s%s f%d,f%d,f%d", FixOp(op), rc ? "." : "", f0, f1, f2)); } - void DisAsm_F3(const wxString& op, OP_REG f0, OP_REG f1, OP_REG f2) + void DisAsm_F3(const wxString& op, u32 f0, u32 f1, u32 f2) { DisAsm_F3_RC(op, f0, f1, f2, false); } - void DisAsm_F2_RC(const wxString& op, OP_REG f0, OP_REG f1, bool rc) + void DisAsm_F2_RC(const wxString& op, u32 f0, u32 f1, bool rc) { Write(wxString::Format("%s%s f%d,f%d", FixOp(op), rc ? "." : "", f0, f1)); } - void DisAsm_F2(const wxString& op, OP_REG f0, OP_REG f1) + void DisAsm_F2(const wxString& op, u32 f0, u32 f1) { DisAsm_F2_RC(op, f0, f1, false); } - void DisAsm_F1_R2(const wxString& op, OP_REG f0, OP_REG r0, OP_REG r1) + void DisAsm_F1_R2(const wxString& op, u32 f0, u32 r0, u32 r1) { if(m_mode == CompilerElfMode) { @@ -162,7 +162,7 @@ protected: Write(wxString::Format("%s f%d,r%d(r%d)", FixOp(op), f0, r0, r1)); } - void DisAsm_F1_IMM_R1_RC(const wxString& op, OP_REG f0, OP_sIMM imm0, OP_REG r0, bool rc) + void DisAsm_F1_IMM_R1_RC(const wxString& op, u32 f0, s32 imm0, u32 r0, bool rc) { if(m_mode == CompilerElfMode) { @@ -172,75 +172,75 @@ protected: Write(wxString::Format("%s%s f%d,%d(r%d) #%x", FixOp(op), rc ? "." : "", f0, imm0, r0, imm0)); } - void DisAsm_F1_IMM_R1(const wxString& op, OP_REG f0, OP_sIMM imm0, OP_REG r0) + void DisAsm_F1_IMM_R1(const wxString& op, u32 f0, s32 imm0, u32 r0) { DisAsm_F1_IMM_R1_RC(op, f0, imm0, r0, false); } - void DisAsm_F1_RC(const wxString& op, OP_REG f0, bool rc) + void DisAsm_F1_RC(const wxString& op, u32 f0, bool rc) { Write(wxString::Format("%s%s f%d", FixOp(op), rc ? "." : "", f0)); } - void DisAsm_R1_RC(const wxString& op, OP_REG r0, bool rc) + void DisAsm_R1_RC(const wxString& op, u32 r0, bool rc) { Write(wxString::Format("%s%s r%d", FixOp(op), rc ? "." : "", r0)); } - void DisAsm_R1(const wxString& op, OP_REG r0) + void DisAsm_R1(const wxString& op, u32 r0) { DisAsm_R1_RC(op, r0, false); } - void DisAsm_R2_OE_RC(const wxString& op, OP_REG r0, OP_REG r1, OP_REG oe, bool rc) + void DisAsm_R2_OE_RC(const wxString& op, u32 r0, u32 r1, u32 oe, bool rc) { Write(wxString::Format("%s%s%s r%d,r%d", FixOp(op), oe ? "o" : "", rc ? "." : "", r0, r1)); } - void DisAsm_R2_RC(const wxString& op, OP_REG r0, OP_REG r1, bool rc) + void DisAsm_R2_RC(const wxString& op, u32 r0, u32 r1, bool rc) { DisAsm_R2_OE_RC(op, r0, r1, false, rc); } - void DisAsm_R2(const wxString& op, OP_REG r0, OP_REG r1) + void DisAsm_R2(const wxString& op, u32 r0, u32 r1) { DisAsm_R2_RC(op, r0, r1, false); } - void DisAsm_R3_OE_RC(const wxString& op, OP_REG r0, OP_REG r1, OP_REG r2, OP_REG oe, bool rc) + void DisAsm_R3_OE_RC(const wxString& op, u32 r0, u32 r1, u32 r2, u32 oe, bool rc) { Write(wxString::Format("%s%s%s r%d,r%d,r%d", FixOp(op), oe ? "o" : "", rc ? "." : "", r0, r1, r2)); } - void DisAsm_R3_INT2_RC(const wxString& op, OP_REG r0, OP_REG r1, OP_REG r2, OP_sIMM i0, OP_sIMM i1, bool rc) + void DisAsm_R3_INT2_RC(const wxString& op, u32 r0, u32 r1, u32 r2, s32 i0, s32 i1, bool rc) { Write(wxString::Format("%s%s r%d,r%d,r%d,%d,%d", FixOp(op), rc ? "." : "", r0, r1, r2, i0, i1)); } - void DisAsm_R3_RC(const wxString& op, OP_REG r0, OP_REG r1, OP_REG r2, bool rc) + void DisAsm_R3_RC(const wxString& op, u32 r0, u32 r1, u32 r2, bool rc) { DisAsm_R3_OE_RC(op, r0, r1, r2, false, rc); } - void DisAsm_R3(const wxString& op, OP_REG r0, OP_REG r1, OP_REG r2) + void DisAsm_R3(const wxString& op, u32 r0, u32 r1, u32 r2) { DisAsm_R3_RC(op, r0, r1, r2, false); } - void DisAsm_R2_INT3_RC(const wxString& op, OP_REG r0, OP_REG r1, OP_sIMM i0, OP_sIMM i1, OP_sIMM i2, bool rc) + void DisAsm_R2_INT3_RC(const wxString& op, u32 r0, u32 r1, s32 i0, s32 i1, s32 i2, bool rc) { Write(wxString::Format("%s%s r%d,r%d,%d,%d,%d", FixOp(op), rc ? "." : "", r0, r1, i0, i1, i2)); } - void DisAsm_R2_INT3(const wxString& op, OP_REG r0, OP_REG r1, OP_sIMM i0, OP_sIMM i1, OP_sIMM i2) + void DisAsm_R2_INT3(const wxString& op, u32 r0, u32 r1, s32 i0, s32 i1, s32 i2) { DisAsm_R2_INT3_RC(op, r0, r1, i0, i1, i2, false); } - void DisAsm_R2_INT2_RC(const wxString& op, OP_REG r0, OP_REG r1, OP_sIMM i0, OP_sIMM i1, bool rc) + void DisAsm_R2_INT2_RC(const wxString& op, u32 r0, u32 r1, s32 i0, s32 i1, bool rc) { Write(wxString::Format("%s%s r%d,r%d,%d,%d", FixOp(op), rc ? "." : "", r0, r1, i0, i1)); } - void DisAsm_R2_INT2(const wxString& op, OP_REG r0, OP_REG r1, OP_sIMM i0, OP_sIMM i1) + void DisAsm_R2_INT2(const wxString& op, u32 r0, u32 r1, s32 i0, s32 i1) { DisAsm_R2_INT2_RC(op, r0, r1, i0, i1, false); } - void DisAsm_R2_INT1_RC(const wxString& op, OP_REG r0, OP_REG r1, OP_sIMM i0, bool rc) + void DisAsm_R2_INT1_RC(const wxString& op, u32 r0, u32 r1, s32 i0, bool rc) { Write(wxString::Format("%s%s r%d,r%d,%d", FixOp(op), rc ? "." : "", r0, r1, i0)); } - void DisAsm_R2_INT1(const wxString& op, OP_REG r0, OP_REG r1, OP_sIMM i0) + void DisAsm_R2_INT1(const wxString& op, u32 r0, u32 r1, s32 i0) { DisAsm_R2_INT1_RC(op, r0, r1, i0, false); } - void DisAsm_R2_IMM(const wxString& op, OP_REG r0, OP_REG r1, OP_sIMM imm0) + void DisAsm_R2_IMM(const wxString& op, u32 r0, u32 r1, s32 imm0) { if(m_mode == CompilerElfMode) { @@ -250,27 +250,27 @@ protected: Write(wxString::Format("%s r%d,%d(r%d) #%x", FixOp(op), r0, imm0, r1, imm0)); } - void DisAsm_R1_IMM(const wxString& op, OP_REG r0, OP_sIMM imm0) + void DisAsm_R1_IMM(const wxString& op, u32 r0, s32 imm0) { Write(wxString::Format("%s r%d,%d #%x", FixOp(op), r0, imm0, imm0)); } - void DisAsm_IMM_R1(const wxString& op, OP_sIMM imm0, OP_REG r0) + void DisAsm_IMM_R1(const wxString& op, s32 imm0, u32 r0) { Write(wxString::Format("%s %d,r%d #%x", FixOp(op), imm0, r0, imm0)); } - void DisAsm_CR1_R1_IMM(const wxString& op, OP_REG cr0, OP_REG r0, OP_sIMM imm0) + void DisAsm_CR1_R1_IMM(const wxString& op, u32 cr0, u32 r0, s32 imm0) { Write(wxString::Format("%s cr%d,r%d,%d #%x", FixOp(op), cr0, r0, imm0, imm0)); } - void DisAsm_CR1_R2_RC(const wxString& op, OP_REG cr0, OP_REG r0, OP_REG r1, bool rc) + void DisAsm_CR1_R2_RC(const wxString& op, u32 cr0, u32 r0, u32 r1, bool rc) { Write(wxString::Format("%s%s cr%d,r%d,r%d", FixOp(op), rc ? "." : "", cr0, r0, r1)); } - void DisAsm_CR1_R2(const wxString& op, OP_REG cr0, OP_REG r0, OP_REG r1) + void DisAsm_CR1_R2(const wxString& op, u32 cr0, u32 r0, u32 r1) { DisAsm_CR1_R2_RC(op, cr0, r0, r1, false); } - void DisAsm_CR2(const wxString& op, OP_REG cr0, OP_REG cr1) + void DisAsm_CR2(const wxString& op, u32 cr0, u32 cr1) { Write(wxString::Format("%s cr%d,cr%d", FixOp(op), cr0, cr1)); } @@ -290,11 +290,11 @@ protected: { Write(wxString::Format("%s 0x%x", FixOp(op), pc)); } - void DisAsm_B2_BRANCH(const wxString& op, OP_REG b0, OP_REG b1, const int pc) + void DisAsm_B2_BRANCH(const wxString& op, u32 b0, u32 b1, const int pc) { Write(wxString::Format("%s %d,%d,0x%x ", FixOp(op), b0, b1, DisAsmBranchTarget(pc))); } - void DisAsm_CR_BRANCH(const wxString& op, OP_REG cr, const int pc) + void DisAsm_CR_BRANCH(const wxString& op, u32 cr, const int pc) { Write(wxString::Format("%s cr%d,0x%x ", FixOp(op), cr, DisAsmBranchTarget(pc))); } diff --git a/rpcs3/Emu/Cell/PPCInstrTable.h b/rpcs3/Emu/Cell/PPCInstrTable.h index 91725c1c7c..76328a8b36 100644 --- a/rpcs3/Emu/Cell/PPCInstrTable.h +++ b/rpcs3/Emu/Cell/PPCInstrTable.h @@ -77,6 +77,8 @@ public: } }; +static CodeField<0, 31> GetCode; + template class DoubleCodeField : public CodeField { @@ -133,3 +135,68 @@ public: return decode(data); } }; + +template +class CodeFieldOffset : public CodeField +{ + static const int offset = _offset; + +public: + CodeFieldOffset(CodeFieldType type = FIELD_IMM) : CodeField(type) + { + } + + static __forceinline u32 decode(u32 data) + { + return ((data & mask) >> shift) << offset; + } + + static __forceinline void encode(u32& data, u32 value) + { + data &= ~mask; + data |= ((value >> offset) << shift) & mask; + } + + virtual u32 operator ()(u32 data) const + { + return decode(data); + } + + virtual void operator ()(u32& data, u32 value) const + { + return encode(data, value); + } +}; + +template +class CodeFieldSignedOffset : public CodeFieldSigned +{ + static const int offset = _offset; + +public: + CodeFieldSignedOffset(CodeFieldType type = FIELD_IMM) : CodeFieldSigned(type) + { + } + + static __forceinline u32 decode(u32 data) + { + return sign((data & mask) >> shift) << offset; + } + + static __forceinline void encode(u32& data, u32 value) + { + data &= ~mask; + data |= ((value >> offset) << shift) & mask; + } + + virtual u32 operator ()(u32 data) const + { + return decode(data); + } + + virtual void operator ()(u32& data, u32 value) const + { + return encode(data, value); + } +}; + diff --git a/rpcs3/Emu/Cell/PPUDisAsm.h b/rpcs3/Emu/Cell/PPUDisAsm.h index 6efde556b7..a413498113 100644 --- a/rpcs3/Emu/Cell/PPUDisAsm.h +++ b/rpcs3/Emu/Cell/PPUDisAsm.h @@ -6,9 +6,6 @@ #include "Gui/DisAsmFrame.h" #include "Emu/Memory/Memory.h" -#define START_OPCODES_GROUP(x) /*x*/ -#define END_OPCODES_GROUP(x) /*x*/ - class PPU_DisAsm : public PPU_Opcodes , public PPC_DisAsm @@ -57,671 +54,667 @@ private: Write( "nop" ); } - void TDI(OP_REG to, OP_REG ra, OP_sIMM simm16) + void TDI(u32 to, u32 ra, s32 simm16) { DisAsm_INT1_R1_IMM("tdi", to, ra, simm16); } - void TWI(OP_REG to, OP_REG ra, OP_sIMM simm16) + void TWI(u32 to, u32 ra, s32 simm16) { DisAsm_INT1_R1_IMM("twi", to, ra, simm16); } - - START_OPCODES_GROUP(G_04) - void MFVSCR(OP_REG vd) - { - DisAsm_V1("mfvscr", vd); - } - void MTVSCR(OP_REG vb) - { - DisAsm_V1("mtvscr", vb); - } - void VADDCUW(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vaddcuw", vd, va, vb); - } - void VADDFP(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vaddfp", vd, va, vb); - } - void VADDSBS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vaddsbs", vd, va, vb); - } - void VADDSHS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vaddshs", vd, va, vb); - } - void VADDSWS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vaddsws", vd, va, vb); - } - void VADDUBM(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vaddubm", vd, va, vb); - } - void VADDUBS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vaddubs", vd, va, vb); - } - void VADDUHM(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vadduhm", vd, va, vb); - } - void VADDUHS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vadduhs", vd, va, vb); - } - void VADDUWM(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vadduwm", vd, va, vb); - } - void VADDUWS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vadduws", vd, va, vb); - } - void VAND(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vand", vd, va, vb); - } - void VANDC(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vandc", vd, va, vb); - } - void VAVGSB(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vavgsb", vd, va, vb); - } - void VAVGSH(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vavgsh", vd, va, vb); - } - void VAVGSW(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vavgsw", vd, va, vb); - } - void VAVGUB(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vavgub", vd, va, vb); - } - void VAVGUH(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vavguh", vd, va, vb); - } - void VAVGUW(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vavguw", vd, va, vb); - } - void VCFSX(OP_REG vd, OP_uIMM uimm5, OP_REG vb) - { - DisAsm_V2_UIMM("vcfsx", vd, vb, uimm5); - } - void VCFUX(OP_REG vd, OP_uIMM uimm5, OP_REG vb) - { - DisAsm_V2_UIMM("vcfux", vd, vb, uimm5); - } - void VCMPBFP(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpbfp", vd, va, vb); - } - void VCMPBFP_(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpbfp.", vd, va, vb); - } - void VCMPEQFP(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpeqfp", vd, va, vb); - } - void VCMPEQFP_(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpeqfp.", vd, va, vb); - } - void VCMPEQUB(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpequb", vd, va, vb); - } - void VCMPEQUB_(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpequb.", vd, va, vb); - } - void VCMPEQUH(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpequh", vd, va, vb); - } - void VCMPEQUH_(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpequh.", vd, va, vb); - } - void VCMPEQUW(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpequw", vd, va, vb); - } - void VCMPEQUW_(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpequw.", vd, va, vb); - } - void VCMPGEFP(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpgefp", vd, va, vb); - } - void VCMPGEFP_(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpgefp.", vd, va, vb); - } - void VCMPGTFP(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpgtfp", vd, va, vb); - } - void VCMPGTFP_(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpgtfp.", vd, va, vb); - } - void VCMPGTSB(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpgtsb", vd, va, vb); - } - void VCMPGTSB_(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpgtsb.", vd, va, vb); - } - void VCMPGTSH(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpgtsh", vd, va, vb); - } - void VCMPGTSH_(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpgtsh.", vd, va, vb); - } - void VCMPGTSW(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpgtsw", vd, va, vb); - } - void VCMPGTSW_(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpgtsw.", vd, va, vb); - } - void VCMPGTUB(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpgtub", vd, va, vb); - } - void VCMPGTUB_(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpgtub.", vd, va, vb); - } - void VCMPGTUH(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpgtuh", vd, va, vb); - } - void VCMPGTUH_(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpgtuh.", vd, va, vb); - } - void VCMPGTUW(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpgtuw", vd, va, vb); - } - void VCMPGTUW_(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vcmpgtuw.", vd, va, vb); - } - void VCTSXS(OP_REG vd, OP_uIMM uimm5, OP_REG vb) - { - DisAsm_V2_UIMM("vctsxs", vd, vb, uimm5); - } - void VCTUXS(OP_REG vd, OP_uIMM uimm5, OP_REG vb) - { - DisAsm_V2_UIMM("vctuxs", vd, vb, uimm5); - } - void VEXPTEFP(OP_REG vd, OP_REG vb) - { - DisAsm_V2("vexptefp", vd, vb); - } - void VLOGEFP(OP_REG vd, OP_REG vb) - { - DisAsm_V2("vlogefp", vd, vb); - } - void VMADDFP(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - DisAsm_V4("vmaddfp", vd, va, vb, vc); - } - void VMAXFP(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vmaxfp", vd, va, vb); - } - void VMAXSB(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vmaxsb", vd, va, vb); - } - void VMAXSH(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vmaxsh", vd, va, vb); - } - void VMAXSW(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vmaxsw", vd, va, vb); - } - void VMAXUB(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vmaxub", vd, va, vb); - } - void VMAXUH(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vmaxuh", vd, va, vb); - } - void VMAXUW(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vmaxuw", vd, va, vb); - } - void VMHADDSHS(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - DisAsm_V4("vmhaddshs", vd, va, vb, vc); - } - void VMHRADDSHS(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - DisAsm_V4("vmhraddshs", vd, va, vb, vc); - } - void VMINFP(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vminfp", vd, va, vb); - } - void VMINSB(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vminsb", vd, va, vb); - } - void VMINSH(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vminsh", vd, va, vb); - } - void VMINSW(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vminsw", vd, va, vb); - } - void VMINUB(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vminub", vd, va, vb); - } - void VMINUH(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vminuh", vd, va, vb); - } - void VMINUW(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vminuw", vd, va, vb); - } - void VMLADDUHM(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - DisAsm_V4("vmladduhm", vd, va, vb, vc); - } - void VMRGHB(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vmrghb", vd, va, vb); - } - void VMRGHH(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vmrghh", vd, va, vb); - } - void VMRGHW(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vmrghw", vd, va, vb); - } - void VMRGLB(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vmrglb", vd, va, vb); - } - void VMRGLH(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vmrglh", vd, va, vb); - } - void VMRGLW(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vmrglw", vd, va, vb); - } - void VMSUMMBM(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - DisAsm_V4("vmsummbm", vd, va, vb, vc); - } - void VMSUMSHM(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - DisAsm_V4("vmsumshm", vd, va, vb, vc); - } - void VMSUMSHS(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - DisAsm_V4("vmsumshs", vd, va, vb, vc); - } - void VMSUMUBM(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - DisAsm_V4("vmsumubm", vd, va, vb, vc); - } - void VMSUMUHM(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - DisAsm_V4("vmsumuhm", vd, va, vb, vc); - } - void VMSUMUHS(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - DisAsm_V4("vmsumuhs", vd, va, vb, vc); - } - void VMULESB(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vmulesb", vd, va, vb); - } - void VMULESH(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vmulesh", vd, va, vb); - } - void VMULEUB(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vmuleub", vd, va, vb); - } - void VMULEUH(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vmuleuh", vd, va, vb); - } - void VMULOSB(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vmulosb", vd, va, vb); - } - void VMULOSH(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vmulosh", vd, va, vb); - } - void VMULOUB(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vmuloub", vd, va, vb); - } - void VMULOUH(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vmulouh", vd, va, vb); - } - void VNMSUBFP(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - DisAsm_V4("vnmsubfp", vd, va, vb, vc); - } - void VNOR(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vnor", vd, va, vb); - } - void VOR(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vor", vd, va, vb); - } - void VPERM(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - DisAsm_V4("vperm", vd, va, vb, vc); - } - void VPKPX(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vpkpx", vd, va, vb); - } - void VPKSHSS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vpkshss", vd, va, vb); - } - void VPKSHUS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vpkshus", vd, va, vb); - } - void VPKSWSS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vpkswss", vd, va, vb); - } - void VPKSWUS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vpkswus", vd, va, vb); - } - void VPKUHUM(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vpkuhum", vd, va, vb); - } - void VPKUHUS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vpkuhus", vd, va, vb); - } - void VPKUWUM(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vpkuwum", vd, va, vb); - } - void VPKUWUS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vpkuwus", vd, va, vb); - } - void VREFP(OP_REG vd, OP_REG vb) - { - DisAsm_V2("vrefp", vd, vb); - } - void VRFIM(OP_REG vd, OP_REG vb) - { - DisAsm_V2("vrfim", vd, vb); - } - void VRFIN(OP_REG vd, OP_REG vb) - { - DisAsm_V2("vrfin", vd, vb); - } - void VRFIP(OP_REG vd, OP_REG vb) - { - DisAsm_V2("vrfip", vd, vb); - } - void VRFIZ(OP_REG vd, OP_REG vb) - { - DisAsm_V2("vrfiz", vd, vb); - } - void VRLB(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vrlb", vd, va, vb); - } - void VRLH(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vrlh", vd, va, vb); - } - void VRLW(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vrlw", vd, va, vb); - } - void VRSQRTEFP(OP_REG vd, OP_REG vb) - { - DisAsm_V2("vrsqrtefp", vd, vb); - } - void VSEL(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - DisAsm_V4("vsel", vd, va, vb, vc); - } - void VSL(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsl", vd, va, vb); - } - void VSLB(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vslb", vd, va, vb); - } - void VSLDOI(OP_REG vd, OP_REG va, OP_REG vb, OP_uIMM sh) - { - DisAsm_V3_UIMM("vsldoi", vd, va, vb, sh); - } - void VSLH(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vslh", vd, va, vb); - } - void VSLO(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vslo", vd, va, vb); - } - void VSLW(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vslw", vd, va, vb); - } - void VSPLTB(OP_REG vd, OP_uIMM uimm5, OP_REG vb) - { - DisAsm_V2_UIMM("vspltb", vd, vb, uimm5); - } - void VSPLTH(OP_REG vd, OP_uIMM uimm5, OP_REG vb) - { - DisAsm_V2_UIMM("vsplth", vd, vb, uimm5); - } - void VSPLTISB(OP_REG vd, OP_sIMM simm5) - { - DisAsm_V1_SIMM("vspltisb", vd, simm5); - } - void VSPLTISH(OP_REG vd, OP_sIMM simm5) - { - DisAsm_V1_SIMM("vspltish", vd, simm5); - } - void VSPLTISW(OP_REG vd, OP_sIMM simm5) - { - DisAsm_V1_SIMM("vspltisw", vd, simm5); - } - void VSPLTW(OP_REG vd, OP_uIMM uimm5, OP_REG vb) - { - DisAsm_V2_UIMM("vspltw", vd, vb, uimm5); - } - void VSR(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsr", vd, va, vb); - } - void VSRAB(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsrab", vd, va, vb); - } - void VSRAH(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsrah", vd, va, vb); - } - void VSRAW(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsraw", vd, va, vb); - } - void VSRB(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsrb", vd, va, vb); - } - void VSRH(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsrh", vd, va, vb); - } - void VSRO(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsro", vd, va, vb); - } - void VSRW(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsrw", vd, va, vb); - } - void VSUBCUW(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsubcuw", vd, va, vb); - } - void VSUBFP(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsubfp", vd, va, vb); - } - void VSUBSBS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsubsbs", vd, va, vb); - } - void VSUBSHS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsubshs", vd, va, vb); - } - void VSUBSWS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsubsws", vd, va, vb); - } - void VSUBUBM(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsububm", vd, va, vb); - } - void VSUBUBS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsububs", vd, va, vb); - } - void VSUBUHM(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsubuhm", vd, va, vb); - } - void VSUBUHS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsubuhs", vd, va, vb); - } - void VSUBUWM(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsubuwm", vd, va, vb); - } - void VSUBUWS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsubuws", vd, va, vb); - } - void VSUMSWS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsumsws", vd, va, vb); - } - void VSUM2SWS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsum2sws", vd, va, vb); - } - void VSUM4SBS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsum4sbs", vd, va, vb); - } - void VSUM4SHS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsum4shs", vd, va, vb); - } - void VSUM4UBS(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vsum4ubs", vd, va, vb); - } - void VUPKHPX(OP_REG vd, OP_REG vb) - { - DisAsm_V2("vupkhpx", vd, vb); - } - void VUPKHSB(OP_REG vd, OP_REG vb) - { - DisAsm_V2("vupkhsb", vd, vb); - } - void VUPKHSH(OP_REG vd, OP_REG vb) - { - DisAsm_V2("vupkhsh", vd, vb); - } - void VUPKLPX(OP_REG vd, OP_REG vb) - { - DisAsm_V2("vupklpx", vd, vb); - } - void VUPKLSB(OP_REG vd, OP_REG vb) - { - DisAsm_V2("vupklsb", vd, vb); - } - void VUPKLSH(OP_REG vd, OP_REG vb) - { - DisAsm_V2("vupklsh", vd, vb); - } - void VXOR(OP_REG vd, OP_REG va, OP_REG vb) - { - DisAsm_V3("vxor", vd, va, vb); - } - END_OPCODES_GROUP(G_04); - - void MULLI(OP_REG rd, OP_REG ra, OP_sIMM simm16) + void MFVSCR(u32 vd) + { + DisAsm_V1("mfvscr", vd); + } + void MTVSCR(u32 vb) + { + DisAsm_V1("mtvscr", vb); + } + void VADDCUW(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vaddcuw", vd, va, vb); + } + void VADDFP(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vaddfp", vd, va, vb); + } + void VADDSBS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vaddsbs", vd, va, vb); + } + void VADDSHS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vaddshs", vd, va, vb); + } + void VADDSWS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vaddsws", vd, va, vb); + } + void VADDUBM(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vaddubm", vd, va, vb); + } + void VADDUBS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vaddubs", vd, va, vb); + } + void VADDUHM(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vadduhm", vd, va, vb); + } + void VADDUHS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vadduhs", vd, va, vb); + } + void VADDUWM(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vadduwm", vd, va, vb); + } + void VADDUWS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vadduws", vd, va, vb); + } + void VAND(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vand", vd, va, vb); + } + void VANDC(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vandc", vd, va, vb); + } + void VAVGSB(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vavgsb", vd, va, vb); + } + void VAVGSH(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vavgsh", vd, va, vb); + } + void VAVGSW(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vavgsw", vd, va, vb); + } + void VAVGUB(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vavgub", vd, va, vb); + } + void VAVGUH(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vavguh", vd, va, vb); + } + void VAVGUW(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vavguw", vd, va, vb); + } + void VCFSX(u32 vd, u32 uimm5, u32 vb) + { + DisAsm_V2_UIMM("vcfsx", vd, vb, uimm5); + } + void VCFUX(u32 vd, u32 uimm5, u32 vb) + { + DisAsm_V2_UIMM("vcfux", vd, vb, uimm5); + } + void VCMPBFP(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpbfp", vd, va, vb); + } + void VCMPBFP_(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpbfp.", vd, va, vb); + } + void VCMPEQFP(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpeqfp", vd, va, vb); + } + void VCMPEQFP_(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpeqfp.", vd, va, vb); + } + void VCMPEQUB(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpequb", vd, va, vb); + } + void VCMPEQUB_(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpequb.", vd, va, vb); + } + void VCMPEQUH(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpequh", vd, va, vb); + } + void VCMPEQUH_(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpequh.", vd, va, vb); + } + void VCMPEQUW(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpequw", vd, va, vb); + } + void VCMPEQUW_(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpequw.", vd, va, vb); + } + void VCMPGEFP(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpgefp", vd, va, vb); + } + void VCMPGEFP_(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpgefp.", vd, va, vb); + } + void VCMPGTFP(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpgtfp", vd, va, vb); + } + void VCMPGTFP_(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpgtfp.", vd, va, vb); + } + void VCMPGTSB(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpgtsb", vd, va, vb); + } + void VCMPGTSB_(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpgtsb.", vd, va, vb); + } + void VCMPGTSH(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpgtsh", vd, va, vb); + } + void VCMPGTSH_(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpgtsh.", vd, va, vb); + } + void VCMPGTSW(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpgtsw", vd, va, vb); + } + void VCMPGTSW_(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpgtsw.", vd, va, vb); + } + void VCMPGTUB(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpgtub", vd, va, vb); + } + void VCMPGTUB_(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpgtub.", vd, va, vb); + } + void VCMPGTUH(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpgtuh", vd, va, vb); + } + void VCMPGTUH_(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpgtuh.", vd, va, vb); + } + void VCMPGTUW(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpgtuw", vd, va, vb); + } + void VCMPGTUW_(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vcmpgtuw.", vd, va, vb); + } + void VCTSXS(u32 vd, u32 uimm5, u32 vb) + { + DisAsm_V2_UIMM("vctsxs", vd, vb, uimm5); + } + void VCTUXS(u32 vd, u32 uimm5, u32 vb) + { + DisAsm_V2_UIMM("vctuxs", vd, vb, uimm5); + } + void VEXPTEFP(u32 vd, u32 vb) + { + DisAsm_V2("vexptefp", vd, vb); + } + void VLOGEFP(u32 vd, u32 vb) + { + DisAsm_V2("vlogefp", vd, vb); + } + void VMADDFP(u32 vd, u32 va, u32 vb, u32 vc) + { + DisAsm_V4("vmaddfp", vd, va, vb, vc); + } + void VMAXFP(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vmaxfp", vd, va, vb); + } + void VMAXSB(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vmaxsb", vd, va, vb); + } + void VMAXSH(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vmaxsh", vd, va, vb); + } + void VMAXSW(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vmaxsw", vd, va, vb); + } + void VMAXUB(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vmaxub", vd, va, vb); + } + void VMAXUH(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vmaxuh", vd, va, vb); + } + void VMAXUW(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vmaxuw", vd, va, vb); + } + void VMHADDSHS(u32 vd, u32 va, u32 vb, u32 vc) + { + DisAsm_V4("vmhaddshs", vd, va, vb, vc); + } + void VMHRADDSHS(u32 vd, u32 va, u32 vb, u32 vc) + { + DisAsm_V4("vmhraddshs", vd, va, vb, vc); + } + void VMINFP(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vminfp", vd, va, vb); + } + void VMINSB(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vminsb", vd, va, vb); + } + void VMINSH(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vminsh", vd, va, vb); + } + void VMINSW(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vminsw", vd, va, vb); + } + void VMINUB(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vminub", vd, va, vb); + } + void VMINUH(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vminuh", vd, va, vb); + } + void VMINUW(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vminuw", vd, va, vb); + } + void VMLADDUHM(u32 vd, u32 va, u32 vb, u32 vc) + { + DisAsm_V4("vmladduhm", vd, va, vb, vc); + } + void VMRGHB(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vmrghb", vd, va, vb); + } + void VMRGHH(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vmrghh", vd, va, vb); + } + void VMRGHW(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vmrghw", vd, va, vb); + } + void VMRGLB(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vmrglb", vd, va, vb); + } + void VMRGLH(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vmrglh", vd, va, vb); + } + void VMRGLW(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vmrglw", vd, va, vb); + } + void VMSUMMBM(u32 vd, u32 va, u32 vb, u32 vc) + { + DisAsm_V4("vmsummbm", vd, va, vb, vc); + } + void VMSUMSHM(u32 vd, u32 va, u32 vb, u32 vc) + { + DisAsm_V4("vmsumshm", vd, va, vb, vc); + } + void VMSUMSHS(u32 vd, u32 va, u32 vb, u32 vc) + { + DisAsm_V4("vmsumshs", vd, va, vb, vc); + } + void VMSUMUBM(u32 vd, u32 va, u32 vb, u32 vc) + { + DisAsm_V4("vmsumubm", vd, va, vb, vc); + } + void VMSUMUHM(u32 vd, u32 va, u32 vb, u32 vc) + { + DisAsm_V4("vmsumuhm", vd, va, vb, vc); + } + void VMSUMUHS(u32 vd, u32 va, u32 vb, u32 vc) + { + DisAsm_V4("vmsumuhs", vd, va, vb, vc); + } + void VMULESB(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vmulesb", vd, va, vb); + } + void VMULESH(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vmulesh", vd, va, vb); + } + void VMULEUB(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vmuleub", vd, va, vb); + } + void VMULEUH(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vmuleuh", vd, va, vb); + } + void VMULOSB(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vmulosb", vd, va, vb); + } + void VMULOSH(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vmulosh", vd, va, vb); + } + void VMULOUB(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vmuloub", vd, va, vb); + } + void VMULOUH(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vmulouh", vd, va, vb); + } + void VNMSUBFP(u32 vd, u32 va, u32 vb, u32 vc) + { + DisAsm_V4("vnmsubfp", vd, va, vb, vc); + } + void VNOR(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vnor", vd, va, vb); + } + void VOR(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vor", vd, va, vb); + } + void VPERM(u32 vd, u32 va, u32 vb, u32 vc) + { + DisAsm_V4("vperm", vd, va, vb, vc); + } + void VPKPX(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vpkpx", vd, va, vb); + } + void VPKSHSS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vpkshss", vd, va, vb); + } + void VPKSHUS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vpkshus", vd, va, vb); + } + void VPKSWSS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vpkswss", vd, va, vb); + } + void VPKSWUS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vpkswus", vd, va, vb); + } + void VPKUHUM(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vpkuhum", vd, va, vb); + } + void VPKUHUS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vpkuhus", vd, va, vb); + } + void VPKUWUM(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vpkuwum", vd, va, vb); + } + void VPKUWUS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vpkuwus", vd, va, vb); + } + void VREFP(u32 vd, u32 vb) + { + DisAsm_V2("vrefp", vd, vb); + } + void VRFIM(u32 vd, u32 vb) + { + DisAsm_V2("vrfim", vd, vb); + } + void VRFIN(u32 vd, u32 vb) + { + DisAsm_V2("vrfin", vd, vb); + } + void VRFIP(u32 vd, u32 vb) + { + DisAsm_V2("vrfip", vd, vb); + } + void VRFIZ(u32 vd, u32 vb) + { + DisAsm_V2("vrfiz", vd, vb); + } + void VRLB(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vrlb", vd, va, vb); + } + void VRLH(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vrlh", vd, va, vb); + } + void VRLW(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vrlw", vd, va, vb); + } + void VRSQRTEFP(u32 vd, u32 vb) + { + DisAsm_V2("vrsqrtefp", vd, vb); + } + void VSEL(u32 vd, u32 va, u32 vb, u32 vc) + { + DisAsm_V4("vsel", vd, va, vb, vc); + } + void VSL(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsl", vd, va, vb); + } + void VSLB(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vslb", vd, va, vb); + } + void VSLDOI(u32 vd, u32 va, u32 vb, u32 sh) + { + DisAsm_V3_UIMM("vsldoi", vd, va, vb, sh); + } + void VSLH(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vslh", vd, va, vb); + } + void VSLO(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vslo", vd, va, vb); + } + void VSLW(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vslw", vd, va, vb); + } + void VSPLTB(u32 vd, u32 uimm5, u32 vb) + { + DisAsm_V2_UIMM("vspltb", vd, vb, uimm5); + } + void VSPLTH(u32 vd, u32 uimm5, u32 vb) + { + DisAsm_V2_UIMM("vsplth", vd, vb, uimm5); + } + void VSPLTISB(u32 vd, s32 simm5) + { + DisAsm_V1_SIMM("vspltisb", vd, simm5); + } + void VSPLTISH(u32 vd, s32 simm5) + { + DisAsm_V1_SIMM("vspltish", vd, simm5); + } + void VSPLTISW(u32 vd, s32 simm5) + { + DisAsm_V1_SIMM("vspltisw", vd, simm5); + } + void VSPLTW(u32 vd, u32 uimm5, u32 vb) + { + DisAsm_V2_UIMM("vspltw", vd, vb, uimm5); + } + void VSR(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsr", vd, va, vb); + } + void VSRAB(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsrab", vd, va, vb); + } + void VSRAH(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsrah", vd, va, vb); + } + void VSRAW(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsraw", vd, va, vb); + } + void VSRB(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsrb", vd, va, vb); + } + void VSRH(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsrh", vd, va, vb); + } + void VSRO(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsro", vd, va, vb); + } + void VSRW(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsrw", vd, va, vb); + } + void VSUBCUW(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsubcuw", vd, va, vb); + } + void VSUBFP(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsubfp", vd, va, vb); + } + void VSUBSBS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsubsbs", vd, va, vb); + } + void VSUBSHS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsubshs", vd, va, vb); + } + void VSUBSWS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsubsws", vd, va, vb); + } + void VSUBUBM(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsububm", vd, va, vb); + } + void VSUBUBS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsububs", vd, va, vb); + } + void VSUBUHM(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsubuhm", vd, va, vb); + } + void VSUBUHS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsubuhs", vd, va, vb); + } + void VSUBUWM(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsubuwm", vd, va, vb); + } + void VSUBUWS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsubuws", vd, va, vb); + } + void VSUMSWS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsumsws", vd, va, vb); + } + void VSUM2SWS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsum2sws", vd, va, vb); + } + void VSUM4SBS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsum4sbs", vd, va, vb); + } + void VSUM4SHS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsum4shs", vd, va, vb); + } + void VSUM4UBS(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vsum4ubs", vd, va, vb); + } + void VUPKHPX(u32 vd, u32 vb) + { + DisAsm_V2("vupkhpx", vd, vb); + } + void VUPKHSB(u32 vd, u32 vb) + { + DisAsm_V2("vupkhsb", vd, vb); + } + void VUPKHSH(u32 vd, u32 vb) + { + DisAsm_V2("vupkhsh", vd, vb); + } + void VUPKLPX(u32 vd, u32 vb) + { + DisAsm_V2("vupklpx", vd, vb); + } + void VUPKLSB(u32 vd, u32 vb) + { + DisAsm_V2("vupklsb", vd, vb); + } + void VUPKLSH(u32 vd, u32 vb) + { + DisAsm_V2("vupklsh", vd, vb); + } + void VXOR(u32 vd, u32 va, u32 vb) + { + DisAsm_V3("vxor", vd, va, vb); + } + void MULLI(u32 rd, u32 ra, s32 simm16) { DisAsm_R2_IMM("mulli", rd, ra, simm16); } - void SUBFIC(OP_REG rd, OP_REG ra, OP_sIMM simm16) + void SUBFIC(u32 rd, u32 ra, s32 simm16) { DisAsm_R2_IMM("subfic", rd, ra, simm16); } - void CMPLI(OP_REG crfd, OP_REG l, OP_REG ra, OP_uIMM uimm16) + void CMPLI(u32 crfd, u32 l, u32 ra, u32 uimm16) { DisAsm_CR1_R1_IMM(wxString::Format("cmpl%si", l ? "d" : "w"), crfd, ra, uimm16); } - void CMPI(OP_REG crfd, OP_REG l, OP_REG ra, OP_sIMM simm16) + void CMPI(u32 crfd, u32 l, u32 ra, s32 simm16) { DisAsm_CR1_R1_IMM(wxString::Format("cmp%si", l ? "d" : "w"), crfd, ra, simm16); } - void ADDIC(OP_REG rd, OP_REG ra, OP_sIMM simm16) + void ADDIC(u32 rd, u32 ra, s32 simm16) { DisAsm_R2_IMM("addic", rd, ra, simm16); } - void ADDIC_(OP_REG rd, OP_REG ra, OP_sIMM simm16) + void ADDIC_(u32 rd, u32 ra, s32 simm16) { DisAsm_R2_IMM("addic.", rd, ra, simm16); } - void ADDI(OP_REG rd, OP_REG ra, OP_sIMM simm16) + void ADDI(u32 rd, u32 ra, s32 simm16) { if(ra == 0) { @@ -732,7 +725,7 @@ private: DisAsm_R2_IMM("addi", rd, ra, simm16); } } - void ADDIS(OP_REG rd, OP_REG ra, OP_sIMM simm16) + void ADDIS(u32 rd, u32 ra, s32 simm16) { if(ra == 0) { @@ -743,8 +736,7 @@ private: DisAsm_R2_IMM("addis", rd, ra, simm16); } } - - void BC(OP_REG bo, OP_REG bi, OP_sIMM bd, OP_REG aa, OP_REG lk) + void BC(u32 bo, u32 bi, s32 bd, u32 aa, u32 lk) { if(m_mode == CompilerElfMode) { @@ -840,7 +832,7 @@ private: Write(wxString::Format("bc [%x:%x:%x:%x:%x], cr%d[%x], 0x%x, %d, %d", bo0, bo1, bo2, bo3, bo4, bi/4, bi%4, bd, aa, lk)); } - void SC(OP_sIMM sc_code) + void SC(s32 sc_code) { switch(sc_code) { @@ -850,7 +842,7 @@ private: default: Write(wxString::Format("Unknown sc: %x", sc_code)); } } - void B(OP_sIMM ll, OP_REG aa, OP_REG lk) + void B(s32 ll, u32 aa, u32 lk) { if(m_mode == CompilerElfMode) { @@ -877,82 +869,77 @@ private: break; } } - - START_OPCODES_GROUP(G_13) - void MCRF(OP_REG crfd, OP_REG crfs) - { - DisAsm_CR2("mcrf", crfd, crfs); - } - void BCLR(OP_REG bo, OP_REG bi, OP_REG bh, OP_REG lk) - { - const u8 bo0 = (bo & 0x10) ? 1 : 0; - const u8 bo1 = (bo & 0x08) ? 1 : 0; - const u8 bo2 = (bo & 0x04) ? 1 : 0; - const u8 bo3 = (bo & 0x02) ? 1 : 0; + void MCRF(u32 crfd, u32 crfs) + { + DisAsm_CR2("mcrf", crfd, crfs); + } + void BCLR(u32 bo, u32 bi, u32 bh, u32 lk) + { + const u8 bo0 = (bo & 0x10) ? 1 : 0; + const u8 bo1 = (bo & 0x08) ? 1 : 0; + const u8 bo2 = (bo & 0x04) ? 1 : 0; + const u8 bo3 = (bo & 0x02) ? 1 : 0; - if(bo0 && !bo1 && bo2 && !bo3) {Write("blr"); return;} - Write(wxString::Format("bclr [%x:%x:%x:%x], cr%d[%x], %d, %d", bo0, bo1, bo2, bo3, bi/4, bi%4, bh, lk)); - } - void CRNOR(OP_REG bt, OP_REG ba, OP_REG bb) + if(bo0 && !bo1 && bo2 && !bo3) {Write("blr"); return;} + Write(wxString::Format("bclr [%x:%x:%x:%x], cr%d[%x], %d, %d", bo0, bo1, bo2, bo3, bi/4, bi%4, bh, lk)); + } + void CRNOR(u32 bt, u32 ba, u32 bb) + { + DisAsm_INT3("crnor", bt, ba, bb); + } + void CRANDC(u32 bt, u32 ba, u32 bb) + { + DisAsm_INT3("crandc", bt, ba, bb); + } + void ISYNC() + { + Write("isync"); + } + void CRXOR(u32 bt, u32 ba, u32 bb) + { + DisAsm_INT3("crxor", bt, ba, bb); + } + void CRNAND(u32 bt, u32 ba, u32 bb) + { + DisAsm_INT3("crnand", bt, ba, bb); + } + void CRAND(u32 bt, u32 ba, u32 bb) + { + DisAsm_INT3("crand", bt, ba, bb); + } + void CREQV(u32 bt, u32 ba, u32 bb) + { + DisAsm_INT3("creqv", bt, ba, bb); + } + void CRORC(u32 bt, u32 ba, u32 bb) + { + DisAsm_INT3("crorc", bt, ba, bb); + } + void CROR(u32 bt, u32 ba, u32 bb) + { + DisAsm_INT3("cror", bt, ba, bb); + } + void BCCTR(u32 bo, u32 bi, u32 bh, u32 lk) + { + switch(lk) { - DisAsm_INT3("crnor", bt, ba, bb); + case 0: DisAsm_INT3("bcctr", bo, bi, bh); break; + case 1: DisAsm_INT3("bcctrl", bo, bi, bh); break; } - void CRANDC(OP_REG bt, OP_REG ba, OP_REG bb) - { - DisAsm_INT3("crandc", bt, ba, bb); - } - void ISYNC() - { - Write("isync"); - } - void CRXOR(OP_REG bt, OP_REG ba, OP_REG bb) - { - DisAsm_INT3("crxor", bt, ba, bb); - } - void CRNAND(OP_REG bt, OP_REG ba, OP_REG bb) - { - DisAsm_INT3("crnand", bt, ba, bb); - } - void CRAND(OP_REG bt, OP_REG ba, OP_REG bb) - { - DisAsm_INT3("crand", bt, ba, bb); - } - void CREQV(OP_REG bt, OP_REG ba, OP_REG bb) - { - DisAsm_INT3("creqv", bt, ba, bb); - } - void CRORC(OP_REG bt, OP_REG ba, OP_REG bb) - { - DisAsm_INT3("crorc", bt, ba, bb); - } - void CROR(OP_REG bt, OP_REG ba, OP_REG bb) - { - DisAsm_INT3("cror", bt, ba, bb); - } - void BCCTR(OP_REG bo, OP_REG bi, OP_REG bh, OP_REG lk) - { - switch(lk) - { - case 0: DisAsm_INT3("bcctr", bo, bi, bh); break; - case 1: DisAsm_INT3("bcctrl", bo, bi, bh); break; - } - } - END_OPCODES_GROUP(G_13); - - - void RLWIMI(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, OP_REG me, bool rc) + } + void RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) { DisAsm_R2_INT3_RC("rlwimi", ra, rs, sh, mb, me, rc); } - void RLWINM(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, OP_REG me, bool rc) + void RLWINM(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) { DisAsm_R2_INT3_RC("rlwinm", ra, rs, sh, mb, me, rc); } - void RLWNM(OP_REG ra, OP_REG rs, OP_REG rb, OP_REG MB, OP_REG ME, bool rc) + void RLWNM(u32 ra, u32 rs, u32 rb, u32 MB, u32 ME, bool rc) { DisAsm_R3_INT2_RC("rlwnm", ra, rs, rb, MB, ME, rc); } - void ORI(OP_REG rs, OP_REG ra, OP_uIMM uimm16) + void ORI(u32 rs, u32 ra, u32 uimm16) { if(rs == 0 && ra == 0 && uimm16 == 0) { @@ -961,7 +948,7 @@ private: } DisAsm_R2_IMM("ori", rs, ra, uimm16); } - void ORIS(OP_REG rs, OP_REG ra, OP_uIMM uimm16) + void ORIS(u32 rs, u32 ra, u32 uimm16) { if(rs == 0 && ra == 0 && uimm16 == 0) { @@ -970,833 +957,814 @@ private: } DisAsm_R2_IMM("oris", rs, ra, uimm16); } - void XORI(OP_REG ra, OP_REG rs, OP_uIMM uimm16) + void XORI(u32 ra, u32 rs, u32 uimm16) { DisAsm_R2_IMM("xori", ra, rs, uimm16); } - void XORIS(OP_REG ra, OP_REG rs, OP_uIMM uimm16) + void XORIS(u32 ra, u32 rs, u32 uimm16) { DisAsm_R2_IMM("xoris", ra, rs, uimm16); } - void ANDI_(OP_REG ra, OP_REG rs, OP_uIMM uimm16) + void ANDI_(u32 ra, u32 rs, u32 uimm16) { DisAsm_R2_IMM("andi.", ra, rs, uimm16); } - void ANDIS_(OP_REG ra, OP_REG rs, OP_uIMM uimm16) + void ANDIS_(u32 ra, u32 rs, u32 uimm16) { DisAsm_R2_IMM("andis.", ra, rs, uimm16); } + void RLDICL(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) + { + if(sh == 0) + { + DisAsm_R2_INT1_RC("clrldi", ra, rs, mb, rc); + } + else if(mb == 0) + { + DisAsm_R2_INT1_RC("rotldi", ra, rs, sh, rc); + } + else if(mb == 64 - sh) + { + DisAsm_R2_INT1_RC("srdi", ra, rs, mb, rc); + } + else + { + DisAsm_R2_INT2_RC("rldicl", ra, rs, sh, mb, rc); + } + } + void RLDICR(u32 ra, u32 rs, u32 sh, u32 me, bool rc) + { + DisAsm_R2_INT2_RC("rldicr", ra, rs, sh, me, rc); + } + void RLDIC(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) + { + DisAsm_R2_INT2_RC("rldic", ra, rs, sh, mb, rc); + } + void RLDIMI(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) + { + DisAsm_R2_INT2_RC("rldimi", ra, rs, sh, mb, rc); + } + void CMP(u32 crfd, u32 l, u32 ra, u32 rb) + { + DisAsm_CR1_R2(wxString::Format("cmp%s", l ? "d" : "w"), crfd, ra, rb); + } + void TW(u32 to, u32 ra, u32 rb) + { + DisAsm_INT1_R2("tw", to, ra, rb); + } + void LVSL(u32 vd, u32 ra, u32 rb) + { + DisAsm_V1_R2("lvsl", vd, ra, rb); + } + void LVEBX(u32 vd, u32 ra, u32 rb) + { + DisAsm_V1_R2("lvebx", vd, ra, rb); + } + void SUBFC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + DisAsm_R3_OE_RC("subfc", rd, ra, rb, oe, rc); + } + void ADDC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + DisAsm_R3_OE_RC("addc", rd, ra, rb, oe, rc); + } + void MULHDU(u32 rd, u32 ra, u32 rb, bool rc) + { + DisAsm_R3_RC("mulhdu", rd, ra, rb, rc); + } + void MULHWU(u32 rd, u32 ra, u32 rb, bool rc) + { + DisAsm_R3_RC("mulhwu", rd, ra, rb, rc); + } + void MFOCRF(u32 a, u32 rd, u32 crm) + { + if(a) + { + DisAsm_R1_IMM("mfocrf", rd, crm); + } + else + { + DisAsm_R1("mfcr", rd); + } + } + void LWARX(u32 rd, u32 ra, u32 rb) + { + DisAsm_R3("lwarx", rd, ra, rb); + } + void LDX(u32 ra, u32 rs, u32 rb) + { + DisAsm_R3("ldx", ra, rs, rb); + } + void LWZX(u32 rd, u32 ra, u32 rb) + { + DisAsm_R3("lwzx", rd, ra, rb); + } + void SLW(u32 ra, u32 rs, u32 rb, bool rc) + { + DisAsm_R3_RC("slw", ra, rs, rb, rc); + } + void CNTLZW(u32 ra, u32 rs, bool rc) + { + DisAsm_R2_RC("cntlzw", ra, rs, rc); + } + void SLD(u32 ra, u32 rs, u32 rb, bool rc) + { + DisAsm_R3_RC("sld", ra, rs, rb, rc); + } + void AND(u32 ra, u32 rs, u32 rb, bool rc) + { + DisAsm_R3_RC("and", ra, rs, rb, rc); + } + void CMPL(u32 crfd, u32 l, u32 ra, u32 rb) + { + DisAsm_CR1_R2(wxString::Format("cmpl%s", l ? "d" : "w"), crfd, ra, rb); + } + void LVSR(u32 vd, u32 ra, u32 rb) + { + DisAsm_V1_R2("lvsr", vd, ra, rb); + } + void LVEHX(u32 vd, u32 ra, u32 rb) + { + DisAsm_V1_R2("lvehx", vd, ra, rb); + } + void SUBF(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + DisAsm_R3_OE_RC("subf", rd, ra, rb, oe, rc); + } + void LDUX(u32 rd, u32 ra, u32 rb) + { + DisAsm_R3("ldux", rd, ra, rb); + } + void DCBST(u32 ra, u32 rb) + { + DisAsm_R2("dcbst", ra, rb); + } + void CNTLZD(u32 ra, u32 rs, bool rc) + { + DisAsm_R2_RC("cntlzd", ra, rs, rc); + } + void ANDC(u32 ra, u32 rs, u32 rb, bool rc) + { + DisAsm_R3_RC("andc", ra, rs, rb, rc); + } + void LVEWX(u32 vd, u32 ra, u32 rb) + { + DisAsm_V1_R2("lvewx", vd, ra, rb); + } + void MULHD(u32 rd, u32 ra, u32 rb, bool rc) + { + DisAsm_R3_RC("mulhd", rd, ra, rb, rc); + } + void MULHW(u32 rd, u32 ra, u32 rb, bool rc) + { + DisAsm_R3_RC("mulhw", rd, ra, rb, rc); + } + void LDARX(u32 rd, u32 ra, u32 rb) + { + DisAsm_R3("ldarx", rd, ra, rb); + } + void DCBF(u32 ra, u32 rb) + { + DisAsm_R2("dcbf", ra, rb); + } + void LBZX(u32 rd, u32 ra, u32 rb) + { + DisAsm_R3("lbzx", rd, ra, rb); + } + void LVX(u32 vd, u32 ra, u32 rb) + { + DisAsm_V1_R2("lvx", vd, ra, rb); + } + void NEG(u32 rd, u32 ra, u32 oe, bool rc) + { + DisAsm_R2_OE_RC("neg", rd, ra, oe, rc); + } + void LBZUX(u32 rd, u32 ra, u32 rb) + { + DisAsm_R3("lbzux", rd, ra, rb); + } + void NOR(u32 ra, u32 rs, u32 rb, bool rc) + { + if(rs == rb) + { + DisAsm_R2_RC("not", ra, rs, rc); + } + else + { + DisAsm_R3_RC("nor", ra, rs, rb, rc); + } + } + void STVEBX(u32 vs, u32 ra, u32 rb) + { + DisAsm_V1_R2("stvebx", vs, ra, rb); + } + void SUBFE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + DisAsm_R3_OE_RC("subfe", rd, ra, rb, oe, rc); + } + void ADDE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + DisAsm_R3_OE_RC("adde", rd, ra, rb, oe, rc); + } + void MTOCRF(u32 crm, u32 rs) + { + DisAsm_INT1_R1("mtocrf", crm, rs); + } + void STDX(u32 rs, u32 ra, u32 rb) + { + DisAsm_R3("stdx.", rs, ra, rb); + } + void STWCX_(u32 rs, u32 ra, u32 rb) + { + DisAsm_R3("stwcx.", rs, ra, rb); + } + void STWX(u32 rs, u32 ra, u32 rb) + { + DisAsm_R3("stwx", rs, ra, rb); + } + void STVEHX(u32 vs, u32 ra, u32 rb) + { + DisAsm_V1_R2("stvehx", vs, ra, rb); + } + void STDUX(u32 rs, u32 ra, u32 rb) + { + DisAsm_R3("stdux", rs, ra, rb); + } + void STVEWX(u32 vs, u32 ra, u32 rb) + { + DisAsm_V1_R2("stvewx", vs, ra, rb); + } + void ADDZE(u32 rd, u32 ra, u32 oe, bool rc) + { + DisAsm_R2_OE_RC("addze", rd, ra, oe, rc); + } + void STDCX_(u32 rs, u32 ra, u32 rb) + { + DisAsm_R3("stdcx.", rs, ra, rb); + } + void STBX(u32 rs, u32 ra, u32 rb) + { + DisAsm_R3("stbx", rs, ra, rb); + } + void STVX(u32 vd, u32 ra, u32 rb) + { + DisAsm_V1_R2("stvx", vd, ra, rb); + } + void MULLD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + DisAsm_R3_OE_RC("mulld", rd, ra, rb, oe, rc); + } + void ADDME(u32 rd, u32 ra, u32 oe, bool rc) + { + DisAsm_R2_OE_RC("addme", rd, ra, oe, rc); + } + void MULLW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + DisAsm_R3_OE_RC("mullw", rd, ra, rb, oe, rc); + } + void DCBTST(u32 th, u32 ra, u32 rb) + { + DisAsm_R3("dcbtst", th, ra, rb); + } + void ADD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + DisAsm_R3_OE_RC("add", rd, ra, rb, oe, rc); + } + void DCBT(u32 ra, u32 rb, u32 th) + { + DisAsm_R2("dcbt", ra, rb); + } + void LHZX(u32 rd, u32 ra, u32 rb) + { + DisAsm_R3("lhzx", rd, ra, rb); + } + void EQV(u32 ra, u32 rs, u32 rb, bool rc) + { + DisAsm_R3_RC("eqv", ra, rs, rb, rc); + } + void ECIWX(u32 rd, u32 ra, u32 rb) + { + DisAsm_R3("eciwx", rd, ra, rb); + } + void LHZUX(u32 rd, u32 ra, u32 rb) + { + DisAsm_R3("lhzux", rd, ra, rb); + } + void XOR(u32 ra, u32 rs, u32 rb, bool rc) + { + DisAsm_R3_RC("xor", ra, rs, rb, rc); + } + void MFSPR(u32 rd, u32 spr) + { + const u32 n = (spr >> 5) | ((spr & 0x1f) << 5); + switch(n) + { + case 0x001: DisAsm_R1("mfxer", rd); break; + case 0x008: DisAsm_R1("mflr", rd); break; + case 0x009: DisAsm_R1("mfctr", rd); break; + default: DisAsm_R1_IMM("mfspr", rd, spr); break; + } + } + void DST(u32 ra, u32 rb, u32 strm, u32 t) + { + if(t) + { + DisAsm_R2_INT1("dstt", ra, rb, strm); + } + else + { + DisAsm_R2_INT1("dst", ra, rb, strm); + } + } + void LHAX(u32 rd, u32 ra, u32 rb) + { + DisAsm_R3("lhax", rd, ra, rb); + } + void LVXL(u32 vd, u32 ra, u32 rb) + { + DisAsm_V1_R2("lvxl", vd, ra, rb); + } + void ABS(u32 rd, u32 ra, u32 oe, bool rc) + { + DisAsm_R2_OE_RC("abs", rd, ra, oe, rc); + } + void MFTB(u32 rd, u32 spr) + { + const u32 n = (spr >> 5) | ((spr & 0x1f) << 5); + switch(n) + { + case 268: DisAsm_R1("mftb", rd); break; + case 269: DisAsm_R1("mftbu", rd); break; + default: DisAsm_R1_IMM("mftb", rd, spr); break; + } + } + void DSTST(u32 ra, u32 rb, u32 strm, u32 t) + { + if(t) + { + DisAsm_R2_INT1("dststt", ra, rb, strm); + } + else + { + DisAsm_R2_INT1("dstst", ra, rb, strm); + } + } + void LHAUX(u32 rd, u32 ra, u32 rb) + { + DisAsm_R3("lhaux", rd, ra, rb); + } + void STHX(u32 rs, u32 ra, u32 rb) + { + DisAsm_R3("sthx", rs, ra, rb); + } + void ORC(u32 ra, u32 rs, u32 rb, bool rc) + { + DisAsm_R3_RC("orc", ra, rs, rb, rc); + } + void ECOWX(u32 rs, u32 ra, u32 rb) + { + DisAsm_R3("ecowx", rs, ra, rb); + } + void OR(u32 ra, u32 rs, u32 rb, bool rc) + { + if(rs==rb) + { + DisAsm_R2_RC("mr", ra, rb, rc); + } + else + { + DisAsm_R3_RC("or", ra, rs, rb, rc); + } + } + void DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + DisAsm_R3_OE_RC("divdu", rd, ra, rb, oe, rc); + } + void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + DisAsm_R3_OE_RC("divwu", rd, ra, rb, oe, rc); + } + void MTSPR(u32 spr, u32 rs) + { + const u32 n = (spr & 0x1f) + ((spr >> 5) & 0x1f); - START_OPCODES_GROUP(G_1e) - void RLDICL(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, bool rc) - { - if(sh == 0) - { - DisAsm_R2_INT1_RC("clrldi", ra, rs, mb, rc); - } - else if(mb == 0) - { - DisAsm_R2_INT1_RC("rotldi", ra, rs, sh, rc); - } - else if(mb == 64 - sh) - { - DisAsm_R2_INT1_RC("srdi", ra, rs, mb, rc); - } - else - { - DisAsm_R2_INT2_RC("rldicl", ra, rs, sh, mb, rc); - } - } - void RLDICR(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG me, bool rc) - { - DisAsm_R2_INT2_RC("rldicr", ra, rs, sh, me, rc); - } - void RLDIC(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, bool rc) - { - DisAsm_R2_INT2_RC("rldic", ra, rs, sh, mb, rc); - } - void RLDIMI(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, bool rc) - { - DisAsm_R2_INT2_RC("rldimi", ra, rs, sh, mb, rc); - } - END_OPCODES_GROUP(G_1e); - - START_OPCODES_GROUP(G_1f) - void CMP(OP_REG crfd, OP_REG l, OP_REG ra, OP_REG rb) - { - DisAsm_CR1_R2(wxString::Format("cmp%s", l ? "d" : "w"), crfd, ra, rb); - } - void TW(OP_REG to, OP_REG ra, OP_REG rb) - { - DisAsm_INT1_R2("tw", to, ra, rb); - } - void LVSL(OP_REG vd, OP_REG ra, OP_REG rb) - { - DisAsm_V1_R2("lvsl", vd, ra, rb); - } - void LVEBX(OP_REG vd, OP_REG ra, OP_REG rb) - { - DisAsm_V1_R2("lvebx", vd, ra, rb); - } - void SUBFC(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - DisAsm_R3_OE_RC("subfc", rd, ra, rb, oe, rc); - } - void ADDC(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - DisAsm_R3_OE_RC("addc", rd, ra, rb, oe, rc); - } - void MULHDU(OP_REG rd, OP_REG ra, OP_REG rb, bool rc) - { - DisAsm_R3_RC("mulhdu", rd, ra, rb, rc); - } - void MULHWU(OP_REG rd, OP_REG ra, OP_REG rb, bool rc) - { - DisAsm_R3_RC("mulhwu", rd, ra, rb, rc); - } - void MFOCRF(OP_uIMM a, OP_REG rd, OP_uIMM crm) - { - if(a) - { - DisAsm_R1_IMM("mfocrf", rd, crm); - } - else - { - DisAsm_R1("mfcr", rd); - } - } - void LWARX(OP_REG rd, OP_REG ra, OP_REG rb) - { - DisAsm_R3("lwarx", rd, ra, rb); - } - void LDX(OP_REG ra, OP_REG rs, OP_REG rb) - { - DisAsm_R3("ldx", ra, rs, rb); - } - void LWZX(OP_REG rd, OP_REG ra, OP_REG rb) - { - DisAsm_R3("lwzx", rd, ra, rb); - } - void SLW(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - DisAsm_R3_RC("slw", ra, rs, rb, rc); - } - void CNTLZW(OP_REG ra, OP_REG rs, bool rc) - { - DisAsm_R2_RC("cntlzw", ra, rs, rc); - } - void SLD(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - DisAsm_R3_RC("sld", ra, rs, rb, rc); - } - void AND(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - DisAsm_R3_RC("and", ra, rs, rb, rc); - } - void CMPL(OP_REG crfd, OP_REG l, OP_REG ra, OP_REG rb) - { - DisAsm_CR1_R2(wxString::Format("cmpl%s", l ? "d" : "w"), crfd, ra, rb); - } - void LVSR(OP_REG vd, OP_REG ra, OP_REG rb) - { - DisAsm_V1_R2("lvsr", vd, ra, rb); - } - void LVEHX(OP_REG vd, OP_REG ra, OP_REG rb) - { - DisAsm_V1_R2("lvehx", vd, ra, rb); - } - void SUBF(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - DisAsm_R3_OE_RC("subf", rd, ra, rb, oe, rc); - } - void LDUX(OP_REG rd, OP_REG ra, OP_REG rb) - { - DisAsm_R3("ldux", rd, ra, rb); - } - void DCBST(OP_REG ra, OP_REG rb) - { - DisAsm_R2("dcbst", ra, rb); - } - void CNTLZD(OP_REG ra, OP_REG rs, bool rc) - { - DisAsm_R2_RC("cntlzd", ra, rs, rc); - } - void ANDC(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - DisAsm_R3_RC("andc", ra, rs, rb, rc); - } - void LVEWX(OP_REG vd, OP_REG ra, OP_REG rb) - { - DisAsm_V1_R2("lvewx", vd, ra, rb); - } - void MULHD(OP_REG rd, OP_REG ra, OP_REG rb, bool rc) - { - DisAsm_R3_RC("mulhd", rd, ra, rb, rc); - } - void MULHW(OP_REG rd, OP_REG ra, OP_REG rb, bool rc) - { - DisAsm_R3_RC("mulhw", rd, ra, rb, rc); - } - void LDARX(OP_REG rd, OP_REG ra, OP_REG rb) - { - DisAsm_R3("ldarx", rd, ra, rb); - } - void DCBF(OP_REG ra, OP_REG rb) - { - DisAsm_R2("dcbf", ra, rb); - } - void LBZX(OP_REG rd, OP_REG ra, OP_REG rb) - { - DisAsm_R3("lbzx", rd, ra, rb); - } - void LVX(OP_REG vd, OP_REG ra, OP_REG rb) - { - DisAsm_V1_R2("lvx", vd, ra, rb); - } - void NEG(OP_REG rd, OP_REG ra, OP_REG oe, bool rc) - { - DisAsm_R2_OE_RC("neg", rd, ra, oe, rc); - } - void LBZUX(OP_REG rd, OP_REG ra, OP_REG rb) - { - DisAsm_R3("lbzux", rd, ra, rb); - } - void NOR(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - if(rs == rb) - { - DisAsm_R2_RC("not", ra, rs, rc); - } - else - { - DisAsm_R3_RC("nor", ra, rs, rb, rc); - } - } - void STVEBX(OP_REG vs, OP_REG ra, OP_REG rb) - { - DisAsm_V1_R2("stvebx", vs, ra, rb); - } - void SUBFE(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - DisAsm_R3_OE_RC("subfe", rd, ra, rb, oe, rc); - } - void ADDE(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - DisAsm_R3_OE_RC("adde", rd, ra, rb, oe, rc); - } - void MTOCRF(OP_REG crm, OP_REG rs) - { - DisAsm_INT1_R1("mtocrf", crm, rs); - } - void STDX(OP_REG rs, OP_REG ra, OP_REG rb) - { - DisAsm_R3("stdx.", rs, ra, rb); - } - void STWCX_(OP_REG rs, OP_REG ra, OP_REG rb) - { - DisAsm_R3("stwcx.", rs, ra, rb); - } - void STWX(OP_REG rs, OP_REG ra, OP_REG rb) - { - DisAsm_R3("stwx", rs, ra, rb); - } - void STVEHX(OP_REG vs, OP_REG ra, OP_REG rb) - { - DisAsm_V1_R2("stvehx", vs, ra, rb); - } - void STDUX(OP_REG rs, OP_REG ra, OP_REG rb) - { - DisAsm_R3("stdux", rs, ra, rb); - } - void STVEWX(OP_REG vs, OP_REG ra, OP_REG rb) - { - DisAsm_V1_R2("stvewx", vs, ra, rb); - } - void ADDZE(OP_REG rd, OP_REG ra, OP_REG oe, bool rc) - { - DisAsm_R2_OE_RC("addze", rd, ra, oe, rc); - } - void STDCX_(OP_REG rs, OP_REG ra, OP_REG rb) - { - DisAsm_R3("stdcx.", rs, ra, rb); - } - void STBX(OP_REG rs, OP_REG ra, OP_REG rb) - { - DisAsm_R3("stbx", rs, ra, rb); - } - void STVX(OP_REG vd, OP_REG ra, OP_REG rb) - { - DisAsm_V1_R2("stvx", vd, ra, rb); - } - void MULLD(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - DisAsm_R3_OE_RC("mulld", rd, ra, rb, oe, rc); - } - void ADDME(OP_REG rd, OP_REG ra, OP_REG oe, bool rc) - { - DisAsm_R2_OE_RC("addme", rd, ra, oe, rc); - } - void MULLW(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - DisAsm_R3_OE_RC("mullw", rd, ra, rb, oe, rc); - } - void DCBTST(OP_REG th, OP_REG ra, OP_REG rb) - { - DisAsm_R3("dcbtst", th, ra, rb); - } - void ADD(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - DisAsm_R3_OE_RC("add", rd, ra, rb, oe, rc); - } - void DCBT(OP_REG ra, OP_REG rb, OP_REG th) - { - DisAsm_R2("dcbt", ra, rb); - } - void LHZX(OP_REG rd, OP_REG ra, OP_REG rb) - { - DisAsm_R3("lhzx", rd, ra, rb); - } - void EQV(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - DisAsm_R3_RC("eqv", ra, rs, rb, rc); - } - void ECIWX(OP_REG rd, OP_REG ra, OP_REG rb) - { - DisAsm_R3("eciwx", rd, ra, rb); - } - void LHZUX(OP_REG rd, OP_REG ra, OP_REG rb) - { - DisAsm_R3("lhzux", rd, ra, rb); - } - void XOR(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - DisAsm_R3_RC("xor", ra, rs, rb, rc); - } - void MFSPR(OP_REG rd, OP_REG spr) - { - const u32 n = (spr >> 5) | ((spr & 0x1f) << 5); - switch(n) - { - case 0x001: DisAsm_R1("mfxer", rd); break; - case 0x008: DisAsm_R1("mflr", rd); break; - case 0x009: DisAsm_R1("mfctr", rd); break; - default: DisAsm_R1_IMM("mfspr", rd, spr); break; - } - } - void DST(OP_REG ra, OP_REG rb, OP_uIMM strm, OP_uIMM t) - { - if(t) - { - DisAsm_R2_INT1("dstt", ra, rb, strm); - } - else - { - DisAsm_R2_INT1("dst", ra, rb, strm); - } - } - void LHAX(OP_REG rd, OP_REG ra, OP_REG rb) - { - DisAsm_R3("lhax", rd, ra, rb); - } - void LVXL(OP_REG vd, OP_REG ra, OP_REG rb) - { - DisAsm_V1_R2("lvxl", vd, ra, rb); - } - void ABS(OP_REG rd, OP_REG ra, OP_REG oe, bool rc) - { - DisAsm_R2_OE_RC("abs", rd, ra, oe, rc); - } - void MFTB(OP_REG rd, OP_REG spr) - { - const u32 n = (spr >> 5) | ((spr & 0x1f) << 5); - switch(n) - { - case 268: DisAsm_R1("mftb", rd); break; - case 269: DisAsm_R1("mftbu", rd); break; - default: DisAsm_R1_IMM("mftb", rd, spr); break; - } - } - void DSTST(OP_REG ra, OP_REG rb, OP_uIMM strm, OP_uIMM t) - { - if(t) - { - DisAsm_R2_INT1("dststt", ra, rb, strm); - } - else - { - DisAsm_R2_INT1("dstst", ra, rb, strm); - } - } - void LHAUX(OP_REG rd, OP_REG ra, OP_REG rb) - { - DisAsm_R3("lhaux", rd, ra, rb); - } - void STHX(OP_REG rs, OP_REG ra, OP_REG rb) - { - DisAsm_R3("sthx", rs, ra, rb); - } - void ORC(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - DisAsm_R3_RC("orc", ra, rs, rb, rc); - } - void ECOWX(OP_REG rs, OP_REG ra, OP_REG rb) - { - DisAsm_R3("ecowx", rs, ra, rb); - } - void OR(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - if(rs==rb) - { - DisAsm_R2_RC("mr", ra, rb, rc); - } - else - { - DisAsm_R3_RC("or", ra, rs, rb, rc); - } - } - void DIVDU(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - DisAsm_R3_OE_RC("divdu", rd, ra, rb, oe, rc); - } - void DIVWU(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - DisAsm_R3_OE_RC("divwu", rd, ra, rb, oe, rc); - } - void MTSPR(OP_REG spr, OP_REG rs) - { - const u32 n = (spr & 0x1f) + ((spr >> 5) & 0x1f); - - switch(n) - { - case 0x001: DisAsm_R1("mtxer", rs); break; - case 0x008: DisAsm_R1("mtlr", rs); break; - case 0x009: DisAsm_R1("mtctr", rs); break; - default: DisAsm_IMM_R1("mtspr", spr, rs); break; - } - } - /*0x1d6*///DCBI - void NAND(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - DisAsm_R3_RC("nand", ra, rs, rb, rc); - } - void STVXL(OP_REG vs, OP_REG ra, OP_REG rb) - { - DisAsm_V1_R2("stvxl", vs, ra, rb); - } - void DIVD(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - DisAsm_R3_OE_RC("divd", rd, ra, rb, oe, rc); - } - void DIVW(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - DisAsm_R3_OE_RC("divw", rd, ra, rb, oe, rc); - } - void LVLX(OP_REG vd, OP_REG ra, OP_REG rb) - { - DisAsm_V1_R2("lvlx", vd, ra, rb); - } - void LWBRX(OP_REG rd, OP_REG ra, OP_REG rb) - { - DisAsm_R3("lwbrx", rd, ra, rb); - } - void LFSX(OP_REG frd, OP_REG ra, OP_REG rb) - { - DisAsm_F1_R2("lfsx", frd, ra, rb); - } - void SRW(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - DisAsm_R3_RC("srw", ra, rs, rb, rc); - } - void SRD(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - DisAsm_R3_RC("srd", ra, rs, rb, rc); - } - void LVRX(OP_REG vd, OP_REG ra, OP_REG rb) - { - DisAsm_V1_R2("lvrx", vd, ra, rb); - } - void LFSUX(OP_REG frd, OP_REG ra, OP_REG rb) - { - DisAsm_F1_R2("lfsux", frd, ra, rb); - } - void SYNC(OP_uIMM l) - { - DisAsm_INT1("sync", l); - } - void LFDX(OP_REG frd, OP_REG ra, OP_REG rb) - { - DisAsm_F1_R2("lfdx", frd, ra, rb); - } - void LFDUX(OP_REG frd, OP_REG ra, OP_REG rb) - { - DisAsm_F1_R2("lfdux", frd, ra, rb); - } - void STVLX(OP_REG sd, OP_REG ra, OP_REG rb) - { - DisAsm_V1_R2("stvlx", sd, ra, rb); - } - void STFSX(OP_REG frs, OP_REG ra, OP_REG rb) - { - DisAsm_F1_R2("stfsx", frs, ra, rb); - } - void STVRX(OP_REG sd, OP_REG ra, OP_REG rb) - { - DisAsm_V1_R2("stvrx", sd, ra, rb); - } - void STFDX(OP_REG frs, OP_REG ra, OP_REG rb) - { - DisAsm_F1_R2("stfdx", frs, ra, rb); - } - void LVLXL(OP_REG vd, OP_REG ra, OP_REG rb) - { - DisAsm_V1_R2("lvlxl", vd, ra, rb); - } - void LHBRX(OP_REG rd, OP_REG ra, OP_REG rb) - { - DisAsm_R3("lhbrx", rd, ra, rb); - } - void SRAW(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - DisAsm_R3_RC("sraw", ra, rs, rb, rc); - } - void SRAD(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - DisAsm_R3_RC("srad", ra, rs, rb, rc); - } - void LVRXL(OP_REG vd, OP_REG ra, OP_REG rb) - { - DisAsm_V1_R2("lvrxl", vd, ra, rb); - } - void DSS(OP_uIMM strm, OP_uIMM a) - { - if(a) - { - Write("dssall"); - } - else - { - DisAsm_INT1("dss", strm); - } - } - void SRAWI(OP_REG ra, OP_REG rs, OP_REG sh, bool rc) - { - DisAsm_R2_INT1_RC("srawi", ra, rs, sh, rc); - } - void SRADI1(OP_REG ra, OP_REG rs, OP_REG sh, bool rc) - { - DisAsm_R2_INT1_RC("sradi", ra, rs, sh, rc); - } - void SRADI2(OP_REG ra, OP_REG rs, OP_REG sh, bool rc) - { - DisAsm_R2_INT1_RC("sradi", ra, rs, sh, rc); - } - void EIEIO() - { - Write("eieio"); - } - void STVLXL(OP_REG sd, OP_REG ra, OP_REG rb) - { - DisAsm_V1_R2("stvlxl", sd, ra, rb); - } - void EXTSH(OP_REG ra, OP_REG rs, bool rc) - { - DisAsm_R2_RC("extsh", ra, rs, rc); - } - void STVRXL(OP_REG sd, OP_REG ra, OP_REG rb) - { - DisAsm_V1_R2("stvrxl", sd, ra, rb); - } - void EXTSB(OP_REG ra, OP_REG rs, bool rc) - { - DisAsm_R2_RC("extsb", ra, rs, rc); - } - void STFIWX(OP_REG frs, OP_REG ra, OP_REG rb) - { - DisAsm_F1_R2("stfiwx", frs, ra, rb); - } - void EXTSW(OP_REG ra, OP_REG rs, bool rc) - { - DisAsm_R2_RC("extsw", ra, rs, rc); - } - /*0x3d6*///ICBI - void DCBZ(OP_REG ra, OP_REG rs) - { - DisAsm_R2("dcbz", ra, rs); - } - END_OPCODES_GROUP(G_1f); - - void LWZ(OP_REG rd, OP_REG ra, OP_sIMM d) + switch(n) + { + case 0x001: DisAsm_R1("mtxer", rs); break; + case 0x008: DisAsm_R1("mtlr", rs); break; + case 0x009: DisAsm_R1("mtctr", rs); break; + default: DisAsm_IMM_R1("mtspr", spr, rs); break; + } + } + /*0x1d6*///DCBI + void NAND(u32 ra, u32 rs, u32 rb, bool rc) + { + DisAsm_R3_RC("nand", ra, rs, rb, rc); + } + void STVXL(u32 vs, u32 ra, u32 rb) + { + DisAsm_V1_R2("stvxl", vs, ra, rb); + } + void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + DisAsm_R3_OE_RC("divd", rd, ra, rb, oe, rc); + } + void DIVW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + DisAsm_R3_OE_RC("divw", rd, ra, rb, oe, rc); + } + void LVLX(u32 vd, u32 ra, u32 rb) + { + DisAsm_V1_R2("lvlx", vd, ra, rb); + } + void LWBRX(u32 rd, u32 ra, u32 rb) + { + DisAsm_R3("lwbrx", rd, ra, rb); + } + void LFSX(u32 frd, u32 ra, u32 rb) + { + DisAsm_F1_R2("lfsx", frd, ra, rb); + } + void SRW(u32 ra, u32 rs, u32 rb, bool rc) + { + DisAsm_R3_RC("srw", ra, rs, rb, rc); + } + void SRD(u32 ra, u32 rs, u32 rb, bool rc) + { + DisAsm_R3_RC("srd", ra, rs, rb, rc); + } + void LVRX(u32 vd, u32 ra, u32 rb) + { + DisAsm_V1_R2("lvrx", vd, ra, rb); + } + void LFSUX(u32 frd, u32 ra, u32 rb) + { + DisAsm_F1_R2("lfsux", frd, ra, rb); + } + void SYNC(u32 l) + { + DisAsm_INT1("sync", l); + } + void LFDX(u32 frd, u32 ra, u32 rb) + { + DisAsm_F1_R2("lfdx", frd, ra, rb); + } + void LFDUX(u32 frd, u32 ra, u32 rb) + { + DisAsm_F1_R2("lfdux", frd, ra, rb); + } + void STVLX(u32 sd, u32 ra, u32 rb) + { + DisAsm_V1_R2("stvlx", sd, ra, rb); + } + void STFSX(u32 frs, u32 ra, u32 rb) + { + DisAsm_F1_R2("stfsx", frs, ra, rb); + } + void STVRX(u32 sd, u32 ra, u32 rb) + { + DisAsm_V1_R2("stvrx", sd, ra, rb); + } + void STFDX(u32 frs, u32 ra, u32 rb) + { + DisAsm_F1_R2("stfdx", frs, ra, rb); + } + void LVLXL(u32 vd, u32 ra, u32 rb) + { + DisAsm_V1_R2("lvlxl", vd, ra, rb); + } + void LHBRX(u32 rd, u32 ra, u32 rb) + { + DisAsm_R3("lhbrx", rd, ra, rb); + } + void SRAW(u32 ra, u32 rs, u32 rb, bool rc) + { + DisAsm_R3_RC("sraw", ra, rs, rb, rc); + } + void SRAD(u32 ra, u32 rs, u32 rb, bool rc) + { + DisAsm_R3_RC("srad", ra, rs, rb, rc); + } + void LVRXL(u32 vd, u32 ra, u32 rb) + { + DisAsm_V1_R2("lvrxl", vd, ra, rb); + } + void DSS(u32 strm, u32 a) + { + if(a) + { + Write("dssall"); + } + else + { + DisAsm_INT1("dss", strm); + } + } + void SRAWI(u32 ra, u32 rs, u32 sh, bool rc) + { + DisAsm_R2_INT1_RC("srawi", ra, rs, sh, rc); + } + void SRADI1(u32 ra, u32 rs, u32 sh, bool rc) + { + DisAsm_R2_INT1_RC("sradi", ra, rs, sh, rc); + } + void SRADI2(u32 ra, u32 rs, u32 sh, bool rc) + { + DisAsm_R2_INT1_RC("sradi", ra, rs, sh, rc); + } + void EIEIO() + { + Write("eieio"); + } + void STVLXL(u32 sd, u32 ra, u32 rb) + { + DisAsm_V1_R2("stvlxl", sd, ra, rb); + } + void EXTSH(u32 ra, u32 rs, bool rc) + { + DisAsm_R2_RC("extsh", ra, rs, rc); + } + void STVRXL(u32 sd, u32 ra, u32 rb) + { + DisAsm_V1_R2("stvrxl", sd, ra, rb); + } + void EXTSB(u32 ra, u32 rs, bool rc) + { + DisAsm_R2_RC("extsb", ra, rs, rc); + } + void STFIWX(u32 frs, u32 ra, u32 rb) + { + DisAsm_F1_R2("stfiwx", frs, ra, rb); + } + void EXTSW(u32 ra, u32 rs, bool rc) + { + DisAsm_R2_RC("extsw", ra, rs, rc); + } + /*0x3d6*///ICBI + void DCBZ(u32 ra, u32 rs) + { + DisAsm_R2("dcbz", ra, rs); + } + void LWZ(u32 rd, u32 ra, s32 d) { DisAsm_R2_IMM("lwz", rd, ra, d); } - void LWZU(OP_REG rd, OP_REG ra, OP_sIMM d) + void LWZU(u32 rd, u32 ra, s32 d) { DisAsm_R2_IMM("lwzu", rd, ra, d); } - void LBZ(OP_REG rd, OP_REG ra, OP_sIMM d) + void LBZ(u32 rd, u32 ra, s32 d) { DisAsm_R2_IMM("lbz", rd, ra, d); } - void LBZU(OP_REG rd, OP_REG ra, OP_sIMM d) + void LBZU(u32 rd, u32 ra, s32 d) { DisAsm_R2_IMM("lbzu", rd, ra, d); } - void STW(OP_REG rs, OP_REG ra, OP_sIMM d) + void STW(u32 rs, u32 ra, s32 d) { DisAsm_R2_IMM("stw", rs, ra, d); } - void STWU(OP_REG rs, OP_REG ra, OP_sIMM d) + void STWU(u32 rs, u32 ra, s32 d) { DisAsm_R2_IMM("stwu", rs, ra, d); } - void STB(OP_REG rs, OP_REG ra, OP_sIMM d) + void STB(u32 rs, u32 ra, s32 d) { DisAsm_R2_IMM("stb", rs, ra, d); } - void STBU(OP_REG rs, OP_REG ra, OP_sIMM d) + void STBU(u32 rs, u32 ra, s32 d) { DisAsm_R2_IMM("stbu", rs, ra, d); } - void LHZ(OP_REG rs, OP_REG ra, OP_sIMM d) + void LHZ(u32 rs, u32 ra, s32 d) { DisAsm_R2_IMM("lhz", rs, ra, d); } - void LHZU(OP_REG rs, OP_REG ra, OP_sIMM d) + void LHZU(u32 rs, u32 ra, s32 d) { DisAsm_R2_IMM("lhzu", rs, ra, d); } - void STH(OP_REG rs, OP_REG ra, OP_sIMM d) + void STH(u32 rs, u32 ra, s32 d) { DisAsm_R2_IMM("sth", rs, ra, d); } - void STHU(OP_REG rs, OP_REG ra, OP_sIMM d) + void STHU(u32 rs, u32 ra, s32 d) { DisAsm_R2_IMM("sthu", rs, ra, d); } - void LMW(OP_REG rd, OP_REG ra, OP_sIMM d) + void LMW(u32 rd, u32 ra, s32 d) { DisAsm_R2_IMM("lmw", rd, ra, d); } - void STMW(OP_REG rs, OP_REG ra, OP_sIMM d) + void STMW(u32 rs, u32 ra, s32 d) { DisAsm_R2_IMM("stmw", rs, ra, d); } - void LFS(OP_REG frd, OP_REG ra, OP_sIMM d) + void LFS(u32 frd, u32 ra, s32 d) { DisAsm_F1_IMM_R1("lfs", frd, d, ra); } - void LFSU(OP_REG frd, OP_REG ra, OP_sIMM ds) + void LFSU(u32 frd, u32 ra, s32 ds) { DisAsm_F1_IMM_R1("lfsu", frd, ds, ra); } - void LFD(OP_REG frd, OP_REG ra, OP_sIMM d) + void LFD(u32 frd, u32 ra, s32 d) { DisAsm_F1_IMM_R1("lfd", frd, d, ra); } - void LFDU(OP_REG frd, OP_REG ra, OP_sIMM ds) + void LFDU(u32 frd, u32 ra, s32 ds) { DisAsm_F1_IMM_R1("lfdu", frd, ds, ra); } - void STFS(OP_REG frs, OP_REG ra, OP_sIMM d) + void STFS(u32 frs, u32 ra, s32 d) { DisAsm_F1_IMM_R1("stfs", frs, d, ra); } - void STFSU(OP_REG frs, OP_REG ra, OP_sIMM d) + void STFSU(u32 frs, u32 ra, s32 d) { DisAsm_F1_IMM_R1("stfsu", frs, d, ra); } - void STFD(OP_REG frs, OP_REG ra, OP_sIMM d) + void STFD(u32 frs, u32 ra, s32 d) { DisAsm_F1_IMM_R1("stfd", frs, d, ra); } - void STFDU(OP_REG frs, OP_REG ra, OP_sIMM d) + void STFDU(u32 frs, u32 ra, s32 d) { DisAsm_F1_IMM_R1("stfdu", frs, d, ra); } - - START_OPCODES_GROUP(G_3a) - void LD(OP_REG rd, OP_REG ra, OP_sIMM ds) - { - DisAsm_R2_IMM("ld", rd, ra, ds); - } - void LDU(OP_REG rd, OP_REG ra, OP_sIMM ds) - { - DisAsm_R2_IMM("ldu", rd, ra, ds); - } - END_OPCODES_GROUP(G_3a); - - START_OPCODES_GROUP(G_3b) - void FDIVS(OP_REG frd, OP_REG fra, OP_REG frb, bool rc) - { - DisAsm_F3_RC("fdivs", frd, fra, frb, rc); - } - void FSUBS(OP_REG frd, OP_REG fra, OP_REG frb, bool rc) - { - DisAsm_F3_RC("fsubs", frd, fra, frb, rc); - } - void FADDS(OP_REG frd, OP_REG fra, OP_REG frb, bool rc) - { - DisAsm_F3_RC("fadds", frd, fra, frb, rc); - } - void FSQRTS(OP_REG frd, OP_REG frb, bool rc) - { - DisAsm_F2_RC("fsqrts", frd, frb, rc); - } - void FRES(OP_REG frd, OP_REG frb, bool rc) - { - DisAsm_F2_RC("fres", frd, frb, rc); - } - void FMULS(OP_REG frd, OP_REG fra, OP_REG frc, bool rc) - { - DisAsm_F3_RC("fmuls", frd, fra, frc, rc); - } - void FMADDS(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc) - { - DisAsm_F4_RC("fmadds", frd, fra, frc, frb, rc); - } - void FMSUBS(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc) - { - DisAsm_F4_RC("fmsubs", frd, fra, frc, frb, rc); - } - void FNMSUBS(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc) - { - DisAsm_F4_RC("fnmsubs", frd, fra, frc, frb, rc); - } - void FNMADDS(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc) - { - DisAsm_F4_RC("fnmadds", frd, fra, frc, frb, rc); - } - END_OPCODES_GROUP(G_3b); - - START_OPCODES_GROUP(G_3e) - void STD(OP_REG rs, OP_REG ra, OP_sIMM ds) - { - DisAsm_R2_IMM("std", rs, ra, ds); - } - void STDU(OP_REG rs, OP_REG ra, OP_sIMM ds) - { - DisAsm_R2_IMM("stdu", rs, ra, ds); - } - END_OPCODES_GROUP(G_3e); - - START_OPCODES_GROUP(G_3f) - void MTFSB1(OP_REG bt, bool rc) - { - DisAsm_F1_RC("mtfsb1", bt, rc); - } - void MCRFS(OP_REG bf, OP_REG bfa) - { - DisAsm_F2("mcrfs", bf, bfa); - } - void MTFSB0(OP_REG bt, bool rc) - { - DisAsm_F1_RC("mtfsb0", bt, rc); - } - void MTFSFI(OP_REG crfd, OP_REG i, bool rc) - { - DisAsm_F2_RC("mtfsfi", crfd, i, rc); - } - void MFFS(OP_REG frd, bool rc) - { - DisAsm_F1_RC("mffs", frd, rc); - } - void MTFSF(OP_REG flm, OP_REG frb, bool rc) - { - DisAsm_F2_RC("mtfsf", flm, frb, rc); - } - void FCMPU(OP_REG crfd, OP_REG fra, OP_REG frb) - { - DisAsm_CR1_F2("fcmpu", crfd, fra, frb); - } - void FRSP(OP_REG frd, OP_REG frb, bool rc) - { - DisAsm_F2_RC("frsp", frd, frb, rc); - } - void FCTIW(OP_REG frd, OP_REG frb, bool rc) - { - DisAsm_F2_RC("fctiw", frd, frb, rc); - } - void FCTIWZ(OP_REG frd, OP_REG frb, bool rc) - { - DisAsm_F2_RC("fctiwz", frd, frb, rc); - } - void FDIV(OP_REG frd, OP_REG fra, OP_REG frb, bool rc) - { - DisAsm_F3_RC("fdiv", frd, fra, frb, rc); - } - void FSUB(OP_REG frd, OP_REG fra, OP_REG frb, bool rc) - { - DisAsm_F3_RC("fsub", frd, fra, frb, rc); - } - void FADD(OP_REG frd, OP_REG fra, OP_REG frb, bool rc) - { - DisAsm_F3_RC("fadd", frd, fra, frb, rc); - } - void FSQRT(OP_REG frd, OP_REG frb, bool rc) - { - DisAsm_F2_RC("fsqrt", frd, frb, rc); - } - void FSEL(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc) - { - DisAsm_F4_RC("fsel", frd, fra, frc, frb, rc); - } - void FMUL(OP_REG frd, OP_REG fra, OP_REG frc, bool rc) - { - DisAsm_F3_RC("fmul", frd, fra, frc, rc); - } - void FRSQRTE(OP_REG frd, OP_REG frb, bool rc) - { - DisAsm_F2_RC("frsqrte", frd, frb, rc); - } - void FMSUB(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc) - { - DisAsm_F4_RC("fmsub", frd, fra, frc, frb, rc); - } - void FMADD(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc) - { - DisAsm_F4_RC("fmadd", frd, fra, frc, frb, rc); - } - void FNMSUB(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc) - { - DisAsm_F4_RC("fnmsub", frd, fra, frc, frb, rc); - } - void FNMADD(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc) - { - DisAsm_F4_RC("fnmadd", frd, fra, frc, frb, rc); - } - void FCMPO(OP_REG crfd, OP_REG fra, OP_REG frb) - { - DisAsm_F3("fcmpo", crfd, fra, frb); - } - void FNEG(OP_REG frd, OP_REG frb, bool rc) - { - DisAsm_F2_RC("fneg", frd, frb, rc); - } - void FMR(OP_REG frd, OP_REG frb, bool rc) - { - DisAsm_F2_RC("fmr", frd, frb, rc); - } - void FNABS(OP_REG frd, OP_REG frb, bool rc) - { - DisAsm_F2_RC("fnabs", frd, frb, rc); - } - void FABS(OP_REG frd, OP_REG frb, bool rc) - { - DisAsm_F2_RC("fabs", frd, frb, rc); - } - void FCTID(OP_REG frd, OP_REG frb, bool rc) - { - DisAsm_F2_RC("fctid", frd, frb, rc); - } - void FCTIDZ(OP_REG frd, OP_REG frb, bool rc) - { - DisAsm_F2_RC("fctidz", frd, frb, rc); - } - void FCFID(OP_REG frd, OP_REG frb, bool rc) - { - DisAsm_F2_RC("fcfid", frd, frb, rc); - } - END_OPCODES_GROUP(G_3f); + void LD(u32 rd, u32 ra, s32 ds) + { + DisAsm_R2_IMM("ld", rd, ra, ds); + } + void LDU(u32 rd, u32 ra, s32 ds) + { + DisAsm_R2_IMM("ldu", rd, ra, ds); + } + void FDIVS(u32 frd, u32 fra, u32 frb, bool rc) + { + DisAsm_F3_RC("fdivs", frd, fra, frb, rc); + } + void FSUBS(u32 frd, u32 fra, u32 frb, bool rc) + { + DisAsm_F3_RC("fsubs", frd, fra, frb, rc); + } + void FADDS(u32 frd, u32 fra, u32 frb, bool rc) + { + DisAsm_F3_RC("fadds", frd, fra, frb, rc); + } + void FSQRTS(u32 frd, u32 frb, bool rc) + { + DisAsm_F2_RC("fsqrts", frd, frb, rc); + } + void FRES(u32 frd, u32 frb, bool rc) + { + DisAsm_F2_RC("fres", frd, frb, rc); + } + void FMULS(u32 frd, u32 fra, u32 frc, bool rc) + { + DisAsm_F3_RC("fmuls", frd, fra, frc, rc); + } + void FMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + { + DisAsm_F4_RC("fmadds", frd, fra, frc, frb, rc); + } + void FMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + { + DisAsm_F4_RC("fmsubs", frd, fra, frc, frb, rc); + } + void FNMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + { + DisAsm_F4_RC("fnmsubs", frd, fra, frc, frb, rc); + } + void FNMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + { + DisAsm_F4_RC("fnmadds", frd, fra, frc, frb, rc); + } + void STD(u32 rs, u32 ra, s32 ds) + { + DisAsm_R2_IMM("std", rs, ra, ds); + } + void STDU(u32 rs, u32 ra, s32 ds) + { + DisAsm_R2_IMM("stdu", rs, ra, ds); + } + void MTFSB1(u32 bt, bool rc) + { + DisAsm_F1_RC("mtfsb1", bt, rc); + } + void MCRFS(u32 bf, u32 bfa) + { + DisAsm_F2("mcrfs", bf, bfa); + } + void MTFSB0(u32 bt, bool rc) + { + DisAsm_F1_RC("mtfsb0", bt, rc); + } + void MTFSFI(u32 crfd, u32 i, bool rc) + { + DisAsm_F2_RC("mtfsfi", crfd, i, rc); + } + void MFFS(u32 frd, bool rc) + { + DisAsm_F1_RC("mffs", frd, rc); + } + void MTFSF(u32 flm, u32 frb, bool rc) + { + DisAsm_F2_RC("mtfsf", flm, frb, rc); + } + void FCMPU(u32 crfd, u32 fra, u32 frb) + { + DisAsm_CR1_F2("fcmpu", crfd, fra, frb); + } + void FRSP(u32 frd, u32 frb, bool rc) + { + DisAsm_F2_RC("frsp", frd, frb, rc); + } + void FCTIW(u32 frd, u32 frb, bool rc) + { + DisAsm_F2_RC("fctiw", frd, frb, rc); + } + void FCTIWZ(u32 frd, u32 frb, bool rc) + { + DisAsm_F2_RC("fctiwz", frd, frb, rc); + } + void FDIV(u32 frd, u32 fra, u32 frb, bool rc) + { + DisAsm_F3_RC("fdiv", frd, fra, frb, rc); + } + void FSUB(u32 frd, u32 fra, u32 frb, bool rc) + { + DisAsm_F3_RC("fsub", frd, fra, frb, rc); + } + void FADD(u32 frd, u32 fra, u32 frb, bool rc) + { + DisAsm_F3_RC("fadd", frd, fra, frb, rc); + } + void FSQRT(u32 frd, u32 frb, bool rc) + { + DisAsm_F2_RC("fsqrt", frd, frb, rc); + } + void FSEL(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + { + DisAsm_F4_RC("fsel", frd, fra, frc, frb, rc); + } + void FMUL(u32 frd, u32 fra, u32 frc, bool rc) + { + DisAsm_F3_RC("fmul", frd, fra, frc, rc); + } + void FRSQRTE(u32 frd, u32 frb, bool rc) + { + DisAsm_F2_RC("frsqrte", frd, frb, rc); + } + void FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + { + DisAsm_F4_RC("fmsub", frd, fra, frc, frb, rc); + } + void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + { + DisAsm_F4_RC("fmadd", frd, fra, frc, frb, rc); + } + void FNMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + { + DisAsm_F4_RC("fnmsub", frd, fra, frc, frb, rc); + } + void FNMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + { + DisAsm_F4_RC("fnmadd", frd, fra, frc, frb, rc); + } + void FCMPO(u32 crfd, u32 fra, u32 frb) + { + DisAsm_F3("fcmpo", crfd, fra, frb); + } + void FNEG(u32 frd, u32 frb, bool rc) + { + DisAsm_F2_RC("fneg", frd, frb, rc); + } + void FMR(u32 frd, u32 frb, bool rc) + { + DisAsm_F2_RC("fmr", frd, frb, rc); + } + void FNABS(u32 frd, u32 frb, bool rc) + { + DisAsm_F2_RC("fnabs", frd, frb, rc); + } + void FABS(u32 frd, u32 frb, bool rc) + { + DisAsm_F2_RC("fabs", frd, frb, rc); + } + void FCTID(u32 frd, u32 frb, bool rc) + { + DisAsm_F2_RC("fctid", frd, frb, rc); + } + void FCTIDZ(u32 frd, u32 frb, bool rc) + { + DisAsm_F2_RC("fctidz", frd, frb, rc); + } + void FCFID(u32 frd, u32 frb, bool rc) + { + DisAsm_F2_RC("fcfid", frd, frb, rc); + } void UNK(const u32 code, const u32 opcode, const u32 gcode) { diff --git a/rpcs3/Emu/Cell/PPUInstrTable.h b/rpcs3/Emu/Cell/PPUInstrTable.h index 67e6f80013..ebd8849ff7 100644 --- a/rpcs3/Emu/Cell/PPUInstrTable.h +++ b/rpcs3/Emu/Cell/PPUInstrTable.h @@ -240,20 +240,19 @@ namespace PPU_instr static CodeField<26, 30> GD_3f;//0x1f static CodeField<21, 30> GD_3f_0; //0x3ff - static CodeField<0, 31> GetCode; static CodeField<9, 10> STRM; - static auto main_list = new_list<0x40>(OPCD, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, OPCD)); - static auto g04_list = new_list<0x40>(main_list, PPU_opcodes::G_04, GD_04); - static auto g04_0_list = new_list<0x800>(g04_list, GD_04_0, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_04_0)); - static auto g13_list = new_list<0x400>(main_list, PPU_opcodes::G_13, GD_13, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_13)); - static auto g1e_list = new_list<0x4>(main_list, PPU_opcodes::G_1e, GD_1e, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_1e)); - static auto g1f_list = new_list<0x400>(main_list, PPU_opcodes::G_1f, GD_1f, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_1f)); - static auto g3a_list = new_list<0x4>(main_list, PPU_opcodes::G_3a, GD_3a, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_3a)); - static auto g3b_list = new_list<0x20>(main_list, PPU_opcodes::G_3b, GD_3b, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_3b)); - static auto g3e_list = new_list<0x4>(main_list, PPU_opcodes::G_3e, GD_3e, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_3e)); - static auto g3f_list = new_list<0x20>(main_list, PPU_opcodes::G_3f, GD_3f); - static auto g3f_0_list = new_list<0x400>(g3f_list, GD_3f_0, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_3f_0)); + static auto main_list = new_list(OPCD, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, OPCD)); + static auto g04_list = new_list(main_list, PPU_opcodes::G_04, GD_04); + static auto g04_0_list = new_list(g04_list, GD_04_0, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_04_0)); + static auto g13_list = new_list(main_list, PPU_opcodes::G_13, GD_13, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_13)); + static auto g1e_list = new_list(main_list, PPU_opcodes::G_1e, GD_1e, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_1e)); + static auto g1f_list = new_list(main_list, PPU_opcodes::G_1f, GD_1f, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_1f)); + static auto g3a_list = new_list(main_list, PPU_opcodes::G_3a, GD_3a, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_3a)); + static auto g3b_list = new_list(main_list, PPU_opcodes::G_3b, GD_3b, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_3b)); + static auto g3e_list = new_list(main_list, PPU_opcodes::G_3e, GD_3e, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_3e)); + static auto g3f_list = new_list(main_list, PPU_opcodes::G_3f, GD_3f); + static auto g3f_0_list = new_list(g3f_list, GD_3f_0, instr_bind(&PPU_Opcodes::UNK, GetCode, OPCD, GD_3f_0)); #define bind_instr(list, name, ...) \ static const auto& name = make_instr(list, #name, &PPU_Opcodes::name, ##__VA_ARGS__) @@ -637,4 +636,6 @@ namespace PPU_instr bind_instr(g3f_0_list, MTFSFI, CRFD, I, RC); bind_instr(g3f_0_list, MFFS, FRD, RC); bind_instr(g3f_0_list, MTFSF, FLM, FRB, RC); + + #undef bind_instr }; \ No newline at end of file diff --git a/rpcs3/Emu/Cell/PPUInterpreter.h b/rpcs3/Emu/Cell/PPUInterpreter.h index 43e43daf68..8aeceb92b6 100644 --- a/rpcs3/Emu/Cell/PPUInterpreter.h +++ b/rpcs3/Emu/Cell/PPUInterpreter.h @@ -7,8 +7,6 @@ #include "rpcs3.h" #include -#define START_OPCODES_GROUP(x) /*x*/ -#define END_OPCODES_GROUP(x) /*x*/ #define UNIMPLEMENTED() UNK(__FUNCTION__) #if 0//def _DEBUG @@ -93,7 +91,7 @@ private: return v; } - bool CheckCondition(OP_uIMM bo, OP_uIMM bi) + bool CheckCondition(u32 bo, u32 bi) { const u8 bo0 = (bo & 0x10) ? 1 : 0; const u8 bo1 = (bo & 0x08) ? 1 : 0; @@ -114,7 +112,7 @@ private: return ctr_ok && cond_ok; } - u64& GetRegBySPR(OP_uIMM spr) + u64& GetRegBySPR(u32 spr) { const u32 n = (spr >> 5) | ((spr & 0x1f) << 5); @@ -130,7 +128,7 @@ private: return CPU.XER.XER; } - void TDI(OP_uIMM to, OP_REG ra, OP_sIMM simm16) + void TDI(u32 to, u32 ra, s32 simm16) { s64 a = CPU.GPR[ra]; @@ -144,7 +142,7 @@ private: } } - void TWI(OP_uIMM to, OP_REG ra, OP_sIMM simm16) + void TWI(u32 to, u32 ra, s32 simm16) { s32 a = CPU.GPR[ra]; @@ -158,1915 +156,1912 @@ private: } } - START_OPCODES_GROUP(G_04) - void MFVSCR(OP_REG vd) + void MFVSCR(u32 vd) + { + CPU.VPR[vd].Clear(); + CPU.VPR[vd]._u32[0] = CPU.VSCR.VSCR; + } + void MTVSCR(u32 vb) + { + CPU.VSCR.VSCR = CPU.VPR[vb]._u32[0]; + CPU.VSCR.X = CPU.VSCR.Y = 0; + } + void VADDCUW(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) { - CPU.VPR[vd].Clear(); - CPU.VPR[vd]._u32[0] = CPU.VSCR.VSCR; + CPU.VPR[vd]._u32[w] = ~CPU.VPR[va]._u32[w] < CPU.VPR[vb]._u32[w]; } - void MTVSCR(OP_REG vb) + } + void VADDFP(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) { - CPU.VSCR.VSCR = CPU.VPR[vb]._u32[0]; - CPU.VSCR.X = CPU.VSCR.Y = 0; + CPU.VPR[vd]._f[w] = CPU.VPR[va]._f[w] + CPU.VPR[vb]._f[w]; } - void VADDCUW(OP_REG vd, OP_REG va, OP_REG vb) + } + void VADDSBS(u32 vd, u32 va, u32 vb) + { + for(u32 b=0; b<16; ++b) { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = ~CPU.VPR[va]._u32[w] < CPU.VPR[vb]._u32[w]; - } - } - void VADDFP(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._f[w] = CPU.VPR[va]._f[w] + CPU.VPR[vb]._f[w]; - } - } - void VADDSBS(OP_REG vd, OP_REG va, OP_REG vb) - { - for(u32 b=0; b<16; ++b) - { - s16 result = (s16)CPU.VPR[va]._s8[b] + (s16)CPU.VPR[vb]._s8[b]; + s16 result = (s16)CPU.VPR[va]._s8[b] + (s16)CPU.VPR[vb]._s8[b]; - if (result > 0x7f) - { - CPU.VPR[vd]._s8[b] = 0x7f; - CPU.VSCR.SAT = 1; - } - else if (result < -0x80) - { - CPU.VPR[vd]._s8[b] = -0x80; - CPU.VSCR.SAT = 1; - } - else - CPU.VPR[vd]._s8[b] = result; - } - } - void VADDSHS(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - s32 result = (s32)CPU.VPR[va]._s16[h] + (s32)CPU.VPR[vb]._s16[h]; - - if (result > 0x7fff) - { - CPU.VPR[vd]._s16[h] = 0x7fff; - CPU.VSCR.SAT = 1; - } - else if (result < -0x8000) - { - CPU.VPR[vd]._s16[h] = -0x8000; - CPU.VSCR.SAT = 1; - } - else - CPU.VPR[vd]._s16[h] = result; - } - } - void VADDSWS(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - s64 result = (s64)CPU.VPR[va]._s32[w] + (s64)CPU.VPR[vb]._s32[w]; - - if (result > 0x7fffffff) - { - CPU.VPR[vd]._s32[w] = 0x7fffffff; - CPU.VSCR.SAT = 1; - } - else if (result < (s32)0x80000000) - { - CPU.VPR[vd]._s32[w] = 0x80000000; - CPU.VSCR.SAT = 1; - } - else - CPU.VPR[vd]._s32[w] = result; - } - } - void VADDUBM(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint b = 0; b < 16; b++) - { - CPU.VPR[vd]._u8[b] = CPU.VPR[va]._u8[b] + CPU.VPR[vb]._u8[b]; - } - } - void VADDUBS(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint b = 0; b < 16; b++) - { - u16 result = (u16)CPU.VPR[va]._u8[b] + (u16)CPU.VPR[vb]._u8[b]; - - if (result > 0xff) - { - CPU.VPR[vd]._u8[b] = 0xff; - CPU.VSCR.SAT = 1; - } - else - CPU.VPR[vd]._u8[b] = result; - } - } - void VADDUHM(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._u16[h] = CPU.VPR[va]._u16[h] + CPU.VPR[vb]._u16[h]; - } - } - void VADDUHS(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - u32 result = (u32)CPU.VPR[va]._u16[h] + (u32)CPU.VPR[vb]._u16[h]; - - if (result > 0xffff) - { - CPU.VPR[vd]._u16[h] = 0xffff; - CPU.VSCR.SAT = 1; - } - else - CPU.VPR[vd]._u16[h] = result; - } - } - void VADDUWM(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] + CPU.VPR[vb]._u32[w]; - } - } - void VADDUWS(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - u64 result = (u64)CPU.VPR[va]._u32[w] + (u64)CPU.VPR[vb]._u32[w]; - - if (result > 0xffffffff) - { - CPU.VPR[vd]._u32[w] = 0xffffffff; - CPU.VSCR.SAT = 1; - } - else - CPU.VPR[vd]._u32[w] = result; - } - } - void VAND(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] & CPU.VPR[vb]._u32[w]; - } - } - void VANDC(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] & (~CPU.VPR[vb]._u32[w]); - } - } - void VAVGSB(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint b = 0; b < 16; b++) - { - CPU.VPR[vd]._s8[b] = (CPU.VPR[va]._s8[b] + CPU.VPR[vb]._s8[b] + 1) >> 1; - } - } - void VAVGSH(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._s16[h] = (CPU.VPR[va]._s16[h] + CPU.VPR[vb]._s16[h] + 1) >> 1; - } - } - void VAVGSW(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._s32[w] = ((s64)CPU.VPR[va]._s32[w] + (s64)CPU.VPR[vb]._s32[w] + 1) >> 1; - } - } - void VAVGUB(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint b = 0; b < 16; b++) - CPU.VPR[vd]._u8[b] = (CPU.VPR[va]._u8[b] + CPU.VPR[vb]._u8[b] + 1) >> 1; - } - void VAVGUH(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._u16[h] = (CPU.VPR[va]._u16[h] + CPU.VPR[vb]._u16[h] + 1) >> 1; - } - } - void VAVGUW(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = ((u64)CPU.VPR[va]._u32[w] + (u64)CPU.VPR[vb]._u32[w] + 1) >> 1; - } - } - void VCFSX(OP_REG vd, OP_uIMM uimm5, OP_REG vb) - { - u32 scale = 1 << uimm5; - - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._f[w] = ((float)CPU.VPR[vb]._s32[w]) / scale; - } - } - void VCFUX(OP_REG vd, OP_uIMM uimm5, OP_REG vb) - { - u32 scale = 1 << uimm5; - - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._f[w] = ((float)CPU.VPR[vb]._u32[w]) / scale; - } - } - void VCMPBFP(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - u32 mask = 0; - - const float A = CheckVSCR_NJ(CPU.VPR[va]._f[w]); - const float B = CheckVSCR_NJ(CPU.VPR[vb]._f[w]); - - if (A > B) mask |= 1 << 31; - if (A < -B) mask |= 1 << 30; - - CPU.VPR[vd]._u32[w] = mask; - } - } - void VCMPBFP_(OP_REG vd, OP_REG va, OP_REG vb) - { - bool allInBounds = true; - - for (uint w = 0; w < 4; w++) - { - u32 mask = 0; - - const float A = CheckVSCR_NJ(CPU.VPR[va]._f[w]); - const float B = CheckVSCR_NJ(CPU.VPR[vb]._f[w]); - - if (A > B) mask |= 1 << 31; - if (A < -B) mask |= 1 << 30; - - CPU.VPR[vd]._u32[w] = mask; - - if (mask) - allInBounds = false; - } - - // Bit n°2 of CR6 - CPU.SetCRBit(6, 0x2, allInBounds); - } - void VCMPEQFP(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = CPU.VPR[va]._f[w] == CPU.VPR[vb]._f[w] ? 0xffffffff : 0; - } - } - void VCMPEQFP_(OP_REG vd, OP_REG va, OP_REG vb) - { - int all_equal = 0x8; - int none_equal = 0x2; - - for (uint w = 0; w < 4; w++) - { - if (CPU.VPR[va]._f[w] == CPU.VPR[vb]._f[w]) - { - CPU.VPR[vd]._u32[w] = 0xffffffff; - none_equal = 0; - } - else - { - CPU.VPR[vd]._u32[w] = 0; - all_equal = 0; - } - } - - CPU.CR.cr6 = all_equal | none_equal; - } - void VCMPEQUB(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint b = 0; b < 16; b++) - { - CPU.VPR[vd]._u8[b] = CPU.VPR[va]._u8[b] == CPU.VPR[vb]._u8[b] ? 0xff : 0; - } - } - void VCMPEQUB_(OP_REG vd, OP_REG va, OP_REG vb) - { - int all_equal = 0x8; - int none_equal = 0x2; - - for (uint b = 0; b < 16; b++) - { - if (CPU.VPR[va]._u8[b] == CPU.VPR[vb]._u8[b]) - { - CPU.VPR[vd]._u8[b] = 0xff; - none_equal = 0; - } - else - { - CPU.VPR[vd]._u8[b] = 0; - all_equal = 0; - } - } - - CPU.CR.cr6 = all_equal | none_equal; - } - void VCMPEQUH(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._u16[h] = CPU.VPR[va]._u16[h] == CPU.VPR[vb]._u16[h] ? 0xffff : 0; - } - } - void VCMPEQUH_(OP_REG vd, OP_REG va, OP_REG vb) - { - int all_equal = 0x8; - int none_equal = 0x2; - - for (uint h = 0; h < 8; h++) - { - if (CPU.VPR[va]._u16[h] == CPU.VPR[vb]._u16[h]) - { - CPU.VPR[vd]._u16[h] = 0xffff; - none_equal = 0; - } - else - { - CPU.VPR[vd]._u16[h] = 0; - all_equal = 0; - } - } - - CPU.CR.cr6 = all_equal | none_equal; - } - void VCMPEQUW(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] == CPU.VPR[vb]._u32[w] ? 0xffffffff : 0; - } - } - void VCMPEQUW_(OP_REG vd, OP_REG va, OP_REG vb) - { - int all_equal = 0x8; - int none_equal = 0x2; - - for (uint w = 0; w < 4; w++) - { - if (CPU.VPR[va]._u32[w] == CPU.VPR[vb]._u32[w]) - { - CPU.VPR[vd]._u32[w] = 0xffffffff; - none_equal = 0; - } - else - { - CPU.VPR[vd]._u32[w] = 0; - all_equal = 0; - } - } - - CPU.CR.cr6 = all_equal | none_equal; - } - void VCMPGEFP(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = CPU.VPR[va]._f[w] >= CPU.VPR[vb]._f[w] ? 0xffffffff : 0; - } - } - void VCMPGEFP_(OP_REG vd, OP_REG va, OP_REG vb) - { - int all_ge = 0x8; - int none_ge = 0x2; - - for (uint w = 0; w < 4; w++) - { - if (CPU.VPR[va]._f[w] >= CPU.VPR[vb]._f[w]) - { - CPU.VPR[vd]._u32[w] = 0xffffffff; - none_ge = 0; - } - else - { - CPU.VPR[vd]._u32[w] = 0; - all_ge = 0; - } - } - - CPU.CR.cr6 = all_ge | none_ge; - } - void VCMPGTFP(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = CPU.VPR[va]._f[w] > CPU.VPR[vb]._f[w] ? 0xffffffff : 0; - } - } - void VCMPGTFP_(OP_REG vd, OP_REG va, OP_REG vb) - { - int all_ge = 0x8; - int none_ge = 0x2; - - for (uint w = 0; w < 4; w++) - { - if (CPU.VPR[va]._f[w] > CPU.VPR[vb]._f[w]) - { - CPU.VPR[vd]._u32[w] = 0xffffffff; - none_ge = 0; - } - else - { - CPU.VPR[vd]._u32[w] = 0; - all_ge = 0; - } - } - - CPU.CR.cr6 = all_ge | none_ge; - } - void VCMPGTSB(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint b = 0; b < 16; b++) - { - CPU.VPR[vd]._u8[b] = CPU.VPR[va]._s8[b] > CPU.VPR[vb]._s8[b] ? 0xff : 0; - } - } - void VCMPGTSB_(OP_REG vd, OP_REG va, OP_REG vb) - { - int all_gt = 0x8; - int none_gt = 0x2; - - for (uint b = 0; b < 16; b++) - { - if (CPU.VPR[va]._s8[b] > CPU.VPR[vb]._s8[b]) - { - CPU.VPR[vd]._u8[b] = 0xff; - none_gt = 0; - } - else - { - CPU.VPR[vd]._u8[b] = 0; - all_gt = 0; - } - } - - CPU.CR.cr6 = all_gt | none_gt; - } - void VCMPGTSH(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._u16[h] = CPU.VPR[va]._s16[h] > CPU.VPR[vb]._s16[h] ? 0xffff : 0; - } - } - void VCMPGTSH_(OP_REG vd, OP_REG va, OP_REG vb) - { - int all_gt = 0x8; - int none_gt = 0x2; - - for (uint h = 0; h < 8; h++) - { - if (CPU.VPR[va]._s16[h] > CPU.VPR[vb]._s16[h]) - { - CPU.VPR[vd]._u16[h] = 0xffff; - none_gt = 0; - } - else - { - CPU.VPR[vd]._u16[h] = 0; - all_gt = 0; - } - } - - CPU.CR.cr6 = all_gt | none_gt; - } - void VCMPGTSW(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = CPU.VPR[va]._s32[w] > CPU.VPR[vb]._s32[w] ? 0xffffffff : 0; - } - } - void VCMPGTSW_(OP_REG vd, OP_REG va, OP_REG vb) - { - int all_gt = 0x8; - int none_gt = 0x2; - - for (uint w = 0; w < 4; w++) - { - if (CPU.VPR[va]._s32[w] > CPU.VPR[vb]._s32[w]) - { - CPU.VPR[vd]._u32[w] = 0xffffffff; - none_gt = 0; - } - else - { - CPU.VPR[vd]._u32[w] = 0; - all_gt = 0; - } - } - - CPU.CR.cr6 = all_gt | none_gt; - } - void VCMPGTUB(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint b = 0; b < 16; b++) - { - CPU.VPR[vd]._u8[b] = CPU.VPR[va]._u8[b] > CPU.VPR[vb]._u8[b] ? 0xff : 0; - } - } - void VCMPGTUB_(OP_REG vd, OP_REG va, OP_REG vb) - { - int all_gt = 0x8; - int none_gt = 0x2; - - for (uint b = 0; b < 16; b++) - { - if (CPU.VPR[va]._u8[b] > CPU.VPR[vb]._u8[b]) - { - CPU.VPR[vd]._u8[b] = 0xff; - none_gt = 0; - } - else - { - CPU.VPR[vd]._u8[b] = 0; - all_gt = 0; - } - } - - CPU.CR.cr6 = all_gt | none_gt; - } - void VCMPGTUH(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._u16[h] = CPU.VPR[va]._u16[h] > CPU.VPR[vb]._u16[h] ? 0xffff : 0; - } - } - void VCMPGTUH_(OP_REG vd, OP_REG va, OP_REG vb) - { - int all_gt = 0x8; - int none_gt = 0x2; - - for (uint h = 0; h < 8; h++) - { - if (CPU.VPR[va]._u16[h] > CPU.VPR[vb]._u16[h]) - { - CPU.VPR[vd]._u16[h] = 0xffff; - none_gt = 0; - } - else - { - CPU.VPR[vd]._u16[h] = 0; - all_gt = 0; - } - } - - CPU.CR.cr6 = all_gt | none_gt; - } - void VCMPGTUW(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] > CPU.VPR[vb]._u32[w] ? 0xffffffff : 0; - } - } - void VCMPGTUW_(OP_REG vd, OP_REG va, OP_REG vb) - { - int all_gt = 0x8; - int none_gt = 0x2; - - for (uint w = 0; w < 4; w++) - { - if (CPU.VPR[va]._u32[w] > CPU.VPR[vb]._u32[w]) - { - CPU.VPR[vd]._u32[w] = 0xffffffff; - none_gt = 0; - } - else - { - CPU.VPR[vd]._u32[w] = 0; - all_gt = 0; - } - } - - CPU.CR.cr6 = all_gt | none_gt; - } - void VCTSXS(OP_REG vd, OP_uIMM uimm5, OP_REG vb) - { - int nScale = 1 << uimm5; - - for (uint w = 0; w < 4; w++) + if (result > 0x7f) { - // C rounding = Round towards 0 - s64 result = (s64)(CPU.VPR[vb]._f[w] * nScale); - - if (result > INT_MAX) - CPU.VPR[vd]._s32[w] = (int)INT_MAX; - else if (result < INT_MIN) - CPU.VPR[vd]._s32[w] = (int)INT_MIN; - else - CPU.VPR[vd]._s32[w] = (int)result; + CPU.VPR[vd]._s8[b] = 0x7f; + CPU.VSCR.SAT = 1; } - } - void VCTUXS(OP_REG vd, OP_uIMM uimm5, OP_REG vb) - { - int nScale = 1 << uimm5; - - for (uint w = 0; w < 4; w++) + else if (result < -0x80) { - // C rounding = Round towards 0 - s64 result = (s64)(CPU.VPR[vb]._f[w] * nScale); - - if (result > UINT_MAX) - CPU.VPR[vd]._u32[w] = (u32)UINT_MAX; - else if (result < 0) - CPU.VPR[vd]._u32[w] = 0; - else - CPU.VPR[vd]._u32[w] = (u32)result; + CPU.VPR[vd]._s8[b] = -0x80; + CPU.VSCR.SAT = 1; } - } - void VEXPTEFP(OP_REG vd, OP_REG vb) - { - // vd = exp(vb * log(2)) - // ISA : Note that the value placed into the element of vD may vary between implementations - // and between different executions on the same implementation. - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._f[w] = exp(CPU.VPR[vb]._f[w] * log(2.0f)); - } - } - void VLOGEFP(OP_REG vd, OP_REG vb) - { - // ISA : Note that the value placed into the element of vD may vary between implementations - // and between different executions on the same implementation. - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._f[w] = log(CPU.VPR[vb]._f[w]) / log(2.0f); - } - } - void VMADDFP(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._f[w] = CPU.VPR[va]._f[w] * CPU.VPR[vc]._f[w] + CPU.VPR[vb]._f[w]; - } - } - void VMAXFP(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._f[w] = max(CPU.VPR[va]._f[w], CPU.VPR[vb]._f[w]); - } - } - void VMAXSB(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint b = 0; b < 16; b++) - CPU.VPR[vd]._s8[b] = max(CPU.VPR[va]._s8[b], CPU.VPR[vb]._s8[b]); - } - void VMAXSH(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._s16[h] = max(CPU.VPR[va]._s16[h], CPU.VPR[vb]._s16[h]); - } - } - void VMAXSW(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._s32[w] = max(CPU.VPR[va]._s32[w], CPU.VPR[vb]._s32[w]); - } - } - void VMAXUB(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint b = 0; b < 16; b++) - CPU.VPR[vd]._u8[b] = max(CPU.VPR[va]._u8[b], CPU.VPR[vb]._u8[b]); - } - void VMAXUH(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._u16[h] = max(CPU.VPR[va]._u16[h], CPU.VPR[vb]._u16[h]); - } - } - void VMAXUW(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = max(CPU.VPR[va]._u32[w], CPU.VPR[vb]._u32[w]); - } - } - void VMHADDSHS(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - for (uint h = 0; h < 8; h++) - { - s32 result = (s32)CPU.VPR[va]._s16[h] * (s32)CPU.VPR[vb]._s16[h] + (s32)CPU.VPR[vc]._s16[h]; - - if (result > INT16_MAX) - { - CPU.VPR[vd]._s16[h] = (s16)INT16_MAX; - CPU.VSCR.SAT = 1; - } - else if (result < INT16_MIN) - { - CPU.VPR[vd]._s16[h] = (s16)INT16_MIN; - CPU.VSCR.SAT = 1; - } - else - CPU.VPR[vd]._s16[h] = (s16)result; - } - } - void VMHRADDSHS(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - for (uint h = 0; h < 8; h++) - { - s32 result = (s32)CPU.VPR[va]._s16[h] * (s32)CPU.VPR[vb]._s16[h] + (s32)CPU.VPR[vc]._s16[h] + 0x4000; - - if (result > INT16_MAX) - { - CPU.VPR[vd]._s16[h] = (s16)INT16_MAX; - CPU.VSCR.SAT = 1; - } - else if (result < INT16_MIN) - { - CPU.VPR[vd]._s16[h] = (s16)INT16_MIN; - CPU.VSCR.SAT = 1; - } - else - CPU.VPR[vd]._s16[h] = (s16)result; - } - } - void VMINFP(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._f[w] = min(CPU.VPR[va]._f[w], CPU.VPR[vb]._f[w]); - } - } - void VMINSB(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint b = 0; b < 16; b++) - { - CPU.VPR[vd]._s8[b] = min(CPU.VPR[va]._s8[b], CPU.VPR[vb]._s8[b]); - } - } - void VMINSH(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._s16[h] = min(CPU.VPR[va]._s16[h], CPU.VPR[vb]._s16[h]); - } - } - void VMINSW(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._s32[w] = min(CPU.VPR[va]._s32[w], CPU.VPR[vb]._s32[w]); - } - } - void VMINUB(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint b = 0; b < 16; b++) - { - CPU.VPR[vd]._u8[b] = min(CPU.VPR[va]._u8[b], CPU.VPR[vb]._u8[b]); - } - } - void VMINUH(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._u16[h] = min(CPU.VPR[va]._u16[h], CPU.VPR[vb]._u16[h]); - } - } - void VMINUW(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = min(CPU.VPR[va]._u32[w], CPU.VPR[vb]._u32[w]); - } - } - void VMLADDUHM(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._u16[h] = CPU.VPR[va]._u16[h] * CPU.VPR[vb]._u16[h] + CPU.VPR[vc]._u16[h]; - } - } - void VMRGHB(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._u8[h*2] = CPU.VPR[va]._u8[h]; - CPU.VPR[vd]._u8[h*2 + 1] = CPU.VPR[vb]._u8[h]; - } - } - void VMRGHH(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u16[w*2] = CPU.VPR[va]._u16[w]; - CPU.VPR[vd]._u16[w*2 + 1] = CPU.VPR[vb]._u16[w]; - } - } - void VMRGHW(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint d = 0; d < 2; d++) - { - CPU.VPR[vd]._u32[d*2] = CPU.VPR[va]._u32[d]; - CPU.VPR[vd]._u32[d*2 + 1] = CPU.VPR[vb]._u32[d]; - } - } - void VMRGLB(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._u8[h*2] = CPU.VPR[va]._u8[h + 8]; - CPU.VPR[vd]._u8[h*2 + 1] = CPU.VPR[vb]._u8[h + 8]; - } - } - void VMRGLH(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u16[w*2] = CPU.VPR[va]._u16[w + 4]; - CPU.VPR[vd]._u16[w*2 + 1] = CPU.VPR[vb]._u16[w + 4]; - } - } - void VMRGLW(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint d = 0; d < 2; d++) - { - CPU.VPR[vd]._u32[d*2] = CPU.VPR[va]._u32[d + 2]; - CPU.VPR[vd]._u32[d*2 + 1] = CPU.VPR[vb]._u32[d + 2]; - } - } - void VMSUMMBM(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - for (uint w = 0; w < 4; w++) - { - s32 result = 0; - - for (uint b = 0; b < 4; b++) - { - result += CPU.VPR[va]._s8[w*4 + b] * CPU.VPR[vb]._u8[w*4 + b]; - } - - result += CPU.VPR[vc]._s32[w]; - CPU.VPR[vd]._s32[w] = result; - } - } - void VMSUMSHM(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - for (uint w = 0; w < 4; w++) - { - s32 result = 0; - - for (uint h = 0; h < 2; h++) - { - result += CPU.VPR[va]._s16[w*2 + h] * CPU.VPR[vb]._s16[w*2 + h]; - } - - result += CPU.VPR[vc]._s32[w]; - CPU.VPR[vd]._s32[w] = result; - } - } - void VMSUMSHS(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - for (uint w = 0; w < 4; w++) - { - s64 result = 0; - s32 saturated = 0; - - for (uint h = 0; h < 2; h++) - { - result += CPU.VPR[va]._s16[w*2 + h] * CPU.VPR[vb]._s16[w*2 + h]; - } - - result += CPU.VPR[vc]._s32[w]; - - if (result > INT_MAX) - { - saturated = INT_MAX; - CPU.VSCR.SAT = 1; - } - else if (result < INT_MIN) - { - saturated = INT_MIN; - CPU.VSCR.SAT = 1; - } - else - saturated = (s32)result; - - CPU.VPR[vd]._s32[w] = saturated; - } - } - void VMSUMUBM(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - for (uint w = 0; w < 4; w++) - { - u32 result = 0; - - for (uint b = 0; b < 4; b++) - { - result += CPU.VPR[va]._u8[w*4 + b] * CPU.VPR[vb]._u8[w*4 + b]; - } - - result += CPU.VPR[vc]._u32[w]; - CPU.VPR[vd]._u32[w] = result; - } - } - void VMSUMUHM(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - for (uint w = 0; w < 4; w++) - { - u32 result = 0; - - for (uint h = 0; h < 2; h++) - { - result += CPU.VPR[va]._u16[w*2 + h] * CPU.VPR[vb]._u16[w*2 + h]; - } - - result += CPU.VPR[vc]._u32[w]; - CPU.VPR[vd]._u32[w] = result; - } - } - void VMSUMUHS(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - for (uint w = 0; w < 4; w++) - { - u64 result = 0; - u32 saturated = 0; - - for (uint h = 0; h < 2; h++) - { - result += CPU.VPR[va]._u16[w*2 + h] * CPU.VPR[vb]._u16[w*2 + h]; - } - - result += CPU.VPR[vc]._u32[w]; - - if (result > UINT_MAX) - { - saturated = UINT_MAX; - CPU.VSCR.SAT = 1; - } - else - saturated = (u32)result; - - CPU.VPR[vd]._u32[w] = saturated; - } - } - void VMULESB(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._s16[h] = (s16)CPU.VPR[va]._s8[h*2+1] * (s16)CPU.VPR[vb]._s8[h*2+1]; - } - } - void VMULESH(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._s32[w] = (s32)CPU.VPR[va]._s16[w*2+1] * (s32)CPU.VPR[vb]._s16[w*2+1]; - } - } - void VMULEUB(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._u16[h] = (u16)CPU.VPR[va]._u8[h*2+1] * (u16)CPU.VPR[vb]._u8[h*2+1]; - } - } - void VMULEUH(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = (u32)CPU.VPR[va]._u16[w*2+1] * (u32)CPU.VPR[vb]._u16[w*2+1]; - } - } - void VMULOSB(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._s16[h] = (s16)CPU.VPR[va]._s8[h*2] * (s16)CPU.VPR[vb]._s8[h*2]; - } - } - void VMULOSH(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._s32[w] = (s32)CPU.VPR[va]._s16[w*2] * (s32)CPU.VPR[vb]._s16[w*2]; - } - } - void VMULOUB(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._u16[h] = (u16)CPU.VPR[va]._u8[h*2] * (u16)CPU.VPR[vb]._u8[h*2]; - } - } - void VMULOUH(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = (u32)CPU.VPR[va]._u16[w*2] * (u32)CPU.VPR[vb]._u16[w*2]; - } - } - void VNMSUBFP(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._f[w] = (double)CPU.VPR[vb]._f[w] - (double)CPU.VPR[va]._f[w] * (double)CPU.VPR[vc]._f[w]; - } - } - void VNOR(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = ~(CPU.VPR[va]._u32[w] | CPU.VPR[vb]._u32[w]); - } - } - void VOR(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] | CPU.VPR[vb]._u32[w]; - } - } - void VPERM(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) - { - for (uint b = 0; b < 16; b++) - { - u8 index = CPU.VPR[vc]._u8[b] & 0x1f; - - CPU.VPR[vd]._u8[b] = index < 0x10 ? CPU.VPR[va]._u8[0xf - index] : CPU.VPR[vb]._u8[0xf - (index - 0x10)]; - } - } - void VPKPX(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 4; h++) - { - u16 bb7 = CPU.VPR[vb]._u8[15 - (h*4 + 0)] & 0x1; - u16 bb8 = CPU.VPR[vb]._u8[15 - (h*4 + 1)] >> 3; - u16 bb16 = CPU.VPR[vb]._u8[15 - (h*4 + 2)] >> 3; - u16 bb24 = CPU.VPR[vb]._u8[15 - (h*4 + 3)] >> 3; - u16 ab7 = CPU.VPR[va]._u8[15 - (h*4 + 0)] & 0x1; - u16 ab8 = CPU.VPR[va]._u8[15 - (h*4 + 1)] >> 3; - u16 ab16 = CPU.VPR[va]._u8[15 - (h*4 + 2)] >> 3; - u16 ab24 = CPU.VPR[va]._u8[15 - (h*4 + 3)] >> 3; - - CPU.VPR[vd]._u16[3 - h] = (bb7 << 15) | (bb8 << 10) | (bb16 << 5) | bb24; - CPU.VPR[vd]._u16[4 + (3 - h)] = (ab7 << 15) | (ab8 << 10) | (ab16 << 5) | ab24; - } - } - void VPKSHSS(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint b = 0; b < 8; b++) - { - s16 result = CPU.VPR[va]._s16[b]; - - if (result > INT8_MAX) - { - result = INT8_MAX; - CPU.VSCR.SAT = 1; - } - else if (result < INT8_MIN) - { - result = INT8_MIN; - CPU.VSCR.SAT = 1; - } - - CPU.VPR[vd]._s8[b+8] = result; - - result = CPU.VPR[vb]._s16[b]; - - if (result > INT8_MAX) - { - result = INT8_MAX; - CPU.VSCR.SAT = 1; - } - else if (result < INT8_MIN) - { - result = INT8_MIN; - CPU.VSCR.SAT = 1; - } - + else CPU.VPR[vd]._s8[b] = result; - } } - void VPKSHUS(OP_REG vd, OP_REG va, OP_REG vb) + } + void VADDSHS(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) { - for (uint b = 0; b < 8; b++) + s32 result = (s32)CPU.VPR[va]._s16[h] + (s32)CPU.VPR[vb]._s16[h]; + + if (result > 0x7fff) { - s16 result = CPU.VPR[va]._s16[b]; - - if (result > UINT8_MAX) - { - result = UINT8_MAX; - CPU.VSCR.SAT = 1; - } - else if (result < 0) - { - result = 0; - CPU.VSCR.SAT = 1; - } - - CPU.VPR[vd]._u8[b+8] = result; - - result = CPU.VPR[vb]._s16[b]; - - if (result > UINT8_MAX) - { - result = UINT8_MAX; - CPU.VSCR.SAT = 1; - } - else if (result < 0) - { - result = 0; - CPU.VSCR.SAT = 1; - } - - CPU.VPR[vd]._u8[b] = result; + CPU.VPR[vd]._s16[h] = 0x7fff; + CPU.VSCR.SAT = 1; } - } - void VPKSWSS(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 4; h++) + else if (result < -0x8000) { - s32 result = CPU.VPR[va]._s32[h]; - - if (result > INT16_MAX) - { - result = INT16_MAX; - CPU.VSCR.SAT = 1; - } - else if (result < INT16_MIN) - { - result = INT16_MIN; - CPU.VSCR.SAT = 1; - } - - CPU.VPR[vd]._s16[h+4] = result; - - result = CPU.VPR[vb]._s32[h]; - - if (result > INT16_MAX) - { - result = INT16_MAX; - CPU.VSCR.SAT = 1; - } - else if (result < INT16_MIN) - { - result = INT16_MIN; - CPU.VSCR.SAT = 1; - } - + CPU.VPR[vd]._s16[h] = -0x8000; + CPU.VSCR.SAT = 1; + } + else CPU.VPR[vd]._s16[h] = result; - } } - void VPKSWUS(OP_REG vd, OP_REG va, OP_REG vb) + } + void VADDSWS(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) { - for (uint h = 0; h < 4; h++) + s64 result = (s64)CPU.VPR[va]._s32[w] + (s64)CPU.VPR[vb]._s32[w]; + + if (result > 0x7fffffff) { - s32 result = CPU.VPR[va]._s32[h]; - - if (result > UINT16_MAX) - { - result = UINT16_MAX; - CPU.VSCR.SAT = 1; - } - else if (result < 0) - { - result = 0; - CPU.VSCR.SAT = 1; - } - - CPU.VPR[vd]._u16[h+4] = result; - - result = CPU.VPR[vb]._s32[h]; - - if (result > UINT16_MAX) - { - result = UINT16_MAX; - CPU.VSCR.SAT = 1; - } - else if (result < 0) - { - result = 0; - CPU.VSCR.SAT = 1; - } - - CPU.VPR[vd]._u16[h] = result; + CPU.VPR[vd]._s32[w] = 0x7fffffff; + CPU.VSCR.SAT = 1; } - } - void VPKUHUM(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint b = 0; b < 8; b++) + else if (result < (s32)0x80000000) { - CPU.VPR[vd]._u8[b+8] = CPU.VPR[va]._u8[b*2]; - CPU.VPR[vd]._u8[b ] = CPU.VPR[vb]._u8[b*2]; + CPU.VPR[vd]._s32[w] = 0x80000000; + CPU.VSCR.SAT = 1; } + else + CPU.VPR[vd]._s32[w] = result; } - void VPKUHUS(OP_REG vd, OP_REG va, OP_REG vb) + } + void VADDUBM(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 16; b++) { - for (uint b = 0; b < 8; b++) + CPU.VPR[vd]._u8[b] = CPU.VPR[va]._u8[b] + CPU.VPR[vb]._u8[b]; + } + } + void VADDUBS(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 16; b++) + { + u16 result = (u16)CPU.VPR[va]._u8[b] + (u16)CPU.VPR[vb]._u8[b]; + + if (result > 0xff) { - u16 result = CPU.VPR[va]._u16[b]; - - if (result > UINT8_MAX) - { - result = UINT8_MAX; - CPU.VSCR.SAT = 1; - } - - CPU.VPR[vd]._u8[b+8] = result; - - result = CPU.VPR[vb]._u16[b]; - - if (result > UINT8_MAX) - { - result = UINT8_MAX; - CPU.VSCR.SAT = 1; - } - + CPU.VPR[vd]._u8[b] = 0xff; + CPU.VSCR.SAT = 1; + } + else CPU.VPR[vd]._u8[b] = result; - } } - void VPKUWUM(OP_REG vd, OP_REG va, OP_REG vb) + } + void VADDUHM(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) { - for (uint h = 0; h < 4; h++) - { - CPU.VPR[vd]._u16[h+4] = CPU.VPR[va]._u16[h*2]; - CPU.VPR[vd]._u16[h ] = CPU.VPR[vb]._u16[h*2]; - } + CPU.VPR[vd]._u16[h] = CPU.VPR[va]._u16[h] + CPU.VPR[vb]._u16[h]; } - void VPKUWUS(OP_REG vd, OP_REG va, OP_REG vb) + } + void VADDUHS(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) { - for (uint h = 0; h < 4; h++) + u32 result = (u32)CPU.VPR[va]._u16[h] + (u32)CPU.VPR[vb]._u16[h]; + + if (result > 0xffff) { - u32 result = CPU.VPR[va]._u32[h]; - - if (result > UINT16_MAX) - { - result = UINT16_MAX; - CPU.VSCR.SAT = 1; - } - - CPU.VPR[vd]._u16[h+4] = result; - - result = CPU.VPR[vb]._u32[h]; - - if (result > UINT16_MAX) - { - result = UINT16_MAX; - CPU.VSCR.SAT = 1; - } - + CPU.VPR[vd]._u16[h] = 0xffff; + CPU.VSCR.SAT = 1; + } + else CPU.VPR[vd]._u16[h] = result; - } } - void VREFP(OP_REG vd, OP_REG vb) + } + void VADDUWM(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._f[w] = 1.0f / CPU.VPR[vb]._f[w]; - } + CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] + CPU.VPR[vb]._u32[w]; } - void VRFIM(OP_REG vd, OP_REG vb) + } + void VADDUWS(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._f[w] = floor(CPU.VPR[vb]._f[w]); - } - } - void VRFIN(OP_REG vd, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._f[w] = floor(CPU.VPR[vb]._f[w] + 0.5f); - } - } - void VRFIP(OP_REG vd, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._f[w] = ceil(CPU.VPR[vb]._f[w]); - } - } - void VRFIZ(OP_REG vd, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - float f; - modf(CPU.VPR[vb]._f[w], &f); - CPU.VPR[vd]._f[w] = f; - } - } - void VRLB(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint b = 0; b < 16; b++) - { - int nRot = CPU.VPR[vb]._u8[b] & 0x7; + u64 result = (u64)CPU.VPR[va]._u32[w] + (u64)CPU.VPR[vb]._u32[w]; - CPU.VPR[vd]._u8[b] = (CPU.VPR[va]._u8[b] << nRot) | (CPU.VPR[va]._u8[b] >> (8 - nRot)); - } - } - void VRLH(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) + if (result > 0xffffffff) { - CPU.VPR[vd]._u16[h] = rotl16(CPU.VPR[va]._u16[h], CPU.VPR[vb]._u8[h*2] & 0xf); + CPU.VPR[vd]._u32[w] = 0xffffffff; + CPU.VSCR.SAT = 1; } + else + CPU.VPR[vd]._u32[w] = result; } - void VRLW(OP_REG vd, OP_REG va, OP_REG vb) + } + void VAND(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = rotl32(CPU.VPR[va]._u32[w], CPU.VPR[vb]._u8[w*4] & 0x1f); - } + CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] & CPU.VPR[vb]._u32[w]; } - void VRSQRTEFP(OP_REG vd, OP_REG vb) + } + void VANDC(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) { - for (uint w = 0; w < 4; w++) - { - //TODO: accurate div - CPU.VPR[vd]._f[w] = 1.0f / sqrtf(CPU.VPR[vb]._f[w]); - } + CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] & (~CPU.VPR[vb]._u32[w]); } - void VSEL(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc) + } + void VAVGSB(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 16; b++) { - for (uint b = 0; b < 16; b++) - { - CPU.VPR[vd]._u8[b] = (CPU.VPR[vb]._u8[b] & CPU.VPR[vc]._u8[b]) | (CPU.VPR[va]._u8[b] & (~CPU.VPR[vc]._u8[b])); - } + CPU.VPR[vd]._s8[b] = (CPU.VPR[va]._s8[b] + CPU.VPR[vb]._s8[b] + 1) >> 1; } - void VSL(OP_REG vd, OP_REG va, OP_REG vb) + } + void VAVGSH(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) { - u8 sh = CPU.VPR[vb]._u8[0] & 0x7; + CPU.VPR[vd]._s16[h] = (CPU.VPR[va]._s16[h] + CPU.VPR[vb]._s16[h] + 1) >> 1; + } + } + void VAVGSW(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._s32[w] = ((s64)CPU.VPR[va]._s32[w] + (s64)CPU.VPR[vb]._s32[w] + 1) >> 1; + } + } + void VAVGUB(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 16; b++) + CPU.VPR[vd]._u8[b] = (CPU.VPR[va]._u8[b] + CPU.VPR[vb]._u8[b] + 1) >> 1; + } + void VAVGUH(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) + { + CPU.VPR[vd]._u16[h] = (CPU.VPR[va]._u16[h] + CPU.VPR[vb]._u16[h] + 1) >> 1; + } + } + void VAVGUW(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u32[w] = ((u64)CPU.VPR[va]._u32[w] + (u64)CPU.VPR[vb]._u32[w] + 1) >> 1; + } + } + void VCFSX(u32 vd, u32 uimm5, u32 vb) + { + u32 scale = 1 << uimm5; + + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._f[w] = ((float)CPU.VPR[vb]._s32[w]) / scale; + } + } + void VCFUX(u32 vd, u32 uimm5, u32 vb) + { + u32 scale = 1 << uimm5; + + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._f[w] = ((float)CPU.VPR[vb]._u32[w]) / scale; + } + } + void VCMPBFP(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + u32 mask = 0; - u32 t = 1; + const float A = CheckVSCR_NJ(CPU.VPR[va]._f[w]); + const float B = CheckVSCR_NJ(CPU.VPR[vb]._f[w]); - for (uint b = 0; b < 16; b++) + if (A > B) mask |= 1 << 31; + if (A < -B) mask |= 1 << 30; + + CPU.VPR[vd]._u32[w] = mask; + } + } + void VCMPBFP_(u32 vd, u32 va, u32 vb) + { + bool allInBounds = true; + + for (uint w = 0; w < 4; w++) + { + u32 mask = 0; + + const float A = CheckVSCR_NJ(CPU.VPR[va]._f[w]); + const float B = CheckVSCR_NJ(CPU.VPR[vb]._f[w]); + + if (A > B) mask |= 1 << 31; + if (A < -B) mask |= 1 << 30; + + CPU.VPR[vd]._u32[w] = mask; + + if (mask) + allInBounds = false; + } + + // Bit n°2 of CR6 + CPU.SetCRBit(6, 0x2, allInBounds); + } + void VCMPEQFP(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u32[w] = CPU.VPR[va]._f[w] == CPU.VPR[vb]._f[w] ? 0xffffffff : 0; + } + } + void VCMPEQFP_(u32 vd, u32 va, u32 vb) + { + int all_equal = 0x8; + int none_equal = 0x2; + + for (uint w = 0; w < 4; w++) + { + if (CPU.VPR[va]._f[w] == CPU.VPR[vb]._f[w]) { - t &= (CPU.VPR[vb]._u8[b] & 0x7) == sh; - } - - if(t) - { - CPU.VPR[vd]._u8[0] = CPU.VPR[va]._u8[0] << sh; - - for (uint b = 1; b < 16; b++) - { - CPU.VPR[vd]._u8[b] = (CPU.VPR[va]._u8[b] << sh) | (CPU.VPR[va]._u8[b-1] >> (8 - sh)); - } + CPU.VPR[vd]._u32[w] = 0xffffffff; + none_equal = 0; } else { - //undefined - CPU.VPR[vd]._u32[0] = 0xCDCDCDCD; - CPU.VPR[vd]._u32[1] = 0xCDCDCDCD; - CPU.VPR[vd]._u32[2] = 0xCDCDCDCD; - CPU.VPR[vd]._u32[3] = 0xCDCDCDCD; + CPU.VPR[vd]._u32[w] = 0; + all_equal = 0; } } - void VSLB(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint b = 0; b < 16; b++) - { - CPU.VPR[vd]._u8[b] = CPU.VPR[va]._u8[b] << (CPU.VPR[vb]._u8[b] & 0x7); - } - } - void VSLDOI(OP_REG vd, OP_REG va, OP_REG vb, OP_uIMM sh) - { - for (uint b = 0; b < 16 - sh; b++) - { - CPU.VPR[vd]._u8[15 - b] = CPU.VPR[va]._u8[15 - (b + sh)]; - } - for (uint b = 16 - sh; b < 16; b++) - { - CPU.VPR[vd]._u8[15 - b] = CPU.VPR[vb]._u8[15 - (b - (16 - sh))]; - } - } - void VSLH(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._u16[h] = CPU.VPR[va]._u16[h] << (CPU.VPR[vb]._u8[h*2] & 0xf); - } - } - void VSLO(OP_REG vd, OP_REG va, OP_REG vb) - { - u8 nShift = (CPU.VPR[vb]._u8[0] >> 3) & 0xf; - CPU.VPR[vd].Clear(); - - for (u8 b = 0; b < 16 - nShift; b++) - { - CPU.VPR[vd]._u8[15 - b] = CPU.VPR[va]._u8[15 - (b + nShift)]; - } - } - void VSLW(OP_REG vd, OP_REG va, OP_REG vb) + CPU.CR.cr6 = all_equal | none_equal; + } + void VCMPEQUB(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 16; b++) { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] << (CPU.VPR[vb]._u8[w*4] & 0x1f); - } + CPU.VPR[vd]._u8[b] = CPU.VPR[va]._u8[b] == CPU.VPR[vb]._u8[b] ? 0xff : 0; } - void VSPLTB(OP_REG vd, OP_uIMM uimm5, OP_REG vb) - { - u8 byte = CPU.VPR[vb]._u8[15 - uimm5]; + } + void VCMPEQUB_(u32 vd, u32 va, u32 vb) + { + int all_equal = 0x8; + int none_equal = 0x2; - for (uint b = 0; b < 16; b++) - { - CPU.VPR[vd]._u8[b] = byte; - } - } - void VSPLTH(OP_REG vd, OP_uIMM uimm5, OP_REG vb) + for (uint b = 0; b < 16; b++) { - assert(uimm5 < 8); - - u16 hword = CPU.VPR[vb]._u16[7 - uimm5]; - - for (uint h = 0; h < 8; h++) + if (CPU.VPR[va]._u8[b] == CPU.VPR[vb]._u8[b]) { - CPU.VPR[vd]._u16[h] = hword; - } - } - void VSPLTISB(OP_REG vd, OP_sIMM simm5) - { - for (uint b = 0; b < 16; b++) - { - CPU.VPR[vd]._u8[b] = simm5; - } - } - void VSPLTISH(OP_REG vd, OP_sIMM simm5) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._u16[h] = (s16)simm5; - } - } - void VSPLTISW(OP_REG vd, OP_sIMM simm5) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = (s32)simm5; - } - } - void VSPLTW(OP_REG vd, OP_uIMM uimm5, OP_REG vb) - { - assert(uimm5 < 4); - - u32 word = CPU.VPR[vb]._u32[uimm5]; - - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = word; - } - } - void VSR(OP_REG vd, OP_REG va, OP_REG vb) - { - u8 sh = CPU.VPR[vb]._u8[0] & 0x7; - u32 t = 1; - - for (uint b = 0; b < 16; b++) - { - t &= (CPU.VPR[vb]._u8[b] & 0x7) == sh; - } - - if(t) - { - CPU.VPR[vd]._u8[15] = CPU.VPR[va]._u8[15] >> sh; - - for (uint b = 14; b >= 0; b--) - { - CPU.VPR[vd]._u8[b] = (CPU.VPR[va]._u8[b] >> sh) | (CPU.VPR[va]._u8[b+1] << (8 - sh)); - } + CPU.VPR[vd]._u8[b] = 0xff; + none_equal = 0; } else { - //undefined - CPU.VPR[vd]._u32[0] = 0xCDCDCDCD; - CPU.VPR[vd]._u32[1] = 0xCDCDCDCD; - CPU.VPR[vd]._u32[2] = 0xCDCDCDCD; - CPU.VPR[vd]._u32[3] = 0xCDCDCDCD; + CPU.VPR[vd]._u8[b] = 0; + all_equal = 0; } } - void VSRAB(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint b = 0; b < 16; b++) - { - CPU.VPR[vd]._s8[b] = CPU.VPR[va]._s8[b] >> (CPU.VPR[vb]._u8[b] & 0x7); - } - } - void VSRAH(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._s16[h] = CPU.VPR[va]._s16[h] >> (CPU.VPR[vb]._u8[h*2] & 0xf); - } - } - void VSRAW(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._s32[w] = CPU.VPR[va]._s32[w] >> (CPU.VPR[vb]._u8[w*4] & 0x1f); - } - } - void VSRB(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint b = 0; b < 16; b++) - { - CPU.VPR[vd]._u8[b] = CPU.VPR[va]._u8[b] >> (CPU.VPR[vb]._u8[b] & 0x7); - } - } - void VSRH(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._u16[h] = CPU.VPR[va]._u16[h] >> (CPU.VPR[vb]._u8[h*2] & 0xf); - } - } - void VSRO(OP_REG vd, OP_REG va, OP_REG vb) - { - u8 nShift = (CPU.VPR[vb]._u8[0] >> 3) & 0xf; - CPU.VPR[vd].Clear(); - - for (u8 b = 0; b < 16 - nShift; b++) - { - CPU.VPR[vd]._u8[b] = CPU.VPR[va]._u8[b + nShift]; - } - } - void VSRW(OP_REG vd, OP_REG va, OP_REG vb) + CPU.CR.cr6 = all_equal | none_equal; + } + void VCMPEQUH(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] >> (CPU.VPR[vb]._u8[w*4] & 0x1f); - } + CPU.VPR[vd]._u16[h] = CPU.VPR[va]._u16[h] == CPU.VPR[vb]._u16[h] ? 0xffff : 0; } - void VSUBCUW(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] < CPU.VPR[vb]._u32[w] ? 0 : 1; - } - } - void VSUBFP(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._f[w] = CPU.VPR[va]._f[w] - CPU.VPR[vb]._f[w]; - } - } - void VSUBSBS(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint b = 0; b < 16; b++) - { - s16 result = (s16)CPU.VPR[va]._s8[b] - (s16)CPU.VPR[vb]._s8[b]; - - if (result < INT8_MIN) - { - CPU.VPR[vd]._s8[b] = INT8_MIN; - CPU.VSCR.SAT = 1; - } - else if (result > INT8_MAX) - { - CPU.VPR[vd]._s8[b] = INT8_MAX; - CPU.VSCR.SAT = 1; - } - else - CPU.VPR[vd]._s8[b] = (s8)result; - } - } - void VSUBSHS(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - s32 result = (s32)CPU.VPR[va]._s16[h] - (s32)CPU.VPR[vb]._s16[h]; - - if (result < INT16_MIN) - { - CPU.VPR[vd]._s16[h] = (s16)INT16_MIN; - CPU.VSCR.SAT = 1; - } - else if (result > INT16_MAX) - { - CPU.VPR[vd]._s16[h] = (s16)INT16_MAX; - CPU.VSCR.SAT = 1; - } - else - CPU.VPR[vd]._s16[h] = (s16)result; - } - } - void VSUBSWS(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - s64 result = (s64)CPU.VPR[va]._s32[w] - (s64)CPU.VPR[vb]._s32[w]; - - if (result < INT32_MIN) - { - CPU.VPR[vd]._s32[w] = (s32)INT32_MIN; - CPU.VSCR.SAT = 1; - } - else if (result > INT32_MAX) - { - CPU.VPR[vd]._s32[w] = (s32)INT32_MAX; - CPU.VSCR.SAT = 1; - } - else - CPU.VPR[vd]._s32[w] = (s32)result; - } - } - void VSUBUBM(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint b = 0; b < 16; b++) - { - CPU.VPR[vd]._u8[b] = (u8)((CPU.VPR[va]._u8[b] - CPU.VPR[vb]._u8[b]) & 0xff); - } - } - void VSUBUBS(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint b = 0; b < 16; b++) - { - s16 result = (s16)CPU.VPR[va]._u8[b] - (s16)CPU.VPR[vb]._u8[b]; - - if (result < 0) - { - CPU.VPR[vd]._u8[b] = 0; - CPU.VSCR.SAT = 1; - } - else - CPU.VPR[vd]._u8[b] = (u8)result; - } - } - void VSUBUHM(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._u16[h] = CPU.VPR[va]._u16[h] - CPU.VPR[vb]._u16[h]; - } - } - void VSUBUHS(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint h = 0; h < 8; h++) - { - s32 result = (s32)CPU.VPR[va]._u16[h] - (s32)CPU.VPR[vb]._u16[h]; - - if (result < 0) - { - CPU.VPR[vd]._u16[h] = 0; - CPU.VSCR.SAT = 1; - } - else - CPU.VPR[vd]._u16[h] = (u16)result; - } - } - void VSUBUWM(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] - CPU.VPR[vb]._u32[w]; - } - } - void VSUBUWS(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) - { - s64 result = (s64)CPU.VPR[va]._u32[w] - (s64)CPU.VPR[vb]._u32[w]; - - if (result < 0) - { - CPU.VPR[vd]._u32[w] = 0; - CPU.VSCR.SAT = 1; - } - else - CPU.VPR[vd]._u32[w] = (u32)result; - } - } - void VSUMSWS(OP_REG vd, OP_REG va, OP_REG vb) - { - CPU.VPR[vd].Clear(); + } + void VCMPEQUH_(u32 vd, u32 va, u32 vb) + { + int all_equal = 0x8; + int none_equal = 0x2; - s64 sum = CPU.VPR[vb]._s32[3]; - - for (uint w = 0; w < 4; w++) + for (uint h = 0; h < 8; h++) + { + if (CPU.VPR[va]._u16[h] == CPU.VPR[vb]._u16[h]) { - sum += CPU.VPR[va]._s32[w]; + CPU.VPR[vd]._u16[h] = 0xffff; + none_equal = 0; } + else + { + CPU.VPR[vd]._u16[h] = 0; + all_equal = 0; + } + } + + CPU.CR.cr6 = all_equal | none_equal; + } + void VCMPEQUW(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] == CPU.VPR[vb]._u32[w] ? 0xffffffff : 0; + } + } + void VCMPEQUW_(u32 vd, u32 va, u32 vb) + { + int all_equal = 0x8; + int none_equal = 0x2; + + for (uint w = 0; w < 4; w++) + { + if (CPU.VPR[va]._u32[w] == CPU.VPR[vb]._u32[w]) + { + CPU.VPR[vd]._u32[w] = 0xffffffff; + none_equal = 0; + } + else + { + CPU.VPR[vd]._u32[w] = 0; + all_equal = 0; + } + } + + CPU.CR.cr6 = all_equal | none_equal; + } + void VCMPGEFP(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u32[w] = CPU.VPR[va]._f[w] >= CPU.VPR[vb]._f[w] ? 0xffffffff : 0; + } + } + void VCMPGEFP_(u32 vd, u32 va, u32 vb) + { + int all_ge = 0x8; + int none_ge = 0x2; + + for (uint w = 0; w < 4; w++) + { + if (CPU.VPR[va]._f[w] >= CPU.VPR[vb]._f[w]) + { + CPU.VPR[vd]._u32[w] = 0xffffffff; + none_ge = 0; + } + else + { + CPU.VPR[vd]._u32[w] = 0; + all_ge = 0; + } + } + + CPU.CR.cr6 = all_ge | none_ge; + } + void VCMPGTFP(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u32[w] = CPU.VPR[va]._f[w] > CPU.VPR[vb]._f[w] ? 0xffffffff : 0; + } + } + void VCMPGTFP_(u32 vd, u32 va, u32 vb) + { + int all_ge = 0x8; + int none_ge = 0x2; + + for (uint w = 0; w < 4; w++) + { + if (CPU.VPR[va]._f[w] > CPU.VPR[vb]._f[w]) + { + CPU.VPR[vd]._u32[w] = 0xffffffff; + none_ge = 0; + } + else + { + CPU.VPR[vd]._u32[w] = 0; + all_ge = 0; + } + } + + CPU.CR.cr6 = all_ge | none_ge; + } + void VCMPGTSB(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 16; b++) + { + CPU.VPR[vd]._u8[b] = CPU.VPR[va]._s8[b] > CPU.VPR[vb]._s8[b] ? 0xff : 0; + } + } + void VCMPGTSB_(u32 vd, u32 va, u32 vb) + { + int all_gt = 0x8; + int none_gt = 0x2; + + for (uint b = 0; b < 16; b++) + { + if (CPU.VPR[va]._s8[b] > CPU.VPR[vb]._s8[b]) + { + CPU.VPR[vd]._u8[b] = 0xff; + none_gt = 0; + } + else + { + CPU.VPR[vd]._u8[b] = 0; + all_gt = 0; + } + } + + CPU.CR.cr6 = all_gt | none_gt; + } + void VCMPGTSH(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) + { + CPU.VPR[vd]._u16[h] = CPU.VPR[va]._s16[h] > CPU.VPR[vb]._s16[h] ? 0xffff : 0; + } + } + void VCMPGTSH_(u32 vd, u32 va, u32 vb) + { + int all_gt = 0x8; + int none_gt = 0x2; + + for (uint h = 0; h < 8; h++) + { + if (CPU.VPR[va]._s16[h] > CPU.VPR[vb]._s16[h]) + { + CPU.VPR[vd]._u16[h] = 0xffff; + none_gt = 0; + } + else + { + CPU.VPR[vd]._u16[h] = 0; + all_gt = 0; + } + } + + CPU.CR.cr6 = all_gt | none_gt; + } + void VCMPGTSW(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u32[w] = CPU.VPR[va]._s32[w] > CPU.VPR[vb]._s32[w] ? 0xffffffff : 0; + } + } + void VCMPGTSW_(u32 vd, u32 va, u32 vb) + { + int all_gt = 0x8; + int none_gt = 0x2; + + for (uint w = 0; w < 4; w++) + { + if (CPU.VPR[va]._s32[w] > CPU.VPR[vb]._s32[w]) + { + CPU.VPR[vd]._u32[w] = 0xffffffff; + none_gt = 0; + } + else + { + CPU.VPR[vd]._u32[w] = 0; + all_gt = 0; + } + } + + CPU.CR.cr6 = all_gt | none_gt; + } + void VCMPGTUB(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 16; b++) + { + CPU.VPR[vd]._u8[b] = CPU.VPR[va]._u8[b] > CPU.VPR[vb]._u8[b] ? 0xff : 0; + } + } + void VCMPGTUB_(u32 vd, u32 va, u32 vb) + { + int all_gt = 0x8; + int none_gt = 0x2; + + for (uint b = 0; b < 16; b++) + { + if (CPU.VPR[va]._u8[b] > CPU.VPR[vb]._u8[b]) + { + CPU.VPR[vd]._u8[b] = 0xff; + none_gt = 0; + } + else + { + CPU.VPR[vd]._u8[b] = 0; + all_gt = 0; + } + } + + CPU.CR.cr6 = all_gt | none_gt; + } + void VCMPGTUH(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) + { + CPU.VPR[vd]._u16[h] = CPU.VPR[va]._u16[h] > CPU.VPR[vb]._u16[h] ? 0xffff : 0; + } + } + void VCMPGTUH_(u32 vd, u32 va, u32 vb) + { + int all_gt = 0x8; + int none_gt = 0x2; + + for (uint h = 0; h < 8; h++) + { + if (CPU.VPR[va]._u16[h] > CPU.VPR[vb]._u16[h]) + { + CPU.VPR[vd]._u16[h] = 0xffff; + none_gt = 0; + } + else + { + CPU.VPR[vd]._u16[h] = 0; + all_gt = 0; + } + } + + CPU.CR.cr6 = all_gt | none_gt; + } + void VCMPGTUW(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] > CPU.VPR[vb]._u32[w] ? 0xffffffff : 0; + } + } + void VCMPGTUW_(u32 vd, u32 va, u32 vb) + { + int all_gt = 0x8; + int none_gt = 0x2; + + for (uint w = 0; w < 4; w++) + { + if (CPU.VPR[va]._u32[w] > CPU.VPR[vb]._u32[w]) + { + CPU.VPR[vd]._u32[w] = 0xffffffff; + none_gt = 0; + } + else + { + CPU.VPR[vd]._u32[w] = 0; + all_gt = 0; + } + } + + CPU.CR.cr6 = all_gt | none_gt; + } + void VCTSXS(u32 vd, u32 uimm5, u32 vb) + { + int nScale = 1 << uimm5; + + for (uint w = 0; w < 4; w++) + { + // C rounding = Round towards 0 + s64 result = (s64)(CPU.VPR[vb]._f[w] * nScale); + + if (result > INT_MAX) + CPU.VPR[vd]._s32[w] = (int)INT_MAX; + else if (result < INT_MIN) + CPU.VPR[vd]._s32[w] = (int)INT_MIN; + else + CPU.VPR[vd]._s32[w] = (int)result; + } + } + void VCTUXS(u32 vd, u32 uimm5, u32 vb) + { + int nScale = 1 << uimm5; + + for (uint w = 0; w < 4; w++) + { + // C rounding = Round towards 0 + s64 result = (s64)(CPU.VPR[vb]._f[w] * nScale); + + if (result > UINT_MAX) + CPU.VPR[vd]._u32[w] = (u32)UINT_MAX; + else if (result < 0) + CPU.VPR[vd]._u32[w] = 0; + else + CPU.VPR[vd]._u32[w] = (u32)result; + } + } + void VEXPTEFP(u32 vd, u32 vb) + { + // vd = exp(vb * log(2)) + // ISA : Note that the value placed into the element of vD may vary between implementations + // and between different executions on the same implementation. + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._f[w] = exp(CPU.VPR[vb]._f[w] * log(2.0f)); + } + } + void VLOGEFP(u32 vd, u32 vb) + { + // ISA : Note that the value placed into the element of vD may vary between implementations + // and between different executions on the same implementation. + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._f[w] = log(CPU.VPR[vb]._f[w]) / log(2.0f); + } + } + void VMADDFP(u32 vd, u32 va, u32 vb, u32 vc) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._f[w] = CPU.VPR[va]._f[w] * CPU.VPR[vc]._f[w] + CPU.VPR[vb]._f[w]; + } + } + void VMAXFP(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._f[w] = max(CPU.VPR[va]._f[w], CPU.VPR[vb]._f[w]); + } + } + void VMAXSB(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 16; b++) + CPU.VPR[vd]._s8[b] = max(CPU.VPR[va]._s8[b], CPU.VPR[vb]._s8[b]); + } + void VMAXSH(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) + { + CPU.VPR[vd]._s16[h] = max(CPU.VPR[va]._s16[h], CPU.VPR[vb]._s16[h]); + } + } + void VMAXSW(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._s32[w] = max(CPU.VPR[va]._s32[w], CPU.VPR[vb]._s32[w]); + } + } + void VMAXUB(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 16; b++) + CPU.VPR[vd]._u8[b] = max(CPU.VPR[va]._u8[b], CPU.VPR[vb]._u8[b]); + } + void VMAXUH(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) + { + CPU.VPR[vd]._u16[h] = max(CPU.VPR[va]._u16[h], CPU.VPR[vb]._u16[h]); + } + } + void VMAXUW(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u32[w] = max(CPU.VPR[va]._u32[w], CPU.VPR[vb]._u32[w]); + } + } + void VMHADDSHS(u32 vd, u32 va, u32 vb, u32 vc) + { + for (uint h = 0; h < 8; h++) + { + s32 result = (s32)CPU.VPR[va]._s16[h] * (s32)CPU.VPR[vb]._s16[h] + (s32)CPU.VPR[vc]._s16[h]; + + if (result > INT16_MAX) + { + CPU.VPR[vd]._s16[h] = (s16)INT16_MAX; + CPU.VSCR.SAT = 1; + } + else if (result < INT16_MIN) + { + CPU.VPR[vd]._s16[h] = (s16)INT16_MIN; + CPU.VSCR.SAT = 1; + } + else + CPU.VPR[vd]._s16[h] = (s16)result; + } + } + void VMHRADDSHS(u32 vd, u32 va, u32 vb, u32 vc) + { + for (uint h = 0; h < 8; h++) + { + s32 result = (s32)CPU.VPR[va]._s16[h] * (s32)CPU.VPR[vb]._s16[h] + (s32)CPU.VPR[vc]._s16[h] + 0x4000; + + if (result > INT16_MAX) + { + CPU.VPR[vd]._s16[h] = (s16)INT16_MAX; + CPU.VSCR.SAT = 1; + } + else if (result < INT16_MIN) + { + CPU.VPR[vd]._s16[h] = (s16)INT16_MIN; + CPU.VSCR.SAT = 1; + } + else + CPU.VPR[vd]._s16[h] = (s16)result; + } + } + void VMINFP(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._f[w] = min(CPU.VPR[va]._f[w], CPU.VPR[vb]._f[w]); + } + } + void VMINSB(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 16; b++) + { + CPU.VPR[vd]._s8[b] = min(CPU.VPR[va]._s8[b], CPU.VPR[vb]._s8[b]); + } + } + void VMINSH(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) + { + CPU.VPR[vd]._s16[h] = min(CPU.VPR[va]._s16[h], CPU.VPR[vb]._s16[h]); + } + } + void VMINSW(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._s32[w] = min(CPU.VPR[va]._s32[w], CPU.VPR[vb]._s32[w]); + } + } + void VMINUB(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 16; b++) + { + CPU.VPR[vd]._u8[b] = min(CPU.VPR[va]._u8[b], CPU.VPR[vb]._u8[b]); + } + } + void VMINUH(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) + { + CPU.VPR[vd]._u16[h] = min(CPU.VPR[va]._u16[h], CPU.VPR[vb]._u16[h]); + } + } + void VMINUW(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u32[w] = min(CPU.VPR[va]._u32[w], CPU.VPR[vb]._u32[w]); + } + } + void VMLADDUHM(u32 vd, u32 va, u32 vb, u32 vc) + { + for (uint h = 0; h < 8; h++) + { + CPU.VPR[vd]._u16[h] = CPU.VPR[va]._u16[h] * CPU.VPR[vb]._u16[h] + CPU.VPR[vc]._u16[h]; + } + } + void VMRGHB(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) + { + CPU.VPR[vd]._u8[h*2] = CPU.VPR[va]._u8[h]; + CPU.VPR[vd]._u8[h*2 + 1] = CPU.VPR[vb]._u8[h]; + } + } + void VMRGHH(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u16[w*2] = CPU.VPR[va]._u16[w]; + CPU.VPR[vd]._u16[w*2 + 1] = CPU.VPR[vb]._u16[w]; + } + } + void VMRGHW(u32 vd, u32 va, u32 vb) + { + for (uint d = 0; d < 2; d++) + { + CPU.VPR[vd]._u32[d*2] = CPU.VPR[va]._u32[d]; + CPU.VPR[vd]._u32[d*2 + 1] = CPU.VPR[vb]._u32[d]; + } + } + void VMRGLB(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) + { + CPU.VPR[vd]._u8[h*2] = CPU.VPR[va]._u8[h + 8]; + CPU.VPR[vd]._u8[h*2 + 1] = CPU.VPR[vb]._u8[h + 8]; + } + } + void VMRGLH(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u16[w*2] = CPU.VPR[va]._u16[w + 4]; + CPU.VPR[vd]._u16[w*2 + 1] = CPU.VPR[vb]._u16[w + 4]; + } + } + void VMRGLW(u32 vd, u32 va, u32 vb) + { + for (uint d = 0; d < 2; d++) + { + CPU.VPR[vd]._u32[d*2] = CPU.VPR[va]._u32[d + 2]; + CPU.VPR[vd]._u32[d*2 + 1] = CPU.VPR[vb]._u32[d + 2]; + } + } + void VMSUMMBM(u32 vd, u32 va, u32 vb, u32 vc) + { + for (uint w = 0; w < 4; w++) + { + s32 result = 0; + + for (uint b = 0; b < 4; b++) + { + result += CPU.VPR[va]._s8[w*4 + b] * CPU.VPR[vb]._u8[w*4 + b]; + } + + result += CPU.VPR[vc]._s32[w]; + CPU.VPR[vd]._s32[w] = result; + } + } + void VMSUMSHM(u32 vd, u32 va, u32 vb, u32 vc) + { + for (uint w = 0; w < 4; w++) + { + s32 result = 0; + + for (uint h = 0; h < 2; h++) + { + result += CPU.VPR[va]._s16[w*2 + h] * CPU.VPR[vb]._s16[w*2 + h]; + } + + result += CPU.VPR[vc]._s32[w]; + CPU.VPR[vd]._s32[w] = result; + } + } + void VMSUMSHS(u32 vd, u32 va, u32 vb, u32 vc) + { + for (uint w = 0; w < 4; w++) + { + s64 result = 0; + s32 saturated = 0; + + for (uint h = 0; h < 2; h++) + { + result += CPU.VPR[va]._s16[w*2 + h] * CPU.VPR[vb]._s16[w*2 + h]; + } + + result += CPU.VPR[vc]._s32[w]; + + if (result > INT_MAX) + { + saturated = INT_MAX; + CPU.VSCR.SAT = 1; + } + else if (result < INT_MIN) + { + saturated = INT_MIN; + CPU.VSCR.SAT = 1; + } + else + saturated = (s32)result; + + CPU.VPR[vd]._s32[w] = saturated; + } + } + void VMSUMUBM(u32 vd, u32 va, u32 vb, u32 vc) + { + for (uint w = 0; w < 4; w++) + { + u32 result = 0; + + for (uint b = 0; b < 4; b++) + { + result += CPU.VPR[va]._u8[w*4 + b] * CPU.VPR[vb]._u8[w*4 + b]; + } + + result += CPU.VPR[vc]._u32[w]; + CPU.VPR[vd]._u32[w] = result; + } + } + void VMSUMUHM(u32 vd, u32 va, u32 vb, u32 vc) + { + for (uint w = 0; w < 4; w++) + { + u32 result = 0; + + for (uint h = 0; h < 2; h++) + { + result += CPU.VPR[va]._u16[w*2 + h] * CPU.VPR[vb]._u16[w*2 + h]; + } + + result += CPU.VPR[vc]._u32[w]; + CPU.VPR[vd]._u32[w] = result; + } + } + void VMSUMUHS(u32 vd, u32 va, u32 vb, u32 vc) + { + for (uint w = 0; w < 4; w++) + { + u64 result = 0; + u32 saturated = 0; + + for (uint h = 0; h < 2; h++) + { + result += CPU.VPR[va]._u16[w*2 + h] * CPU.VPR[vb]._u16[w*2 + h]; + } + + result += CPU.VPR[vc]._u32[w]; + + if (result > UINT_MAX) + { + saturated = UINT_MAX; + CPU.VSCR.SAT = 1; + } + else + saturated = (u32)result; + + CPU.VPR[vd]._u32[w] = saturated; + } + } + void VMULESB(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) + { + CPU.VPR[vd]._s16[h] = (s16)CPU.VPR[va]._s8[h*2+1] * (s16)CPU.VPR[vb]._s8[h*2+1]; + } + } + void VMULESH(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._s32[w] = (s32)CPU.VPR[va]._s16[w*2+1] * (s32)CPU.VPR[vb]._s16[w*2+1]; + } + } + void VMULEUB(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) + { + CPU.VPR[vd]._u16[h] = (u16)CPU.VPR[va]._u8[h*2+1] * (u16)CPU.VPR[vb]._u8[h*2+1]; + } + } + void VMULEUH(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u32[w] = (u32)CPU.VPR[va]._u16[w*2+1] * (u32)CPU.VPR[vb]._u16[w*2+1]; + } + } + void VMULOSB(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) + { + CPU.VPR[vd]._s16[h] = (s16)CPU.VPR[va]._s8[h*2] * (s16)CPU.VPR[vb]._s8[h*2]; + } + } + void VMULOSH(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._s32[w] = (s32)CPU.VPR[va]._s16[w*2] * (s32)CPU.VPR[vb]._s16[w*2]; + } + } + void VMULOUB(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) + { + CPU.VPR[vd]._u16[h] = (u16)CPU.VPR[va]._u8[h*2] * (u16)CPU.VPR[vb]._u8[h*2]; + } + } + void VMULOUH(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u32[w] = (u32)CPU.VPR[va]._u16[w*2] * (u32)CPU.VPR[vb]._u16[w*2]; + } + } + void VNMSUBFP(u32 vd, u32 va, u32 vb, u32 vc) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._f[w] = (double)CPU.VPR[vb]._f[w] - (double)CPU.VPR[va]._f[w] * (double)CPU.VPR[vc]._f[w]; + } + } + void VNOR(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u32[w] = ~(CPU.VPR[va]._u32[w] | CPU.VPR[vb]._u32[w]); + } + } + void VOR(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] | CPU.VPR[vb]._u32[w]; + } + } + void VPERM(u32 vd, u32 va, u32 vb, u32 vc) + { + for (uint b = 0; b < 16; b++) + { + u8 index = CPU.VPR[vc]._u8[b] & 0x1f; + + CPU.VPR[vd]._u8[b] = index < 0x10 ? CPU.VPR[va]._u8[0xf - index] : CPU.VPR[vb]._u8[0xf - (index - 0x10)]; + } + } + void VPKPX(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 4; h++) + { + u16 bb7 = CPU.VPR[vb]._u8[15 - (h*4 + 0)] & 0x1; + u16 bb8 = CPU.VPR[vb]._u8[15 - (h*4 + 1)] >> 3; + u16 bb16 = CPU.VPR[vb]._u8[15 - (h*4 + 2)] >> 3; + u16 bb24 = CPU.VPR[vb]._u8[15 - (h*4 + 3)] >> 3; + u16 ab7 = CPU.VPR[va]._u8[15 - (h*4 + 0)] & 0x1; + u16 ab8 = CPU.VPR[va]._u8[15 - (h*4 + 1)] >> 3; + u16 ab16 = CPU.VPR[va]._u8[15 - (h*4 + 2)] >> 3; + u16 ab24 = CPU.VPR[va]._u8[15 - (h*4 + 3)] >> 3; + + CPU.VPR[vd]._u16[3 - h] = (bb7 << 15) | (bb8 << 10) | (bb16 << 5) | bb24; + CPU.VPR[vd]._u16[4 + (3 - h)] = (ab7 << 15) | (ab8 << 10) | (ab16 << 5) | ab24; + } + } + void VPKSHSS(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 8; b++) + { + s16 result = CPU.VPR[va]._s16[b]; + + if (result > INT8_MAX) + { + result = INT8_MAX; + CPU.VSCR.SAT = 1; + } + else if (result < INT8_MIN) + { + result = INT8_MIN; + CPU.VSCR.SAT = 1; + } + + CPU.VPR[vd]._s8[b+8] = result; + + result = CPU.VPR[vb]._s16[b]; + + if (result > INT8_MAX) + { + result = INT8_MAX; + CPU.VSCR.SAT = 1; + } + else if (result < INT8_MIN) + { + result = INT8_MIN; + CPU.VSCR.SAT = 1; + } + + CPU.VPR[vd]._s8[b] = result; + } + } + void VPKSHUS(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 8; b++) + { + s16 result = CPU.VPR[va]._s16[b]; + + if (result > UINT8_MAX) + { + result = UINT8_MAX; + CPU.VSCR.SAT = 1; + } + else if (result < 0) + { + result = 0; + CPU.VSCR.SAT = 1; + } + + CPU.VPR[vd]._u8[b+8] = result; + + result = CPU.VPR[vb]._s16[b]; + + if (result > UINT8_MAX) + { + result = UINT8_MAX; + CPU.VSCR.SAT = 1; + } + else if (result < 0) + { + result = 0; + CPU.VSCR.SAT = 1; + } + + CPU.VPR[vd]._u8[b] = result; + } + } + void VPKSWSS(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 4; h++) + { + s32 result = CPU.VPR[va]._s32[h]; + + if (result > INT16_MAX) + { + result = INT16_MAX; + CPU.VSCR.SAT = 1; + } + else if (result < INT16_MIN) + { + result = INT16_MIN; + CPU.VSCR.SAT = 1; + } + + CPU.VPR[vd]._s16[h+4] = result; + + result = CPU.VPR[vb]._s32[h]; + + if (result > INT16_MAX) + { + result = INT16_MAX; + CPU.VSCR.SAT = 1; + } + else if (result < INT16_MIN) + { + result = INT16_MIN; + CPU.VSCR.SAT = 1; + } + + CPU.VPR[vd]._s16[h] = result; + } + } + void VPKSWUS(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 4; h++) + { + s32 result = CPU.VPR[va]._s32[h]; + + if (result > UINT16_MAX) + { + result = UINT16_MAX; + CPU.VSCR.SAT = 1; + } + else if (result < 0) + { + result = 0; + CPU.VSCR.SAT = 1; + } + + CPU.VPR[vd]._u16[h+4] = result; + + result = CPU.VPR[vb]._s32[h]; + + if (result > UINT16_MAX) + { + result = UINT16_MAX; + CPU.VSCR.SAT = 1; + } + else if (result < 0) + { + result = 0; + CPU.VSCR.SAT = 1; + } + + CPU.VPR[vd]._u16[h] = result; + } + } + void VPKUHUM(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 8; b++) + { + CPU.VPR[vd]._u8[b+8] = CPU.VPR[va]._u8[b*2]; + CPU.VPR[vd]._u8[b ] = CPU.VPR[vb]._u8[b*2]; + } + } + void VPKUHUS(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 8; b++) + { + u16 result = CPU.VPR[va]._u16[b]; + + if (result > UINT8_MAX) + { + result = UINT8_MAX; + CPU.VSCR.SAT = 1; + } + + CPU.VPR[vd]._u8[b+8] = result; + + result = CPU.VPR[vb]._u16[b]; + + if (result > UINT8_MAX) + { + result = UINT8_MAX; + CPU.VSCR.SAT = 1; + } + + CPU.VPR[vd]._u8[b] = result; + } + } + void VPKUWUM(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 4; h++) + { + CPU.VPR[vd]._u16[h+4] = CPU.VPR[va]._u16[h*2]; + CPU.VPR[vd]._u16[h ] = CPU.VPR[vb]._u16[h*2]; + } + } + void VPKUWUS(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 4; h++) + { + u32 result = CPU.VPR[va]._u32[h]; + + if (result > UINT16_MAX) + { + result = UINT16_MAX; + CPU.VSCR.SAT = 1; + } + + CPU.VPR[vd]._u16[h+4] = result; + + result = CPU.VPR[vb]._u32[h]; + + if (result > UINT16_MAX) + { + result = UINT16_MAX; + CPU.VSCR.SAT = 1; + } + + CPU.VPR[vd]._u16[h] = result; + } + } + void VREFP(u32 vd, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._f[w] = 1.0f / CPU.VPR[vb]._f[w]; + } + } + void VRFIM(u32 vd, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._f[w] = floor(CPU.VPR[vb]._f[w]); + } + } + void VRFIN(u32 vd, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._f[w] = floor(CPU.VPR[vb]._f[w] + 0.5f); + } + } + void VRFIP(u32 vd, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._f[w] = ceil(CPU.VPR[vb]._f[w]); + } + } + void VRFIZ(u32 vd, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + float f; + modf(CPU.VPR[vb]._f[w], &f); + CPU.VPR[vd]._f[w] = f; + } + } + void VRLB(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 16; b++) + { + int nRot = CPU.VPR[vb]._u8[b] & 0x7; + + CPU.VPR[vd]._u8[b] = (CPU.VPR[va]._u8[b] << nRot) | (CPU.VPR[va]._u8[b] >> (8 - nRot)); + } + } + void VRLH(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) + { + CPU.VPR[vd]._u16[h] = rotl16(CPU.VPR[va]._u16[h], CPU.VPR[vb]._u8[h*2] & 0xf); + } + } + void VRLW(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u32[w] = rotl32(CPU.VPR[va]._u32[w], CPU.VPR[vb]._u8[w*4] & 0x1f); + } + } + void VRSQRTEFP(u32 vd, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + //TODO: accurate div + CPU.VPR[vd]._f[w] = 1.0f / sqrtf(CPU.VPR[vb]._f[w]); + } + } + void VSEL(u32 vd, u32 va, u32 vb, u32 vc) + { + for (uint b = 0; b < 16; b++) + { + CPU.VPR[vd]._u8[b] = (CPU.VPR[vb]._u8[b] & CPU.VPR[vc]._u8[b]) | (CPU.VPR[va]._u8[b] & (~CPU.VPR[vc]._u8[b])); + } + } + void VSL(u32 vd, u32 va, u32 vb) + { + u8 sh = CPU.VPR[vb]._u8[0] & 0x7; + + u32 t = 1; + + for (uint b = 0; b < 16; b++) + { + t &= (CPU.VPR[vb]._u8[b] & 0x7) == sh; + } + + if(t) + { + CPU.VPR[vd]._u8[0] = CPU.VPR[va]._u8[0] << sh; + + for (uint b = 1; b < 16; b++) + { + CPU.VPR[vd]._u8[b] = (CPU.VPR[va]._u8[b] << sh) | (CPU.VPR[va]._u8[b-1] >> (8 - sh)); + } + } + else + { + //undefined + CPU.VPR[vd]._u32[0] = 0xCDCDCDCD; + CPU.VPR[vd]._u32[1] = 0xCDCDCDCD; + CPU.VPR[vd]._u32[2] = 0xCDCDCDCD; + CPU.VPR[vd]._u32[3] = 0xCDCDCDCD; + } + } + void VSLB(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 16; b++) + { + CPU.VPR[vd]._u8[b] = CPU.VPR[va]._u8[b] << (CPU.VPR[vb]._u8[b] & 0x7); + } + } + void VSLDOI(u32 vd, u32 va, u32 vb, u32 sh) + { + for (uint b = 0; b < 16 - sh; b++) + { + CPU.VPR[vd]._u8[15 - b] = CPU.VPR[va]._u8[15 - (b + sh)]; + } + for (uint b = 16 - sh; b < 16; b++) + { + CPU.VPR[vd]._u8[15 - b] = CPU.VPR[vb]._u8[15 - (b - (16 - sh))]; + } + } + void VSLH(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) + { + CPU.VPR[vd]._u16[h] = CPU.VPR[va]._u16[h] << (CPU.VPR[vb]._u8[h*2] & 0xf); + } + } + void VSLO(u32 vd, u32 va, u32 vb) + { + u8 nShift = (CPU.VPR[vb]._u8[0] >> 3) & 0xf; + + CPU.VPR[vd].Clear(); + + for (u8 b = 0; b < 16 - nShift; b++) + { + CPU.VPR[vd]._u8[15 - b] = CPU.VPR[va]._u8[15 - (b + nShift)]; + } + } + void VSLW(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] << (CPU.VPR[vb]._u8[w*4] & 0x1f); + } + } + void VSPLTB(u32 vd, u32 uimm5, u32 vb) + { + u8 byte = CPU.VPR[vb]._u8[15 - uimm5]; + + for (uint b = 0; b < 16; b++) + { + CPU.VPR[vd]._u8[b] = byte; + } + } + void VSPLTH(u32 vd, u32 uimm5, u32 vb) + { + assert(uimm5 < 8); + + u16 hword = CPU.VPR[vb]._u16[7 - uimm5]; + + for (uint h = 0; h < 8; h++) + { + CPU.VPR[vd]._u16[h] = hword; + } + } + void VSPLTISB(u32 vd, s32 simm5) + { + for (uint b = 0; b < 16; b++) + { + CPU.VPR[vd]._u8[b] = simm5; + } + } + void VSPLTISH(u32 vd, s32 simm5) + { + for (uint h = 0; h < 8; h++) + { + CPU.VPR[vd]._u16[h] = (s16)simm5; + } + } + void VSPLTISW(u32 vd, s32 simm5) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u32[w] = (s32)simm5; + } + } + void VSPLTW(u32 vd, u32 uimm5, u32 vb) + { + assert(uimm5 < 4); + + u32 word = CPU.VPR[vb]._u32[uimm5]; + + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u32[w] = word; + } + } + void VSR(u32 vd, u32 va, u32 vb) + { + u8 sh = CPU.VPR[vb]._u8[0] & 0x7; + u32 t = 1; + + for (uint b = 0; b < 16; b++) + { + t &= (CPU.VPR[vb]._u8[b] & 0x7) == sh; + } + + if(t) + { + CPU.VPR[vd]._u8[15] = CPU.VPR[va]._u8[15] >> sh; + + for (uint b = 14; b >= 0; b--) + { + CPU.VPR[vd]._u8[b] = (CPU.VPR[va]._u8[b] >> sh) | (CPU.VPR[va]._u8[b+1] << (8 - sh)); + } + } + else + { + //undefined + CPU.VPR[vd]._u32[0] = 0xCDCDCDCD; + CPU.VPR[vd]._u32[1] = 0xCDCDCDCD; + CPU.VPR[vd]._u32[2] = 0xCDCDCDCD; + CPU.VPR[vd]._u32[3] = 0xCDCDCDCD; + } + } + void VSRAB(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 16; b++) + { + CPU.VPR[vd]._s8[b] = CPU.VPR[va]._s8[b] >> (CPU.VPR[vb]._u8[b] & 0x7); + } + } + void VSRAH(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) + { + CPU.VPR[vd]._s16[h] = CPU.VPR[va]._s16[h] >> (CPU.VPR[vb]._u8[h*2] & 0xf); + } + } + void VSRAW(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._s32[w] = CPU.VPR[va]._s32[w] >> (CPU.VPR[vb]._u8[w*4] & 0x1f); + } + } + void VSRB(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 16; b++) + { + CPU.VPR[vd]._u8[b] = CPU.VPR[va]._u8[b] >> (CPU.VPR[vb]._u8[b] & 0x7); + } + } + void VSRH(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) + { + CPU.VPR[vd]._u16[h] = CPU.VPR[va]._u16[h] >> (CPU.VPR[vb]._u8[h*2] & 0xf); + } + } + void VSRO(u32 vd, u32 va, u32 vb) + { + u8 nShift = (CPU.VPR[vb]._u8[0] >> 3) & 0xf; + + CPU.VPR[vd].Clear(); + + for (u8 b = 0; b < 16 - nShift; b++) + { + CPU.VPR[vd]._u8[b] = CPU.VPR[va]._u8[b + nShift]; + } + } + void VSRW(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] >> (CPU.VPR[vb]._u8[w*4] & 0x1f); + } + } + void VSUBCUW(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] < CPU.VPR[vb]._u32[w] ? 0 : 1; + } + } + void VSUBFP(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._f[w] = CPU.VPR[va]._f[w] - CPU.VPR[vb]._f[w]; + } + } + void VSUBSBS(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 16; b++) + { + s16 result = (s16)CPU.VPR[va]._s8[b] - (s16)CPU.VPR[vb]._s8[b]; + + if (result < INT8_MIN) + { + CPU.VPR[vd]._s8[b] = INT8_MIN; + CPU.VSCR.SAT = 1; + } + else if (result > INT8_MAX) + { + CPU.VPR[vd]._s8[b] = INT8_MAX; + CPU.VSCR.SAT = 1; + } + else + CPU.VPR[vd]._s8[b] = (s8)result; + } + } + void VSUBSHS(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) + { + s32 result = (s32)CPU.VPR[va]._s16[h] - (s32)CPU.VPR[vb]._s16[h]; + + if (result < INT16_MIN) + { + CPU.VPR[vd]._s16[h] = (s16)INT16_MIN; + CPU.VSCR.SAT = 1; + } + else if (result > INT16_MAX) + { + CPU.VPR[vd]._s16[h] = (s16)INT16_MAX; + CPU.VSCR.SAT = 1; + } + else + CPU.VPR[vd]._s16[h] = (s16)result; + } + } + void VSUBSWS(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + s64 result = (s64)CPU.VPR[va]._s32[w] - (s64)CPU.VPR[vb]._s32[w]; + + if (result < INT32_MIN) + { + CPU.VPR[vd]._s32[w] = (s32)INT32_MIN; + CPU.VSCR.SAT = 1; + } + else if (result > INT32_MAX) + { + CPU.VPR[vd]._s32[w] = (s32)INT32_MAX; + CPU.VSCR.SAT = 1; + } + else + CPU.VPR[vd]._s32[w] = (s32)result; + } + } + void VSUBUBM(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 16; b++) + { + CPU.VPR[vd]._u8[b] = (u8)((CPU.VPR[va]._u8[b] - CPU.VPR[vb]._u8[b]) & 0xff); + } + } + void VSUBUBS(u32 vd, u32 va, u32 vb) + { + for (uint b = 0; b < 16; b++) + { + s16 result = (s16)CPU.VPR[va]._u8[b] - (s16)CPU.VPR[vb]._u8[b]; + + if (result < 0) + { + CPU.VPR[vd]._u8[b] = 0; + CPU.VSCR.SAT = 1; + } + else + CPU.VPR[vd]._u8[b] = (u8)result; + } + } + void VSUBUHM(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) + { + CPU.VPR[vd]._u16[h] = CPU.VPR[va]._u16[h] - CPU.VPR[vb]._u16[h]; + } + } + void VSUBUHS(u32 vd, u32 va, u32 vb) + { + for (uint h = 0; h < 8; h++) + { + s32 result = (s32)CPU.VPR[va]._u16[h] - (s32)CPU.VPR[vb]._u16[h]; + + if (result < 0) + { + CPU.VPR[vd]._u16[h] = 0; + CPU.VSCR.SAT = 1; + } + else + CPU.VPR[vd]._u16[h] = (u16)result; + } + } + void VSUBUWM(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] - CPU.VPR[vb]._u32[w]; + } + } + void VSUBUWS(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + s64 result = (s64)CPU.VPR[va]._u32[w] - (s64)CPU.VPR[vb]._u32[w]; + + if (result < 0) + { + CPU.VPR[vd]._u32[w] = 0; + CPU.VSCR.SAT = 1; + } + else + CPU.VPR[vd]._u32[w] = (u32)result; + } + } + void VSUMSWS(u32 vd, u32 va, u32 vb) + { + CPU.VPR[vd].Clear(); + + s64 sum = CPU.VPR[vb]._s32[3]; + + for (uint w = 0; w < 4; w++) + { + sum += CPU.VPR[va]._s32[w]; + } + + if (sum > INT32_MAX) + { + CPU.VPR[vd]._s32[0] = (s32)INT32_MAX; + CPU.VSCR.SAT = 1; + } + else if (sum < INT32_MIN) + { + CPU.VPR[vd]._s32[0] = (s32)INT32_MIN; + CPU.VSCR.SAT = 1; + } + else + CPU.VPR[vd]._s32[0] = (s32)sum; + } + void VSUM2SWS(u32 vd, u32 va, u32 vb) + { + CPU.VPR[vd].Clear(); + + for (uint n = 0; n < 2; n++) + { + s64 sum = (s64)CPU.VPR[va]._s32[n*2] + CPU.VPR[va]._s32[n*2 + 1] + CPU.VPR[vb]._s32[n*2]; if (sum > INT32_MAX) { - CPU.VPR[vd]._s32[0] = (s32)INT32_MAX; + CPU.VPR[vd]._s32[n*2] = (s32)INT32_MAX; CPU.VSCR.SAT = 1; } else if (sum < INT32_MIN) { - CPU.VPR[vd]._s32[0] = (s32)INT32_MIN; + CPU.VPR[vd]._s32[n*2] = (s32)INT32_MIN; CPU.VSCR.SAT = 1; } else - CPU.VPR[vd]._s32[0] = (s32)sum; + CPU.VPR[vd]._s32[n*2] = (s32)sum; } - void VSUM2SWS(OP_REG vd, OP_REG va, OP_REG vb) + } + void VSUM4SBS(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) { - CPU.VPR[vd].Clear(); + s64 sum = CPU.VPR[vb]._s32[w]; - for (uint n = 0; n < 2; n++) + for (uint b = 0; b < 4; b++) { - s64 sum = (s64)CPU.VPR[va]._s32[n*2] + CPU.VPR[va]._s32[n*2 + 1] + CPU.VPR[vb]._s32[n*2]; + sum += CPU.VPR[va]._s8[w*4 + b]; + } - if (sum > INT32_MAX) - { - CPU.VPR[vd]._s32[n*2] = (s32)INT32_MAX; - CPU.VSCR.SAT = 1; - } - else if (sum < INT32_MIN) - { - CPU.VPR[vd]._s32[n*2] = (s32)INT32_MIN; - CPU.VSCR.SAT = 1; - } - else - CPU.VPR[vd]._s32[n*2] = (s32)sum; - } - } - void VSUM4SBS(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) + if (sum > INT32_MAX) { - s64 sum = CPU.VPR[vb]._s32[w]; + CPU.VPR[vd]._s32[w] = (s32)INT32_MAX; + CPU.VSCR.SAT = 1; + } + else if (sum < INT32_MIN) + { + CPU.VPR[vd]._s32[w] = (s32)INT32_MIN; + CPU.VSCR.SAT = 1; + } + else + CPU.VPR[vd]._s32[w] = (s32)sum; + } + } + void VSUM4SHS(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + s64 sum = CPU.VPR[vb]._s32[w]; - for (uint b = 0; b < 4; b++) - { - sum += CPU.VPR[va]._s8[w*4 + b]; - } + for (uint h = 0; h < 2; h++) + { + sum += CPU.VPR[va]._s16[w*2 + h]; + } - if (sum > INT32_MAX) - { - CPU.VPR[vd]._s32[w] = (s32)INT32_MAX; - CPU.VSCR.SAT = 1; - } - else if (sum < INT32_MIN) - { - CPU.VPR[vd]._s32[w] = (s32)INT32_MIN; - CPU.VSCR.SAT = 1; - } - else - CPU.VPR[vd]._s32[w] = (s32)sum; - } - } - void VSUM4SHS(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) + if (sum > INT32_MAX) { - s64 sum = CPU.VPR[vb]._s32[w]; + CPU.VPR[vd]._s32[w] = (s32)INT32_MAX; + CPU.VSCR.SAT = 1; + } + else if (sum < INT32_MIN) + { + CPU.VPR[vd]._s32[w] = (s32)INT32_MIN; + CPU.VSCR.SAT = 1; + } + else + CPU.VPR[vd]._s32[w] = (s32)sum; + } + } + void VSUM4UBS(u32 vd, u32 va, u32 vb) + { + for (uint w = 0; w < 4; w++) + { + u64 sum = CPU.VPR[vb]._u32[w]; - for (uint h = 0; h < 2; h++) - { - sum += CPU.VPR[va]._s16[w*2 + h]; - } + for (uint b = 0; b < 4; b++) + { + sum += CPU.VPR[va]._u8[w*4 + b]; + } - if (sum > INT32_MAX) - { - CPU.VPR[vd]._s32[w] = (s32)INT32_MAX; - CPU.VSCR.SAT = 1; - } - else if (sum < INT32_MIN) - { - CPU.VPR[vd]._s32[w] = (s32)INT32_MIN; - CPU.VSCR.SAT = 1; - } - else - CPU.VPR[vd]._s32[w] = (s32)sum; - } - } - void VSUM4UBS(OP_REG vd, OP_REG va, OP_REG vb) - { - for (uint w = 0; w < 4; w++) + if (sum > UINT32_MAX) { - u64 sum = CPU.VPR[vb]._u32[w]; - - for (uint b = 0; b < 4; b++) - { - sum += CPU.VPR[va]._u8[w*4 + b]; - } - - if (sum > UINT32_MAX) - { - CPU.VPR[vd]._u32[w] = (u32)UINT32_MAX; - CPU.VSCR.SAT = 1; - } - else - CPU.VPR[vd]._u32[w] = (u32)sum; + CPU.VPR[vd]._u32[w] = (u32)UINT32_MAX; + CPU.VSCR.SAT = 1; } + else + CPU.VPR[vd]._u32[w] = (u32)sum; } - void VUPKHPX(OP_REG vd, OP_REG vb) + } + void VUPKHPX(u32 vd, u32 vb) + { + for (uint w = 0; w < 4; w++) { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._s8[(3 - w)*4 + 3] = CPU.VPR[vb]._s8[w*2 + 0] >> 7; // signed shift sign extends - CPU.VPR[vd]._u8[(3 - w)*4 + 2] = (CPU.VPR[vb]._u8[w*2 + 0] >> 2) & 0x1f; - CPU.VPR[vd]._u8[(3 - w)*4 + 1] = ((CPU.VPR[vb]._u8[w*2 + 0] & 0x3) << 3) | ((CPU.VPR[vb]._u8[w*2 + 1] >> 5) & 0x7); - CPU.VPR[vd]._u8[(3 - w)*4 + 0] = CPU.VPR[vb]._u8[w*2 + 1] & 0x1f; - } + CPU.VPR[vd]._s8[(3 - w)*4 + 3] = CPU.VPR[vb]._s8[w*2 + 0] >> 7; // signed shift sign extends + CPU.VPR[vd]._u8[(3 - w)*4 + 2] = (CPU.VPR[vb]._u8[w*2 + 0] >> 2) & 0x1f; + CPU.VPR[vd]._u8[(3 - w)*4 + 1] = ((CPU.VPR[vb]._u8[w*2 + 0] & 0x3) << 3) | ((CPU.VPR[vb]._u8[w*2 + 1] >> 5) & 0x7); + CPU.VPR[vd]._u8[(3 - w)*4 + 0] = CPU.VPR[vb]._u8[w*2 + 1] & 0x1f; } - void VUPKHSB(OP_REG vd, OP_REG vb) + } + void VUPKHSB(u32 vd, u32 vb) + { + for (uint h = 0; h < 8; h++) { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._s16[h] = CPU.VPR[vb]._s8[h]; - } + CPU.VPR[vd]._s16[h] = CPU.VPR[vb]._s8[h]; } - void VUPKHSH(OP_REG vd, OP_REG vb) + } + void VUPKHSH(u32 vd, u32 vb) + { + for (uint w = 0; w < 4; w++) { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._s32[w] = CPU.VPR[vb]._s16[w]; - } + CPU.VPR[vd]._s32[w] = CPU.VPR[vb]._s16[w]; } - void VUPKLPX(OP_REG vd, OP_REG vb) + } + void VUPKLPX(u32 vd, u32 vb) + { + for (uint w = 0; w < 4; w++) { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._s8[(3 - w)*4 + 3] = CPU.VPR[vb]._s8[8 + w*2 + 0] >> 7; // signed shift sign extends - CPU.VPR[vd]._u8[(3 - w)*4 + 2] = (CPU.VPR[vb]._u8[8 + w*2 + 0] >> 2) & 0x1f; - CPU.VPR[vd]._u8[(3 - w)*4 + 1] = ((CPU.VPR[vb]._u8[8 + w*2 + 0] & 0x3) << 3) | ((CPU.VPR[vb]._u8[8 + w*2 + 1] >> 5) & 0x7); - CPU.VPR[vd]._u8[(3 - w)*4 + 0] = CPU.VPR[vb]._u8[8 + w*2 + 1] & 0x1f; - } + CPU.VPR[vd]._s8[(3 - w)*4 + 3] = CPU.VPR[vb]._s8[8 + w*2 + 0] >> 7; // signed shift sign extends + CPU.VPR[vd]._u8[(3 - w)*4 + 2] = (CPU.VPR[vb]._u8[8 + w*2 + 0] >> 2) & 0x1f; + CPU.VPR[vd]._u8[(3 - w)*4 + 1] = ((CPU.VPR[vb]._u8[8 + w*2 + 0] & 0x3) << 3) | ((CPU.VPR[vb]._u8[8 + w*2 + 1] >> 5) & 0x7); + CPU.VPR[vd]._u8[(3 - w)*4 + 0] = CPU.VPR[vb]._u8[8 + w*2 + 1] & 0x1f; } - void VUPKLSB(OP_REG vd, OP_REG vb) + } + void VUPKLSB(u32 vd, u32 vb) + { + for (uint h = 0; h < 8; h++) { - for (uint h = 0; h < 8; h++) - { - CPU.VPR[vd]._s16[h] = CPU.VPR[vb]._s8[8 + h]; - } + CPU.VPR[vd]._s16[h] = CPU.VPR[vb]._s8[8 + h]; } - void VUPKLSH(OP_REG vd, OP_REG vb) + } + void VUPKLSH(u32 vd, u32 vb) + { + for (uint w = 0; w < 4; w++) { - for (uint w = 0; w < 4; w++) - { - CPU.VPR[vd]._s32[w] = CPU.VPR[vb]._s16[4 + w]; - } + CPU.VPR[vd]._s32[w] = CPU.VPR[vb]._s16[4 + w]; } - void VXOR(OP_REG vd, OP_REG va, OP_REG vb) - { - CPU.VPR[vd]._u32[0] = CPU.VPR[va]._u32[0] ^ CPU.VPR[vb]._u32[0]; - CPU.VPR[vd]._u32[1] = CPU.VPR[va]._u32[1] ^ CPU.VPR[vb]._u32[1]; - CPU.VPR[vd]._u32[2] = CPU.VPR[va]._u32[2] ^ CPU.VPR[vb]._u32[2]; - CPU.VPR[vd]._u32[3] = CPU.VPR[va]._u32[3] ^ CPU.VPR[vb]._u32[3]; - } - END_OPCODES_GROUP(G_04); - - void MULLI(OP_REG rd, OP_REG ra, OP_sIMM simm16) + } + void VXOR(u32 vd, u32 va, u32 vb) + { + CPU.VPR[vd]._u32[0] = CPU.VPR[va]._u32[0] ^ CPU.VPR[vb]._u32[0]; + CPU.VPR[vd]._u32[1] = CPU.VPR[va]._u32[1] ^ CPU.VPR[vb]._u32[1]; + CPU.VPR[vd]._u32[2] = CPU.VPR[va]._u32[2] ^ CPU.VPR[vb]._u32[2]; + CPU.VPR[vd]._u32[3] = CPU.VPR[va]._u32[3] ^ CPU.VPR[vb]._u32[3]; + } + void MULLI(u32 rd, u32 ra, s32 simm16) { CPU.GPR[rd] = (s64)CPU.GPR[ra] * simm16; } - void SUBFIC(OP_REG rd, OP_REG ra, OP_sIMM simm16) + void SUBFIC(u32 rd, u32 ra, s32 simm16) { s64 RA = CPU.GPR[ra]; CPU.GPR[rd] = (s64)simm16 - RA; CPU.XER.CA = RA <= simm16; } - void CMPLI(OP_REG crfd, OP_REG l, OP_REG ra, OP_uIMM uimm16) + void CMPLI(u32 crfd, u32 l, u32 ra, u32 uimm16) { CPU.UpdateCRn(crfd, l ? CPU.GPR[ra] : (u32)CPU.GPR[ra], uimm16); } - void CMPI(OP_REG crfd, OP_REG l, OP_REG ra, OP_sIMM simm16) + void CMPI(u32 crfd, u32 l, u32 ra, s32 simm16) { CPU.UpdateCRn(crfd, l ? CPU.GPR[ra] : (s32)CPU.GPR[ra], simm16); } - void ADDIC(OP_REG rd, OP_REG ra, OP_sIMM simm16) + void ADDIC(u32 rd, u32 ra, s32 simm16) { const u64 RA = CPU.GPR[ra]; CPU.GPR[rd] = RA + simm16; CPU.XER.CA = CPU.IsCarry(RA, simm16); } - void ADDIC_(OP_REG rd, OP_REG ra, OP_sIMM simm16) + void ADDIC_(u32 rd, u32 ra, s32 simm16) { const u64 RA = CPU.GPR[ra]; CPU.GPR[rd] = RA + simm16; CPU.XER.CA = CPU.IsCarry(RA, simm16); CPU.UpdateCR0(CPU.GPR[rd]); } - void ADDI(OP_REG rd, OP_REG ra, OP_sIMM simm16) + void ADDI(u32 rd, u32 ra, s32 simm16) { CPU.GPR[rd] = ra ? ((s64)CPU.GPR[ra] + simm16) : simm16; } - void ADDIS(OP_REG rd, OP_REG ra, OP_sIMM simm16) + void ADDIS(u32 rd, u32 ra, s32 simm16) { CPU.GPR[rd] = ra ? ((s64)CPU.GPR[ra] + (simm16 << 16)) : (simm16 << 16); } - void BC(OP_REG bo, OP_REG bi, OP_sIMM bd, OP_REG aa, OP_REG lk) + void BC(u32 bo, u32 bi, s32 bd, u32 aa, u32 lk) { if(!CheckCondition(bo, bi)) return; CPU.SetBranch(branchTarget((aa ? 0 : CPU.PC), bd)); if(lk) CPU.LR = CPU.PC + 4; } - void SC(OP_sIMM sc_code) + void SC(s32 sc_code) { switch(sc_code) { @@ -2076,492 +2071,241 @@ private: default: UNK(wxString::Format("Unknown sc: %x", sc_code)); } } - void B(OP_sIMM ll, OP_REG aa, OP_REG lk) + void B(s32 ll, u32 aa, u32 lk) { CPU.SetBranch(branchTarget(aa ? 0 : CPU.PC, ll)); if(lk) CPU.LR = CPU.PC + 4; } - - START_OPCODES_GROUP(G_13) - void MCRF(OP_REG crfd, OP_REG crfs) + void MCRF(u32 crfd, u32 crfs) + { + CPU.SetCR(crfd, CPU.GetCR(crfs)); + } + void BCLR(u32 bo, u32 bi, u32 bh, u32 lk) + { + if(!CheckCondition(bo, bi)) return; + CPU.SetBranch(branchTarget(0, CPU.LR)); + if(lk) CPU.LR = CPU.PC + 4; + } + void CRNOR(u32 bt, u32 ba, u32 bb) + { + const u8 v = 1 ^ (CPU.IsCR(ba) | CPU.IsCR(bb)); + CPU.SetCRBit2(bt, v & 0x1); + } + void CRANDC(u32 bt, u32 ba, u32 bb) + { + const u8 v = CPU.IsCR(ba) & (1 ^ CPU.IsCR(bb)); + CPU.SetCRBit2(bt, v & 0x1); + } + void ISYNC() + { + } + void CRXOR(u32 bt, u32 ba, u32 bb) + { + const u8 v = CPU.IsCR(ba) ^ CPU.IsCR(bb); + CPU.SetCRBit2(bt, v & 0x1); + } + void CRNAND(u32 bt, u32 ba, u32 bb) + { + const u8 v = 1 ^ (CPU.IsCR(ba) & CPU.IsCR(bb)); + CPU.SetCRBit2(bt, v & 0x1); + } + void CRAND(u32 bt, u32 ba, u32 bb) + { + const u8 v = CPU.IsCR(ba) & CPU.IsCR(bb); + CPU.SetCRBit2(bt, v & 0x1); + } + void CREQV(u32 bt, u32 ba, u32 bb) + { + const u8 v = 1 ^ (CPU.IsCR(ba) ^ CPU.IsCR(bb)); + CPU.SetCRBit2(bt, v & 0x1); + } + void CRORC(u32 bt, u32 ba, u32 bb) + { + const u8 v = CPU.IsCR(ba) | (1 ^ CPU.IsCR(bb)); + CPU.SetCRBit2(bt, v & 0x1); + } + void CROR(u32 bt, u32 ba, u32 bb) + { + const u8 v = CPU.IsCR(ba) | CPU.IsCR(bb); + CPU.SetCRBit2(bt, v & 0x1); + } + void BCCTR(u32 bo, u32 bi, u32 bh, u32 lk) + { + if(bo & 0x10 || CPU.IsCR(bi) == (bo & 0x8)) { - CPU.SetCR(crfd, CPU.GetCR(crfs)); - } - void BCLR(OP_REG bo, OP_REG bi, OP_REG bh, OP_REG lk) - { - if(!CheckCondition(bo, bi)) return; - CPU.SetBranch(branchTarget(0, CPU.LR)); + CPU.SetBranch(branchTarget(0, CPU.CTR)); if(lk) CPU.LR = CPU.PC + 4; } - void CRNOR(OP_REG bt, OP_REG ba, OP_REG bb) - { - const u8 v = 1 ^ (CPU.IsCR(ba) | CPU.IsCR(bb)); - CPU.SetCRBit2(bt, v & 0x1); - } - void CRANDC(OP_REG bt, OP_REG ba, OP_REG bb) - { - const u8 v = CPU.IsCR(ba) & (1 ^ CPU.IsCR(bb)); - CPU.SetCRBit2(bt, v & 0x1); - } - void ISYNC() - { - } - void CRXOR(OP_REG bt, OP_REG ba, OP_REG bb) - { - const u8 v = CPU.IsCR(ba) ^ CPU.IsCR(bb); - CPU.SetCRBit2(bt, v & 0x1); - } - void CRNAND(OP_REG bt, OP_REG ba, OP_REG bb) - { - const u8 v = 1 ^ (CPU.IsCR(ba) & CPU.IsCR(bb)); - CPU.SetCRBit2(bt, v & 0x1); - } - void CRAND(OP_REG bt, OP_REG ba, OP_REG bb) - { - const u8 v = CPU.IsCR(ba) & CPU.IsCR(bb); - CPU.SetCRBit2(bt, v & 0x1); - } - void CREQV(OP_REG bt, OP_REG ba, OP_REG bb) - { - const u8 v = 1 ^ (CPU.IsCR(ba) ^ CPU.IsCR(bb)); - CPU.SetCRBit2(bt, v & 0x1); - } - void CRORC(OP_REG bt, OP_REG ba, OP_REG bb) - { - const u8 v = CPU.IsCR(ba) | (1 ^ CPU.IsCR(bb)); - CPU.SetCRBit2(bt, v & 0x1); - } - void CROR(OP_REG bt, OP_REG ba, OP_REG bb) - { - const u8 v = CPU.IsCR(ba) | CPU.IsCR(bb); - CPU.SetCRBit2(bt, v & 0x1); - } - void BCCTR(OP_REG bo, OP_REG bi, OP_REG bh, OP_REG lk) - { - if(bo & 0x10 || CPU.IsCR(bi) == (bo & 0x8)) - { - CPU.SetBranch(branchTarget(0, CPU.CTR)); - if(lk) CPU.LR = CPU.PC + 4; - } - } - END_OPCODES_GROUP(G_13); - - void RLWIMI(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, OP_REG me, bool rc) + } + void RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) { const u32 mask = rotate_mask[32 + mb][32 + me]; CPU.GPR[ra] = (CPU.GPR[ra] & ~mask) | (rotl32(CPU.GPR[rs], sh) & mask); if(rc) CPU.UpdateCR0(CPU.GPR[ra]); } - void RLWINM(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, OP_REG me, bool rc) + void RLWINM(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) { CPU.GPR[ra] = rotl32(CPU.GPR[rs], sh) & rotate_mask[32 + mb][32 + me]; if(rc) CPU.UpdateCR0(CPU.GPR[ra]); } - void RLWNM(OP_REG ra, OP_REG rs, OP_REG rb, OP_REG mb, OP_REG me, bool rc) + void RLWNM(u32 ra, u32 rs, u32 rb, u32 mb, u32 me, bool rc) { CPU.GPR[ra] = rotl32(CPU.GPR[rs], CPU.GPR[rb] & 0x1f) & rotate_mask[32 + mb][32 + me]; if(rc) CPU.UpdateCR0(CPU.GPR[ra]); } - void ORI(OP_REG ra, OP_REG rs, OP_uIMM uimm16) + void ORI(u32 ra, u32 rs, u32 uimm16) { CPU.GPR[ra] = CPU.GPR[rs] | uimm16; } - void ORIS(OP_REG ra, OP_REG rs, OP_uIMM uimm16) + void ORIS(u32 ra, u32 rs, u32 uimm16) { CPU.GPR[ra] = CPU.GPR[rs] | (uimm16 << 16); } - void XORI(OP_REG ra, OP_REG rs, OP_uIMM uimm16) + void XORI(u32 ra, u32 rs, u32 uimm16) { CPU.GPR[ra] = CPU.GPR[rs] ^ uimm16; } - void XORIS(OP_REG ra, OP_REG rs, OP_uIMM uimm16) + void XORIS(u32 ra, u32 rs, u32 uimm16) { CPU.GPR[ra] = CPU.GPR[rs] ^ (uimm16 << 16); } - void ANDI_(OP_REG ra, OP_REG rs, OP_uIMM uimm16) + void ANDI_(u32 ra, u32 rs, u32 uimm16) { CPU.GPR[ra] = CPU.GPR[rs] & uimm16; CPU.UpdateCR0(CPU.GPR[ra]); } - void ANDIS_(OP_REG ra, OP_REG rs, OP_uIMM uimm16) + void ANDIS_(u32 ra, u32 rs, u32 uimm16) { CPU.GPR[ra] = CPU.GPR[rs] & (uimm16 << 16); CPU.UpdateCR0(CPU.GPR[ra]); } + void RLDICL(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) + { + CPU.GPR[ra] = rotl64(CPU.GPR[rs], sh) & rotate_mask[mb][63]; + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void RLDICR(u32 ra, u32 rs, u32 sh, u32 me, bool rc) + { + CPU.GPR[ra] = rotl64(CPU.GPR[rs], sh) & rotate_mask[0][me]; + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void RLDIC(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) + { + CPU.GPR[ra] = rotl64(CPU.GPR[rs], sh) & rotate_mask[mb][63-sh]; + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void RLDIMI(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) + { + const u64 mask = rotate_mask[mb][63-sh]; + CPU.GPR[ra] = (CPU.GPR[ra] & ~mask) | (rotl64(CPU.GPR[rs], sh) & mask); + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void CMP(u32 crfd, u32 l, u32 ra, u32 rb) + { + CPU.UpdateCRn(crfd, l ? CPU.GPR[ra] : (s32)CPU.GPR[ra], l ? CPU.GPR[rb] : (s32)CPU.GPR[rb]); + } + void TW(u32 to, u32 ra, u32 rb) + { + s32 a = CPU.GPR[ra]; + s32 b = CPU.GPR[rb]; - START_OPCODES_GROUP(G_1e) - void RLDICL(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, bool rc) + if( (a < b && (to & 0x10)) || + (a > b && (to & 0x8)) || + (a == b && (to & 0x4)) || + ((u32)a < (u32)b && (to & 0x2)) || + ((u32)a > (u32)b && (to & 0x1)) ) { - CPU.GPR[ra] = rotl64(CPU.GPR[rs], sh) & rotate_mask[mb][63]; - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + UNK(wxString::Format("Trap! (tw %x, r%d, r%d)", to, ra, rb)); } - void RLDICR(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG me, bool rc) - { - CPU.GPR[ra] = rotl64(CPU.GPR[rs], sh) & rotate_mask[0][me]; - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void RLDIC(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, bool rc) - { - CPU.GPR[ra] = rotl64(CPU.GPR[rs], sh) & rotate_mask[mb][63-sh]; - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void RLDIMI(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, bool rc) - { - const u64 mask = rotate_mask[mb][63-sh]; - CPU.GPR[ra] = (CPU.GPR[ra] & ~mask) | (rotl64(CPU.GPR[rs], sh) & mask); - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - END_OPCODES_GROUP(G_1e); - - START_OPCODES_GROUP(G_1f) - void CMP(OP_REG crfd, OP_REG l, OP_REG ra, OP_REG rb) - { - CPU.UpdateCRn(crfd, l ? CPU.GPR[ra] : (s32)CPU.GPR[ra], l ? CPU.GPR[rb] : (s32)CPU.GPR[rb]); - } - void TW(OP_uIMM to, OP_REG ra, OP_REG rb) - { - s32 a = CPU.GPR[ra]; - s32 b = CPU.GPR[rb]; + } + void LVSL(u32 vd, u32 ra, u32 rb) + { + const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; - if( (a < b && (to & 0x10)) || - (a > b && (to & 0x8)) || - (a == b && (to & 0x4)) || - ((u32)a < (u32)b && (to & 0x2)) || - ((u32)a > (u32)b && (to & 0x1)) ) - { - UNK(wxString::Format("Trap! (tw %x, r%d, r%d)", to, ra, rb)); - } - } - void LVSL(OP_REG vd, OP_REG ra, OP_REG rb) + static const u64 lvsl_values[0x10][2] = { - const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; + {0x08090A0B0C0D0E0F, 0x0001020304050607}, + {0x090A0B0C0D0E0F10, 0x0102030405060708}, + {0x0A0B0C0D0E0F1011, 0x0203040506070809}, + {0x0B0C0D0E0F101112, 0x030405060708090A}, + {0x0C0D0E0F10111213, 0x0405060708090A0B}, + {0x0D0E0F1011121314, 0x05060708090A0B0C}, + {0x0E0F101112131415, 0x060708090A0B0C0D}, + {0x0F10111213141516, 0x0708090A0B0C0D0E}, + {0x1011121314151617, 0x08090A0B0C0D0E0F}, + {0x1112131415161718, 0x090A0B0C0D0E0F10}, + {0x1213141516171819, 0x0A0B0C0D0E0F1011}, + {0x131415161718191A, 0x0B0C0D0E0F101112}, + {0x1415161718191A1B, 0x0C0D0E0F10111213}, + {0x15161718191A1B1C, 0x0D0E0F1011121314}, + {0x161718191A1B1C1D, 0x0E0F101112131415}, + {0x1718191A1B1C1D1E, 0x0F10111213141516}, + }; - static const u64 lvsl_values[0x10][2] = - { - {0x08090A0B0C0D0E0F, 0x0001020304050607}, - {0x090A0B0C0D0E0F10, 0x0102030405060708}, - {0x0A0B0C0D0E0F1011, 0x0203040506070809}, - {0x0B0C0D0E0F101112, 0x030405060708090A}, - {0x0C0D0E0F10111213, 0x0405060708090A0B}, - {0x0D0E0F1011121314, 0x05060708090A0B0C}, - {0x0E0F101112131415, 0x060708090A0B0C0D}, - {0x0F10111213141516, 0x0708090A0B0C0D0E}, - {0x1011121314151617, 0x08090A0B0C0D0E0F}, - {0x1112131415161718, 0x090A0B0C0D0E0F10}, - {0x1213141516171819, 0x0A0B0C0D0E0F1011}, - {0x131415161718191A, 0x0B0C0D0E0F101112}, - {0x1415161718191A1B, 0x0C0D0E0F10111213}, - {0x15161718191A1B1C, 0x0D0E0F1011121314}, - {0x161718191A1B1C1D, 0x0E0F101112131415}, - {0x1718191A1B1C1D1E, 0x0F10111213141516}, - }; + CPU.VPR[vd]._u64[0] = lvsl_values[addr & 0xf][0]; + CPU.VPR[vd]._u64[1] = lvsl_values[addr & 0xf][1]; + } + void LVEBX(u32 vd, u32 ra, u32 rb) + { + //const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; + //CPU.VPR[vd].Clear(); + //CPU.VPR[vd]._u8[addr & 0xf] = Memory.Read8(addr); + CPU.VPR[vd]._u128 = Memory.Read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL); + } + void SUBFC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + const s64 RA = CPU.GPR[ra]; + const s64 RB = CPU.GPR[rb]; + CPU.GPR[rd] = RB - RA; + CPU.XER.CA = CPU.IsCarry(RA, RB); + if(oe) UNK("subfco"); + if(rc) CPU.UpdateCR0(CPU.GPR[rd]); + } + void ADDC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + const s64 RA = CPU.GPR[ra]; + const s64 RB = CPU.GPR[rb]; + CPU.GPR[rd] = RA + RB; + CPU.XER.CA = RA <= RB; + if(oe) UNK("addco"); + if(rc) CPU.UpdateCR0(CPU.GPR[rd]); + } + void MULHDU(u32 rd, u32 ra, u32 rb, bool rc) + { + const u64 RA = CPU.GPR[ra]; + const u64 RB = CPU.GPR[rb]; - CPU.VPR[vd]._u64[0] = lvsl_values[addr & 0xf][0]; - CPU.VPR[vd]._u64[1] = lvsl_values[addr & 0xf][1]; - } - void LVEBX(OP_REG vd, OP_REG ra, OP_REG rb) - { - //const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; - //CPU.VPR[vd].Clear(); - //CPU.VPR[vd]._u8[addr & 0xf] = Memory.Read8(addr); - CPU.VPR[vd]._u128 = Memory.Read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL); - } - void SUBFC(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - const s64 RA = CPU.GPR[ra]; - const s64 RB = CPU.GPR[rb]; - CPU.GPR[rd] = RB - RA; - CPU.XER.CA = CPU.IsCarry(RA, RB); - if(oe) UNK("subfco"); - if(rc) CPU.UpdateCR0(CPU.GPR[rd]); - } - void ADDC(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - const s64 RA = CPU.GPR[ra]; - const s64 RB = CPU.GPR[rb]; - CPU.GPR[rd] = RA + RB; - CPU.XER.CA = RA <= RB; - if(oe) UNK("addco"); - if(rc) CPU.UpdateCR0(CPU.GPR[rd]); - } - void MULHDU(OP_REG rd, OP_REG ra, OP_REG rb, bool rc) - { - const u64 RA = CPU.GPR[ra]; - const u64 RB = CPU.GPR[rb]; + u128 RD; - u128 RD; + u64& lo = (u64&)((u32*)&RD)[0]; + u64& mid = (u64&)((u32*)&RD)[1]; + u64& hi = (u64&)((u32*)&RD)[2]; - u64& lo = (u64&)((u32*)&RD)[0]; - u64& mid = (u64&)((u32*)&RD)[1]; - u64& hi = (u64&)((u32*)&RD)[2]; + const u64 a0 = ((u32*)&RA)[0]; + const u64 a1 = ((u32*)&RA)[1]; + const u64 b0 = ((u32*)&RB)[0]; + const u64 b1 = ((u32*)&RB)[1]; - const u64 a0 = ((u32*)&RA)[0]; - const u64 a1 = ((u32*)&RA)[1]; - const u64 b0 = ((u32*)&RB)[0]; - const u64 b1 = ((u32*)&RB)[1]; + lo = a0 * b0; + hi = a1 * b1; - lo = a0 * b0; - hi = a1 * b1; + mid += (a0 + a1) * (b0 + b1) - (lo + hi); - mid += (a0 + a1) * (b0 + b1) - (lo + hi); + CPU.GPR[rd] = RD._u64[1]; - CPU.GPR[rd] = RD._u64[1]; - - if(rc) CPU.UpdateCR0(CPU.GPR[rd]); - } - void MULHWU(OP_REG rd, OP_REG ra, OP_REG rb, bool rc) - { - CPU.GPR[rd] = (CPU.GPR[ra] * CPU.GPR[rb]) >> 32; - if(rc) CPU.UpdateCR0(CPU.GPR[rd]); - } - void MFOCRF(OP_uIMM a, OP_REG rd, OP_uIMM crm) - { - if(a) - { - u32 n = 0, count = 0; - for(u32 i = 0; i < 8; ++i) - { - if(crm & (1 << i)) - { - n = i; - count++; - } - } - - if(count == 1) - { - //RD[32+4*n : 32+4*n+3] = CR[4*n : 4*n+3]; - CPU.GPR[rd] = (u64)CPU.GetCR(n) << (n * 4); - } - else - CPU.GPR[rd] = 0; - } - else - { - CPU.GPR[rd] = CPU.CR.CR; - } - } - void LWARX(OP_REG rd, OP_REG ra, OP_REG rb) - { - const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; - CPU.reserve_addr = addr; - CPU.reserve = true; - CPU.GPR[rd] = Memory.Read32(addr); - } - void LDX(OP_REG ra, OP_REG rs, OP_REG rb) - { - CPU.GPR[ra] = Memory.Read64(rs ? CPU.GPR[rs] + CPU.GPR[rb] : CPU.GPR[rb]); - } - void LWZX(OP_REG rd, OP_REG ra, OP_REG rb) - { - CPU.GPR[rd] = Memory.Read32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]); - } - void SLW(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - const u32 n = CPU.GPR[rb] & 0x1f; - const u32 r = rotl32((u32)CPU.GPR[rs], n); - const u32 m = (CPU.GPR[rb] & 0x20) ? 0 : rotate_mask[32][63 - n]; - - CPU.GPR[ra] = r & m; - - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void CNTLZW(OP_REG ra, OP_REG rs, bool rc) - { - u32 i; - for(i=0; i < 32; i++) - { - if(CPU.GPR[rs] & (0x80000000 >> i)) break; - } - - CPU.GPR[ra] = i; - - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void SLD(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - CPU.GPR[ra] = CPU.GPR[rb] & 0x40 ? 0 : CPU.GPR[rs] << (CPU.GPR[rb] & 0x3f); - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void AND(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - CPU.GPR[ra] = CPU.GPR[rs] & CPU.GPR[rb]; - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void CMPL(OP_REG crfd, OP_REG l, OP_REG ra, OP_REG rb) - { - CPU.UpdateCRn(crfd, l ? CPU.GPR[ra] : (u32)CPU.GPR[ra], l ? CPU.GPR[rb] : (u32)CPU.GPR[rb]); - } - void LVSR(OP_REG vd, OP_REG ra, OP_REG rb) - { - const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; - - static const u64 lvsr_values[0x10][2] = - { - {0x18191A1B1C1D1E1F, 0x1011121314151617}, - {0x1718191A1B1C1D1E, 0x0F10111213141516}, - {0x161718191A1B1C1D, 0x0E0F101112131415}, - {0x15161718191A1B1C, 0x0D0E0F1011121314}, - {0x1415161718191A1B, 0x0C0D0E0F10111213}, - {0x131415161718191A, 0x0B0C0D0E0F101112}, - {0x1213141516171819, 0x0A0B0C0D0E0F1011}, - {0x1112131415161718, 0x090A0B0C0D0E0F10}, - {0x1011121314151617, 0x08090A0B0C0D0E0F}, - {0x0F10111213141516, 0x0708090A0B0C0D0E}, - {0x0E0F101112131415, 0x060708090A0B0C0D}, - {0x0D0E0F1011121314, 0x05060708090A0B0C}, - {0x0C0D0E0F10111213, 0x0405060708090A0B}, - {0x0B0C0D0E0F101112, 0x030405060708090A}, - {0x0A0B0C0D0E0F1011, 0x0203040506070809}, - {0x090A0B0C0D0E0F10, 0x0102030405060708}, - }; - - CPU.VPR[vd]._u64[0] = lvsr_values[addr & 0xf][0]; - CPU.VPR[vd]._u64[1] = lvsr_values[addr & 0xf][1]; - } - void LVEHX(OP_REG vd, OP_REG ra, OP_REG rb) - { - //const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~1ULL; - //CPU.VPR[vd].Clear(); - //(u16&)CPU.VPR[vd]._u8[addr & 0xf] = Memory.Read16(addr); - CPU.VPR[vd]._u128 = Memory.Read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL); - } - void SUBF(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - CPU.GPR[rd] = CPU.GPR[rb] - CPU.GPR[ra]; - if(oe) UNK("subfo"); - if(rc) CPU.UpdateCR0(CPU.GPR[rd]); - } - void LDUX(OP_REG rd, OP_REG ra, OP_REG rb) - { - const u64 addr = CPU.GPR[ra] + CPU.GPR[rb]; - CPU.GPR[rd] = Memory.Read64(addr); - CPU.GPR[ra] = addr; - } - void DCBST(OP_REG ra, OP_REG rb) - { - //UNK("dcbst", false); - } - void CNTLZD(OP_REG ra, OP_REG rs, bool rc) - { - u32 i = 0; - - for(u64 mask = 1ULL << 63; i < 64; i++, mask >>= 1) - { - if(CPU.GPR[rs] & mask) break; - } - - CPU.GPR[ra] = i; - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void ANDC(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - CPU.GPR[ra] = CPU.GPR[rs] & ~CPU.GPR[rb]; - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void LVEWX(OP_REG vd, OP_REG ra, OP_REG rb) - { - //const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~3ULL; - //CPU.VPR[vd].Clear(); - //(u32&)CPU.VPR[vd]._u8[addr & 0xf] = Memory.Read32(addr); - CPU.VPR[vd]._u128 = Memory.Read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL); - } - void MULHD(OP_REG rd, OP_REG ra, OP_REG rb, bool rc) - { - const s64 RA = CPU.GPR[ra]; - const s64 RB = CPU.GPR[rb]; - - u128 RT; - - s64& lo = (s64&)((s32*)&RT)[0]; - s64& mid = (s64&)((s32*)&RT)[1]; - s64& hi = (s64&)((s32*)&RT)[2]; - - const s64 a0 = ((s32*)&RA)[0]; - const s64 a1 = ((s32*)&RA)[1]; - const s64 b0 = ((s32*)&RB)[0]; - const s64 b1 = ((s32*)&RB)[1]; - - lo = a0 * b0; - hi = a1 * b1; - - mid += (a0 + a1) * (b0 + b1) - (lo + hi); - - CPU.GPR[rd] = RT._u64[1]; - - if(rc) CPU.UpdateCR0(CPU.GPR[rd]); - } - void MULHW(OP_REG rd, OP_REG ra, OP_REG rb, bool rc) - { - CPU.GPR[rd] = (s64)(s32)((CPU.GPR[ra] * CPU.GPR[rb]) >> 32); - if(rc) CPU.UpdateCR0(CPU.GPR[rd]); - } - void LDARX(OP_REG rd, OP_REG ra, OP_REG rb) - { - const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; - CPU.reserve_addr = addr; - CPU.reserve = true; - CPU.GPR[rd] = Memory.Read64(addr); - } - void DCBF(OP_REG ra, OP_REG rb) - { - //UNK("dcbf", false); - } - void LBZX(OP_REG rd, OP_REG ra, OP_REG rb) - { - CPU.GPR[rd] = Memory.Read8(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]); - } - void LVX(OP_REG vd, OP_REG ra, OP_REG rb) - { - CPU.VPR[vd]._u128 = Memory.Read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL); - } - void NEG(OP_REG rd, OP_REG ra, OP_REG oe, bool rc) - { - CPU.GPR[rd] = 0-CPU.GPR[ra]; - if(oe) UNK("nego"); - if(rc) CPU.UpdateCR0(CPU.GPR[rd]); - } - void LBZUX(OP_REG rd, OP_REG ra, OP_REG rb) - { - //if(ra == 0 || ra == rd) throw "Bad instruction [LBZUX]"; - - const u64 addr = CPU.GPR[ra] + CPU.GPR[rb]; - CPU.GPR[rd] = Memory.Read8(addr); - CPU.GPR[ra] = addr; - } - void NOR(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - CPU.GPR[ra] = ~(CPU.GPR[rs] | CPU.GPR[rb]); - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void STVEBX(OP_REG vs, OP_REG ra, OP_REG rb) - { - const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; - const u8 eb = addr & 0xf; - Memory.Write8(addr, CPU.VPR[vs]._u8[15 - eb]); - } - void SUBFE(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - const s64 RA = CPU.GPR[ra]; - const s64 RB = CPU.GPR[rb]; - CPU.GPR[ra] = ~RA + RB + CPU.XER.CA; - CPU.XER.CA = ((u64)~RA + CPU.XER.CA > ~(u64)RB) | ((RA == 0) & CPU.XER.CA); - if(rc) CPU.UpdateCR0(CPU.GPR[rd]); - if(oe) UNK("subfeo"); - } - void ADDE(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - const s64 RA = CPU.GPR[ra]; - const s64 RB = CPU.GPR[rb]; - CPU.GPR[rd] = RA + RB + CPU.XER.CA; - CPU.XER.CA = ((u64)RA + CPU.XER.CA > ~(u64)RB) | ((RA == -1) & CPU.XER.CA); - if(rc) CPU.UpdateCR0(CPU.GPR[rd]); - if(oe) UNK("addeo"); - } - void MTOCRF(OP_REG crm, OP_REG rs) + if(rc) CPU.UpdateCR0(CPU.GPR[rd]); + } + void MULHWU(u32 rd, u32 ra, u32 rb, bool rc) + { + CPU.GPR[rd] = (CPU.GPR[ra] * CPU.GPR[rb]) >> 32; + if(rc) CPU.UpdateCR0(CPU.GPR[rd]); + } + void MFOCRF(u32 a, u32 rd, u32 crm) + { + if(a) { u32 n = 0, count = 0; - for(u32 i=0; i<8; ++i) + for(u32 i = 0; i < 8; ++i) { if(crm & (1 << i)) { @@ -2572,539 +2316,779 @@ private: if(count == 1) { - //CR[4*n : 4*n+3] = RS[32+4*n : 32+4*n+3]; - CPU.SetCR(n, (CPU.GPR[rs] >> (4*n)) & 0xf); - } - else CPU.CR.CR = 0; - } - void STDX(OP_REG rs, OP_REG ra, OP_REG rb) - { - Memory.Write64((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), CPU.GPR[rs]); - } - void STWCX_(OP_REG rs, OP_REG ra, OP_REG rb) - { - CPU.SetCR(0, CPU.XER.SO ? CR_SO : 0); - if(!CPU.reserve) return; - - const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; - - if(addr == CPU.reserve_addr) - { - Memory.Write32(addr, CPU.GPR[rs]); - CPU.SetCR_EQ(0, true); + //RD[32+4*n : 32+4*n+3] = CR[4*n : 4*n+3]; + CPU.GPR[rd] = (u64)CPU.GetCR(n) << (n * 4); } else + CPU.GPR[rd] = 0; + } + else + { + CPU.GPR[rd] = CPU.CR.CR; + } + } + void LWARX(u32 rd, u32 ra, u32 rb) + { + const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; + CPU.reserve_addr = addr; + CPU.reserve = true; + CPU.GPR[rd] = Memory.Read32(addr); + } + void LDX(u32 ra, u32 rs, u32 rb) + { + CPU.GPR[ra] = Memory.Read64(rs ? CPU.GPR[rs] + CPU.GPR[rb] : CPU.GPR[rb]); + } + void LWZX(u32 rd, u32 ra, u32 rb) + { + CPU.GPR[rd] = Memory.Read32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]); + } + void SLW(u32 ra, u32 rs, u32 rb, bool rc) + { + const u32 n = CPU.GPR[rb] & 0x1f; + const u32 r = rotl32((u32)CPU.GPR[rs], n); + const u32 m = (CPU.GPR[rb] & 0x20) ? 0 : rotate_mask[32][63 - n]; + + CPU.GPR[ra] = r & m; + + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void CNTLZW(u32 ra, u32 rs, bool rc) + { + u32 i; + for(i=0; i < 32; i++) + { + if(CPU.GPR[rs] & (0x80000000 >> i)) break; + } + + CPU.GPR[ra] = i; + + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void SLD(u32 ra, u32 rs, u32 rb, bool rc) + { + CPU.GPR[ra] = CPU.GPR[rb] & 0x40 ? 0 : CPU.GPR[rs] << (CPU.GPR[rb] & 0x3f); + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void AND(u32 ra, u32 rs, u32 rb, bool rc) + { + CPU.GPR[ra] = CPU.GPR[rs] & CPU.GPR[rb]; + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void CMPL(u32 crfd, u32 l, u32 ra, u32 rb) + { + CPU.UpdateCRn(crfd, l ? CPU.GPR[ra] : (u32)CPU.GPR[ra], l ? CPU.GPR[rb] : (u32)CPU.GPR[rb]); + } + void LVSR(u32 vd, u32 ra, u32 rb) + { + const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; + + static const u64 lvsr_values[0x10][2] = + { + {0x18191A1B1C1D1E1F, 0x1011121314151617}, + {0x1718191A1B1C1D1E, 0x0F10111213141516}, + {0x161718191A1B1C1D, 0x0E0F101112131415}, + {0x15161718191A1B1C, 0x0D0E0F1011121314}, + {0x1415161718191A1B, 0x0C0D0E0F10111213}, + {0x131415161718191A, 0x0B0C0D0E0F101112}, + {0x1213141516171819, 0x0A0B0C0D0E0F1011}, + {0x1112131415161718, 0x090A0B0C0D0E0F10}, + {0x1011121314151617, 0x08090A0B0C0D0E0F}, + {0x0F10111213141516, 0x0708090A0B0C0D0E}, + {0x0E0F101112131415, 0x060708090A0B0C0D}, + {0x0D0E0F1011121314, 0x05060708090A0B0C}, + {0x0C0D0E0F10111213, 0x0405060708090A0B}, + {0x0B0C0D0E0F101112, 0x030405060708090A}, + {0x0A0B0C0D0E0F1011, 0x0203040506070809}, + {0x090A0B0C0D0E0F10, 0x0102030405060708}, + }; + + CPU.VPR[vd]._u64[0] = lvsr_values[addr & 0xf][0]; + CPU.VPR[vd]._u64[1] = lvsr_values[addr & 0xf][1]; + } + void LVEHX(u32 vd, u32 ra, u32 rb) + { + //const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~1ULL; + //CPU.VPR[vd].Clear(); + //(u16&)CPU.VPR[vd]._u8[addr & 0xf] = Memory.Read16(addr); + CPU.VPR[vd]._u128 = Memory.Read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL); + } + void SUBF(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + CPU.GPR[rd] = CPU.GPR[rb] - CPU.GPR[ra]; + if(oe) UNK("subfo"); + if(rc) CPU.UpdateCR0(CPU.GPR[rd]); + } + void LDUX(u32 rd, u32 ra, u32 rb) + { + const u64 addr = CPU.GPR[ra] + CPU.GPR[rb]; + CPU.GPR[rd] = Memory.Read64(addr); + CPU.GPR[ra] = addr; + } + void DCBST(u32 ra, u32 rb) + { + //UNK("dcbst", false); + } + void CNTLZD(u32 ra, u32 rs, bool rc) + { + u32 i = 0; + + for(u64 mask = 1ULL << 63; i < 64; i++, mask >>= 1) + { + if(CPU.GPR[rs] & mask) break; + } + + CPU.GPR[ra] = i; + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void ANDC(u32 ra, u32 rs, u32 rb, bool rc) + { + CPU.GPR[ra] = CPU.GPR[rs] & ~CPU.GPR[rb]; + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void LVEWX(u32 vd, u32 ra, u32 rb) + { + //const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~3ULL; + //CPU.VPR[vd].Clear(); + //(u32&)CPU.VPR[vd]._u8[addr & 0xf] = Memory.Read32(addr); + CPU.VPR[vd]._u128 = Memory.Read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL); + } + void MULHD(u32 rd, u32 ra, u32 rb, bool rc) + { + const s64 RA = CPU.GPR[ra]; + const s64 RB = CPU.GPR[rb]; + + u128 RT; + + s64& lo = (s64&)((s32*)&RT)[0]; + s64& mid = (s64&)((s32*)&RT)[1]; + s64& hi = (s64&)((s32*)&RT)[2]; + + const s64 a0 = ((s32*)&RA)[0]; + const s64 a1 = ((s32*)&RA)[1]; + const s64 b0 = ((s32*)&RB)[0]; + const s64 b1 = ((s32*)&RB)[1]; + + lo = a0 * b0; + hi = a1 * b1; + + mid += (a0 + a1) * (b0 + b1) - (lo + hi); + + CPU.GPR[rd] = RT._u64[1]; + + if(rc) CPU.UpdateCR0(CPU.GPR[rd]); + } + void MULHW(u32 rd, u32 ra, u32 rb, bool rc) + { + CPU.GPR[rd] = (s64)(s32)((CPU.GPR[ra] * CPU.GPR[rb]) >> 32); + if(rc) CPU.UpdateCR0(CPU.GPR[rd]); + } + void LDARX(u32 rd, u32 ra, u32 rb) + { + const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; + CPU.reserve_addr = addr; + CPU.reserve = true; + CPU.GPR[rd] = Memory.Read64(addr); + } + void DCBF(u32 ra, u32 rb) + { + //UNK("dcbf", false); + } + void LBZX(u32 rd, u32 ra, u32 rb) + { + CPU.GPR[rd] = Memory.Read8(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]); + } + void LVX(u32 vd, u32 ra, u32 rb) + { + CPU.VPR[vd]._u128 = Memory.Read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL); + } + void NEG(u32 rd, u32 ra, u32 oe, bool rc) + { + CPU.GPR[rd] = 0-CPU.GPR[ra]; + if(oe) UNK("nego"); + if(rc) CPU.UpdateCR0(CPU.GPR[rd]); + } + void LBZUX(u32 rd, u32 ra, u32 rb) + { + //if(ra == 0 || ra == rd) throw "Bad instruction [LBZUX]"; + + const u64 addr = CPU.GPR[ra] + CPU.GPR[rb]; + CPU.GPR[rd] = Memory.Read8(addr); + CPU.GPR[ra] = addr; + } + void NOR(u32 ra, u32 rs, u32 rb, bool rc) + { + CPU.GPR[ra] = ~(CPU.GPR[rs] | CPU.GPR[rb]); + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void STVEBX(u32 vs, u32 ra, u32 rb) + { + const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; + const u8 eb = addr & 0xf; + Memory.Write8(addr, CPU.VPR[vs]._u8[15 - eb]); + } + void SUBFE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + const s64 RA = CPU.GPR[ra]; + const s64 RB = CPU.GPR[rb]; + CPU.GPR[ra] = ~RA + RB + CPU.XER.CA; + CPU.XER.CA = ((u64)~RA + CPU.XER.CA > ~(u64)RB) | ((RA == 0) & CPU.XER.CA); + if(rc) CPU.UpdateCR0(CPU.GPR[rd]); + if(oe) UNK("subfeo"); + } + void ADDE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + const s64 RA = CPU.GPR[ra]; + const s64 RB = CPU.GPR[rb]; + CPU.GPR[rd] = RA + RB + CPU.XER.CA; + CPU.XER.CA = ((u64)RA + CPU.XER.CA > ~(u64)RB) | ((RA == -1) & CPU.XER.CA); + if(rc) CPU.UpdateCR0(CPU.GPR[rd]); + if(oe) UNK("addeo"); + } + void MTOCRF(u32 crm, u32 rs) + { + u32 n = 0, count = 0; + for(u32 i=0; i<8; ++i) + { + if(crm & (1 << i)) { - static const bool u = 0; - if(u) Memory.Write32(addr, CPU.GPR[rs]); - CPU.SetCR_EQ(0, u); - CPU.reserve = false; + n = i; + count++; } } - void STWX(OP_REG rs, OP_REG ra, OP_REG rb) + + if(count == 1) { - Memory.Write32((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), CPU.GPR[rs]); + //CR[4*n : 4*n+3] = RS[32+4*n : 32+4*n+3]; + CPU.SetCR(n, (CPU.GPR[rs] >> (4*n)) & 0xf); } - void STVEHX(OP_REG vs, OP_REG ra, OP_REG rb) + else CPU.CR.CR = 0; + } + void STDX(u32 rs, u32 ra, u32 rb) + { + Memory.Write64((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), CPU.GPR[rs]); + } + void STWCX_(u32 rs, u32 ra, u32 rb) + { + CPU.SetCR(0, CPU.XER.SO ? CR_SO : 0); + if(!CPU.reserve) return; + + const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; + + if(addr == CPU.reserve_addr) { - const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~1ULL; - const u8 eb = (addr & 0xf) >> 1; - Memory.Write16(addr, CPU.VPR[vs]._u16[7 - eb]); + Memory.Write32(addr, CPU.GPR[rs]); + CPU.SetCR_EQ(0, true); } - void STDUX(OP_REG rs, OP_REG ra, OP_REG rb) + else + { + static const bool u = 0; + if(u) Memory.Write32(addr, CPU.GPR[rs]); + CPU.SetCR_EQ(0, u); + CPU.reserve = false; + } + } + void STWX(u32 rs, u32 ra, u32 rb) + { + Memory.Write32((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), CPU.GPR[rs]); + } + void STVEHX(u32 vs, u32 ra, u32 rb) + { + const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~1ULL; + const u8 eb = (addr & 0xf) >> 1; + Memory.Write16(addr, CPU.VPR[vs]._u16[7 - eb]); + } + void STDUX(u32 rs, u32 ra, u32 rb) + { + const u64 addr = CPU.GPR[ra] + CPU.GPR[rb]; + Memory.Write64(addr, CPU.GPR[rs]); + CPU.GPR[ra] = addr; + } + void STVEWX(u32 vs, u32 ra, u32 rb) + { + const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~3ULL; + const u8 eb = (addr & 0xf) >> 2; + Memory.Write32(addr, CPU.VPR[vs]._u32[3 - eb]); + } + void ADDZE(u32 rd, u32 ra, u32 oe, bool rc) + { + const s64 RA = CPU.GPR[ra]; + CPU.GPR[rd] = RA + CPU.XER.CA; + + CPU.XER.CA = CPU.IsCarry(RA, CPU.XER.CA); + if(oe) ConLog.Warning("addzeo"); + if(rc) CPU.UpdateCR0(CPU.GPR[rd]); + } + void STDCX_(u32 rs, u32 ra, u32 rb) + { + CPU.SetCR(0, CPU.XER.SO ? CR_SO : 0); + if(!CPU.reserve) return; + + const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; + + if(addr == CPU.reserve_addr) { - const u64 addr = CPU.GPR[ra] + CPU.GPR[rb]; Memory.Write64(addr, CPU.GPR[rs]); - CPU.GPR[ra] = addr; + CPU.SetCR_EQ(0, true); } - void STVEWX(OP_REG vs, OP_REG ra, OP_REG rb) + else { - const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~3ULL; - const u8 eb = (addr & 0xf) >> 2; - Memory.Write32(addr, CPU.VPR[vs]._u32[3 - eb]); + static const bool u = 0; + if(u) Memory.Write64(addr, CPU.GPR[rs]); + CPU.SetCR_EQ(0, u); + CPU.reserve = false; } - void ADDZE(OP_REG rd, OP_REG ra, OP_REG oe, bool rc) - { - const s64 RA = CPU.GPR[ra]; - CPU.GPR[rd] = RA + CPU.XER.CA; + } + void STBX(u32 rs, u32 ra, u32 rb) + { + Memory.Write8((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), CPU.GPR[rs]); + } + void STVX(u32 vs, u32 ra, u32 rb) + { + Memory.Write128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL, CPU.VPR[vs]._u128); + } + void MULLD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + CPU.GPR[rd] = CPU.GPR[ra] * CPU.GPR[rb]; + if(rc) CPU.UpdateCR0(CPU.GPR[rd]); + if(oe) UNK("mulldo"); + } + void ADDME(u32 rd, u32 ra, u32 oe, bool rc) + { + const s64 RA = CPU.GPR[ra]; + CPU.GPR[rd] = RA + CPU.XER.CA - 1; + CPU.XER.CA |= RA != 0; - CPU.XER.CA = CPU.IsCarry(RA, CPU.XER.CA); - if(oe) ConLog.Warning("addzeo"); - if(rc) CPU.UpdateCR0(CPU.GPR[rd]); - } - void STDCX_(OP_REG rs, OP_REG ra, OP_REG rb) - { - CPU.SetCR(0, CPU.XER.SO ? CR_SO : 0); - if(!CPU.reserve) return; + if(oe) UNK("addmeo"); + if(rc) CPU.UpdateCR0(CPU.GPR[rd]); + } + void MULLW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + CPU.GPR[rd] = (s64)(s32)((s32)CPU.GPR[ra] * (s32)CPU.GPR[rb]); + if(rc) CPU.UpdateCR0(CPU.GPR[rd]); + if(oe) UNK("mullwo"); + } + void DCBTST(u32 th, u32 ra, u32 rb) + { + //UNK("dcbtst", false); + } + void ADD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + const u64 RA = CPU.GPR[ra]; + const u64 RB = CPU.GPR[rb]; + CPU.GPR[rd] = RA + RB; + CPU.XER.CA = CPU.IsCarry(RA, RB); + if(oe) UNK("addo"); + if(rc) CPU.UpdateCR0(CPU.GPR[rd]); + } + void DCBT(u32 ra, u32 rb, u32 th) + { + //UNK("dcbt", false); + } + void LHZX(u32 rd, u32 ra, u32 rb) + { + CPU.GPR[rd] = Memory.Read16(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]); + } + void EQV(u32 ra, u32 rs, u32 rb, bool rc) + { + CPU.GPR[ra] = ~(CPU.GPR[rs] ^ CPU.GPR[rb]); + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void ECIWX(u32 rd, u32 ra, u32 rb) + { + //HACK! + CPU.GPR[rd] = Memory.Read32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]); + } + void LHZUX(u32 rd, u32 ra, u32 rb) + { + const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; + CPU.GPR[rd] = Memory.Read16(addr); + CPU.GPR[ra] = addr; + } + void XOR(u32 ra, u32 rs, u32 rb, bool rc) + { + CPU.GPR[ra] = CPU.GPR[rs] ^ CPU.GPR[rb]; + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void MFSPR(u32 rd, u32 spr) + { + CPU.GPR[rd] = GetRegBySPR(spr); + } + void DST(u32 ra, u32 rb, u32 strm, u32 t) + { + } + void LHAX(u32 rd, u32 ra, u32 rb) + { + CPU.GPR[rd] = (s64)(s16)Memory.Read16(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]); + } + void LVXL(u32 vd, u32 ra, u32 rb) + { + CPU.VPR[vd]._u128 = Memory.Read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL); + } + void ABS(u32 rd, u32 ra, u32 oe, bool rc) + { + CPU.GPR[rd] = abs((s64)CPU.GPR[ra]); + if(oe) UNK("abso"); + if(rc) CPU.UpdateCR0(CPU.GPR[rd]); + } + void MFTB(u32 rd, u32 spr) + { + const u32 n = (spr >> 5) | ((spr & 0x1f) << 5); - const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; + switch(n) + { + case 0x10C: CPU.GPR[rd] = CPU.TB; break; + case 0x10D: CPU.GPR[rd] = CPU.TBH; break; + default: UNK(wxString::Format("mftb r%d, %d", rd, spr)); break; + } + } + void DSTST(u32 ra, u32 rb, u32 strm, u32 t) + { + } + void LHAUX(u32 rd, u32 ra, u32 rb) + { + const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; + CPU.GPR[rd] = (s64)(s16)Memory.Read16(addr); + CPU.GPR[ra] = addr; + } + void STHX(u32 rs, u32 ra, u32 rb) + { + const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; + Memory.Write16(addr, CPU.GPR[rs]); + } + void ORC(u32 ra, u32 rs, u32 rb, bool rc) + { + CPU.GPR[ra] = CPU.GPR[rs] | ~CPU.GPR[rb]; + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void ECOWX(u32 rs, u32 ra, u32 rb) + { + //HACK! + Memory.Write32((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), CPU.GPR[rs]); + } + void OR(u32 ra, u32 rs, u32 rb, bool rc) + { + CPU.GPR[ra] = CPU.GPR[rs] | CPU.GPR[rb]; + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + const u64 RA = CPU.GPR[ra]; + const u64 RB = CPU.GPR[rb]; - if(addr == CPU.reserve_addr) - { - Memory.Write64(addr, CPU.GPR[rs]); - CPU.SetCR_EQ(0, true); - } - else - { - static const bool u = 0; - if(u) Memory.Write64(addr, CPU.GPR[rs]); - CPU.SetCR_EQ(0, u); - CPU.reserve = false; - } - } - void STBX(OP_REG rs, OP_REG ra, OP_REG rb) + if(RB == 0) { - Memory.Write8((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), CPU.GPR[rs]); + if(oe) UNK("divduo"); + CPU.GPR[rd] = 0; } - void STVX(OP_REG vs, OP_REG ra, OP_REG rb) + else { - Memory.Write128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL, CPU.VPR[vs]._u128); + CPU.GPR[rd] = RA / RB; } - void MULLD(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - CPU.GPR[rd] = CPU.GPR[ra] * CPU.GPR[rb]; - if(rc) CPU.UpdateCR0(CPU.GPR[rd]); - if(oe) UNK("mulldo"); - } - void ADDME(OP_REG rd, OP_REG ra, OP_REG oe, bool rc) - { - const s64 RA = CPU.GPR[ra]; - CPU.GPR[rd] = RA + CPU.XER.CA - 1; - CPU.XER.CA |= RA != 0; - if(oe) UNK("addmeo"); - if(rc) CPU.UpdateCR0(CPU.GPR[rd]); - } - void MULLW(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - CPU.GPR[rd] = (s64)(s32)((s32)CPU.GPR[ra] * (s32)CPU.GPR[rb]); - if(rc) CPU.UpdateCR0(CPU.GPR[rd]); - if(oe) UNK("mullwo"); - } - void DCBTST(OP_REG th, OP_REG ra, OP_REG rb) - { - //UNK("dcbtst", false); - } - void ADD(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - const u64 RA = CPU.GPR[ra]; - const u64 RB = CPU.GPR[rb]; - CPU.GPR[rd] = RA + RB; - CPU.XER.CA = CPU.IsCarry(RA, RB); - if(oe) UNK("addo"); - if(rc) CPU.UpdateCR0(CPU.GPR[rd]); - } - void DCBT(OP_REG ra, OP_REG rb, OP_REG th) - { - //UNK("dcbt", false); - } - void LHZX(OP_REG rd, OP_REG ra, OP_REG rb) - { - CPU.GPR[rd] = Memory.Read16(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]); - } - void EQV(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - CPU.GPR[ra] = ~(CPU.GPR[rs] ^ CPU.GPR[rb]); - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void ECIWX(OP_REG rd, OP_REG ra, OP_REG rb) - { - //HACK! - CPU.GPR[rd] = Memory.Read32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]); - } - void LHZUX(OP_REG rd, OP_REG ra, OP_REG rb) - { - const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; - CPU.GPR[rd] = Memory.Read16(addr); - CPU.GPR[ra] = addr; - } - void XOR(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - CPU.GPR[ra] = CPU.GPR[rs] ^ CPU.GPR[rb]; - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void MFSPR(OP_REG rd, OP_REG spr) - { - CPU.GPR[rd] = GetRegBySPR(spr); - } - void DST(OP_REG ra, OP_REG rb, OP_uIMM strm, OP_uIMM t) - { - } - void LHAX(OP_REG rd, OP_REG ra, OP_REG rb) - { - CPU.GPR[rd] = (s64)(s16)Memory.Read16(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]); - } - void LVXL(OP_REG vd, OP_REG ra, OP_REG rb) - { - CPU.VPR[vd]._u128 = Memory.Read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL); - } - void ABS(OP_REG rd, OP_REG ra, OP_REG oe, bool rc) - { - CPU.GPR[rd] = abs((s64)CPU.GPR[ra]); - if(oe) UNK("abso"); - if(rc) CPU.UpdateCR0(CPU.GPR[rd]); - } - void MFTB(OP_REG rd, OP_REG spr) - { - const u32 n = (spr >> 5) | ((spr & 0x1f) << 5); + if(rc) CPU.UpdateCR0(CPU.GPR[rd]); + } + void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + const u32 RA = CPU.GPR[ra]; + const u32 RB = CPU.GPR[rb]; - switch(n) - { - case 0x10C: CPU.GPR[rd] = CPU.TB; break; - case 0x10D: CPU.GPR[rd] = CPU.TBH; break; - default: UNK(wxString::Format("mftb r%d, %d", rd, spr)); break; - } - } - void DSTST(OP_REG ra, OP_REG rb, OP_uIMM strm, OP_uIMM t) + if(RB == 0) { + if(oe) UNK("divwuo"); + CPU.GPR[rd] = 0; } - void LHAUX(OP_REG rd, OP_REG ra, OP_REG rb) + else { - const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; - CPU.GPR[rd] = (s64)(s16)Memory.Read16(addr); - CPU.GPR[ra] = addr; + CPU.GPR[rd] = RA / RB; } - void STHX(OP_REG rs, OP_REG ra, OP_REG rb) - { - const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; - Memory.Write16(addr, CPU.GPR[rs]); - } - void ORC(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - CPU.GPR[ra] = CPU.GPR[rs] | ~CPU.GPR[rb]; - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void ECOWX(OP_REG rs, OP_REG ra, OP_REG rb) - { - //HACK! - Memory.Write32((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), CPU.GPR[rs]); - } - void OR(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - CPU.GPR[ra] = CPU.GPR[rs] | CPU.GPR[rb]; - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void DIVDU(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - const u64 RA = CPU.GPR[ra]; - const u64 RB = CPU.GPR[rb]; - if(RB == 0) - { - if(oe) UNK("divduo"); - CPU.GPR[rd] = 0; - } - else - { - CPU.GPR[rd] = RA / RB; - } + if(rc) CPU.UpdateCR0(CPU.GPR[rd]); + } + void MTSPR(u32 spr, u32 rs) + { + GetRegBySPR(spr) = CPU.GPR[rs]; + } + /*0x1d6*///DCBI + void NAND(u32 ra, u32 rs, u32 rb, bool rc) + { + CPU.GPR[ra] = ~(CPU.GPR[rs] & CPU.GPR[rb]); - if(rc) CPU.UpdateCR0(CPU.GPR[rd]); - } - void DIVWU(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - const u32 RA = CPU.GPR[ra]; - const u32 RB = CPU.GPR[rb]; + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void STVXL(u32 vs, u32 ra, u32 rb) + { + Memory.Write128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL, CPU.VPR[vs]._u128); + } + void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + const s64 RA = CPU.GPR[ra]; + const s64 RB = CPU.GPR[rb]; - if(RB == 0) - { - if(oe) UNK("divwuo"); - CPU.GPR[rd] = 0; - } - else - { - CPU.GPR[rd] = RA / RB; - } + if (RB == 0 || ((u64)RA == 0x8000000000000000 && RB == -1)) + { + if(oe) UNK("divdo"); + CPU.GPR[rd] = (((u64)RA & 0x8000000000000000) && RB == 0) ? -1 : 0; + } + else + { + CPU.GPR[rd] = RA / RB; + } - if(rc) CPU.UpdateCR0(CPU.GPR[rd]); - } - void MTSPR(OP_REG spr, OP_REG rs) - { - GetRegBySPR(spr) = CPU.GPR[rs]; - } - /*0x1d6*///DCBI - void NAND(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - CPU.GPR[ra] = ~(CPU.GPR[rs] & CPU.GPR[rb]); + if(rc) CPU.UpdateCR0(CPU.GPR[rd]); + } + void DIVW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) + { + const s32 RA = CPU.GPR[ra]; + const s32 RB = CPU.GPR[rb]; - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void STVXL(OP_REG vs, OP_REG ra, OP_REG rb) + if (RB == 0 || ((u32)RA == 0x80000000 && RB == -1)) { - Memory.Write128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL, CPU.VPR[vs]._u128); + if(oe) UNK("divwo"); + CPU.GPR[rd] = (((u32)RA & 0x80000000) && RB == 0) ? -1 : 0; } - void DIVD(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) + else { - const s64 RA = CPU.GPR[ra]; - const s64 RB = CPU.GPR[rb]; + CPU.GPR[rd] = (s64)(RA / RB); + } - if (RB == 0 || ((u64)RA == 0x8000000000000000 && RB == -1)) - { - if(oe) UNK("divdo"); - CPU.GPR[rd] = (((u64)RA & 0x8000000000000000) && RB == 0) ? -1 : 0; - } - else - { - CPU.GPR[rd] = RA / RB; - } + if(rc) CPU.UpdateCR0(CPU.GPR[rd]); + } + void LVLX(u32 vd, u32 ra, u32 rb) + { + const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; + const u8 eb = addr & 0xf; - if(rc) CPU.UpdateCR0(CPU.GPR[rd]); - } - void DIVW(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc) - { - const s32 RA = CPU.GPR[ra]; - const s32 RB = CPU.GPR[rb]; + Memory.ReadLeft(CPU.VPR[vd]._u8 + eb, addr, 16 - eb); + } + void LWBRX(u32 rd, u32 ra, u32 rb) + { + CPU.GPR[rd] = (u32&)Memory[ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]]; + } + void LFSX(u32 frd, u32 ra, u32 rb) + { + (u32&)CPU.FPR[frd] = Memory.Read32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]); + CPU.FPR[frd] = (float&)CPU.FPR[frd]; + } + void SRW(u32 ra, u32 rs, u32 rb, bool rc) + { + CPU.GPR[ra] = CPU.GPR[rb] & 0x20 ? 0 : (u32)CPU.GPR[rs] >> (CPU.GPR[rb] & 0x1f); + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void SRD(u32 ra, u32 rs, u32 rb, bool rc) + { + CPU.GPR[ra] = CPU.GPR[rb] & 0x40 ? 0 : CPU.GPR[rs] >> (CPU.GPR[rb] & 0x3f); + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void LVRX(u32 vd, u32 ra, u32 rb) + { + const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; + const u8 eb = addr & 0xf; - if (RB == 0 || ((u32)RA == 0x80000000 && RB == -1)) - { - if(oe) UNK("divwo"); - CPU.GPR[rd] = (((u32)RA & 0x80000000) && RB == 0) ? -1 : 0; - } - else - { - CPU.GPR[rd] = (s64)(RA / RB); - } + Memory.ReadRight(CPU.VPR[vd]._u8, addr & ~0xf, eb); + } + void LFSUX(u32 frd, u32 ra, u32 rb) + { + const u64 addr = CPU.GPR[ra] + CPU.GPR[rb]; + (u64&)CPU.FPR[frd] = Memory.Read32(addr); + CPU.FPR[frd] = (float&)CPU.FPR[frd]; + CPU.GPR[ra] = addr; + } + void SYNC(u32 l) + { + } + void LFDX(u32 frd, u32 ra, u32 rb) + { + (u64&)CPU.FPR[frd] = Memory.Read64(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]); + } + void LFDUX(u32 frd, u32 ra, u32 rb) + { + const u64 addr = CPU.GPR[ra] + CPU.GPR[rb]; + (u64&)CPU.FPR[frd] = Memory.Read64(addr); + CPU.GPR[ra] = addr; + } + void STVLX(u32 vs, u32 ra, u32 rb) + { + const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; + const u8 eb = addr & 0xf; - if(rc) CPU.UpdateCR0(CPU.GPR[rd]); - } - void LVLX(OP_REG vd, OP_REG ra, OP_REG rb) - { - const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; - const u8 eb = addr & 0xf; + Memory.WriteLeft(addr, 16 - eb, CPU.VPR[vs]._u8 + eb); + } + void STFSX(u32 frs, u32 ra, u32 rb) + { + Memory.Write32((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), PPCdouble(CPU.FPR[frs]).To32()); + } + void STVRX(u32 vs, u32 ra, u32 rb) + { + const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; + const u8 eb = addr & 0xf; - Memory.ReadLeft(CPU.VPR[vd]._u8 + eb, addr, 16 - eb); - } - void LWBRX(OP_REG rd, OP_REG ra, OP_REG rb) - { - CPU.GPR[rd] = (u32&)Memory[ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]]; - } - void LFSX(OP_REG frd, OP_REG ra, OP_REG rb) - { - (u32&)CPU.FPR[frd] = Memory.Read32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]); - CPU.FPR[frd] = (float&)CPU.FPR[frd]; - } - void SRW(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - CPU.GPR[ra] = CPU.GPR[rb] & 0x20 ? 0 : (u32)CPU.GPR[rs] >> (CPU.GPR[rb] & 0x1f); - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void SRD(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - CPU.GPR[ra] = CPU.GPR[rb] & 0x40 ? 0 : CPU.GPR[rs] >> (CPU.GPR[rb] & 0x3f); - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void LVRX(OP_REG vd, OP_REG ra, OP_REG rb) - { - const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; - const u8 eb = addr & 0xf; + Memory.WriteRight(addr - eb, eb, CPU.VPR[vs]._u8); + } + void STFDX(u32 frs, u32 ra, u32 rb) + { + Memory.Write64((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), (u64&)CPU.FPR[frs]); + } + void LVLXL(u32 vd, u32 ra, u32 rb) + { + const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; + const u8 eb = addr & 0xf; - Memory.ReadRight(CPU.VPR[vd]._u8, addr & ~0xf, eb); - } - void LFSUX(OP_REG frd, OP_REG ra, OP_REG rb) - { - const u64 addr = CPU.GPR[ra] + CPU.GPR[rb]; - (u64&)CPU.FPR[frd] = Memory.Read32(addr); - CPU.FPR[frd] = (float&)CPU.FPR[frd]; - CPU.GPR[ra] = addr; - } - void SYNC(OP_uIMM l) - { - } - void LFDX(OP_REG frd, OP_REG ra, OP_REG rb) - { - (u64&)CPU.FPR[frd] = Memory.Read64(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]); - } - void LFDUX(OP_REG frd, OP_REG ra, OP_REG rb) - { - const u64 addr = CPU.GPR[ra] + CPU.GPR[rb]; - (u64&)CPU.FPR[frd] = Memory.Read64(addr); - CPU.GPR[ra] = addr; - } - void STVLX(OP_REG vs, OP_REG ra, OP_REG rb) - { - const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; - const u8 eb = addr & 0xf; + Memory.ReadLeft(CPU.VPR[vd]._u8 + eb, addr, 16 - eb); + } + void LHBRX(u32 rd, u32 ra, u32 rb) + { + CPU.GPR[rd] = (u16&)Memory[ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]]; + } + void SRAW(u32 ra, u32 rs, u32 rb, bool rc) + { + s32 RS = CPU.GPR[rs]; + s32 RB = CPU.GPR[rb]; + CPU.GPR[ra] = RS >> RB; + CPU.XER.CA = (RS < 0) & ((CPU.GPR[ra] << RB) != RS); - Memory.WriteLeft(addr, 16 - eb, CPU.VPR[vs]._u8 + eb); - } - void STFSX(OP_REG frs, OP_REG ra, OP_REG rb) - { - Memory.Write32((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), PPCdouble(CPU.FPR[frs]).To32()); - } - void STVRX(OP_REG vs, OP_REG ra, OP_REG rb) - { - const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; - const u8 eb = addr & 0xf; + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void SRAD(u32 ra, u32 rs, u32 rb, bool rc) + { + s64 RS = CPU.GPR[rs]; + s64 RB = CPU.GPR[rb]; + CPU.GPR[ra] = RS >> RB; + CPU.XER.CA = (RS < 0) & ((CPU.GPR[ra] << RB) != RS); - Memory.WriteRight(addr - eb, eb, CPU.VPR[vs]._u8); - } - void STFDX(OP_REG frs, OP_REG ra, OP_REG rb) - { - Memory.Write64((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), (u64&)CPU.FPR[frs]); - } - void LVLXL(OP_REG vd, OP_REG ra, OP_REG rb) - { - const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; - const u8 eb = addr & 0xf; + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void LVRXL(u32 vd, u32 ra, u32 rb) + { + const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; + const u8 eb = addr & 0xf; - Memory.ReadLeft(CPU.VPR[vd]._u8 + eb, addr, 16 - eb); - } - void LHBRX(OP_REG rd, OP_REG ra, OP_REG rb) - { - CPU.GPR[rd] = (u16&)Memory[ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]]; - } - void SRAW(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - s32 RS = CPU.GPR[rs]; - s32 RB = CPU.GPR[rb]; - CPU.GPR[ra] = RS >> RB; - CPU.XER.CA = (RS < 0) & ((CPU.GPR[ra] << RB) != RS); + Memory.ReadRight(CPU.VPR[vd]._u8, addr & ~0xf, eb); + } + void DSS(u32 strm, u32 a) + { + } + void SRAWI(u32 ra, u32 rs, u32 sh, bool rc) + { + s32 RS = CPU.GPR[rs]; + CPU.GPR[ra] = RS >> sh; + CPU.XER.CA = (RS < 0) & ((CPU.GPR[ra] << sh) != RS); - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void SRAD(OP_REG ra, OP_REG rs, OP_REG rb, bool rc) - { - s64 RS = CPU.GPR[rs]; - s64 RB = CPU.GPR[rb]; - CPU.GPR[ra] = RS >> RB; - CPU.XER.CA = (RS < 0) & ((CPU.GPR[ra] << RB) != RS); + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void SRADI1(u32 ra, u32 rs, u32 sh, bool rc) + { + s64 RS = CPU.GPR[rs]; + CPU.GPR[ra] = RS >> sh; + CPU.XER.CA = (RS < 0) & ((CPU.GPR[ra] << sh) != RS); - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void LVRXL(OP_REG vd, OP_REG ra, OP_REG rb) - { - const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; - const u8 eb = addr & 0xf; + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void SRADI2(u32 ra, u32 rs, u32 sh, bool rc) + { + SRADI1(ra, rs, sh, rc); + } + void EIEIO() + { + } + void STVLXL(u32 vs, u32 ra, u32 rb) + { + const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; + const u8 eb = addr & 0xf; - Memory.ReadRight(CPU.VPR[vd]._u8, addr & ~0xf, eb); - } - void DSS(OP_uIMM strm, OP_uIMM a) - { - } - void SRAWI(OP_REG ra, OP_REG rs, OP_REG sh, bool rc) - { - s32 RS = CPU.GPR[rs]; - CPU.GPR[ra] = RS >> sh; - CPU.XER.CA = (RS < 0) & ((CPU.GPR[ra] << sh) != RS); + Memory.WriteLeft(addr, 16 - eb, CPU.VPR[vs]._u8 + eb); + } + void EXTSH(u32 ra, u32 rs, bool rc) + { + CPU.GPR[ra] = (s64)(s16)CPU.GPR[rs]; + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void STVRXL(u32 vs, u32 ra, u32 rb) + { + const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; + const u8 eb = addr & 0xf; - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void SRADI1(OP_REG ra, OP_REG rs, OP_REG sh, bool rc) - { - s64 RS = CPU.GPR[rs]; - CPU.GPR[ra] = RS >> sh; - CPU.XER.CA = (RS < 0) & ((CPU.GPR[ra] << sh) != RS); - - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void SRADI2(OP_REG ra, OP_REG rs, OP_REG sh, bool rc) - { - SRADI1(ra, rs, sh, rc); - } - void EIEIO() - { - } - void STVLXL(OP_REG vs, OP_REG ra, OP_REG rb) - { - const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; - const u8 eb = addr & 0xf; - - Memory.WriteLeft(addr, 16 - eb, CPU.VPR[vs]._u8 + eb); - } - void EXTSH(OP_REG ra, OP_REG rs, bool rc) - { - CPU.GPR[ra] = (s64)(s16)CPU.GPR[rs]; - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void STVRXL(OP_REG vs, OP_REG ra, OP_REG rb) - { - const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; - const u8 eb = addr & 0xf; - - Memory.WriteRight(addr - eb, eb, CPU.VPR[vs]._u8); - } - void EXTSB(OP_REG ra, OP_REG rs, bool rc) - { - CPU.GPR[ra] = (s64)(s8)CPU.GPR[rs]; - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - void STFIWX(OP_REG frs, OP_REG ra, OP_REG rb) - { - Memory.Write32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb], (u32&)CPU.FPR[frs]); - } - void EXTSW(OP_REG ra, OP_REG rs, bool rc) - { - CPU.GPR[ra] = (s64)(s32)CPU.GPR[rs]; - if(rc) CPU.UpdateCR0(CPU.GPR[ra]); - } - /*0x3d6*///ICBI - void DCBZ(OP_REG ra, OP_REG rs) - { - //UNK("dcbz", false); - } - END_OPCODES_GROUP(G_1f); - - void LWZ(OP_REG rd, OP_REG ra, OP_sIMM d) + Memory.WriteRight(addr - eb, eb, CPU.VPR[vs]._u8); + } + void EXTSB(u32 ra, u32 rs, bool rc) + { + CPU.GPR[ra] = (s64)(s8)CPU.GPR[rs]; + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + void STFIWX(u32 frs, u32 ra, u32 rb) + { + Memory.Write32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb], (u32&)CPU.FPR[frs]); + } + void EXTSW(u32 ra, u32 rs, bool rc) + { + CPU.GPR[ra] = (s64)(s32)CPU.GPR[rs]; + if(rc) CPU.UpdateCR0(CPU.GPR[ra]); + } + /*0x3d6*///ICBI + void DCBZ(u32 ra, u32 rs) + { + //UNK("dcbz", false); + } + void LWZ(u32 rd, u32 ra, s32 d) { CPU.GPR[rd] = Memory.Read32(ra ? CPU.GPR[ra] + d : d); } - void LWZU(OP_REG rd, OP_REG ra, OP_sIMM d) + void LWZU(u32 rd, u32 ra, s32 d) { const u64 addr = CPU.GPR[ra] + d; CPU.GPR[rd] = Memory.Read32(addr); CPU.GPR[ra] = addr; } - void LBZ(OP_REG rd, OP_REG ra, OP_sIMM d) + void LBZ(u32 rd, u32 ra, s32 d) { CPU.GPR[rd] = Memory.Read8(ra ? CPU.GPR[ra] + d : d); } - void LBZU(OP_REG rd, OP_REG ra, OP_sIMM d) + void LBZU(u32 rd, u32 ra, s32 d) { const u64 addr = CPU.GPR[ra] + d; CPU.GPR[rd] = Memory.Read8(addr); CPU.GPR[ra] = addr; } - void STW(OP_REG rs, OP_REG ra, OP_sIMM d) + void STW(u32 rs, u32 ra, s32 d) { Memory.Write32(ra ? CPU.GPR[ra] + d : d, CPU.GPR[rs]); } - void STWU(OP_REG rs, OP_REG ra, OP_sIMM d) + void STWU(u32 rs, u32 ra, s32 d) { const u64 addr = CPU.GPR[ra] + d; Memory.Write32(addr, CPU.GPR[rs]); CPU.GPR[ra] = addr; } - void STB(OP_REG rs, OP_REG ra, OP_sIMM d) + void STB(u32 rs, u32 ra, s32 d) { Memory.Write8(ra ? CPU.GPR[ra] + d : d, CPU.GPR[rs]); } - void STBU(OP_REG rs, OP_REG ra, OP_sIMM d) + void STBU(u32 rs, u32 ra, s32 d) { const u64 addr = CPU.GPR[ra] + d; Memory.Write8(addr, CPU.GPR[rs]); CPU.GPR[ra] = addr; } - void LHZ(OP_REG rd, OP_REG ra, OP_sIMM d) + void LHZ(u32 rd, u32 ra, s32 d) { CPU.GPR[rd] = Memory.Read16(ra ? CPU.GPR[ra] + d : d); } - void LHZU(OP_REG rd, OP_REG ra, OP_sIMM d) + void LHZU(u32 rd, u32 ra, s32 d) { const u64 addr = CPU.GPR[ra] + d; CPU.GPR[rd] = Memory.Read16(addr); CPU.GPR[ra] = addr; } - void STH(OP_REG rs, OP_REG ra, OP_sIMM d) + void STH(u32 rs, u32 ra, s32 d) { Memory.Write16(ra ? CPU.GPR[ra] + d : d, CPU.GPR[rs]); } - void STHU(OP_REG rs, OP_REG ra, OP_sIMM d) + void STHU(u32 rs, u32 ra, s32 d) { const u64 addr = CPU.GPR[ra] + d; Memory.Write16(addr, CPU.GPR[rs]); CPU.GPR[ra] = addr; } - void LMW(OP_REG rd, OP_REG ra, OP_sIMM d) + void LMW(u32 rd, u32 ra, s32 d) { u64 addr = ra ? CPU.GPR[ra] + d : d; for(u32 i=rd; i<32; ++i, addr += 4) @@ -3112,7 +3096,7 @@ private: CPU.GPR[i] = Memory.Read32(addr); } } - void STMW(OP_REG rs, OP_REG ra, OP_sIMM d) + void STMW(u32 rs, u32 ra, s32 d) { u64 addr = ra ? CPU.GPR[ra] + d : d; for(u32 i=rs; i<32; ++i, addr += 4) @@ -3120,527 +3104,515 @@ private: Memory.Write32(addr, CPU.GPR[i]); } } - void LFS(OP_REG frd, OP_REG ra, OP_sIMM d) + void LFS(u32 frd, u32 ra, s32 d) { const u32 v = Memory.Read32(ra ? CPU.GPR[ra] + d : d); CPU.FPR[frd] = (float&)v; } - void LFSU(OP_REG frd, OP_REG ra, OP_sIMM ds) + void LFSU(u32 frd, u32 ra, s32 ds) { const u64 addr = CPU.GPR[ra] + ds; const u32 v = Memory.Read32(addr); CPU.FPR[frd] = (float&)v; CPU.GPR[ra] = addr; } - void LFD(OP_REG frd, OP_REG ra, OP_sIMM d) + void LFD(u32 frd, u32 ra, s32 d) { (u64&)CPU.FPR[frd] = Memory.Read64(ra ? CPU.GPR[ra] + d : d); } - void LFDU(OP_REG frd, OP_REG ra, OP_sIMM ds) + void LFDU(u32 frd, u32 ra, s32 ds) { const u64 addr = CPU.GPR[ra] + ds; (u64&)CPU.FPR[frd] = Memory.Read64(addr); CPU.GPR[ra] = addr; } - void STFS(OP_REG frs, OP_REG ra, OP_sIMM d) + void STFS(u32 frs, u32 ra, s32 d) { Memory.Write32(ra ? CPU.GPR[ra] + d : d, PPCdouble(CPU.FPR[frs]).To32()); } - void STFSU(OP_REG frs, OP_REG ra, OP_sIMM d) + void STFSU(u32 frs, u32 ra, s32 d) { const u64 addr = CPU.GPR[ra] + d; Memory.Write32(addr, PPCdouble(CPU.FPR[frs]).To32()); CPU.GPR[ra] = addr; } - void STFD(OP_REG frs, OP_REG ra, OP_sIMM d) + void STFD(u32 frs, u32 ra, s32 d) { Memory.Write64(ra ? CPU.GPR[ra] + d : d, (u64&)CPU.FPR[frs]); } - void STFDU(OP_REG frs, OP_REG ra, OP_sIMM d) + void STFDU(u32 frs, u32 ra, s32 d) { const u64 addr = CPU.GPR[ra] + d; Memory.Write64(addr, (u64&)CPU.FPR[frs]); CPU.GPR[ra] = addr; } - - START_OPCODES_GROUP(G_3a) - void LD(OP_REG rd, OP_REG ra, OP_sIMM ds) + void LD(u32 rd, u32 ra, s32 ds) + { + CPU.GPR[rd] = Memory.Read64(ra ? CPU.GPR[ra] + ds : ds); + } + void LDU(u32 rd, u32 ra, s32 ds) + { + //if(ra == 0 || rt == ra) return; + const u64 addr = CPU.GPR[ra] + ds; + CPU.GPR[rd] = Memory.Read64(addr); + CPU.GPR[ra] = addr; + } + void FDIVS(u32 frd, u32 fra, u32 frb, bool rc) + { + if(CPU.FPR[frb] == 0.0) CPU.SetFPSCRException(FPSCR_ZX); + CPU.FPR[frd] = static_cast(CPU.FPR[fra] / CPU.FPR[frb]); + CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); + if(rc) UNK("fdivs.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FSUBS(u32 frd, u32 fra, u32 frb, bool rc) + { + CPU.FPR[frd] = static_cast(CPU.FPR[fra] - CPU.FPR[frb]); + CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); + if(rc) UNK("fsubs.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FADDS(u32 frd, u32 fra, u32 frb, bool rc) + { + CPU.FPR[frd] = static_cast(CPU.FPR[fra] + CPU.FPR[frb]); + CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); + if(rc) UNK("fadds.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FSQRTS(u32 frd, u32 frb, bool rc) + { + CPU.FPR[frd] = static_cast(sqrt((float)CPU.FPR[frb])); + if(rc) UNK("fsqrts.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FRES(u32 frd, u32 frb, bool rc) + { + if(CPU.FPR[frb] == 0.0) CPU.SetFPSCRException(FPSCR_ZX); + CPU.FPR[frd] = static_cast(1.0f/CPU.FPR[frb]); + if(rc) UNK("fres.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FMULS(u32 frd, u32 fra, u32 frc, bool rc) + { + CPU.FPR[frd] = static_cast(CPU.FPR[fra] * CPU.FPR[frc]); + CPU.FPSCR.FI = 0; + CPU.FPSCR.FR = 0; + CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); + if(rc) UNK("fmuls.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + { + CPU.FPR[frd] = static_cast(CPU.FPR[fra] * CPU.FPR[frc] + CPU.FPR[frb]); + CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); + if(rc) UNK("fmadds.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + { + CPU.FPR[frd] = static_cast(CPU.FPR[fra] * CPU.FPR[frc] - CPU.FPR[frb]); + CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); + if(rc) UNK("fmsubs.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FNMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + { + CPU.FPR[frd] = static_cast(-(CPU.FPR[fra] * CPU.FPR[frc] - CPU.FPR[frb])); + CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); + if(rc) UNK("fnmsubs.");////CPU.UpdateCR1(CPU.FPR[frd]); + } + void FNMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + { + CPU.FPR[frd] = static_cast(-(CPU.FPR[fra] * CPU.FPR[frc] + CPU.FPR[frb])); + CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); + if(rc) UNK("fnmadds.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void STD(u32 rs, u32 ra, s32 d) + { + Memory.Write64(ra ? CPU.GPR[ra] + d : d, CPU.GPR[rs]); + } + void STDU(u32 rs, u32 ra, s32 ds) + { + //if(ra == 0 || rs == ra) return; + const u64 addr = CPU.GPR[ra] + ds; + Memory.Write64(addr, CPU.GPR[rs]); + CPU.GPR[ra] = addr; + } + void MTFSB1(u32 bt, bool rc) + { + UNIMPLEMENTED(); + } + void MCRFS(u32 bf, u32 bfa) + { + UNIMPLEMENTED(); + } + void MTFSB0(u32 bt, bool rc) + { + UNIMPLEMENTED(); + } + void MTFSFI(u32 crfd, u32 i, bool rc) + { + UNIMPLEMENTED(); + } + void MFFS(u32 frd, bool rc) + { + (u64&)CPU.FPR[frd] = CPU.FPSCR.FPSCR; + if(rc) UNK("mffs."); + } + void MTFSF(u32 flm, u32 frb, bool rc) + { + u32 mask = 0; + for(u32 i=0; i<8; ++i) { - CPU.GPR[rd] = Memory.Read64(ra ? CPU.GPR[ra] + ds : ds); + if(flm & (1 << i)) mask |= 0xf << (i * 4); } - void LDU(OP_REG rd, OP_REG ra, OP_sIMM ds) - { - //if(ra == 0 || rt == ra) return; - const u64 addr = CPU.GPR[ra] + ds; - CPU.GPR[rd] = Memory.Read64(addr); - CPU.GPR[ra] = addr; - } - END_OPCODES_GROUP(G_3a); - START_OPCODES_GROUP(G_3b) - void FDIVS(OP_REG frd, OP_REG fra, OP_REG frb, bool rc) + CPU.FPSCR.FPSCR = (CPU.FPSCR.FPSCR & ~mask) | ((u32&)CPU.FPR[frb] & mask); + if(rc) UNK("mtfsf."); + } + void FCMPU(u32 crfd, u32 fra, u32 frb) + { + if((CPU.FPSCR.FPRF = FPRdouble::Cmp(CPU.FPR[fra], CPU.FPR[frb])) == 1) { - if(CPU.FPR[frb] == 0.0) CPU.SetFPSCRException(FPSCR_ZX); - CPU.FPR[frd] = static_cast(CPU.FPR[fra] / CPU.FPR[frb]); - CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); - if(rc) UNK("fdivs.");//CPU.UpdateCR1(CPU.FPR[frd]); + if(FPRdouble::IsSNaN(CPU.FPR[fra]) || FPRdouble::IsSNaN(CPU.FPR[frb])) + { + CPU.SetFPSCRException(FPSCR_VXSNAN); + } } - void FSUBS(OP_REG frd, OP_REG fra, OP_REG frb, bool rc) + + CPU.SetCR(crfd, CPU.FPSCR.FPRF); + } + void FRSP(u32 frd, u32 frb, bool rc) + { + const double b = CPU.FPR[frb]; + double b0 = b; + if(CPU.FPSCR.NI) { - CPU.FPR[frd] = static_cast(CPU.FPR[fra] - CPU.FPR[frb]); - CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); - if(rc) UNK("fsubs.");//CPU.UpdateCR1(CPU.FPR[frd]); + if (((u64&)b0 & DOUBLE_EXP) < 0x3800000000000000ULL) (u64&)b0 &= DOUBLE_SIGN; } - void FADDS(OP_REG frd, OP_REG fra, OP_REG frb, bool rc) + const double r = static_cast(b0); + CPU.FPSCR.FR = fabs(r) > fabs(b); + CPU.SetFPSCR_FI(b != r); + CPU.FPSCR.FPRF = PPCdouble(r).GetType(); + CPU.FPR[frd] = r; + } + void FCTIW(u32 frd, u32 frb, bool rc) + { + const double b = CPU.FPR[frb]; + u32 r; + if(b > (double)0x7fffffff) { - CPU.FPR[frd] = static_cast(CPU.FPR[fra] + CPU.FPR[frb]); - CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); - if(rc) UNK("fadds.");//CPU.UpdateCR1(CPU.FPR[frd]); - } - void FSQRTS(OP_REG frd, OP_REG frb, bool rc) - { - CPU.FPR[frd] = static_cast(sqrt((float)CPU.FPR[frb])); - if(rc) UNK("fsqrts.");//CPU.UpdateCR1(CPU.FPR[frd]); - } - void FRES(OP_REG frd, OP_REG frb, bool rc) - { - if(CPU.FPR[frb] == 0.0) CPU.SetFPSCRException(FPSCR_ZX); - CPU.FPR[frd] = static_cast(1.0f/CPU.FPR[frb]); - if(rc) UNK("fres.");//CPU.UpdateCR1(CPU.FPR[frd]); - } - void FMULS(OP_REG frd, OP_REG fra, OP_REG frc, bool rc) - { - CPU.FPR[frd] = static_cast(CPU.FPR[fra] * CPU.FPR[frc]); + r = 0x7fffffff; + CPU.SetFPSCRException(FPSCR_VXCVI); CPU.FPSCR.FI = 0; CPU.FPSCR.FR = 0; - CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); - if(rc) UNK("fmuls.");//CPU.UpdateCR1(CPU.FPR[frd]); } - void FMADDS(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc) + else if (b < -(double)0x80000000) { - CPU.FPR[frd] = static_cast(CPU.FPR[fra] * CPU.FPR[frc] + CPU.FPR[frb]); - CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); - if(rc) UNK("fmadds.");//CPU.UpdateCR1(CPU.FPR[frd]); - } - void FMSUBS(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc) - { - CPU.FPR[frd] = static_cast(CPU.FPR[fra] * CPU.FPR[frc] - CPU.FPR[frb]); - CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); - if(rc) UNK("fmsubs.");//CPU.UpdateCR1(CPU.FPR[frd]); - } - void FNMSUBS(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc) - { - CPU.FPR[frd] = static_cast(-(CPU.FPR[fra] * CPU.FPR[frc] - CPU.FPR[frb])); - CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); - if(rc) UNK("fnmsubs.");////CPU.UpdateCR1(CPU.FPR[frd]); - } - void FNMADDS(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc) - { - CPU.FPR[frd] = static_cast(-(CPU.FPR[fra] * CPU.FPR[frc] + CPU.FPR[frb])); - CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); - if(rc) UNK("fnmadds.");//CPU.UpdateCR1(CPU.FPR[frd]); - } - END_OPCODES_GROUP(G_3b); - - START_OPCODES_GROUP(G_3e) - void STD(OP_REG rs, OP_REG ra, OP_sIMM d) - { - Memory.Write64(ra ? CPU.GPR[ra] + d : d, CPU.GPR[rs]); - } - void STDU(OP_REG rs, OP_REG ra, OP_sIMM ds) - { - //if(ra == 0 || rs == ra) return; - const u64 addr = CPU.GPR[ra] + ds; - Memory.Write64(addr, CPU.GPR[rs]); - CPU.GPR[ra] = addr; - } - END_OPCODES_GROUP(G_3e); - - START_OPCODES_GROUP(G_3f) - void MTFSB1(OP_REG bt, bool rc) - { - UNIMPLEMENTED(); - } - void MCRFS(OP_REG bf, OP_REG bfa) - { - UNIMPLEMENTED(); - } - void MTFSB0(OP_REG bt, bool rc) - { - UNIMPLEMENTED(); - } - void MTFSFI(OP_REG crfd, OP_REG i, bool rc) - { - UNIMPLEMENTED(); - } - void MFFS(OP_REG frd, bool rc) - { - (u64&)CPU.FPR[frd] = CPU.FPSCR.FPSCR; - if(rc) UNK("mffs."); - } - void MTFSF(OP_REG flm, OP_REG frb, bool rc) - { - u32 mask = 0; - for(u32 i=0; i<8; ++i) - { - if(flm & (1 << i)) mask |= 0xf << (i * 4); - } - - CPU.FPSCR.FPSCR = (CPU.FPSCR.FPSCR & ~mask) | ((u32&)CPU.FPR[frb] & mask); - if(rc) UNK("mtfsf."); - } - void FCMPU(OP_REG crfd, OP_REG fra, OP_REG frb) - { - if((CPU.FPSCR.FPRF = FPRdouble::Cmp(CPU.FPR[fra], CPU.FPR[frb])) == 1) - { - if(FPRdouble::IsSNaN(CPU.FPR[fra]) || FPRdouble::IsSNaN(CPU.FPR[frb])) - { - CPU.SetFPSCRException(FPSCR_VXSNAN); - } - } - - CPU.SetCR(crfd, CPU.FPSCR.FPRF); - } - void FRSP(OP_REG frd, OP_REG frb, bool rc) - { - const double b = CPU.FPR[frb]; - double b0 = b; - if(CPU.FPSCR.NI) - { - if (((u64&)b0 & DOUBLE_EXP) < 0x3800000000000000ULL) (u64&)b0 &= DOUBLE_SIGN; - } - const double r = static_cast(b0); - CPU.FPSCR.FR = fabs(r) > fabs(b); - CPU.SetFPSCR_FI(b != r); - CPU.FPSCR.FPRF = PPCdouble(r).GetType(); - CPU.FPR[frd] = r; - } - void FCTIW(OP_REG frd, OP_REG frb, bool rc) - { - const double b = CPU.FPR[frb]; - u32 r; - if(b > (double)0x7fffffff) - { - r = 0x7fffffff; - CPU.SetFPSCRException(FPSCR_VXCVI); - CPU.FPSCR.FI = 0; - CPU.FPSCR.FR = 0; - } - else if (b < -(double)0x80000000) - { - r = 0x80000000; - CPU.SetFPSCRException(FPSCR_VXCVI); - CPU.FPSCR.FI = 0; - CPU.FPSCR.FR = 0; - } - else - { - s32 i = 0; - switch(CPU.FPSCR.RN) - { - case FPSCR_RN_NEAR: - { - double t = b + 0.5; - i = (s32)t; - if (t - i < 0 || (t - i == 0 && b > 0)) i--; - break; - } - case FPSCR_RN_ZERO: - i = (s32)b; - break; - case FPSCR_RN_PINF: - i = (s32)b; - if (b - i > 0) i++; - break; - case FPSCR_RN_MINF: - i = (s32)b; - if (b - i < 0) i--; - break; - } - r = (u32)i; - double di = i; - if (di == b) - { - CPU.SetFPSCR_FI(0); - CPU.FPSCR.FR = 0; - } - else - { - CPU.SetFPSCR_FI(1); - CPU.FPSCR.FR = fabs(di) > fabs(b); - } - } - - (u64&)CPU.FPR[frd] = 0xfff8000000000000ull | r; - if(r == 0 && ( (u64&)b & DOUBLE_SIGN )) (u64&)CPU.FPR[frd] |= 0x100000000ull; - - if(rc) UNK("fctiw."); - } - void FCTIWZ(OP_REG frd, OP_REG frb, bool rc) - { - const double b = CPU.FPR[frb]; - u32 value; - if (b > (double)0x7fffffff) - { - value = 0x7fffffff; - CPU.SetFPSCRException(FPSCR_VXCVI); - CPU.FPSCR.FI = 0; - CPU.FPSCR.FR = 0; - } - else if (b < -(double)0x80000000) - { - value = 0x80000000; - CPU.SetFPSCRException(FPSCR_VXCVI); - CPU.FPSCR.FI = 0; - CPU.FPSCR.FR = 0; - } - else - { - s32 i = (s32)b; - double di = i; - if (di == b) - { - CPU.SetFPSCR_FI(0); - CPU.FPSCR.FR = 0; - } - else - { - CPU.SetFPSCR_FI(1); - CPU.FPSCR.FR = fabs(di) > fabs(b); - } - value = (u32)i; - } - - (u64&)CPU.FPR[frd] = 0xfff8000000000000ull | value; - if (value == 0 && ( (u64&)b & DOUBLE_SIGN )) - (u64&)CPU.FPR[frd] |= 0x100000000ull; - - if(rc) UNK("fctiwz."); - } - void FDIV(OP_REG frd, OP_REG fra, OP_REG frb, bool rc) - { - if(FPRdouble::IsINF(CPU.FPR[fra]) == 0.0 && CPU.FPR[frb] == 0.0) - { - CPU.FPSCR.VXZDZ = 1; - } - else if(FPRdouble::IsINF(CPU.FPR[fra]) && FPRdouble::IsINF(CPU.FPR[frb])) - { - CPU.FPSCR.VXIDI = 1; - } - else if(CPU.FPR[fra] != 0.0 && CPU.FPR[frb] == 0.0) - { - CPU.SetFPSCRException(FPSCR_ZX); - } - - CPU.FPR[frd] = CPU.FPR[fra] / CPU.FPR[frb]; - CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); - if(rc) UNK("fdiv.");//CPU.UpdateCR1(CPU.FPR[frd]); - } - void FSUB(OP_REG frd, OP_REG fra, OP_REG frb, bool rc) - { - CPU.FPR[frd] = CPU.FPR[fra] - CPU.FPR[frb]; - CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); - if(rc) UNK("fsub.");//CPU.UpdateCR1(CPU.FPR[frd]); - } - void FADD(OP_REG frd, OP_REG fra, OP_REG frb, bool rc) - { - CPU.FPR[frd] = CPU.FPR[fra] + CPU.FPR[frb]; - CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); - if(rc) UNK("fadd.");//CPU.UpdateCR1(CPU.FPR[frd]); - } - void FSQRT(OP_REG frd, OP_REG frb, bool rc) - { - CPU.FPR[frd] = sqrt(CPU.FPR[frb]); - CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); - if(rc) UNK("fsqrt.");//CPU.UpdateCR1(CPU.FPR[frd]); - } - void FSEL(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc) - { - CPU.FPR[frd] = CPU.FPR[fra] < 0.0 ? CPU.FPR[frc] : CPU.FPR[frb]; - if(rc) UNK("fsel.");//CPU.UpdateCR1(CPU.FPR[frd]); - } - void FMUL(OP_REG frd, OP_REG fra, OP_REG frc, bool rc) - { - CPU.FPR[frd] = CPU.FPR[fra] * CPU.FPR[frc]; + r = 0x80000000; + CPU.SetFPSCRException(FPSCR_VXCVI); CPU.FPSCR.FI = 0; CPU.FPSCR.FR = 0; - CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); - if(rc) UNK("fmul.");//CPU.UpdateCR1(CPU.FPR[frd]); } - void FRSQRTE(OP_REG frd, OP_REG frb, bool rc) + else { - UNIMPLEMENTED(); - } - void FMSUB(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc) - { - CPU.FPR[frd] = CPU.FPR[fra] * CPU.FPR[frc] - CPU.FPR[frb]; - CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); - if(rc) UNK("fmsub.");//CPU.UpdateCR1(CPU.FPR[frd]); - } - void FMADD(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc) - { - CPU.FPR[frd] = CPU.FPR[fra] * CPU.FPR[frc] + CPU.FPR[frb]; - CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); - if(rc) UNK("fmadd.");//CPU.UpdateCR1(CPU.FPR[frd]); - } - void FNMSUB(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc) - { - CPU.FPR[frd] = -(CPU.FPR[fra] * CPU.FPR[frc] - CPU.FPR[frb]); - CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); - if(rc) UNK("fnmsub.");//CPU.UpdateCR1(CPU.FPR[frd]); - } - void FNMADD(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc) - { - CPU.FPR[frd] = -(CPU.FPR[fra] * CPU.FPR[frc] + CPU.FPR[frb]); - CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); - if(rc) UNK("fnmadd.");//CPU.UpdateCR1(CPU.FPR[frd]); - } - void FCMPO(OP_REG crfd, OP_REG fra, OP_REG frb) - { - if((CPU.FPSCR.FPRF = FPRdouble::Cmp(CPU.FPR[fra], CPU.FPR[frb])) == 1) + s32 i = 0; + switch(CPU.FPSCR.RN) { - if(FPRdouble::IsSNaN(CPU.FPR[fra]) || FPRdouble::IsSNaN(CPU.FPR[frb])) + case FPSCR_RN_NEAR: { - CPU.SetFPSCRException(FPSCR_VXSNAN); - if(!CPU.FPSCR.VE) CPU.SetFPSCRException(FPSCR_VXVC); + double t = b + 0.5; + i = (s32)t; + if (t - i < 0 || (t - i == 0 && b > 0)) i--; + break; } - else if(FPRdouble::IsQNaN(CPU.FPR[fra]) || FPRdouble::IsQNaN(CPU.FPR[frb])) - { - CPU.SetFPSCRException(FPSCR_VXVC); - } - - CPU.FPSCR.FX = 1; + case FPSCR_RN_ZERO: + i = (s32)b; + break; + case FPSCR_RN_PINF: + i = (s32)b; + if (b - i > 0) i++; + break; + case FPSCR_RN_MINF: + i = (s32)b; + if (b - i < 0) i--; + break; } - - CPU.SetCR(crfd, CPU.FPSCR.FPRF); - } - void FNEG(OP_REG frd, OP_REG frb, bool rc) - { - CPU.FPR[frd] = -CPU.FPR[frb]; - if(rc) UNK("fneg.");//CPU.UpdateCR1(CPU.FPR[frd]); - } - void FMR(OP_REG frd, OP_REG frb, bool rc) - { - CPU.FPR[frd] = CPU.FPR[frb]; - if(rc) UNK("fmr.");//CPU.UpdateCR1(CPU.FPR[frd]); - } - void FNABS(OP_REG frd, OP_REG frb, bool rc) - { - (u64&)CPU.FPR[frd] = (u64&)CPU.FPR[frb] | 0x8000000000000000ULL; - if(rc) UNK("fnabs.");//CPU.UpdateCR1(CPU.FPR[frd]); - } - void FABS(OP_REG frd, OP_REG frb, bool rc) - { - CPU.FPR[frd] = fabs(CPU.FPR[frb]); - if(rc) UNK("fabs.");//CPU.UpdateCR1(CPU.FPR[frd]); - } - void FCTID(OP_REG frd, OP_REG frb, bool rc) - { - const double b = CPU.FPR[frb]; - u64 r; - if(b > (double)0x7fffffffffffffff) + r = (u32)i; + double di = i; + if (di == b) { - r = 0x7fffffffffffffff; - CPU.SetFPSCRException(FPSCR_VXCVI); - CPU.FPSCR.FI = 0; - CPU.FPSCR.FR = 0; - } - else if (b < -(double)0x8000000000000000) - { - r = 0x8000000000000000; - CPU.SetFPSCRException(FPSCR_VXCVI); - CPU.FPSCR.FI = 0; + CPU.SetFPSCR_FI(0); CPU.FPSCR.FR = 0; } else { - s64 i = 0; - switch(CPU.FPSCR.RN) - { - case FPSCR_RN_NEAR: - { - double t = b + 0.5; - i = (s64)t; - if (t - i < 0 || (t - i == 0 && b > 0)) i--; - break; - } - case FPSCR_RN_ZERO: - i = (s64)b; - break; - case FPSCR_RN_PINF: - i = (s64)b; - if (b - i > 0) i++; - break; - case FPSCR_RN_MINF: - i = (s64)b; - if (b - i < 0) i--; - break; - } - r = (u64)i; - double di = i; - if (di == b) - { - CPU.SetFPSCR_FI(0); - CPU.FPSCR.FR = 0; - } - else - { - CPU.SetFPSCR_FI(1); - CPU.FPSCR.FR = fabs(di) > fabs(b); - } + CPU.SetFPSCR_FI(1); + CPU.FPSCR.FR = fabs(di) > fabs(b); } - - (u64&)CPU.FPR[frd] = 0xfff8000000000000ull | r; - if(r == 0 && ( (u64&)b & DOUBLE_SIGN )) (u64&)CPU.FPR[frd] |= 0x100000000ull; - - if(rc) UNK("fctid."); } - void FCTIDZ(OP_REG frd, OP_REG frb, bool rc) + + (u64&)CPU.FPR[frd] = 0xfff8000000000000ull | r; + if(r == 0 && ( (u64&)b & DOUBLE_SIGN )) (u64&)CPU.FPR[frd] |= 0x100000000ull; + + if(rc) UNK("fctiw."); + } + void FCTIWZ(u32 frd, u32 frb, bool rc) + { + const double b = CPU.FPR[frb]; + u32 value; + if (b > (double)0x7fffffff) { - const double b = CPU.FPR[frb]; - u64 r; - if(b > (double)0x7fffffffffffffff) + value = 0x7fffffff; + CPU.SetFPSCRException(FPSCR_VXCVI); + CPU.FPSCR.FI = 0; + CPU.FPSCR.FR = 0; + } + else if (b < -(double)0x80000000) + { + value = 0x80000000; + CPU.SetFPSCRException(FPSCR_VXCVI); + CPU.FPSCR.FI = 0; + CPU.FPSCR.FR = 0; + } + else + { + s32 i = (s32)b; + double di = i; + if (di == b) { - r = 0x7fffffffffffffff; - CPU.SetFPSCRException(FPSCR_VXCVI); - CPU.FPSCR.FI = 0; - CPU.FPSCR.FR = 0; - } - else if (b < -(double)0x8000000000000000) - { - r = 0x8000000000000000; - CPU.SetFPSCRException(FPSCR_VXCVI); - CPU.FPSCR.FI = 0; + CPU.SetFPSCR_FI(0); CPU.FPSCR.FR = 0; } else { - s64 i = (s64)b; - double di = i; - if (di == b) - { - CPU.SetFPSCR_FI(0); - CPU.FPSCR.FR = 0; - } - else - { - CPU.SetFPSCR_FI(1); - CPU.FPSCR.FR = fabs(di) > fabs(b); - } - r = (u64)i; + CPU.SetFPSCR_FI(1); + CPU.FPSCR.FR = fabs(di) > fabs(b); + } + value = (u32)i; + } + + (u64&)CPU.FPR[frd] = 0xfff8000000000000ull | value; + if (value == 0 && ( (u64&)b & DOUBLE_SIGN )) + (u64&)CPU.FPR[frd] |= 0x100000000ull; + + if(rc) UNK("fctiwz."); + } + void FDIV(u32 frd, u32 fra, u32 frb, bool rc) + { + if(FPRdouble::IsINF(CPU.FPR[fra]) == 0.0 && CPU.FPR[frb] == 0.0) + { + CPU.FPSCR.VXZDZ = 1; + } + else if(FPRdouble::IsINF(CPU.FPR[fra]) && FPRdouble::IsINF(CPU.FPR[frb])) + { + CPU.FPSCR.VXIDI = 1; + } + else if(CPU.FPR[fra] != 0.0 && CPU.FPR[frb] == 0.0) + { + CPU.SetFPSCRException(FPSCR_ZX); + } + + CPU.FPR[frd] = CPU.FPR[fra] / CPU.FPR[frb]; + CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); + if(rc) UNK("fdiv.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FSUB(u32 frd, u32 fra, u32 frb, bool rc) + { + CPU.FPR[frd] = CPU.FPR[fra] - CPU.FPR[frb]; + CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); + if(rc) UNK("fsub.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FADD(u32 frd, u32 fra, u32 frb, bool rc) + { + CPU.FPR[frd] = CPU.FPR[fra] + CPU.FPR[frb]; + CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); + if(rc) UNK("fadd.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FSQRT(u32 frd, u32 frb, bool rc) + { + CPU.FPR[frd] = sqrt(CPU.FPR[frb]); + CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); + if(rc) UNK("fsqrt.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FSEL(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + { + CPU.FPR[frd] = CPU.FPR[fra] < 0.0 ? CPU.FPR[frc] : CPU.FPR[frb]; + if(rc) UNK("fsel.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FMUL(u32 frd, u32 fra, u32 frc, bool rc) + { + CPU.FPR[frd] = CPU.FPR[fra] * CPU.FPR[frc]; + CPU.FPSCR.FI = 0; + CPU.FPSCR.FR = 0; + CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); + if(rc) UNK("fmul.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FRSQRTE(u32 frd, u32 frb, bool rc) + { + UNIMPLEMENTED(); + } + void FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + { + CPU.FPR[frd] = CPU.FPR[fra] * CPU.FPR[frc] - CPU.FPR[frb]; + CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); + if(rc) UNK("fmsub.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + { + CPU.FPR[frd] = CPU.FPR[fra] * CPU.FPR[frc] + CPU.FPR[frb]; + CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); + if(rc) UNK("fmadd.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FNMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + { + CPU.FPR[frd] = -(CPU.FPR[fra] * CPU.FPR[frc] - CPU.FPR[frb]); + CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); + if(rc) UNK("fnmsub.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FNMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) + { + CPU.FPR[frd] = -(CPU.FPR[fra] * CPU.FPR[frc] + CPU.FPR[frb]); + CPU.FPSCR.FPRF = PPCdouble(CPU.FPR[frd]).GetType(); + if(rc) UNK("fnmadd.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FCMPO(u32 crfd, u32 fra, u32 frb) + { + if((CPU.FPSCR.FPRF = FPRdouble::Cmp(CPU.FPR[fra], CPU.FPR[frb])) == 1) + { + if(FPRdouble::IsSNaN(CPU.FPR[fra]) || FPRdouble::IsSNaN(CPU.FPR[frb])) + { + CPU.SetFPSCRException(FPSCR_VXSNAN); + if(!CPU.FPSCR.VE) CPU.SetFPSCRException(FPSCR_VXVC); + } + else if(FPRdouble::IsQNaN(CPU.FPR[fra]) || FPRdouble::IsQNaN(CPU.FPR[frb])) + { + CPU.SetFPSCRException(FPSCR_VXVC); } - (u64&)CPU.FPR[frd] = 0xfff8000000000000ull | r; - if(r == 0 && ( (u64&)b & DOUBLE_SIGN )) (u64&)CPU.FPR[frd] |= 0x100000000ull; + CPU.FPSCR.FX = 1; + } - if(rc) UNK("fctidz."); - } - void FCFID(OP_REG frd, OP_REG frb, bool rc) + CPU.SetCR(crfd, CPU.FPSCR.FPRF); + } + void FNEG(u32 frd, u32 frb, bool rc) + { + CPU.FPR[frd] = -CPU.FPR[frb]; + if(rc) UNK("fneg.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FMR(u32 frd, u32 frb, bool rc) + { + CPU.FPR[frd] = CPU.FPR[frb]; + if(rc) UNK("fmr.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FNABS(u32 frd, u32 frb, bool rc) + { + (u64&)CPU.FPR[frd] = (u64&)CPU.FPR[frb] | 0x8000000000000000ULL; + if(rc) UNK("fnabs.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FABS(u32 frd, u32 frb, bool rc) + { + CPU.FPR[frd] = fabs(CPU.FPR[frb]); + if(rc) UNK("fabs.");//CPU.UpdateCR1(CPU.FPR[frd]); + } + void FCTID(u32 frd, u32 frb, bool rc) + { + const double b = CPU.FPR[frb]; + u64 r; + if(b > (double)0x7fffffffffffffff) { - CPU.FPR[frd] = (double)(u64&)CPU.FPR[frb]; - if(rc) UNK("fcfid.");//CPU.UpdateCR1(CPU.FPR[frd]); + r = 0x7fffffffffffffff; + CPU.SetFPSCRException(FPSCR_VXCVI); + CPU.FPSCR.FI = 0; + CPU.FPSCR.FR = 0; } - END_OPCODES_GROUP(G_3f); + else if (b < -(double)0x8000000000000000) + { + r = 0x8000000000000000; + CPU.SetFPSCRException(FPSCR_VXCVI); + CPU.FPSCR.FI = 0; + CPU.FPSCR.FR = 0; + } + else + { + s64 i = 0; + switch(CPU.FPSCR.RN) + { + case FPSCR_RN_NEAR: + { + double t = b + 0.5; + i = (s64)t; + if (t - i < 0 || (t - i == 0 && b > 0)) i--; + break; + } + case FPSCR_RN_ZERO: + i = (s64)b; + break; + case FPSCR_RN_PINF: + i = (s64)b; + if (b - i > 0) i++; + break; + case FPSCR_RN_MINF: + i = (s64)b; + if (b - i < 0) i--; + break; + } + r = (u64)i; + double di = i; + if (di == b) + { + CPU.SetFPSCR_FI(0); + CPU.FPSCR.FR = 0; + } + else + { + CPU.SetFPSCR_FI(1); + CPU.FPSCR.FR = fabs(di) > fabs(b); + } + } + + (u64&)CPU.FPR[frd] = 0xfff8000000000000ull | r; + if(r == 0 && ( (u64&)b & DOUBLE_SIGN )) (u64&)CPU.FPR[frd] |= 0x100000000ull; + + if(rc) UNK("fctid."); + } + void FCTIDZ(u32 frd, u32 frb, bool rc) + { + const double b = CPU.FPR[frb]; + u64 r; + if(b > (double)0x7fffffffffffffff) + { + r = 0x7fffffffffffffff; + CPU.SetFPSCRException(FPSCR_VXCVI); + CPU.FPSCR.FI = 0; + CPU.FPSCR.FR = 0; + } + else if (b < -(double)0x8000000000000000) + { + r = 0x8000000000000000; + CPU.SetFPSCRException(FPSCR_VXCVI); + CPU.FPSCR.FI = 0; + CPU.FPSCR.FR = 0; + } + else + { + s64 i = (s64)b; + double di = i; + if (di == b) + { + CPU.SetFPSCR_FI(0); + CPU.FPSCR.FR = 0; + } + else + { + CPU.SetFPSCR_FI(1); + CPU.FPSCR.FR = fabs(di) > fabs(b); + } + r = (u64)i; + } + + (u64&)CPU.FPR[frd] = 0xfff8000000000000ull | r; + if(r == 0 && ( (u64&)b & DOUBLE_SIGN )) (u64&)CPU.FPR[frd] |= 0x100000000ull; + + if(rc) UNK("fctidz."); + } + void FCFID(u32 frd, u32 frb, bool rc) + { + CPU.FPR[frd] = (double)(u64&)CPU.FPR[frb]; + if(rc) UNK("fcfid.");//CPU.UpdateCR1(CPU.FPR[frd]); + } void UNK(const u32 code, const u32 opcode, const u32 gcode) { @@ -3677,6 +3649,3 @@ private: CPU.FPSCR.XX, CPU.FPSCR.ZX, CPU.FPSCR.UX, CPU.FPSCR.OX, CPU.FPSCR.VX, CPU.FPSCR.FEX, CPU.FPSCR.FX); } }; - -#undef START_OPCODES_GROUP -#undef END_OPCODES_GROUP \ No newline at end of file diff --git a/rpcs3/Emu/Cell/PPUOpcodes.h b/rpcs3/Emu/Cell/PPUOpcodes.h index 60fddbe261..bd25e4025a 100644 --- a/rpcs3/Emu/Cell/PPUOpcodes.h +++ b/rpcs3/Emu/Cell/PPUOpcodes.h @@ -1,13 +1,5 @@ #pragma once -#define OP_REG u32 -#define OP_sIMM s32 -#define OP_uIMM u32 -#define START_OPCODES_GROUP(x) /*x*/ -#define ADD_OPCODE(name, regs) virtual void(##name##)##regs##=0 -#define ADD_NULL_OPCODE(name) virtual void(##name##)()=0 -#define END_OPCODES_GROUP(x) /*x*/ - namespace PPU_opcodes { enum PPU_MainOpcodes @@ -447,415 +439,382 @@ public: return pc + (imm & ~0x3); } - ADD_NULL_OPCODE(NULL_OP); - ADD_NULL_OPCODE(NOP); + virtual void NULL_OP() = 0; + virtual void NOP() = 0; - ADD_OPCODE(TDI,(OP_uIMM to, OP_REG ra, OP_sIMM simm16)); - ADD_OPCODE(TWI,(OP_uIMM to, OP_REG ra, OP_sIMM simm16)); + virtual void TDI(u32 to, u32 ra, s32 simm16) = 0; + virtual void TWI(u32 to, u32 ra, s32 simm16) = 0; - START_OPCODES_GROUP(G_04) - ADD_OPCODE(MFVSCR,(OP_REG vd)); - ADD_OPCODE(MTVSCR,(OP_REG vb)); - ADD_OPCODE(VADDCUW,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VADDFP,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VADDSBS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VADDSHS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VADDSWS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VADDUBM,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VADDUBS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VADDUHM,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VADDUHS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VADDUWM,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VADDUWS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VAND,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VANDC,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VAVGSB,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VAVGSH,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VAVGSW,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VAVGUB,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VAVGUH,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VAVGUW,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCFSX,(OP_REG vd, OP_uIMM uimm5, OP_REG vb)); - ADD_OPCODE(VCFUX,(OP_REG vd, OP_uIMM uimm5, OP_REG vb)); - ADD_OPCODE(VCMPBFP,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPBFP_,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPEQFP,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPEQFP_,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPEQUB,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPEQUB_,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPEQUH,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPEQUH_,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPEQUW,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPEQUW_,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPGEFP,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPGEFP_,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPGTFP,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPGTFP_,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPGTSB,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPGTSB_,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPGTSH,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPGTSH_,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPGTSW,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPGTSW_,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPGTUB,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPGTUB_,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPGTUH,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPGTUH_,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPGTUW,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCMPGTUW_,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VCTSXS,(OP_REG vd, OP_uIMM uimm5, OP_REG vb)); - ADD_OPCODE(VCTUXS,(OP_REG vd, OP_uIMM uimm5, OP_REG vb)); - ADD_OPCODE(VEXPTEFP,(OP_REG vd, OP_REG vb)); - ADD_OPCODE(VLOGEFP,(OP_REG vd, OP_REG vb)); - ADD_OPCODE(VMADDFP,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc)); - ADD_OPCODE(VMAXFP,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMAXSB,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMAXSH,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMAXSW,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMAXUB,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMAXUH,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMAXUW,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMHADDSHS,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc)); - ADD_OPCODE(VMHRADDSHS,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc)); - ADD_OPCODE(VMINFP,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMINSB,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMINSH,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMINSW,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMINUB,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMINUH,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMINUW,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMLADDUHM,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc)); - ADD_OPCODE(VMRGHB,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMRGHH,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMRGHW,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMRGLB,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMRGLH,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMRGLW,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMSUMMBM,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc)); - ADD_OPCODE(VMSUMSHM,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc)); - ADD_OPCODE(VMSUMSHS,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc)); - ADD_OPCODE(VMSUMUBM,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc)); - ADD_OPCODE(VMSUMUHM,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc)); - ADD_OPCODE(VMSUMUHS,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc)); - ADD_OPCODE(VMULESB,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMULESH,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMULEUB,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMULEUH,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMULOSB,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMULOSH,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMULOUB,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VMULOUH,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VNMSUBFP,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc)); - ADD_OPCODE(VNOR,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VOR,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VPERM,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc)); - ADD_OPCODE(VPKPX,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VPKSHSS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VPKSHUS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VPKSWSS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VPKSWUS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VPKUHUM,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VPKUHUS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VPKUWUM,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VPKUWUS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VREFP,(OP_REG vd, OP_REG vb)); - ADD_OPCODE(VRFIM,(OP_REG vd, OP_REG vb)); - ADD_OPCODE(VRFIN,(OP_REG vd, OP_REG vb)); - ADD_OPCODE(VRFIP,(OP_REG vd, OP_REG vb)); - ADD_OPCODE(VRFIZ,(OP_REG vd, OP_REG vb)); - ADD_OPCODE(VRLB,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VRLH,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VRLW,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VRSQRTEFP,(OP_REG vd, OP_REG vb)); - ADD_OPCODE(VSEL,(OP_REG vd, OP_REG va, OP_REG vb, OP_REG vc)); - ADD_OPCODE(VSL,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSLB,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSLDOI,(OP_REG vd, OP_REG va, OP_REG vb, OP_uIMM sh)); - ADD_OPCODE(VSLH,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSLO,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSLW,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSPLTB,(OP_REG vd, OP_uIMM uimm5, OP_REG vb)); - ADD_OPCODE(VSPLTH,(OP_REG vd, OP_uIMM uimm5, OP_REG vb)); - ADD_OPCODE(VSPLTISB,(OP_REG vd, OP_sIMM simm5)); - ADD_OPCODE(VSPLTISH,(OP_REG vd, OP_sIMM simm5)); - ADD_OPCODE(VSPLTISW,(OP_REG vd, OP_sIMM simm5)); - ADD_OPCODE(VSPLTW,(OP_REG vd, OP_uIMM uimm5, OP_REG vb)); - ADD_OPCODE(VSR,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSRAB,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSRAH,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSRAW,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSRB,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSRH,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSRO,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSRW,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSUBCUW,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSUBFP,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSUBSBS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSUBSHS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSUBSWS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSUBUBM,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSUBUBS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSUBUHM,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSUBUHS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSUBUWM,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSUBUWS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSUMSWS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSUM2SWS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSUM4SBS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSUM4SHS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VSUM4UBS,(OP_REG vd, OP_REG va, OP_REG vb)); - ADD_OPCODE(VUPKHPX,(OP_REG vd, OP_REG vb)); - ADD_OPCODE(VUPKHSB,(OP_REG vd, OP_REG vb)); - ADD_OPCODE(VUPKHSH,(OP_REG vd, OP_REG vb)); - ADD_OPCODE(VUPKLPX,(OP_REG vd, OP_REG vb)); - ADD_OPCODE(VUPKLSB,(OP_REG vd, OP_REG vb)); - ADD_OPCODE(VUPKLSH,(OP_REG vd, OP_REG vb)); - ADD_OPCODE(VXOR,(OP_REG vd, OP_REG va, OP_REG vb)); - END_OPCODES_GROUP(G_04); + virtual void MFVSCR(u32 vd) = 0; + virtual void MTVSCR(u32 vb) = 0; + virtual void VADDCUW(u32 vd, u32 va, u32 vb) = 0; + virtual void VADDFP(u32 vd, u32 va, u32 vb) = 0; + virtual void VADDSBS(u32 vd, u32 va, u32 vb) = 0; + virtual void VADDSHS(u32 vd, u32 va, u32 vb) = 0; + virtual void VADDSWS(u32 vd, u32 va, u32 vb) = 0; + virtual void VADDUBM(u32 vd, u32 va, u32 vb) = 0; + virtual void VADDUBS(u32 vd, u32 va, u32 vb) = 0; + virtual void VADDUHM(u32 vd, u32 va, u32 vb) = 0; + virtual void VADDUHS(u32 vd, u32 va, u32 vb) = 0; + virtual void VADDUWM(u32 vd, u32 va, u32 vb) = 0; + virtual void VADDUWS(u32 vd, u32 va, u32 vb) = 0; + virtual void VAND(u32 vd, u32 va, u32 vb) = 0; + virtual void VANDC(u32 vd, u32 va, u32 vb) = 0; + virtual void VAVGSB(u32 vd, u32 va, u32 vb) = 0; + virtual void VAVGSH(u32 vd, u32 va, u32 vb) = 0; + virtual void VAVGSW(u32 vd, u32 va, u32 vb) = 0; + virtual void VAVGUB(u32 vd, u32 va, u32 vb) = 0; + virtual void VAVGUH(u32 vd, u32 va, u32 vb) = 0; + virtual void VAVGUW(u32 vd, u32 va, u32 vb) = 0; + virtual void VCFSX(u32 vd, u32 uimm5, u32 vb) = 0; + virtual void VCFUX(u32 vd, u32 uimm5, u32 vb) = 0; + virtual void VCMPBFP(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPBFP_(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPEQFP(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPEQFP_(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPEQUB(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPEQUB_(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPEQUH(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPEQUH_(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPEQUW(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPEQUW_(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPGEFP(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPGEFP_(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPGTFP(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPGTFP_(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPGTSB(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPGTSB_(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPGTSH(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPGTSH_(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPGTSW(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPGTSW_(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPGTUB(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPGTUB_(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPGTUH(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPGTUH_(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPGTUW(u32 vd, u32 va, u32 vb) = 0; + virtual void VCMPGTUW_(u32 vd, u32 va, u32 vb) = 0; + virtual void VCTSXS(u32 vd, u32 uimm5, u32 vb) = 0; + virtual void VCTUXS(u32 vd, u32 uimm5, u32 vb) = 0; + virtual void VEXPTEFP(u32 vd, u32 vb) = 0; + virtual void VLOGEFP(u32 vd, u32 vb) = 0; + virtual void VMADDFP(u32 vd, u32 va, u32 vb, u32 vc) = 0; + virtual void VMAXFP(u32 vd, u32 va, u32 vb) = 0; + virtual void VMAXSB(u32 vd, u32 va, u32 vb) = 0; + virtual void VMAXSH(u32 vd, u32 va, u32 vb) = 0; + virtual void VMAXSW(u32 vd, u32 va, u32 vb) = 0; + virtual void VMAXUB(u32 vd, u32 va, u32 vb) = 0; + virtual void VMAXUH(u32 vd, u32 va, u32 vb) = 0; + virtual void VMAXUW(u32 vd, u32 va, u32 vb) = 0; + virtual void VMHADDSHS(u32 vd, u32 va, u32 vb, u32 vc) = 0; + virtual void VMHRADDSHS(u32 vd, u32 va, u32 vb, u32 vc) = 0; + virtual void VMINFP(u32 vd, u32 va, u32 vb) = 0; + virtual void VMINSB(u32 vd, u32 va, u32 vb) = 0; + virtual void VMINSH(u32 vd, u32 va, u32 vb) = 0; + virtual void VMINSW(u32 vd, u32 va, u32 vb) = 0; + virtual void VMINUB(u32 vd, u32 va, u32 vb) = 0; + virtual void VMINUH(u32 vd, u32 va, u32 vb) = 0; + virtual void VMINUW(u32 vd, u32 va, u32 vb) = 0; + virtual void VMLADDUHM(u32 vd, u32 va, u32 vb, u32 vc) = 0; + virtual void VMRGHB(u32 vd, u32 va, u32 vb) = 0; + virtual void VMRGHH(u32 vd, u32 va, u32 vb) = 0; + virtual void VMRGHW(u32 vd, u32 va, u32 vb) = 0; + virtual void VMRGLB(u32 vd, u32 va, u32 vb) = 0; + virtual void VMRGLH(u32 vd, u32 va, u32 vb) = 0; + virtual void VMRGLW(u32 vd, u32 va, u32 vb) = 0; + virtual void VMSUMMBM(u32 vd, u32 va, u32 vb, u32 vc) = 0; + virtual void VMSUMSHM(u32 vd, u32 va, u32 vb, u32 vc) = 0; + virtual void VMSUMSHS(u32 vd, u32 va, u32 vb, u32 vc) = 0; + virtual void VMSUMUBM(u32 vd, u32 va, u32 vb, u32 vc) = 0; + virtual void VMSUMUHM(u32 vd, u32 va, u32 vb, u32 vc) = 0; + virtual void VMSUMUHS(u32 vd, u32 va, u32 vb, u32 vc) = 0; + virtual void VMULESB(u32 vd, u32 va, u32 vb) = 0; + virtual void VMULESH(u32 vd, u32 va, u32 vb) = 0; + virtual void VMULEUB(u32 vd, u32 va, u32 vb) = 0; + virtual void VMULEUH(u32 vd, u32 va, u32 vb) = 0; + virtual void VMULOSB(u32 vd, u32 va, u32 vb) = 0; + virtual void VMULOSH(u32 vd, u32 va, u32 vb) = 0; + virtual void VMULOUB(u32 vd, u32 va, u32 vb) = 0; + virtual void VMULOUH(u32 vd, u32 va, u32 vb) = 0; + virtual void VNMSUBFP(u32 vd, u32 va, u32 vb, u32 vc) = 0; + virtual void VNOR(u32 vd, u32 va, u32 vb) = 0; + virtual void VOR(u32 vd, u32 va, u32 vb) = 0; + virtual void VPERM(u32 vd, u32 va, u32 vb, u32 vc) = 0; + virtual void VPKPX(u32 vd, u32 va, u32 vb) = 0; + virtual void VPKSHSS(u32 vd, u32 va, u32 vb) = 0; + virtual void VPKSHUS(u32 vd, u32 va, u32 vb) = 0; + virtual void VPKSWSS(u32 vd, u32 va, u32 vb) = 0; + virtual void VPKSWUS(u32 vd, u32 va, u32 vb) = 0; + virtual void VPKUHUM(u32 vd, u32 va, u32 vb) = 0; + virtual void VPKUHUS(u32 vd, u32 va, u32 vb) = 0; + virtual void VPKUWUM(u32 vd, u32 va, u32 vb) = 0; + virtual void VPKUWUS(u32 vd, u32 va, u32 vb) = 0; + virtual void VREFP(u32 vd, u32 vb) = 0; + virtual void VRFIM(u32 vd, u32 vb) = 0; + virtual void VRFIN(u32 vd, u32 vb) = 0; + virtual void VRFIP(u32 vd, u32 vb) = 0; + virtual void VRFIZ(u32 vd, u32 vb) = 0; + virtual void VRLB(u32 vd, u32 va, u32 vb) = 0; + virtual void VRLH(u32 vd, u32 va, u32 vb) = 0; + virtual void VRLW(u32 vd, u32 va, u32 vb) = 0; + virtual void VRSQRTEFP(u32 vd, u32 vb) = 0; + virtual void VSEL(u32 vd, u32 va, u32 vb, u32 vc) = 0; + virtual void VSL(u32 vd, u32 va, u32 vb) = 0; + virtual void VSLB(u32 vd, u32 va, u32 vb) = 0; + virtual void VSLDOI(u32 vd, u32 va, u32 vb, u32 sh) = 0; + virtual void VSLH(u32 vd, u32 va, u32 vb) = 0; + virtual void VSLO(u32 vd, u32 va, u32 vb) = 0; + virtual void VSLW(u32 vd, u32 va, u32 vb) = 0; + virtual void VSPLTB(u32 vd, u32 uimm5, u32 vb) = 0; + virtual void VSPLTH(u32 vd, u32 uimm5, u32 vb) = 0; + virtual void VSPLTISB(u32 vd, s32 simm5) = 0; + virtual void VSPLTISH(u32 vd, s32 simm5) = 0; + virtual void VSPLTISW(u32 vd, s32 simm5) = 0; + virtual void VSPLTW(u32 vd, u32 uimm5, u32 vb) = 0; + virtual void VSR(u32 vd, u32 va, u32 vb) = 0; + virtual void VSRAB(u32 vd, u32 va, u32 vb) = 0; + virtual void VSRAH(u32 vd, u32 va, u32 vb) = 0; + virtual void VSRAW(u32 vd, u32 va, u32 vb) = 0; + virtual void VSRB(u32 vd, u32 va, u32 vb) = 0; + virtual void VSRH(u32 vd, u32 va, u32 vb) = 0; + virtual void VSRO(u32 vd, u32 va, u32 vb) = 0; + virtual void VSRW(u32 vd, u32 va, u32 vb) = 0; + virtual void VSUBCUW(u32 vd, u32 va, u32 vb) = 0; + virtual void VSUBFP(u32 vd, u32 va, u32 vb) = 0; + virtual void VSUBSBS(u32 vd, u32 va, u32 vb) = 0; + virtual void VSUBSHS(u32 vd, u32 va, u32 vb) = 0; + virtual void VSUBSWS(u32 vd, u32 va, u32 vb) = 0; + virtual void VSUBUBM(u32 vd, u32 va, u32 vb) = 0; + virtual void VSUBUBS(u32 vd, u32 va, u32 vb) = 0; + virtual void VSUBUHM(u32 vd, u32 va, u32 vb) = 0; + virtual void VSUBUHS(u32 vd, u32 va, u32 vb) = 0; + virtual void VSUBUWM(u32 vd, u32 va, u32 vb) = 0; + virtual void VSUBUWS(u32 vd, u32 va, u32 vb) = 0; + virtual void VSUMSWS(u32 vd, u32 va, u32 vb) = 0; + virtual void VSUM2SWS(u32 vd, u32 va, u32 vb) = 0; + virtual void VSUM4SBS(u32 vd, u32 va, u32 vb) = 0; + virtual void VSUM4SHS(u32 vd, u32 va, u32 vb) = 0; + virtual void VSUM4UBS(u32 vd, u32 va, u32 vb) = 0; + virtual void VUPKHPX(u32 vd, u32 vb) = 0; + virtual void VUPKHSB(u32 vd, u32 vb) = 0; + virtual void VUPKHSH(u32 vd, u32 vb) = 0; + virtual void VUPKLPX(u32 vd, u32 vb) = 0; + virtual void VUPKLSB(u32 vd, u32 vb) = 0; + virtual void VUPKLSH(u32 vd, u32 vb) = 0; + virtual void VXOR(u32 vd, u32 va, u32 vb) = 0; + virtual void MULLI(u32 rd, u32 ra, s32 simm16) = 0; + virtual void SUBFIC(u32 rd, u32 ra, s32 simm16) = 0; + virtual void CMPLI(u32 bf, u32 l, u32 ra, u32 uimm16) = 0; + virtual void CMPI(u32 bf, u32 l, u32 ra, s32 simm16) = 0; + virtual void ADDIC(u32 rd, u32 ra, s32 simm16) = 0; + virtual void ADDIC_(u32 rd, u32 ra, s32 simm16) = 0; + virtual void ADDI(u32 rd, u32 ra, s32 simm16) = 0; + virtual void ADDIS(u32 rd, u32 ra, s32 simm16) = 0; + virtual void BC(u32 bo, u32 bi, s32 bd, u32 aa, u32 lk) = 0; + virtual void SC(s32 sc_code) = 0; + virtual void B(s32 ll, u32 aa, u32 lk) = 0; + virtual void MCRF(u32 crfd, u32 crfs) = 0; + virtual void BCLR(u32 bo, u32 bi, u32 bh, u32 lk) = 0; + virtual void CRNOR(u32 bt, u32 ba, u32 bb) = 0; + virtual void CRANDC(u32 bt, u32 ba, u32 bb) = 0; + virtual void ISYNC() = 0; + virtual void CRXOR(u32 bt, u32 ba, u32 bb) = 0; + virtual void CRNAND(u32 bt, u32 ba, u32 bb) = 0; + virtual void CRAND(u32 bt, u32 ba, u32 bb) = 0; + virtual void CREQV(u32 bt, u32 ba, u32 bb) = 0; + virtual void CRORC(u32 bt, u32 ba, u32 bb) = 0; + virtual void CROR(u32 bt, u32 ba, u32 bb) = 0; + virtual void BCCTR(u32 bo, u32 bi, u32 bh, u32 lk) = 0; + virtual void RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) = 0; + virtual void RLWINM(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) = 0; + virtual void RLWNM(u32 ra, u32 rs, u32 rb, u32 MB, u32 ME, bool rc) = 0; + virtual void ORI(u32 rs, u32 ra, u32 uimm16) = 0; + virtual void ORIS(u32 rs, u32 ra, u32 uimm16) = 0; + virtual void XORI(u32 ra, u32 rs, u32 uimm16) = 0; + virtual void XORIS(u32 ra, u32 rs, u32 uimm16) = 0; + virtual void ANDI_(u32 ra, u32 rs, u32 uimm16) = 0; + virtual void ANDIS_(u32 ra, u32 rs, u32 uimm16) = 0; + virtual void RLDICL(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) = 0; + virtual void RLDICR(u32 ra, u32 rs, u32 sh, u32 me, bool rc) = 0; + virtual void RLDIC(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) = 0; + virtual void RLDIMI(u32 ra, u32 rs, u32 sh, u32 mb, bool rc) = 0; + virtual void CMP(u32 crfd, u32 l, u32 ra, u32 rb) = 0; + virtual void TW(u32 to, u32 ra, u32 rb) = 0; + virtual void LVSL(u32 vd, u32 ra, u32 rb) = 0; + virtual void LVEBX(u32 vd, u32 ra, u32 rb) = 0; + virtual void SUBFC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; + virtual void MULHDU(u32 rd, u32 ra, u32 rb, bool rc) = 0; + virtual void ADDC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; + virtual void MULHWU(u32 rd, u32 ra, u32 rb, bool rc) = 0; + virtual void MFOCRF(u32 a, u32 rd, u32 crm) = 0; + virtual void LWARX(u32 rd, u32 ra, u32 rb) = 0; + virtual void LDX(u32 ra, u32 rs, u32 rb) = 0; + virtual void LWZX(u32 rd, u32 ra, u32 rb) = 0; + virtual void SLW(u32 ra, u32 rs, u32 rb, bool rc) = 0; + virtual void CNTLZW(u32 ra, u32 rs, bool rc) = 0; + virtual void SLD(u32 ra, u32 rs, u32 rb, bool rc) = 0; + virtual void AND(u32 ra, u32 rs, u32 rb, bool rc) = 0; + virtual void CMPL(u32 bf, u32 l, u32 ra, u32 rb) = 0; + virtual void LVSR(u32 vd, u32 ra, u32 rb) = 0; + virtual void LVEHX(u32 vd, u32 ra, u32 rb) = 0; + virtual void SUBF(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; + virtual void LDUX(u32 rd, u32 ra, u32 rb) = 0; + virtual void DCBST(u32 ra, u32 rb) = 0; + virtual void CNTLZD(u32 ra, u32 rs, bool rc) = 0; + virtual void ANDC(u32 ra, u32 rs, u32 rb, bool rc) = 0; + virtual void LVEWX(u32 vd, u32 ra, u32 rb) = 0; + virtual void MULHD(u32 rd, u32 ra, u32 rb, bool rc) = 0; + virtual void MULHW(u32 rd, u32 ra, u32 rb, bool rc) = 0; + virtual void LDARX(u32 rd, u32 ra, u32 rb) = 0; + virtual void DCBF(u32 ra, u32 rb) = 0; + virtual void LBZX(u32 rd, u32 ra, u32 rb) = 0; + virtual void LVX(u32 vd, u32 ra, u32 rb) = 0; + virtual void NEG(u32 rd, u32 ra, u32 oe, bool rc) = 0; + virtual void LBZUX(u32 rd, u32 ra, u32 rb) = 0; + virtual void NOR(u32 ra, u32 rs, u32 rb, bool rc) = 0; + virtual void STVEBX(u32 vs, u32 ra, u32 rb) = 0; + virtual void SUBFE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; + virtual void ADDE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; + virtual void MTOCRF(u32 crm, u32 rs) = 0; + virtual void STDX(u32 rs, u32 ra, u32 rb) = 0; + virtual void STWCX_(u32 rs, u32 ra, u32 rb) = 0; + virtual void STWX(u32 rs, u32 ra, u32 rb) = 0; + virtual void STVEHX(u32 vs, u32 ra, u32 rb) = 0; + virtual void STDUX(u32 rs, u32 ra, u32 rb) = 0; + virtual void STVEWX(u32 vs, u32 ra, u32 rb) = 0; + virtual void ADDZE(u32 rd, u32 ra, u32 oe, bool rc) = 0; + virtual void STDCX_(u32 rs, u32 ra, u32 rb) = 0; + virtual void STBX(u32 rs, u32 ra, u32 rb) = 0; + virtual void STVX(u32 vs, u32 ra, u32 rb) = 0; + virtual void MULLD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; + virtual void ADDME(u32 rd, u32 ra, u32 oe, bool rc) = 0; + virtual void MULLW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; + virtual void DCBTST(u32 th, u32 ra, u32 rb) = 0; + virtual void ADD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; + virtual void DCBT(u32 ra, u32 rb, u32 th) = 0; + virtual void LHZX(u32 rd, u32 ra, u32 rb) = 0; + virtual void EQV(u32 ra, u32 rs, u32 rb, bool rc) = 0; + virtual void ECIWX(u32 rd, u32 ra, u32 rb) = 0; + virtual void LHZUX(u32 rd, u32 ra, u32 rb) = 0; + virtual void XOR(u32 rs, u32 ra, u32 rb, bool rc) = 0; + virtual void MFSPR(u32 rd, u32 spr) = 0; + virtual void DST(u32 ra, u32 rb, u32 strm, u32 t) = 0; + virtual void LHAX(u32 rd, u32 ra, u32 rb) = 0; + virtual void LVXL(u32 vd, u32 ra, u32 rb) = 0; + virtual void ABS(u32 rd, u32 ra, u32 oe, bool rc) = 0; + virtual void MFTB(u32 rd, u32 spr) = 0; + virtual void DSTST(u32 ra, u32 rb, u32 strm, u32 t) = 0; + virtual void LHAUX(u32 rd, u32 ra, u32 rb) = 0; + virtual void STHX(u32 rs, u32 ra, u32 rb) = 0; + virtual void ORC(u32 rs, u32 ra, u32 rb, bool rc) = 0; + virtual void ECOWX(u32 rs, u32 ra, u32 rb) = 0; + virtual void OR(u32 ra, u32 rs, u32 rb, bool rc) = 0; + virtual void DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; + virtual void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; + virtual void MTSPR(u32 spr, u32 rs) = 0; + //DCBI + virtual void NAND(u32 ra, u32 rs, u32 rb, bool rc) = 0; + virtual void STVXL(u32 vs, u32 ra, u32 rb) = 0; + virtual void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; + virtual void DIVW(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; + virtual void LVLX(u32 vd, u32 ra, u32 rb) = 0; + virtual void LWBRX(u32 rd, u32 ra, u32 rb) = 0; + virtual void LFSX(u32 frd, u32 ra, u32 rb) = 0; + virtual void SRW(u32 ra, u32 rs, u32 rb, bool rc) = 0; + virtual void SRD(u32 ra, u32 rs, u32 rb, bool rc) = 0; + virtual void LVRX(u32 vd, u32 ra, u32 rb) = 0; + virtual void LFSUX(u32 frd, u32 ra, u32 rb) = 0; + virtual void SYNC(u32 l) = 0; + virtual void LFDX(u32 frd, u32 ra, u32 rb) = 0; + virtual void LFDUX(u32 frd, u32 ra, u32 rb) = 0; + virtual void STVLX(u32 vs, u32 ra, u32 rb) = 0; + virtual void STFSX(u32 frs, u32 ra, u32 rb) = 0; + virtual void STVRX(u32 vs, u32 ra, u32 rb) = 0; + virtual void STFDX(u32 frs, u32 ra, u32 rb) = 0; + virtual void LVLXL(u32 vd, u32 ra, u32 rb) = 0; + virtual void LHBRX(u32 rd, u32 ra, u32 rb) = 0; + virtual void SRAW(u32 ra, u32 rs, u32 rb, bool rc) = 0; + virtual void SRAD(u32 ra, u32 rs, u32 rb, bool rc) = 0; + virtual void LVRXL(u32 vd, u32 ra, u32 rb) = 0; + virtual void DSS(u32 strm, u32 a) = 0; + virtual void SRAWI(u32 ra, u32 rs, u32 sh, bool rc) = 0; + virtual void SRADI1(u32 ra, u32 rs, u32 sh, bool rc) = 0; + virtual void SRADI2(u32 ra, u32 rs, u32 sh, bool rc) = 0; + virtual void EIEIO() = 0; + virtual void STVLXL(u32 sd, u32 ra, u32 rb) = 0; + virtual void EXTSH(u32 ra, u32 rs, bool rc) = 0; + virtual void STVRXL(u32 sd, u32 ra, u32 rb) = 0; + virtual void EXTSB(u32 ra, u32 rs, bool rc) = 0; + virtual void STFIWX(u32 frs, u32 ra, u32 rb) = 0; + virtual void EXTSW(u32 ra, u32 rs, bool rc) = 0; + //ICBI + virtual void DCBZ(u32 ra, u32 rb) = 0; + virtual void LWZ(u32 rd, u32 ra, s32 d) = 0; + virtual void LWZU(u32 rd, u32 ra, s32 d) = 0; + virtual void LBZ(u32 rd, u32 ra, s32 d) = 0; + virtual void LBZU(u32 rd, u32 ra, s32 d) = 0; + virtual void STW(u32 rs, u32 ra, s32 d) = 0; + virtual void STWU(u32 rs, u32 ra, s32 d) = 0; + virtual void STB(u32 rs, u32 ra, s32 d) = 0; + virtual void STBU(u32 rs, u32 ra, s32 d) = 0; + virtual void LHZ(u32 rd, u32 ra, s32 d) = 0; + virtual void LHZU(u32 rd, u32 ra, s32 d) = 0; + virtual void STH(u32 rs, u32 ra, s32 d) = 0; + virtual void STHU(u32 rs, u32 ra, s32 d) = 0; + virtual void LMW(u32 rd, u32 ra, s32 d) = 0; + virtual void STMW(u32 rs, u32 ra, s32 d) = 0; + virtual void LFS(u32 frd, u32 ra, s32 d) = 0; + virtual void LFSU(u32 frd, u32 ra, s32 d) = 0; + virtual void LFD(u32 frd, u32 ra, s32 d) = 0; + virtual void LFDU(u32 frd, u32 ra, s32 d) = 0; + virtual void STFS(u32 frs, u32 ra, s32 d) = 0; + virtual void STFSU(u32 frs, u32 ra, s32 d) = 0; + virtual void STFD(u32 frs, u32 ra, s32 d) = 0; + virtual void STFDU(u32 frs, u32 ra, s32 d) = 0; + virtual void LD(u32 rd, u32 ra, s32 ds) = 0; + virtual void LDU(u32 rd, u32 ra, s32 ds) = 0; + virtual void FDIVS(u32 frd, u32 fra, u32 frb, bool rc) = 0; + virtual void FSUBS(u32 frd, u32 fra, u32 frb, bool rc) = 0; + virtual void FADDS(u32 frd, u32 fra, u32 frb, bool rc) = 0; + virtual void FSQRTS(u32 frd, u32 frb, bool rc) = 0; + virtual void FRES(u32 frd, u32 frb, bool rc) = 0; + virtual void FMULS(u32 frd, u32 fra, u32 frc, bool rc) = 0; + virtual void FMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0; + virtual void FMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0; + virtual void FNMSUBS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0; + virtual void FNMADDS(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0; + virtual void STD(u32 rs, u32 ra, s32 ds) = 0; + virtual void STDU(u32 rs, u32 ra, s32 ds) = 0; + virtual void MTFSB1(u32 bt, bool rc) = 0; + virtual void MCRFS(u32 bf, u32 bfa) = 0; + virtual void MTFSB0(u32 bt, bool rc) = 0; + virtual void MTFSFI(u32 crfd, u32 i, bool rc) = 0; + virtual void MFFS(u32 frd, bool rc) = 0; + virtual void MTFSF(u32 flm, u32 frb, bool rc) = 0; - ADD_OPCODE(MULLI,(OP_REG rd, OP_REG ra, OP_sIMM simm16)); - ADD_OPCODE(SUBFIC,(OP_REG rd, OP_REG ra, OP_sIMM simm16)); - ADD_OPCODE(CMPLI,(OP_REG bf, OP_REG l, OP_REG ra, OP_uIMM uimm16)); - ADD_OPCODE(CMPI,(OP_REG bf, OP_REG l, OP_REG ra, OP_sIMM simm16)); - ADD_OPCODE(ADDIC,(OP_REG rd, OP_REG ra, OP_sIMM simm16)); - ADD_OPCODE(ADDIC_,(OP_REG rd, OP_REG ra, OP_sIMM simm16)); - ADD_OPCODE(ADDI,(OP_REG rd, OP_REG ra, OP_sIMM simm16)); - ADD_OPCODE(ADDIS,(OP_REG rd, OP_REG ra, OP_sIMM simm16)); - ADD_OPCODE(BC,(OP_REG bo, OP_REG bi, OP_sIMM bd, OP_REG aa, OP_REG lk)); - ADD_OPCODE(SC,(OP_sIMM sc_code)); - ADD_OPCODE(B,(OP_sIMM ll, OP_REG aa, OP_REG lk)); - - START_OPCODES_GROUP(G_13) - ADD_OPCODE(MCRF,(OP_REG crfd, OP_REG crfs)); - ADD_OPCODE(BCLR,(OP_REG bo, OP_REG bi, OP_REG bh, OP_REG lk)); - ADD_OPCODE(CRNOR,(OP_REG bt, OP_REG ba, OP_REG bb)); - ADD_OPCODE(CRANDC,(OP_REG bt, OP_REG ba, OP_REG bb)); - ADD_OPCODE(ISYNC,()); - ADD_OPCODE(CRXOR,(OP_REG bt, OP_REG ba, OP_REG bb)); - ADD_OPCODE(CRNAND,(OP_REG bt, OP_REG ba, OP_REG bb)); - ADD_OPCODE(CRAND,(OP_REG bt, OP_REG ba, OP_REG bb)); - ADD_OPCODE(CREQV,(OP_REG bt, OP_REG ba, OP_REG bb)); - ADD_OPCODE(CRORC,(OP_REG bt, OP_REG ba, OP_REG bb)); - ADD_OPCODE(CROR,(OP_REG bt, OP_REG ba, OP_REG bb)); - ADD_OPCODE(BCCTR,(OP_REG bo, OP_REG bi, OP_REG bh, OP_REG lk)); - END_OPCODES_GROUP(G_13); - - ADD_OPCODE(RLWIMI,(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, OP_REG me, bool rc)); - ADD_OPCODE(RLWINM,(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, OP_REG me, bool rc)); - ADD_OPCODE(RLWNM,(OP_REG ra, OP_REG rs, OP_REG rb, OP_REG MB, OP_REG ME, bool rc)); - ADD_OPCODE(ORI,(OP_REG rs, OP_REG ra, OP_uIMM uimm16)); - ADD_OPCODE(ORIS,(OP_REG rs, OP_REG ra, OP_uIMM uimm16)); - ADD_OPCODE(XORI,(OP_REG ra, OP_REG rs, OP_uIMM uimm16)); - ADD_OPCODE(XORIS,(OP_REG ra, OP_REG rs, OP_uIMM uimm16)); - ADD_OPCODE(ANDI_,(OP_REG ra, OP_REG rs, OP_uIMM uimm16)); - ADD_OPCODE(ANDIS_,(OP_REG ra, OP_REG rs, OP_uIMM uimm16)); + virtual void FCMPU(u32 bf, u32 fra, u32 frb) = 0; + virtual void FRSP(u32 frd, u32 frb, bool rc) = 0; + virtual void FCTIW(u32 frd, u32 frb, bool rc) = 0; + virtual void FCTIWZ(u32 frd, u32 frb, bool rc) = 0; + virtual void FDIV(u32 frd, u32 fra, u32 frb, bool rc) = 0; + virtual void FSUB(u32 frd, u32 fra, u32 frb, bool rc) = 0; + virtual void FADD(u32 frd, u32 fra, u32 frb, bool rc) = 0; + virtual void FSQRT(u32 frd, u32 frb, bool rc) = 0; + virtual void FSEL(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0; + virtual void FMUL(u32 frd, u32 fra, u32 frc, bool rc) = 0; + virtual void FRSQRTE(u32 frd, u32 frb, bool rc) = 0; + virtual void FMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0; + virtual void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0; + virtual void FNMSUB(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0; + virtual void FNMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) = 0; + virtual void FCMPO(u32 crfd, u32 fra, u32 frb) = 0; + virtual void FNEG(u32 frd, u32 frb, bool rc) = 0; + virtual void FMR(u32 frd, u32 frb, bool rc) = 0; + virtual void FNABS(u32 frd, u32 frb, bool rc) = 0; + virtual void FABS(u32 frd, u32 frb, bool rc) = 0; + virtual void FCTID(u32 frd, u32 frb, bool rc) = 0; + virtual void FCTIDZ(u32 frd, u32 frb, bool rc) = 0; + virtual void FCFID(u32 frd, u32 frb, bool rc) = 0; - START_OPCODES_GROUP(G_1e) - ADD_OPCODE(RLDICL,(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, bool rc)); - ADD_OPCODE(RLDICR,(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG me, bool rc)); - ADD_OPCODE(RLDIC,(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, bool rc)); - ADD_OPCODE(RLDIMI,(OP_REG ra, OP_REG rs, OP_REG sh, OP_REG mb, bool rc)); - END_OPCODES_GROUP(G_1e); - - START_OPCODES_GROUP(G_1f) - /*0x000*/ADD_OPCODE(CMP,(OP_REG crfd, OP_REG l, OP_REG ra, OP_REG rb)); - /*0x004*/ADD_OPCODE(TW,(OP_uIMM to, OP_REG ra, OP_REG rb)); - /*0x006*/ADD_OPCODE(LVSL,(OP_REG vd, OP_REG ra, OP_REG rb)); - /*0x007*/ADD_OPCODE(LVEBX,(OP_REG vd, OP_REG ra, OP_REG rb)); - /*0x008*/ADD_OPCODE(SUBFC,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc)); - /*0x009*/ADD_OPCODE(MULHDU,(OP_REG rd, OP_REG ra, OP_REG rb, bool rc)); - /*0x00a*/ADD_OPCODE(ADDC,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc)); - /*0x00b*/ADD_OPCODE(MULHWU,(OP_REG rd, OP_REG ra, OP_REG rb, bool rc)); - /*0x013*/ADD_OPCODE(MFOCRF,(OP_uIMM a, OP_REG rd, OP_uIMM crm)); - /*0x014*/ADD_OPCODE(LWARX,(OP_REG rd, OP_REG ra, OP_REG rb)); - /*0x015*/ADD_OPCODE(LDX,(OP_REG ra, OP_REG rs, OP_REG rb)); - /*0x017*/ADD_OPCODE(LWZX,(OP_REG rd, OP_REG ra, OP_REG rb)); - /*0x018*/ADD_OPCODE(SLW,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc)); - /*0x01a*/ADD_OPCODE(CNTLZW,(OP_REG ra, OP_REG rs, bool rc)); - /*0x01b*/ADD_OPCODE(SLD,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc)); - /*0x01c*/ADD_OPCODE(AND,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc)); - /*0x020*/ADD_OPCODE(CMPL,(OP_REG bf, OP_REG l, OP_REG ra, OP_REG rb)); - /*0x026*/ADD_OPCODE(LVSR,(OP_REG vd, OP_REG ra, OP_REG rb)); - /*0x027*/ADD_OPCODE(LVEHX,(OP_REG vd, OP_REG ra, OP_REG rb)); - /*0x028*/ADD_OPCODE(SUBF,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc)); - /*0x035*/ADD_OPCODE(LDUX,(OP_REG rd, OP_REG ra, OP_REG rb)); - /*0x036*/ADD_OPCODE(DCBST,(OP_REG ra, OP_REG rb)); - /*0x03a*/ADD_OPCODE(CNTLZD,(OP_REG ra, OP_REG rs, bool rc)); - /*0x03c*/ADD_OPCODE(ANDC,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc)); - /*0x047*/ADD_OPCODE(LVEWX,(OP_REG vd, OP_REG ra, OP_REG rb)); - /*0x049*/ADD_OPCODE(MULHD,(OP_REG rd, OP_REG ra, OP_REG rb, bool rc)); - /*0x04b*/ADD_OPCODE(MULHW,(OP_REG rd, OP_REG ra, OP_REG rb, bool rc)); - /*0x054*/ADD_OPCODE(LDARX,(OP_REG rd, OP_REG ra, OP_REG rb)); - /*0x056*/ADD_OPCODE(DCBF,(OP_REG ra, OP_REG rb)); - /*0x057*/ADD_OPCODE(LBZX,(OP_REG rd, OP_REG ra, OP_REG rb)); - /*0x067*/ADD_OPCODE(LVX,(OP_REG vd, OP_REG ra, OP_REG rb)); - /*0x068*/ADD_OPCODE(NEG,(OP_REG rd, OP_REG ra, OP_REG oe, bool rc)); - /*0x077*/ADD_OPCODE(LBZUX,(OP_REG rd, OP_REG ra, OP_REG rb)); - /*0x07c*/ADD_OPCODE(NOR,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc)); - /*0x087*/ADD_OPCODE(STVEBX,(OP_REG vs, OP_REG ra, OP_REG rb)); - /*0x088*/ADD_OPCODE(SUBFE,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc)); - /*0x08a*/ADD_OPCODE(ADDE,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc)); - /*0x090*/ADD_OPCODE(MTOCRF,(OP_REG crm, OP_REG rs)); - /*0x095*/ADD_OPCODE(STDX,(OP_REG rs, OP_REG ra, OP_REG rb)); - /*0x096*/ADD_OPCODE(STWCX_,(OP_REG rs, OP_REG ra, OP_REG rb)); - /*0x097*/ADD_OPCODE(STWX,(OP_REG rs, OP_REG ra, OP_REG rb)); - /*0x0a7*/ADD_OPCODE(STVEHX,(OP_REG vs, OP_REG ra, OP_REG rb)); - /*0x0b5*/ADD_OPCODE(STDUX,(OP_REG rs, OP_REG ra, OP_REG rb)); - /*0x0c7*/ADD_OPCODE(STVEWX,(OP_REG vs, OP_REG ra, OP_REG rb)); - /*0x0ca*/ADD_OPCODE(ADDZE,(OP_REG rd, OP_REG ra, OP_REG oe, bool rc)); - /*0x0d6*/ADD_OPCODE(STDCX_,(OP_REG rs, OP_REG ra, OP_REG rb)); - /*0x0d7*/ADD_OPCODE(STBX,(OP_REG rs, OP_REG ra, OP_REG rb)); - /*0x0e7*/ADD_OPCODE(STVX,(OP_REG vs, OP_REG ra, OP_REG rb)); - /*0x0e9*/ADD_OPCODE(MULLD,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc)); - /*0x0ea*/ADD_OPCODE(ADDME,(OP_REG rd, OP_REG ra, OP_REG oe, bool rc)); - /*0x0eb*/ADD_OPCODE(MULLW,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc)); - /*0x0f6*/ADD_OPCODE(DCBTST,(OP_REG th, OP_REG ra, OP_REG rb)); - /*0x10a*/ADD_OPCODE(ADD,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc)); - /*0x116*/ADD_OPCODE(DCBT,(OP_REG ra, OP_REG rb, OP_REG th)); - /*0x117*/ADD_OPCODE(LHZX,(OP_REG rd, OP_REG ra, OP_REG rb)); - /*0x11c*/ADD_OPCODE(EQV,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc)); - /*0x136*/ADD_OPCODE(ECIWX,(OP_REG rd, OP_REG ra, OP_REG rb)); - /*0x137*/ADD_OPCODE(LHZUX,(OP_REG rd, OP_REG ra, OP_REG rb)); - /*0x13c*/ADD_OPCODE(XOR,(OP_REG rs, OP_REG ra, OP_REG rb, bool rc)); - /*0x153*/ADD_OPCODE(MFSPR,(OP_REG rd, OP_REG spr)); - /*0x156*/ADD_OPCODE(DST,(OP_REG ra, OP_REG rb, OP_uIMM strm, OP_uIMM t)); - /*0x157*/ADD_OPCODE(LHAX,(OP_REG rd, OP_REG ra, OP_REG rb)); - /*0x167*/ADD_OPCODE(LVXL,(OP_REG vd, OP_REG ra, OP_REG rb)); - /*0x168*/ADD_OPCODE(ABS,(OP_REG rd, OP_REG ra, OP_REG oe, bool rc)); - /*0x173*/ADD_OPCODE(MFTB,(OP_REG rd, OP_REG spr)); - /*0x176*/ADD_OPCODE(DSTST,(OP_REG ra, OP_REG rb, OP_uIMM strm, OP_uIMM t)); - /*0x177*/ADD_OPCODE(LHAUX,(OP_REG rd, OP_REG ra, OP_REG rb)); - /*0x197*/ADD_OPCODE(STHX,(OP_REG rs, OP_REG ra, OP_REG rb)); - /*0x19c*/ADD_OPCODE(ORC,(OP_REG rs, OP_REG ra, OP_REG rb, bool rc)); - /*0x1b6*/ADD_OPCODE(ECOWX,(OP_REG rs, OP_REG ra, OP_REG rb)); - /*0x1bc*/ADD_OPCODE(OR,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc)); - /*0x1c9*/ADD_OPCODE(DIVDU,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc)); - /*0x1cb*/ADD_OPCODE(DIVWU,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc)); - /*0x1d3*/ADD_OPCODE(MTSPR,(OP_REG spr, OP_REG rs)); - /*0x1d6*///DCBI - /*0x1dc*/ADD_OPCODE(NAND,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc)); - /*0x1e7*/ADD_OPCODE(STVXL,(OP_REG vs, OP_REG ra, OP_REG rb)); - /*0x1e9*/ADD_OPCODE(DIVD,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc)); - /*0x1eb*/ADD_OPCODE(DIVW,(OP_REG rd, OP_REG ra, OP_REG rb, OP_REG oe, bool rc)); - /*0x207*/ADD_OPCODE(LVLX,(OP_REG vd, OP_REG ra, OP_REG rb)); - /*0x216*/ADD_OPCODE(LWBRX,(OP_REG rd, OP_REG ra, OP_REG rb)); - /*0x217*/ADD_OPCODE(LFSX,(OP_REG frd, OP_REG ra, OP_REG rb)); - /*0x218*/ADD_OPCODE(SRW,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc)); - /*0x21b*/ADD_OPCODE(SRD,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc)); - /*0x227*/ADD_OPCODE(LVRX,(OP_REG vd, OP_REG ra, OP_REG rb)); - /*0x237*/ADD_OPCODE(LFSUX,(OP_REG frd, OP_REG ra, OP_REG rb)); - /*0x256*/ADD_OPCODE(SYNC,(OP_uIMM l)); - /*0x257*/ADD_OPCODE(LFDX,(OP_REG frd, OP_REG ra, OP_REG rb)); - /*0x277*/ADD_OPCODE(LFDUX,(OP_REG frd, OP_REG ra, OP_REG rb)); - /*0x287*/ADD_OPCODE(STVLX,(OP_REG vs, OP_REG ra, OP_REG rb)); - /*0x297*/ADD_OPCODE(STFSX,(OP_REG frs, OP_REG ra, OP_REG rb)); - /*0x2a7*/ADD_OPCODE(STVRX,(OP_REG vs, OP_REG ra, OP_REG rb)); - /*0x2d7*/ADD_OPCODE(STFDX,(OP_REG frs, OP_REG ra, OP_REG rb)); - /*0x307*/ADD_OPCODE(LVLXL,(OP_REG vd, OP_REG ra, OP_REG rb)); - /*0x316*/ADD_OPCODE(LHBRX,(OP_REG rd, OP_REG ra, OP_REG rb)); - /*0x318*/ADD_OPCODE(SRAW,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc)); - /*0x31a*/ADD_OPCODE(SRAD,(OP_REG ra, OP_REG rs, OP_REG rb, bool rc)); - /*0x327*/ADD_OPCODE(LVRXL,(OP_REG vd, OP_REG ra, OP_REG rb)); - /*0x336*/ADD_OPCODE(DSS,(OP_uIMM strm, OP_uIMM a)); - /*0x338*/ADD_OPCODE(SRAWI,(OP_REG ra, OP_REG rs, OP_REG sh, bool rc)); - /*0x33a*/ADD_OPCODE(SRADI1,(OP_REG ra, OP_REG rs, OP_REG sh, bool rc)); - /*0x33b*/ADD_OPCODE(SRADI2,(OP_REG ra, OP_REG rs, OP_REG sh, bool rc)); - /*0x356*/ADD_OPCODE(EIEIO,()); - /*0x387*/ADD_OPCODE(STVLXL,(OP_REG sd, OP_REG ra, OP_REG rb)); - /*0x39a*/ADD_OPCODE(EXTSH,(OP_REG ra, OP_REG rs, bool rc)); - /*0x3a7*/ADD_OPCODE(STVRXL,(OP_REG sd, OP_REG ra, OP_REG rb)); - /*0x3ba*/ADD_OPCODE(EXTSB,(OP_REG ra, OP_REG rs, bool rc)); - /*0x3d7*/ADD_OPCODE(STFIWX,(OP_REG frs, OP_REG ra, OP_REG rb)); - /*0x3da*/ADD_OPCODE(EXTSW,(OP_REG ra, OP_REG rs, bool rc)); - /*0x3d6*///ICBI - /*0x3f6*/ADD_OPCODE(DCBZ,(OP_REG ra, OP_REG rb)); - END_OPCODES_GROUP(G_1f); - - ADD_OPCODE(LWZ,(OP_REG rd, OP_REG ra, OP_sIMM d)); - ADD_OPCODE(LWZU,(OP_REG rd, OP_REG ra, OP_sIMM d)); - ADD_OPCODE(LBZ,(OP_REG rd, OP_REG ra, OP_sIMM d)); - ADD_OPCODE(LBZU,(OP_REG rd, OP_REG ra, OP_sIMM d)); - ADD_OPCODE(STW,(OP_REG rs, OP_REG ra, OP_sIMM d)); - ADD_OPCODE(STWU,(OP_REG rs, OP_REG ra, OP_sIMM d)); - ADD_OPCODE(STB,(OP_REG rs, OP_REG ra, OP_sIMM d)); - ADD_OPCODE(STBU,(OP_REG rs, OP_REG ra, OP_sIMM d)); - ADD_OPCODE(LHZ,(OP_REG rd, OP_REG ra, OP_sIMM d)); - ADD_OPCODE(LHZU,(OP_REG rd, OP_REG ra, OP_sIMM d)); - ADD_OPCODE(STH,(OP_REG rs, OP_REG ra, OP_sIMM d)); - ADD_OPCODE(STHU,(OP_REG rs, OP_REG ra, OP_sIMM d)); - ADD_OPCODE(LMW,(OP_REG rd, OP_REG ra, OP_sIMM d)); - ADD_OPCODE(STMW,(OP_REG rs, OP_REG ra, OP_sIMM d)); - ADD_OPCODE(LFS,(OP_REG frd, OP_REG ra, OP_sIMM d)); - ADD_OPCODE(LFSU,(OP_REG frd, OP_REG ra, OP_sIMM d)); - ADD_OPCODE(LFD,(OP_REG frd, OP_REG ra, OP_sIMM d)); - ADD_OPCODE(LFDU,(OP_REG frd, OP_REG ra, OP_sIMM d)); - ADD_OPCODE(STFS,(OP_REG frs, OP_REG ra, OP_sIMM d)); - ADD_OPCODE(STFSU,(OP_REG frs, OP_REG ra, OP_sIMM d)); - ADD_OPCODE(STFD,(OP_REG frs, OP_REG ra, OP_sIMM d)); - ADD_OPCODE(STFDU,(OP_REG frs, OP_REG ra, OP_sIMM d)); - - START_OPCODES_GROUP(G_3a) - ADD_OPCODE(LD,(OP_REG rd, OP_REG ra, OP_sIMM ds)); - ADD_OPCODE(LDU,(OP_REG rd, OP_REG ra, OP_sIMM ds)); - END_OPCODES_GROUP(G_3a); - - START_OPCODES_GROUP(G_3b) - ADD_OPCODE(FDIVS,(OP_REG frd, OP_REG fra, OP_REG frb, bool rc)); - ADD_OPCODE(FSUBS,(OP_REG frd, OP_REG fra, OP_REG frb, bool rc)); - ADD_OPCODE(FADDS,(OP_REG frd, OP_REG fra, OP_REG frb, bool rc)); - ADD_OPCODE(FSQRTS,(OP_REG frd, OP_REG frb, bool rc)); - ADD_OPCODE(FRES,(OP_REG frd, OP_REG frb, bool rc)); - ADD_OPCODE(FMULS,(OP_REG frd, OP_REG fra, OP_REG frc, bool rc)); - ADD_OPCODE(FMADDS,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc)); - ADD_OPCODE(FMSUBS,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc)); - ADD_OPCODE(FNMSUBS,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc)); - ADD_OPCODE(FNMADDS,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc)); - END_OPCODES_GROUP(G_3b); - - START_OPCODES_GROUP(G_3e) - ADD_OPCODE(STD,(OP_REG rs, OP_REG ra, OP_sIMM ds)); - ADD_OPCODE(STDU,(OP_REG rs, OP_REG ra, OP_sIMM ds)); - END_OPCODES_GROUP(G_3e); - - START_OPCODES_GROUP(G_3f) - ADD_OPCODE(MTFSB1,(OP_REG bt, bool rc)); - ADD_OPCODE(MCRFS,(OP_REG bf, OP_REG bfa)); - ADD_OPCODE(MTFSB0,(OP_REG bt, bool rc)); - ADD_OPCODE(MTFSFI,(OP_REG crfd, OP_REG i, bool rc)); - ADD_OPCODE(MFFS,(OP_REG frd, bool rc)); - ADD_OPCODE(MTFSF,(OP_REG flm, OP_REG frb, bool rc)); - - ADD_OPCODE(FCMPU,(OP_REG bf, OP_REG fra, OP_REG frb)); - ADD_OPCODE(FRSP,(OP_REG frd, OP_REG frb, bool rc)); - ADD_OPCODE(FCTIW,(OP_REG frd, OP_REG frb, bool rc)); - ADD_OPCODE(FCTIWZ,(OP_REG frd, OP_REG frb, bool rc)); - ADD_OPCODE(FDIV,(OP_REG frd, OP_REG fra, OP_REG frb, bool rc)); - ADD_OPCODE(FSUB,(OP_REG frd, OP_REG fra, OP_REG frb, bool rc)); - ADD_OPCODE(FADD,(OP_REG frd, OP_REG fra, OP_REG frb, bool rc)); - ADD_OPCODE(FSQRT,(OP_REG frd, OP_REG frb, bool rc)); - ADD_OPCODE(FSEL,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc)); - ADD_OPCODE(FMUL,(OP_REG frd, OP_REG fra, OP_REG frc, bool rc)); - ADD_OPCODE(FRSQRTE,(OP_REG frd, OP_REG frb, bool rc)); - ADD_OPCODE(FMSUB,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc)); - ADD_OPCODE(FMADD,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc)); - ADD_OPCODE(FNMSUB,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc)); - ADD_OPCODE(FNMADD,(OP_REG frd, OP_REG fra, OP_REG frc, OP_REG frb, bool rc)); - ADD_OPCODE(FCMPO,(OP_REG crfd, OP_REG fra, OP_REG frb)); - ADD_OPCODE(FNEG,(OP_REG frd, OP_REG frb, bool rc)); - ADD_OPCODE(FMR,(OP_REG frd, OP_REG frb, bool rc)); - ADD_OPCODE(FNABS,(OP_REG frd, OP_REG frb, bool rc)); - ADD_OPCODE(FABS,(OP_REG frd, OP_REG frb, bool rc)); - ADD_OPCODE(FCTID,(OP_REG frd, OP_REG frb, bool rc)); - ADD_OPCODE(FCTIDZ,(OP_REG frd, OP_REG frb, bool rc)); - ADD_OPCODE(FCFID,(OP_REG frd, OP_REG frb, bool rc)); - END_OPCODES_GROUP(G_3f); - - ADD_OPCODE(UNK,(const u32 code, const u32 opcode, const u32 gcode)); + virtual void UNK(const u32 code, const u32 opcode, const u32 gcode) = 0; }; - -//instr_caller* g_instrs[0x40]; - -#undef START_OPCODES_GROUP -#undef ADD_OPCODE -#undef ADD_NULL_OPCODE -#undef END_OPCODES_GROUP \ No newline at end of file diff --git a/rpcs3/Emu/Cell/SPUDecoder.h b/rpcs3/Emu/Cell/SPUDecoder.h index 6d96281c09..eac3dae07a 100644 --- a/rpcs3/Emu/Cell/SPUDecoder.h +++ b/rpcs3/Emu/Cell/SPUDecoder.h @@ -2,327 +2,26 @@ #include "Emu/Cell/SPUOpcodes.h" #include "Emu/Cell/PPCDecoder.h" - -#define START_OPCODES_GROUP_(group, reg) \ - case(##group##): \ - temp=##reg##;\ - switch(temp)\ - { - -#define START_OPCODES_GROUP(group, reg) START_OPCODES_GROUP_(##group##, ##reg##()) - -#define END_OPCODES_GROUP(group) \ - default:\ - m_op.UNK(m_code, opcode, temp);\ - break;\ - }\ - break - -#define ADD_OPCODE(name, regs) case(##name##):m_op.##name####regs##; return -#define ADD_NULL_OPCODE(name) ADD_OPCODE(##name##, ()) +#include "Emu/Cell/SPUInstrtable.h" class SPU_Decoder : public PPC_Decoder { - u32 m_code; - SPU_Opcodes& m_op; - - OP_REG RC() const { return GetField(4, 10); } - OP_REG RT() const { return GetField(25, 31); } - OP_REG RA() const { return GetField(18, 24); } - OP_REG RB() const { return GetField(11, 17); } - - OP_uIMM i7() const { return GetField(11, 17); } - OP_uIMM i8() const { return GetField(10, 17); } - OP_uIMM i10() const { return GetField(8, 17); } - OP_uIMM i16() const { return GetField(9, 24); } - OP_uIMM i18() const { return GetField(7, 24); } - - OP_uIMM ROH() const { return GetField(16, 17); } - OP_uIMM ROL() const { return GetField(25, 31); } - OP_uIMM RO() const { return ROL() | (ROH() << 8); } - - OP_uIMM RR() const { return GetField(0, 10); } - OP_uIMM RRR() const { return GetField(0, 3); } - OP_uIMM RI7() const { return GetField(0, 10); } - OP_uIMM RI8() const { return GetField(0, 9); } - OP_uIMM RI10() const { return GetField(0, 7); } - OP_uIMM RI16() const { return GetField(0, 8); } - OP_uIMM RI18() const { return GetField(0, 6); } - - __forceinline u32 GetField(const u32 p) const - { - return (m_code >> (31 - p)) & 0x1; - } - - __forceinline u32 GetField(const u32 from, const u32 to) const - { - return (m_code >> (31 - to)) & ((1 << ((to - from) + 1)) - 1); - } - - OP_sIMM exts18(OP_sIMM i18) const - { - if(i18 & 0x20000) return i18 - 0x40000; - return i18; - } - - OP_sIMM exts16(OP_sIMM i16) const - { - return (s32)(s16)i16; - } - - OP_sIMM exts10(OP_sIMM i10) const - { - if(i10 & 0x200) return i10 - 0x400; - return i10; - } - - OP_sIMM exts7(OP_sIMM i7) const - { - if(i7 & 0x40) return i7 - 0x80; - return i7; - } + SPU_Opcodes* m_op; public: - SPU_Decoder(SPU_Opcodes& op) : m_op(op) + SPU_Decoder(SPU_Opcodes& op) : m_op(&op) { } ~SPU_Decoder() { - m_op.Exit(); - delete &m_op; + m_op->Exit(); + delete m_op; } virtual void Decode(const u32 code) { - using namespace SPU_opcodes; - - m_code = code; - - switch(RR()) //& RI7 //0 - 10 - { - ADD_OPCODE(STOP,(GetField(18, 31))); - ADD_OPCODE(LNOP,()); - ADD_OPCODE(SYNC,(GetField(11))); - ADD_OPCODE(DSYNC,()); - ADD_OPCODE(MFSPR,(RT(), RA())); - ADD_OPCODE(RDCH,(RT(), RA())); - ADD_OPCODE(RCHCNT,(RT(), RA())); - ADD_OPCODE(SF,(RT(), RA(), RB())); - ADD_OPCODE(OR,(RT(), RA(), RB())); - ADD_OPCODE(BG,(RT(), RA(), RB())); - ADD_OPCODE(SFH,(RT(), RA(), RB())); - ADD_OPCODE(NOR,(RT(), RA(), RB())); - ADD_OPCODE(ABSDB,(RT(), RA(), RB())); - ADD_OPCODE(ROT,(RT(), RA(), RB())); - ADD_OPCODE(ROTM,(RT(), RA(), RB())); - ADD_OPCODE(ROTMA,(RT(), RA(), RB())); - ADD_OPCODE(SHL,(RT(), RA(), RB())); - ADD_OPCODE(ROTH,(RT(), RA(), RB())); - ADD_OPCODE(ROTHM,(RT(), RA(), RB())); - ADD_OPCODE(ROTMAH,(RT(), RA(), RB())); - ADD_OPCODE(SHLH,(RT(), RA(), RB())); - ADD_OPCODE(ROTI,(RT(), RA(), RB())); - ADD_OPCODE(ROTMI,(RT(), RA(), RB())); - ADD_OPCODE(ROTMAI,(RT(), RA(), RB())); - ADD_OPCODE(SHLI,(RT(), RA(), i7())); - ADD_OPCODE(ROTHI,(RT(), RA(), i7())); - ADD_OPCODE(ROTHMI,(RT(), RA(), i7())); - ADD_OPCODE(ROTMAHI,(RT(), RA(), i7())); - ADD_OPCODE(SHLHI,(RT(), RA(), i7())); - ADD_OPCODE(A,(RT(), RA(), RB())); - ADD_OPCODE(AND,(RT(), RA(), RB())); - ADD_OPCODE(CG,(RT(), RA(), RB())); - ADD_OPCODE(AH,(RT(), RA(), RB())); - ADD_OPCODE(NAND,(RT(), RA(), RB())); - ADD_OPCODE(AVGB,(RT(), RA(), RB())); - ADD_OPCODE(MTSPR,(RT(), RA())); - ADD_OPCODE(WRCH,(RA(), RT())); - ADD_OPCODE(BIZ,(RT(), RA())); - ADD_OPCODE(BINZ,(RT(), RA())); - ADD_OPCODE(BIHZ,(RT(), RA())); - ADD_OPCODE(BIHNZ,(RT(), RA())); - ADD_OPCODE(STOPD,(RT(), RA(), RB())); - ADD_OPCODE(STQX,(RT(), RA(), RB())); - ADD_OPCODE(BI,(RA())); - ADD_OPCODE(BISL,(RT(), RA())); - ADD_OPCODE(IRET,(RA())); - ADD_OPCODE(BISLED,(RT(), RA())); - ADD_OPCODE(HBR,(GetField(11), RO(), RA())); - ADD_OPCODE(GB,(RT(), RA())); - ADD_OPCODE(GBH,(RT(), RA())); - ADD_OPCODE(GBB,(RT(), RA())); - ADD_OPCODE(FSM,(RT(), RA())); - ADD_OPCODE(FSMH,(RT(), RA())); - ADD_OPCODE(FSMB,(RT(), RA())); - ADD_OPCODE(FREST,(RT(), RA())); - ADD_OPCODE(FRSQEST,(RT(), RA())); - ADD_OPCODE(LQX,(RT(), RA(), RB())); - ADD_OPCODE(ROTQBYBI,(RT(), RA(), RB())); - ADD_OPCODE(ROTQMBYBI,(RT(), RA(), RB())); - ADD_OPCODE(SHLQBYBI,(RT(), RA(), RB())); - ADD_OPCODE(CBX,(RT(), RA(), RB())); - ADD_OPCODE(CHX,(RT(), RA(), RB())); - ADD_OPCODE(CWX,(RT(), RA(), RB())); - ADD_OPCODE(CDX,(RT(), RA(), RB())); - ADD_OPCODE(ROTQBI,(RT(), RA(), RB())); - ADD_OPCODE(ROTQMBI,(RT(), RA(), RB())); - ADD_OPCODE(SHLQBI,(RT(), RA(), RB())); - ADD_OPCODE(ROTQBY,(RT(), RA(), RB())); - ADD_OPCODE(ROTQMBY,(RT(), RA(), RB())); - ADD_OPCODE(SHLQBY,(RT(), RA(), RB())); - ADD_OPCODE(ORX,(RT(), RA())); - ADD_OPCODE(CBD,(RT(), RA(), exts7(i7()))); - ADD_OPCODE(CHD,(RT(), RA(), exts7(i7()))); - ADD_OPCODE(CWD,(RT(), RA(), exts7(i7()))); - ADD_OPCODE(CDD,(RT(), RA(), exts7(i7()))); - ADD_OPCODE(ROTQBII,(RT(), RA(), i7())); - ADD_OPCODE(ROTQMBII,(RT(), RA(), i7())); - ADD_OPCODE(SHLQBII,(RT(), RA(), i7())); - ADD_OPCODE(ROTQBYI,(RT(), RA(), i7())); - ADD_OPCODE(ROTQMBYI,(RT(), RA(), i7())); - ADD_OPCODE(SHLQBYI,(RT(), RA(), i7())); - ADD_OPCODE(NOP,(RT())); - ADD_OPCODE(CGT,(RT(), RA(), RB())); - ADD_OPCODE(XOR,(RT(), RA(), RB())); - ADD_OPCODE(CGTH,(RT(), RA(), RB())); - ADD_OPCODE(EQV,(RT(), RA(), RB())); - ADD_OPCODE(CGTB,(RT(), RA(), RB())); - ADD_OPCODE(SUMB,(RT(), RA(), RB())); - ADD_OPCODE(HGT,(RT(), RA(), RB())); - ADD_OPCODE(CLZ,(RT(), RA())); - ADD_OPCODE(XSWD,(RT(), RA())); - ADD_OPCODE(XSHW,(RT(), RA())); - ADD_OPCODE(CNTB,(RT(), RA())); - ADD_OPCODE(XSBH,(RT(), RA())); - ADD_OPCODE(CLGT,(RT(), RA(), RB())); - ADD_OPCODE(ANDC,(RT(), RA(), RB())); - ADD_OPCODE(FCGT,(RT(), RA(), RB())); - ADD_OPCODE(DFCGT,(RT(), RA(), RB())); - ADD_OPCODE(FA,(RT(), RA(), RB())); - ADD_OPCODE(FS,(RT(), RA(), RB())); - ADD_OPCODE(FM,(RT(), RA(), RB())); - ADD_OPCODE(CLGTH,(RT(), RA(), RB())); - ADD_OPCODE(ORC,(RT(), RA(), RB())); - ADD_OPCODE(FCMGT,(RT(), RA(), RB())); - ADD_OPCODE(DFCMGT,(RT(), RA(), RB())); - ADD_OPCODE(DFA,(RT(), RA(), RB())); - ADD_OPCODE(DFS,(RT(), RA(), RB())); - ADD_OPCODE(DFM,(RT(), RA(), RB())); - ADD_OPCODE(CLGTB,(RT(), RA(), RB())); - ADD_OPCODE(HLGT,(RT(), RA(), RB())); - ADD_OPCODE(DFMA,(RT(), RA(), RB())); - ADD_OPCODE(DFMS,(RT(), RA(), RB())); - ADD_OPCODE(DFNMS,(RT(), RA(), RB())); - ADD_OPCODE(DFNMA,(RT(), RA(), RB())); - ADD_OPCODE(CEQ,(RT(), RA(), RB())); - ADD_OPCODE(MPYHHU,(RT(), RA(), RB())); - ADD_OPCODE(ADDX,(RT(), RA(), RB())); - ADD_OPCODE(SFX,(RT(), RA(), RB())); - ADD_OPCODE(CGX,(RT(), RA(), RB())); - ADD_OPCODE(BGX,(RT(), RA(), RB())); - ADD_OPCODE(MPYHHA,(RT(), RA(), RB())); - ADD_OPCODE(MPYHHAU,(RT(), RA(), RB())); - ADD_OPCODE(FSCRRD,(RT())); - ADD_OPCODE(FESD,(RT(), RA())); - ADD_OPCODE(FRDS,(RT(), RA())); - ADD_OPCODE(FSCRWR,(RT(), RA())); - ADD_OPCODE(DFTSV,(RT(), RA(), i7())); - ADD_OPCODE(FCEQ,(RT(), RA(), RB())); - ADD_OPCODE(DFCEQ,(RT(), RA(), RB())); - ADD_OPCODE(MPY,(RT(), RA(), RB())); - ADD_OPCODE(MPYH,(RT(), RA(), RB())); - ADD_OPCODE(MPYHH,(RT(), RA(), RB())); - ADD_OPCODE(MPYS,(RT(), RA(), RB())); - ADD_OPCODE(CEQH,(RT(), RA(), RB())); - ADD_OPCODE(FCMEQ,(RT(), RA(), RB())); - ADD_OPCODE(DFCMEQ,(RT(), RA(), RB())); - ADD_OPCODE(MPYU,(RT(), RA(), RB())); - ADD_OPCODE(CEQB,(RT(), RA(), RB())); - ADD_OPCODE(FI,(RT(), RA(), RB())); - ADD_OPCODE(HEQ,(RT(), RA(), RB())); - } - - switch(RI8()) //0 - 9 - { - ADD_OPCODE(CFLTS,(RT(), RA(), i8())); - ADD_OPCODE(CFLTU,(RT(), RA(), i8())); - ADD_OPCODE(CSFLT,(RT(), RA(), i8())); - ADD_OPCODE(CUFLT,(RT(), RA(), i8())); - } - - switch(RI16()) //0 - 8 - { - ADD_OPCODE(BRZ,(RT(), exts16(i16()))); - ADD_OPCODE(STQA,(RT(), exts16(i16()))); - ADD_OPCODE(BRNZ,(RT(), exts16(i16()))); - ADD_OPCODE(BRHZ,(RT(), exts16(i16()))); - ADD_OPCODE(BRHNZ,(RT(), exts16(i16()))); - ADD_OPCODE(STQR,(RT(), i16())); - ADD_OPCODE(BRA,(exts16(i16()))); - ADD_OPCODE(LQA,(RT(), exts16(i16()))); - ADD_OPCODE(BRASL,(RT(), exts16(i16()))); - ADD_OPCODE(BR,(exts16(i16()))); - ADD_OPCODE(FSMBI,(RT(), i16())); - ADD_OPCODE(BRSL,(RT(), exts16(i16()))); - ADD_OPCODE(LQR,(RT(), exts16(i16()))); - ADD_OPCODE(IL,(RT(), exts16(i16()))); - ADD_OPCODE(ILHU,(RT(), i16())); - ADD_OPCODE(ILH,(RT(), i16())); - ADD_OPCODE(IOHL,(RT(), i16())); - } - - switch(RI10()) //0 - 7 - { - ADD_OPCODE(ORI,(RT(), RA(), exts10(i10()))); - ADD_OPCODE(ORHI,(RT(), RA(), exts10(i10()))); - ADD_OPCODE(ORBI,(RT(), RA(), i10())); - ADD_OPCODE(SFI,(RT(), RA(), exts10(i10()))); - ADD_OPCODE(SFHI,(RT(), RA(), exts10(i10()))); - ADD_OPCODE(ANDI,(RT(), RA(), exts10(i10()))); - ADD_OPCODE(ANDHI,(RT(), RA(), exts10(i10()))); - ADD_OPCODE(ANDBI,(RT(), RA(), i10())); - ADD_OPCODE(AI,(RT(), RA(), exts10(i10()))); - ADD_OPCODE(AHI,(RT(), RA(), exts10(i10()))); - ADD_OPCODE(STQD,(RT(), exts10(i10()) << 4, RA())); - ADD_OPCODE(LQD,(RT(), exts10(i10()) << 4, RA())); - ADD_OPCODE(XORI,(RT(), RA(), exts10(i10()))); - ADD_OPCODE(XORHI,(RT(), RA(), exts10(i10()))); - ADD_OPCODE(XORBI,(RT(), RA(), i10())); - ADD_OPCODE(CGTI,(RT(), RA(), exts10(i10()))); - ADD_OPCODE(CGTHI,(RT(), RA(), exts10(i10()))); - ADD_OPCODE(CGTBI,(RT(), RA(), i10())); - ADD_OPCODE(HGTI,(RT(), RA(), exts10(i10()))); - ADD_OPCODE(CLGTI,(RT(), RA(), exts10(i10()))); - ADD_OPCODE(CLGTHI,(RT(), RA(), exts10(i10()))); - ADD_OPCODE(CLGTBI,(RT(), RA(), i10())); - ADD_OPCODE(HLGTI,(RT(), RA(), exts10(i10()))); - ADD_OPCODE(MPYI,(RT(), RA(), exts10(i10()))); - ADD_OPCODE(MPYUI,(RT(), RA(), exts10(i10()))); - ADD_OPCODE(CEQI,(RT(), RA(), exts10(i10()))); - ADD_OPCODE(CEQHI,(RT(), RA(), exts10(i10()))); - ADD_OPCODE(CEQBI,(RT(), RA(), i10())); - ADD_OPCODE(HEQI,(RT(), RA(), exts10(i10()))); - } - - switch(RI18()) //0 - 6 - { - ADD_OPCODE(HBRA,(RO(), i16() << 2)); - ADD_OPCODE(HBRR,(RO(), exts16(i16()))); - ADD_OPCODE(ILA,(RT(), i18())); - } - - switch(RRR()) //0 - 3 - { - ADD_OPCODE(SELB,(RC(), RA(), RB(), RT())); - ADD_OPCODE(SHUFB,(RC(), RA(), RB(), RT())); - ADD_OPCODE(MPYA,(RC(), RA(), RB(), RT())); - ADD_OPCODE(FNMS,(RC(), RA(), RB(), RT())); - ADD_OPCODE(FMA,(RC(), RA(), RB(), RT())); - ADD_OPCODE(FMS,(RC(), RA(), RB(), RT())); - } - - m_op.UNK(m_code, 0, 0); + (*SPU_instr::rrr_list)(m_op, code); } }; diff --git a/rpcs3/Emu/Cell/SPUDisAsm.h b/rpcs3/Emu/Cell/SPUDisAsm.h index c74a58b80c..d8a94307b5 100644 --- a/rpcs3/Emu/Cell/SPUDisAsm.h +++ b/rpcs3/Emu/Cell/SPUDisAsm.h @@ -6,9 +6,6 @@ #include "Gui/DisAsmFrame.h" #include "Emu/Memory/Memory.h" -#define START_OPCODES_GROUP(x) /*x*/ -#define END_OPCODES_GROUP(x) /*x*/ - class SPU_DisAsm : public SPU_Opcodes , public PPC_DisAsm @@ -33,7 +30,7 @@ public: } private: - virtual void Exit() + void Exit() { if(m_mode == NormalMode && !disasm_frame->exit) { @@ -50,817 +47,817 @@ private: private: //0 - 10 - virtual void STOP(OP_uIMM code) + void STOP(u32 code) { Write(wxString::Format("stop 0x%x", code)); } - virtual void LNOP() + void LNOP() { Write("lnop"); } - virtual void SYNC(OP_uIMM Cbit) + void SYNC(u32 Cbit) { Write(wxString::Format("sync %d", Cbit)); } - virtual void DSYNC() + void DSYNC() { Write("dsync"); } - virtual void MFSPR(OP_REG rt, OP_REG sa) + void MFSPR(u32 rt, u32 sa) { Write(wxString::Format("mfspr %s,%s", spu_reg_name[rt], spu_reg_name[sa])); // Are SPR mapped on the GPR or are there 128 additional registers ? } - virtual void RDCH(OP_REG rt, OP_REG ra) + void RDCH(u32 rt, u32 ra) { Write(wxString::Format("rdch %s,%s", spu_reg_name[rt], spu_ch_name[ra])); } - virtual void RCHCNT(OP_REG rt, OP_REG ra) + void RCHCNT(u32 rt, u32 ra) { Write(wxString::Format("rchcnt %s,%s", spu_reg_name[rt], spu_ch_name[ra])); } - virtual void SF(OP_REG rt, OP_REG ra, OP_REG rb) + void SF(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("sf %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void OR(OP_REG rt, OP_REG ra, OP_REG rb) + void OR(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("or %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void BG(OP_REG rt, OP_REG ra, OP_REG rb) + void BG(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("bg %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void SFH(OP_REG rt, OP_REG ra, OP_REG rb) + void SFH(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("sfh %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void NOR(OP_REG rt, OP_REG ra, OP_REG rb) + void NOR(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("nor %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void ABSDB(OP_REG rt, OP_REG ra, OP_REG rb) + void ABSDB(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("absdb %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void ROT(OP_REG rt, OP_REG ra, OP_REG rb) + void ROT(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("rot %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void ROTM(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTM(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("rotm %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void ROTMA(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTMA(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("rotma %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void SHL(OP_REG rt, OP_REG ra, OP_REG rb) + void SHL(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("shl %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void ROTH(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTH(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("roth %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void ROTHM(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTHM(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("rothm %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void ROTMAH(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTMAH(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("rotmah %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void SHLH(OP_REG rt, OP_REG ra, OP_REG rb) + void SHLH(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("shlh %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void ROTI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void ROTI(u32 rt, u32 ra, s32 i7) { Write(wxString::Format("roti %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i7)); } - virtual void ROTMI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void ROTMI(u32 rt, u32 ra, s32 i7) { Write(wxString::Format("rotmi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i7)); } - virtual void ROTMAI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void ROTMAI(u32 rt, u32 ra, s32 i7) { Write(wxString::Format("rotmai %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i7)); } - virtual void SHLI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void SHLI(u32 rt, u32 ra, s32 i7) { Write(wxString::Format("shli %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i7)); } - virtual void ROTHI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void ROTHI(u32 rt, u32 ra, s32 i7) { Write(wxString::Format("rothi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i7)); } - virtual void ROTHMI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void ROTHMI(u32 rt, u32 ra, s32 i7) { Write(wxString::Format("rothmi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i7)); } - virtual void ROTMAHI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void ROTMAHI(u32 rt, u32 ra, s32 i7) { Write(wxString::Format("rotmahi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i7)); } - virtual void SHLHI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void SHLHI(u32 rt, u32 ra, s32 i7) { Write(wxString::Format("shlhi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i7)); } - virtual void A(OP_REG rt, OP_REG ra, OP_REG rb) + void A(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("a %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void AND(OP_REG rt, OP_REG ra, OP_REG rb) + void AND(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("and %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void CG(OP_REG rt, OP_REG ra, OP_REG rb) + void CG(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("cg %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void AH(OP_REG rt, OP_REG ra, OP_REG rb) + void AH(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("ah %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void NAND(OP_REG rt, OP_REG ra, OP_REG rb) + void NAND(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("nand %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void AVGB(OP_REG rt, OP_REG ra, OP_REG rb) + void AVGB(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("avgb %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void MTSPR(OP_REG rt, OP_REG sa) + void MTSPR(u32 rt, u32 sa) { Write(wxString::Format("mtspr %s,%s", spu_reg_name[rt], spu_reg_name[sa])); } - virtual void WRCH(OP_REG ra, OP_REG rt) + void WRCH(u32 ra, u32 rt) { Write(wxString::Format("wrch %s,%s", spu_ch_name[ra], spu_reg_name[rt])); } - virtual void BIZ(OP_REG rt, OP_REG ra) + void BIZ(u32 rt, u32 ra) { Write(wxString::Format("biz %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void BINZ(OP_REG rt, OP_REG ra) + void BINZ(u32 rt, u32 ra) { Write(wxString::Format("binz %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void BIHZ(OP_REG rt, OP_REG ra) + void BIHZ(u32 rt, u32 ra) { Write(wxString::Format("bihz %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void BIHNZ(OP_REG rt, OP_REG ra) + void BIHNZ(u32 rt, u32 ra) { Write(wxString::Format("bihnz %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void STOPD(OP_REG rc, OP_REG ra, OP_REG rb) + void STOPD(u32 rc, u32 ra, u32 rb) { Write(wxString::Format("bihnz %s,%s,%s", spu_reg_name[rc], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void STQX(OP_REG rt, OP_REG ra, OP_REG rb) + void STQX(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("stqx %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void BI(OP_REG ra) + void BI(u32 ra) { Write(wxString::Format("bi %s", spu_reg_name[ra])); } - virtual void BISL(OP_REG rt, OP_REG ra) + void BISL(u32 rt, u32 ra) { Write(wxString::Format("bisl %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void IRET(OP_REG ra) + void IRET(u32 ra) { Write(wxString::Format("iret %s", spu_reg_name[ra])); } - virtual void BISLED(OP_REG rt, OP_REG ra) + void BISLED(u32 rt, u32 ra) { Write(wxString::Format("bisled %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void HBR(OP_REG p, OP_REG ro, OP_REG ra) + void HBR(u32 p, u32 ro, u32 ra) { Write(wxString::Format("hbr 0x%x,%s", DisAsmBranchTarget(ro), spu_reg_name[ra])); } - virtual void GB(OP_REG rt, OP_REG ra) + void GB(u32 rt, u32 ra) { Write(wxString::Format("gb %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void GBH(OP_REG rt, OP_REG ra) + void GBH(u32 rt, u32 ra) { Write(wxString::Format("gbh %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void GBB(OP_REG rt, OP_REG ra) + void GBB(u32 rt, u32 ra) { Write(wxString::Format("gbb %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void FSM(OP_REG rt, OP_REG ra) + void FSM(u32 rt, u32 ra) { Write(wxString::Format("fsm %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void FSMH(OP_REG rt, OP_REG ra) + void FSMH(u32 rt, u32 ra) { Write(wxString::Format("fsmh %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void FSMB(OP_REG rt, OP_REG ra) + void FSMB(u32 rt, u32 ra) { Write(wxString::Format("fsmb %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void FREST(OP_REG rt, OP_REG ra) + void FREST(u32 rt, u32 ra) { Write(wxString::Format("frest %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void FRSQEST(OP_REG rt, OP_REG ra) + void FRSQEST(u32 rt, u32 ra) { Write(wxString::Format("frsqest %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void LQX(OP_REG rt, OP_REG ra, OP_REG rb) + void LQX(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("lqx %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void ROTQBYBI(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTQBYBI(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("rotqbybi %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void ROTQMBYBI(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTQMBYBI(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("rotqmbybi %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void SHLQBYBI(OP_REG rt, OP_REG ra, OP_REG rb) + void SHLQBYBI(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("shlqbybi %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void CBX(OP_REG rt, OP_REG ra, OP_REG rb) + void CBX(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("cbx %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void CHX(OP_REG rt, OP_REG ra, OP_REG rb) + void CHX(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("chx %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void CWX(OP_REG rt, OP_REG ra, OP_REG rb) + void CWX(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("cwx %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void CDX(OP_REG rt, OP_REG ra, OP_REG rb) + void CDX(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("cdx %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void ROTQBI(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTQBI(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("rotqbi %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void ROTQMBI(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTQMBI(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("rotqmbi %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void SHLQBI(OP_REG rt, OP_REG ra, OP_REG rb) + void SHLQBI(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("shlqbi %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void ROTQBY(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTQBY(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("rotqby %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void ROTQMBY(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTQMBY(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("rotqmby %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void SHLQBY(OP_REG rt, OP_REG ra, OP_REG rb) + void SHLQBY(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("shlqby %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void ORX(OP_REG rt, OP_REG ra) + void ORX(u32 rt, u32 ra) { Write(wxString::Format("orx %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void CBD(OP_REG rt, OP_REG ra, OP_sIMM i7) + void CBD(u32 rt, u32 ra, s32 i7) { Write(wxString::Format("cbd %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i7)); } - virtual void CHD(OP_REG rt, OP_REG ra, OP_sIMM i7) + void CHD(u32 rt, u32 ra, s32 i7) { Write(wxString::Format("chd %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i7)); } - virtual void CWD(OP_REG rt, OP_REG ra, OP_sIMM i7) + void CWD(u32 rt, u32 ra, s32 i7) { Write(wxString::Format("cwd %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i7)); } - virtual void CDD(OP_REG rt, OP_REG ra, OP_sIMM i7) + void CDD(u32 rt, u32 ra, s32 i7) { Write(wxString::Format("cdd %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i7)); } - virtual void ROTQBII(OP_REG rt, OP_REG ra, OP_sIMM i7) + void ROTQBII(u32 rt, u32 ra, s32 i7) { Write(wxString::Format("rotqbii %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i7)); } - virtual void ROTQMBII(OP_REG rt, OP_REG ra, OP_sIMM i7) + void ROTQMBII(u32 rt, u32 ra, s32 i7) { Write(wxString::Format("rotqmbii %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i7)); } - virtual void SHLQBII(OP_REG rt, OP_REG ra, OP_sIMM i7) + void SHLQBII(u32 rt, u32 ra, s32 i7) { Write(wxString::Format("shlqbii %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i7)); } - virtual void ROTQBYI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void ROTQBYI(u32 rt, u32 ra, s32 i7) { Write(wxString::Format("rotqbyi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i7)); } - virtual void ROTQMBYI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void ROTQMBYI(u32 rt, u32 ra, s32 i7) { Write(wxString::Format("rotqmbyi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i7)); } - virtual void SHLQBYI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void SHLQBYI(u32 rt, u32 ra, s32 i7) { Write(wxString::Format("shlqbyi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i7)); } - virtual void NOP(OP_REG rt) + void NOP(u32 rt) { Write(wxString::Format("nop %s", spu_reg_name[rt])); } - virtual void CGT(OP_REG rt, OP_REG ra, OP_REG rb) + void CGT(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("cgt %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void XOR(OP_REG rt, OP_REG ra, OP_REG rb) + void XOR(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("xor %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void CGTH(OP_REG rt, OP_REG ra, OP_REG rb) + void CGTH(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("cgth %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void EQV(OP_REG rt, OP_REG ra, OP_REG rb) + void EQV(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("eqv %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void CGTB(OP_REG rt, OP_REG ra, OP_REG rb) + void CGTB(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("cgtb %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void SUMB(OP_REG rt, OP_REG ra, OP_REG rb) + void SUMB(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("sumb %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void HGT(OP_REG rt, OP_REG ra, OP_REG rb) + void HGT(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("hgt %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void CLZ(OP_REG rt, OP_REG ra) + void CLZ(u32 rt, u32 ra) { Write(wxString::Format("clz %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void XSWD(OP_REG rt, OP_REG ra) + void XSWD(u32 rt, u32 ra) { Write(wxString::Format("xswd %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void XSHW(OP_REG rt, OP_REG ra) + void XSHW(u32 rt, u32 ra) { Write(wxString::Format("xshw %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void CNTB(OP_REG rt, OP_REG ra) + void CNTB(u32 rt, u32 ra) { Write(wxString::Format("cntb %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void XSBH(OP_REG rt, OP_REG ra) + void XSBH(u32 rt, u32 ra) { Write(wxString::Format("xsbh %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void CLGT(OP_REG rt, OP_REG ra, OP_REG rb) + void CLGT(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("clgt %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void ANDC(OP_REG rt, OP_REG ra, OP_REG rb) + void ANDC(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("andc %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void FCGT(OP_REG rt, OP_REG ra, OP_REG rb) + void FCGT(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("fcgt %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void DFCGT(OP_REG rt, OP_REG ra, OP_REG rb) + void DFCGT(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("dfcgt %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void FA(OP_REG rt, OP_REG ra, OP_REG rb) + void FA(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("fa %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void FS(OP_REG rt, OP_REG ra, OP_REG rb) + void FS(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("fs %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void FM(OP_REG rt, OP_REG ra, OP_REG rb) + void FM(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("fm %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void CLGTH(OP_REG rt, OP_REG ra, OP_REG rb) + void CLGTH(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("clgth %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void ORC(OP_REG rt, OP_REG ra, OP_REG rb) + void ORC(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("orc %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void FCMGT(OP_REG rt, OP_REG ra, OP_REG rb) + void FCMGT(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("fcmgt %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void DFCMGT(OP_REG rt, OP_REG ra, OP_REG rb) + void DFCMGT(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("dfcmgt %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void DFA(OP_REG rt, OP_REG ra, OP_REG rb) + void DFA(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("dfa %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void DFS(OP_REG rt, OP_REG ra, OP_REG rb) + void DFS(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("dfs %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void DFM(OP_REG rt, OP_REG ra, OP_REG rb) + void DFM(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("dfm %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void CLGTB(OP_REG rt, OP_REG ra, OP_REG rb) + void CLGTB(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("clgtb %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void HLGT(OP_REG rt, OP_REG ra, OP_REG rb) + void HLGT(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("hlgt %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void DFMA(OP_REG rt, OP_REG ra, OP_REG rb) + void DFMA(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("dfma %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void DFMS(OP_REG rt, OP_REG ra, OP_REG rb) + void DFMS(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("dfms %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void DFNMS(OP_REG rt, OP_REG ra, OP_REG rb) + void DFNMS(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("dfnms %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void DFNMA(OP_REG rt, OP_REG ra, OP_REG rb) + void DFNMA(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("dfnma %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void CEQ(OP_REG rt, OP_REG ra, OP_REG rb) + void CEQ(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("ceq %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void MPYHHU(OP_REG rt, OP_REG ra, OP_REG rb) + void MPYHHU(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("mpyhhu %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void ADDX(OP_REG rt, OP_REG ra, OP_REG rb) + void ADDX(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("addx %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void SFX(OP_REG rt, OP_REG ra, OP_REG rb) + void SFX(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("sfx %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void CGX(OP_REG rt, OP_REG ra, OP_REG rb) + void CGX(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("cgx %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void BGX(OP_REG rt, OP_REG ra, OP_REG rb) + void BGX(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("bgx %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void MPYHHA(OP_REG rt, OP_REG ra, OP_REG rb) + void MPYHHA(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("mpyhha %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void MPYHHAU(OP_REG rt, OP_REG ra, OP_REG rb) + void MPYHHAU(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("mpyhhau %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void FSCRRD(OP_REG rt) + void FSCRRD(u32 rt) { Write(wxString::Format("fscrrd %s", spu_reg_name[rt])); } - virtual void FESD(OP_REG rt, OP_REG ra) + void FESD(u32 rt, u32 ra) { Write(wxString::Format("fesd %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void FRDS(OP_REG rt, OP_REG ra) + void FRDS(u32 rt, u32 ra) { Write(wxString::Format("frds %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void FSCRWR(OP_REG rt, OP_REG ra) + void FSCRWR(u32 rt, u32 ra) { Write(wxString::Format("fscrwr %s,%s", spu_reg_name[rt], spu_reg_name[ra])); } - virtual void DFTSV(OP_REG rt, OP_REG ra, OP_sIMM i7) + void DFTSV(u32 rt, u32 ra, s32 i7) { Write(wxString::Format("dftsv %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i7)); } - virtual void FCEQ(OP_REG rt, OP_REG ra, OP_REG rb) + void FCEQ(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("fceq %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void DFCEQ(OP_REG rt, OP_REG ra, OP_REG rb) + void DFCEQ(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("dfceq %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void MPY(OP_REG rt, OP_REG ra, OP_REG rb) + void MPY(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("mpy %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void MPYH(OP_REG rt, OP_REG ra, OP_REG rb) + void MPYH(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("mpyh %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void MPYHH(OP_REG rt, OP_REG ra, OP_REG rb) + void MPYHH(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("mpyhh %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void MPYS(OP_REG rt, OP_REG ra, OP_REG rb) + void MPYS(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("mpys %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void CEQH(OP_REG rt, OP_REG ra, OP_REG rb) + void CEQH(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("ceqh %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void FCMEQ(OP_REG rt, OP_REG ra, OP_REG rb) + void FCMEQ(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("fcmeq %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void DFCMEQ(OP_REG rt, OP_REG ra, OP_REG rb) + void DFCMEQ(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("dfcmeq %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void MPYU(OP_REG rt, OP_REG ra, OP_REG rb) + void MPYU(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("mpyu %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void CEQB(OP_REG rt, OP_REG ra, OP_REG rb) + void CEQB(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("ceqb %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void FI(OP_REG rt, OP_REG ra, OP_REG rb) + void FI(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("fi %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - virtual void HEQ(OP_REG rt, OP_REG ra, OP_REG rb) + void HEQ(u32 rt, u32 ra, u32 rb) { Write(wxString::Format("heq %s,%s,%s", spu_reg_name[rt], spu_reg_name[ra], spu_reg_name[rb])); } - //0 - 9 - virtual void CFLTS(OP_REG rt, OP_REG ra, OP_sIMM i8) + //0 - 9 + void CFLTS(u32 rt, u32 ra, s32 i8) { Write(wxString::Format("cflts %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i8)); } - virtual void CFLTU(OP_REG rt, OP_REG ra, OP_sIMM i8) + void CFLTU(u32 rt, u32 ra, s32 i8) { Write(wxString::Format("cfltu %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i8)); } - virtual void CSFLT(OP_REG rt, OP_REG ra, OP_sIMM i8) + void CSFLT(u32 rt, u32 ra, s32 i8) { Write(wxString::Format("csflt %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i8)); } - virtual void CUFLT(OP_REG rt, OP_REG ra, OP_sIMM i8) + void CUFLT(u32 rt, u32 ra, s32 i8) { Write(wxString::Format("cuflt %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i8)); } //0 - 8 - virtual void BRZ(OP_REG rt, OP_sIMM i16) + void BRZ(u32 rt, s32 i16) { Write(wxString::Format("brz %s,0x%x", spu_reg_name[rt], DisAsmBranchTarget(i16))); } - virtual void STQA(OP_REG rt, OP_sIMM i16) + void STQA(u32 rt, s32 i16) { Write(wxString::Format("stqa %s,0x%x", spu_reg_name[rt], DisAsmBranchTarget(i16))); } - virtual void BRNZ(OP_REG rt, OP_sIMM i16) + void BRNZ(u32 rt, s32 i16) { Write(wxString::Format("brnz %s,0x%x", spu_reg_name[rt], DisAsmBranchTarget(i16))); } - virtual void BRHZ(OP_REG rt, OP_sIMM i16) + void BRHZ(u32 rt, s32 i16) { Write(wxString::Format("brhz %s,0x%x", spu_reg_name[rt], DisAsmBranchTarget(i16))); } - virtual void BRHNZ(OP_REG rt, OP_sIMM i16) + void BRHNZ(u32 rt, s32 i16) { Write(wxString::Format("brhnz %s,0x%x", spu_reg_name[rt], DisAsmBranchTarget(i16))); } - virtual void STQR(OP_REG rt, OP_sIMM i16) + void STQR(u32 rt, s32 i16) { Write(wxString::Format("stqr %s,0x%x", spu_reg_name[rt], DisAsmBranchTarget(i16))); } - virtual void BRA(OP_sIMM i16) + void BRA(s32 i16) { Write(wxString::Format("bra 0x%x", DisAsmBranchTarget(i16))); } - virtual void LQA(OP_REG rt, OP_sIMM i16) + void LQA(u32 rt, s32 i16) { Write(wxString::Format("lqa %s,0x%x", spu_reg_name[rt], DisAsmBranchTarget(i16))); } - virtual void BRASL(OP_REG rt, OP_sIMM i16) + void BRASL(u32 rt, s32 i16) { Write(wxString::Format("brasl %s,0x%x", spu_reg_name[rt], DisAsmBranchTarget(i16))); } - virtual void BR(OP_sIMM i16) + void BR(s32 i16) { Write(wxString::Format("br 0x%x", DisAsmBranchTarget(i16))); } - virtual void FSMBI(OP_REG rt, OP_sIMM i16) + void FSMBI(u32 rt, s32 i16) { Write(wxString::Format("fsmbi %s,%d", spu_reg_name[rt], i16)); } - virtual void BRSL(OP_REG rt, OP_sIMM i16) + void BRSL(u32 rt, s32 i16) { Write(wxString::Format("brsl %s,0x%x", spu_reg_name[rt], DisAsmBranchTarget(i16))); } - virtual void LQR(OP_REG rt, OP_sIMM i16) + void LQR(u32 rt, s32 i16) { Write(wxString::Format("lqr %s,0x%x", spu_reg_name[rt], DisAsmBranchTarget(i16))); } - virtual void IL(OP_REG rt, OP_sIMM i16) + void IL(u32 rt, s32 i16) { Write(wxString::Format("il %s,%d", spu_reg_name[rt], i16)); } - virtual void ILHU(OP_REG rt, OP_sIMM i16) + void ILHU(u32 rt, s32 i16) { Write(wxString::Format("ilhu %s,%d", spu_reg_name[rt], i16)); } - virtual void ILH(OP_REG rt, OP_sIMM i16) + void ILH(u32 rt, s32 i16) { Write(wxString::Format("ilh %s,%d", spu_reg_name[rt], i16)); } - virtual void IOHL(OP_REG rt, OP_sIMM i16) + void IOHL(u32 rt, s32 i16) { Write(wxString::Format("iolh %s,%d", spu_reg_name[rt], i16)); } //0 - 7 - virtual void ORI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void ORI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("ori %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void ORHI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void ORHI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("orhi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void ORBI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void ORBI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("orbi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void SFI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void SFI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("sfi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void SFHI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void SFHI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("sfhi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void ANDI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void ANDI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("andi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void ANDHI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void ANDHI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("andhi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void ANDBI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void ANDBI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("andbi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void AI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void AI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("ai %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void AHI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void AHI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("ahi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void STQD(OP_REG rt, OP_sIMM i10, OP_REG ra) + void STQD(u32 rt, s32 i10, u32 ra) { Write(wxString::Format("stqd %s,%d(%s)", spu_reg_name[rt], i10, spu_reg_name[ra])); } - virtual void LQD(OP_REG rt, OP_sIMM i10, OP_REG ra) + void LQD(u32 rt, s32 i10, u32 ra) { Write(wxString::Format("lqd %s,%d(%s)", spu_reg_name[rt], i10, spu_reg_name[ra])); } - virtual void XORI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void XORI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("xori %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void XORHI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void XORHI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("xorhi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void XORBI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void XORBI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("xorbi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void CGTI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void CGTI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("cgti %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void CGTHI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void CGTHI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("cgthi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void CGTBI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void CGTBI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("cgtbi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void HGTI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void HGTI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("hgti %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void CLGTI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void CLGTI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("clgti %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void CLGTHI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void CLGTHI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("clgthi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void CLGTBI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void CLGTBI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("clgtbi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void HLGTI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void HLGTI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("hlgti %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void MPYI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void MPYI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("mpyi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void MPYUI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void MPYUI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("mpyui %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void CEQI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void CEQI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("ceqi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void CEQHI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void CEQHI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("ceqhi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void CEQBI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void CEQBI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("ceqbi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } - virtual void HEQI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void HEQI(u32 rt, u32 ra, s32 i10) { Write(wxString::Format("heqi %s,%s,%d", spu_reg_name[rt], spu_reg_name[ra], i10)); } //0 - 6 - virtual void HBRA(OP_sIMM ro, OP_sIMM i16) + void HBRA(s32 ro, s32 i16) { Write(wxString::Format("hbra 0x%x,0x%x", DisAsmBranchTarget(ro), DisAsmBranchTarget(i16))); } - virtual void HBRR(OP_sIMM ro, OP_sIMM i16) + void HBRR(s32 ro, s32 i16) { Write(wxString::Format("hbrr 0x%x,0x%x", DisAsmBranchTarget(ro), DisAsmBranchTarget(i16))); } - virtual void ILA(OP_REG rt, OP_sIMM i18) + void ILA(u32 rt, s32 i18) { Write(wxString::Format("ila %s,%d", spu_reg_name[rt], i18)); } //0 - 3 - virtual void SELB(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt) + void SELB(u32 rc, u32 ra, u32 rb, u32 rt) { Write(wxString::Format("selb %s,%s,%s,%s", spu_reg_name[rc], spu_reg_name[ra], spu_reg_name[rb], spu_reg_name[rt])); } - virtual void SHUFB(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt) + void SHUFB(u32 rc, u32 ra, u32 rb, u32 rt) { Write(wxString::Format("shufb %s,%s,%s,%s", spu_reg_name[rc], spu_reg_name[ra], spu_reg_name[rb], spu_reg_name[rt])); } - virtual void MPYA(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt) + void MPYA(u32 rc, u32 ra, u32 rb, u32 rt) { Write(wxString::Format("mpya %s,%s,%s,%s", spu_reg_name[rc], spu_reg_name[ra], spu_reg_name[rb], spu_reg_name[rt])); } - virtual void FNMS(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt) + void FNMS(u32 rc, u32 ra, u32 rb, u32 rt) { Write(wxString::Format("fnms %s,%s,%s,%s", spu_reg_name[rc], spu_reg_name[ra], spu_reg_name[rb], spu_reg_name[rt])); } - virtual void FMA(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt) + void FMA(u32 rc, u32 ra, u32 rb, u32 rt) { Write(wxString::Format("fma %s,%s,%s,%s", spu_reg_name[rc], spu_reg_name[ra], spu_reg_name[rb], spu_reg_name[rt])); } - virtual void FMS(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt) + void FMS(u32 rc, u32 ra, u32 rb, u32 rt) { Write(wxString::Format("fms %s,%s,%s,%s", spu_reg_name[rc], spu_reg_name[ra], spu_reg_name[rb], spu_reg_name[rt])); } - virtual void UNK(const s32 code, const s32 opcode, const s32 gcode) + void UNK(u32 code, u32 opcode, u32 gcode) { - Write(wxString::Format("Unknown/Illegal opcode! (0x%08x)", code)); + Write(wxString::Format("Unknown/Illegal opcode! (0x%08x, 0x%x, 0x%x)", code, opcode, gcode)); } }; diff --git a/rpcs3/Emu/Cell/SPUInstrTable.h b/rpcs3/Emu/Cell/SPUInstrTable.h new file mode 100644 index 0000000000..e8446b18a4 --- /dev/null +++ b/rpcs3/Emu/Cell/SPUInstrTable.h @@ -0,0 +1,258 @@ +#pragma once +#include "PPCInstrTable.h" +#include "PPCDecoder.h" +#include "SPUOpcodes.h" + +namespace SPU_instr +{ + static CodeField<4, 10> RC(FIELD_R_GPR); + static CodeField<25, 31> RT(FIELD_R_GPR); + static CodeField<18, 24> RA(FIELD_R_GPR); + static CodeField<11, 17> RB(FIELD_R_GPR); + + static CodeField<11, 17> i7; + static CodeField<10, 17> i8; + static CodeField<8, 17> i10; + static CodeField<9, 24> i16; + static CodeField<7, 24> i18; + + static CodeFieldSigned<11, 17> si7; + static CodeFieldSigned<10, 17> si8; + static CodeFieldSigned<8, 17> si10; + static CodeFieldSignedOffset<8, 17, 4> si10s4; + static CodeFieldSigned<9, 24> si16; + static CodeFieldOffset<9, 24, 2> i16s2; + static CodeFieldSigned<7, 24> si18; + + static CodeField<16, 17> ROH; + static CodeField<25, 31> ROL; + static DoubleCodeField<16, 17, 25, 31, 8> RO; + + static CodeField<0, 3> RRR; + static CodeField<0, 6> RI18; + static CodeField<0, 7> RI10; + static CodeField<0, 8> RI16; + static CodeField<0, 9> RI8; + static CodeField<0, 10> RI7; + static CodeField<0, 10> RR; + + static CodeField<18, 31> L_18_31; + static CodeField<11> L_11; + + static auto rrr_list = new_list(RRR); + static auto ri18_list = new_list(rrr_list, RI18); + static auto ri10_list = new_list(ri18_list, RI10); + static auto ri16_list = new_list(ri10_list, RI16); + static auto ri8_list = new_list(ri16_list, RI8); + static auto ri7_list = new_list(ri8_list, RI7, instr_bind(&SPU_Opcodes::UNK, GetCode, RRR, RI7)); + + #define bind_instr(list, name, ...) \ + static const auto& name = make_instr(list, #name, &SPU_Opcodes::name, ##__VA_ARGS__) + + bind_instr(ri7_list, STOP, L_18_31); + bind_instr(ri7_list, LNOP); + bind_instr(ri7_list, SYNC, L_11); + bind_instr(ri7_list, DSYNC); + bind_instr(ri7_list, MFSPR, RT, RA); + bind_instr(ri7_list, RDCH, RT, RA); + bind_instr(ri7_list, RCHCNT, RT, RA); + bind_instr(ri7_list, SF, RT, RA, RB); + bind_instr(ri7_list, OR, RT, RA, RB); + bind_instr(ri7_list, BG, RT, RA, RB); + bind_instr(ri7_list, SFH, RT, RA, RB); + bind_instr(ri7_list, NOR, RT, RA, RB); + bind_instr(ri7_list, ABSDB, RT, RA, RB); + bind_instr(ri7_list, ROT, RT, RA, RB); + bind_instr(ri7_list, ROTM, RT, RA, RB); + bind_instr(ri7_list, ROTMA, RT, RA, RB); + bind_instr(ri7_list, SHL, RT, RA, RB); + bind_instr(ri7_list, ROTH, RT, RA, RB); + bind_instr(ri7_list, ROTHM, RT, RA, RB); + bind_instr(ri7_list, ROTMAH, RT, RA, RB); + bind_instr(ri7_list, SHLH, RT, RA, RB); + bind_instr(ri7_list, ROTI, RT, RA, RB); + bind_instr(ri7_list, ROTMI, RT, RA, RB); + bind_instr(ri7_list, ROTMAI, RT, RA, RB); + bind_instr(ri7_list, SHLI, RT, RA, i7); + bind_instr(ri7_list, ROTHI, RT, RA, i7); + bind_instr(ri7_list, ROTHMI, RT, RA, i7); + bind_instr(ri7_list, ROTMAHI, RT, RA, i7); + bind_instr(ri7_list, SHLHI, RT, RA, i7); + bind_instr(ri7_list, A, RT, RA, RB); + bind_instr(ri7_list, AND, RT, RA, RB); + bind_instr(ri7_list, CG, RT, RA, RB); + bind_instr(ri7_list, AH, RT, RA, RB); + bind_instr(ri7_list, NAND, RT, RA, RB); + bind_instr(ri7_list, AVGB, RT, RA, RB); + bind_instr(ri7_list, MTSPR, RT, RA); + bind_instr(ri7_list, WRCH, RA, RT); + bind_instr(ri7_list, BIZ, RT, RA); + bind_instr(ri7_list, BINZ, RT, RA); + bind_instr(ri7_list, BIHZ, RT, RA); + bind_instr(ri7_list, BIHNZ, RT, RA); + bind_instr(ri7_list, STOPD, RT, RA, RB); + bind_instr(ri7_list, STQX, RT, RA, RB); + bind_instr(ri7_list, BI, RA); + bind_instr(ri7_list, BISL, RT, RA); + bind_instr(ri7_list, IRET, RA); + bind_instr(ri7_list, BISLED, RT, RA); + bind_instr(ri7_list, HBR, L_11, RO, RA); + bind_instr(ri7_list, GB, RT, RA); + bind_instr(ri7_list, GBH, RT, RA); + bind_instr(ri7_list, GBB, RT, RA); + bind_instr(ri7_list, FSM, RT, RA); + bind_instr(ri7_list, FSMH, RT, RA); + bind_instr(ri7_list, FSMB, RT, RA); + bind_instr(ri7_list, FREST, RT, RA); + bind_instr(ri7_list, FRSQEST, RT, RA); + bind_instr(ri7_list, LQX, RT, RA, RB); + bind_instr(ri7_list, ROTQBYBI, RT, RA, RB); + bind_instr(ri7_list, ROTQMBYBI, RT, RA, RB); + bind_instr(ri7_list, SHLQBYBI, RT, RA, RB); + bind_instr(ri7_list, CBX, RT, RA, RB); + bind_instr(ri7_list, CHX, RT, RA, RB); + bind_instr(ri7_list, CWX, RT, RA, RB); + bind_instr(ri7_list, CDX, RT, RA, RB); + bind_instr(ri7_list, ROTQBI, RT, RA, RB); + bind_instr(ri7_list, ROTQMBI, RT, RA, RB); + bind_instr(ri7_list, SHLQBI, RT, RA, RB); + bind_instr(ri7_list, ROTQBY, RT, RA, RB); + bind_instr(ri7_list, ROTQMBY, RT, RA, RB); + bind_instr(ri7_list, SHLQBY, RT, RA, RB); + bind_instr(ri7_list, ORX, RT, RA); + bind_instr(ri7_list, CBD, RT, RA, si7); + bind_instr(ri7_list, CHD, RT, RA, si7); + bind_instr(ri7_list, CWD, RT, RA, si7); + bind_instr(ri7_list, CDD, RT, RA, si7); + bind_instr(ri7_list, ROTQBII, RT, RA, i7); + bind_instr(ri7_list, ROTQMBII, RT, RA, i7); + bind_instr(ri7_list, SHLQBII, RT, RA, i7); + bind_instr(ri7_list, ROTQBYI, RT, RA, i7); + bind_instr(ri7_list, ROTQMBYI, RT, RA, i7); + bind_instr(ri7_list, SHLQBYI, RT, RA, i7); + bind_instr(ri7_list, NOP, RT); + bind_instr(ri7_list, CGT, RT, RA, RB); + bind_instr(ri7_list, XOR, RT, RA, RB); + bind_instr(ri7_list, CGTH, RT, RA, RB); + bind_instr(ri7_list, EQV, RT, RA, RB); + bind_instr(ri7_list, CGTB, RT, RA, RB); + bind_instr(ri7_list, SUMB, RT, RA, RB); + bind_instr(ri7_list, HGT, RT, RA, RB); + bind_instr(ri7_list, CLZ, RT, RA); + bind_instr(ri7_list, XSWD, RT, RA); + bind_instr(ri7_list, XSHW, RT, RA); + bind_instr(ri7_list, CNTB, RT, RA); + bind_instr(ri7_list, XSBH, RT, RA); + bind_instr(ri7_list, CLGT, RT, RA, RB); + bind_instr(ri7_list, ANDC, RT, RA, RB); + bind_instr(ri7_list, FCGT, RT, RA, RB); + bind_instr(ri7_list, DFCGT, RT, RA, RB); + bind_instr(ri7_list, FA, RT, RA, RB); + bind_instr(ri7_list, FS, RT, RA, RB); + bind_instr(ri7_list, FM, RT, RA, RB); + bind_instr(ri7_list, CLGTH, RT, RA, RB); + bind_instr(ri7_list, ORC, RT, RA, RB); + bind_instr(ri7_list, FCMGT, RT, RA, RB); + bind_instr(ri7_list, DFCMGT, RT, RA, RB); + bind_instr(ri7_list, DFA, RT, RA, RB); + bind_instr(ri7_list, DFS, RT, RA, RB); + bind_instr(ri7_list, DFM, RT, RA, RB); + bind_instr(ri7_list, CLGTB, RT, RA, RB); + bind_instr(ri7_list, HLGT, RT, RA, RB); + bind_instr(ri7_list, DFMA, RT, RA, RB); + bind_instr(ri7_list, DFMS, RT, RA, RB); + bind_instr(ri7_list, DFNMS, RT, RA, RB); + bind_instr(ri7_list, DFNMA, RT, RA, RB); + bind_instr(ri7_list, CEQ, RT, RA, RB); + bind_instr(ri7_list, MPYHHU, RT, RA, RB); + bind_instr(ri7_list, ADDX, RT, RA, RB); + bind_instr(ri7_list, SFX, RT, RA, RB); + bind_instr(ri7_list, CGX, RT, RA, RB); + bind_instr(ri7_list, BGX, RT, RA, RB); + bind_instr(ri7_list, MPYHHA, RT, RA, RB); + bind_instr(ri7_list, MPYHHAU, RT, RA, RB); + bind_instr(ri7_list, FSCRRD, RT); + bind_instr(ri7_list, FESD, RT, RA); + bind_instr(ri7_list, FRDS, RT, RA); + bind_instr(ri7_list, FSCRWR, RT, RA); + bind_instr(ri7_list, DFTSV, RT, RA, i7); + bind_instr(ri7_list, FCEQ, RT, RA, RB); + bind_instr(ri7_list, DFCEQ, RT, RA, RB); + bind_instr(ri7_list, MPY, RT, RA, RB); + bind_instr(ri7_list, MPYH, RT, RA, RB); + bind_instr(ri7_list, MPYHH, RT, RA, RB); + bind_instr(ri7_list, MPYS, RT, RA, RB); + bind_instr(ri7_list, CEQH, RT, RA, RB); + bind_instr(ri7_list, FCMEQ, RT, RA, RB); + bind_instr(ri7_list, DFCMEQ, RT, RA, RB); + bind_instr(ri7_list, MPYU, RT, RA, RB); + bind_instr(ri7_list, CEQB, RT, RA, RB); + bind_instr(ri7_list, FI, RT, RA, RB); + bind_instr(ri7_list, HEQ, RT, RA, RB); + + bind_instr(ri8_list, CFLTS, RT, RA, i8); + bind_instr(ri8_list, CFLTU, RT, RA, i8); + bind_instr(ri8_list, CSFLT, RT, RA, i8); + bind_instr(ri8_list, CUFLT, RT, RA, i8); + + bind_instr(ri16_list, BRZ, RT, si16); + bind_instr(ri16_list, STQA, RT, si16); + bind_instr(ri16_list, BRNZ, RT, si16); + bind_instr(ri16_list, BRHZ, RT, si16); + bind_instr(ri16_list, BRHNZ, RT, si16); + bind_instr(ri16_list, STQR, RT, i16); + bind_instr(ri16_list, BRA, si16); + bind_instr(ri16_list, LQA, RT, si16); + bind_instr(ri16_list, BRASL, RT, si16); + bind_instr(ri16_list, BR, si16); + bind_instr(ri16_list, FSMBI, RT, i16); + bind_instr(ri16_list, BRSL, RT, si16); + bind_instr(ri16_list, LQR, RT, si16); + bind_instr(ri16_list, IL, RT, si16); + bind_instr(ri16_list, ILHU, RT, i16); + bind_instr(ri16_list, ILH, RT, i16); + bind_instr(ri16_list, IOHL, RT, i16); + + bind_instr(ri10_list, ORI, RT, RA, si10); + bind_instr(ri10_list, ORHI, RT, RA, si10); + bind_instr(ri10_list, ORBI, RT, RA, i10); + bind_instr(ri10_list, SFI, RT, RA, si10); + bind_instr(ri10_list, SFHI, RT, RA, si10); + bind_instr(ri10_list, ANDI, RT, RA, si10); + bind_instr(ri10_list, ANDHI, RT, RA, si10); + bind_instr(ri10_list, ANDBI, RT, RA, i10); + bind_instr(ri10_list, AI, RT, RA, si10); + bind_instr(ri10_list, AHI, RT, RA, si10); + bind_instr(ri10_list, STQD, RT, si10s4, RA); + bind_instr(ri10_list, LQD, RT, si10s4, RA); + bind_instr(ri10_list, XORI, RT, RA, si10); + bind_instr(ri10_list, XORHI, RT, RA, si10); + bind_instr(ri10_list, XORBI, RT, RA, i10); + bind_instr(ri10_list, CGTI, RT, RA, si10); + bind_instr(ri10_list, CGTHI, RT, RA, si10); + bind_instr(ri10_list, CGTBI, RT, RA, i10); + bind_instr(ri10_list, HGTI, RT, RA, si10); + bind_instr(ri10_list, CLGTI, RT, RA, si10); + bind_instr(ri10_list, CLGTHI, RT, RA, si10); + bind_instr(ri10_list, CLGTBI, RT, RA, i10); + bind_instr(ri10_list, HLGTI, RT, RA, si10); + bind_instr(ri10_list, MPYI, RT, RA, si10); + bind_instr(ri10_list, MPYUI, RT, RA, si10); + bind_instr(ri10_list, CEQI, RT, RA, si10); + bind_instr(ri10_list, CEQHI, RT, RA, si10); + bind_instr(ri10_list, CEQBI, RT, RA, i10); + bind_instr(ri10_list, HEQI, RT, RA, si10); + + bind_instr(ri18_list, HBRA, RO, i16s2); + bind_instr(ri18_list, HBRR, RO, si16); + bind_instr(ri18_list, ILA, RT, i18); + + bind_instr(rrr_list, SELB, RC, RA, RB, RT); + bind_instr(rrr_list, SHUFB, RC, RA, RB, RT); + bind_instr(rrr_list, MPYA, RC, RA, RB, RT); + bind_instr(rrr_list, FNMS, RC, RA, RB, RT); + bind_instr(rrr_list, FMA, RC, RA, RB, RT); + bind_instr(rrr_list, FMS, RC, RA, RB, RT); + + #undef bind_instr +}; \ No newline at end of file diff --git a/rpcs3/Emu/Cell/SPUInterpreter.h b/rpcs3/Emu/Cell/SPUInterpreter.h index 9098e80106..39952916ee 100644 --- a/rpcs3/Emu/Cell/SPUInterpreter.h +++ b/rpcs3/Emu/Cell/SPUInterpreter.h @@ -5,8 +5,7 @@ #include "Emu/Cell/SPUThread.h" #include "Emu/SysCalls/SysCalls.h" -#define START_OPCODES_GROUP(x) -#define END_OPCODES_GROUP(x) +#define UNIMPLEMENTED() UNK(__FUNCTION__) class SPU_Interpreter : public SPU_Opcodes { @@ -19,128 +18,128 @@ public: } private: - virtual void Exit(){} + void Exit(){} - virtual void SysCall() + void SysCall() { } //0 - 10 - virtual void STOP(OP_uIMM code) + void STOP(u32 code) { Emu.Pause(); } - virtual void LNOP() + void LNOP() { } - virtual void SYNC(OP_uIMM Cbit) + void SYNC(u32 Cbit) { - // TODO + UNIMPLEMENTED(); } - virtual void DSYNC() + void DSYNC() { - // TODO + UNIMPLEMENTED(); } - virtual void MFSPR(OP_REG rt, OP_REG sa) + void MFSPR(u32 rt, u32 sa) { - // TODO + UNIMPLEMENTED(); } - virtual void RDCH(OP_REG rt, OP_REG ra) + void RDCH(u32 rt, u32 ra) { CPU.ReadChannel(CPU.GPR[rt], ra); } - virtual void RCHCNT(OP_REG rt, OP_REG ra) + void RCHCNT(u32 rt, u32 ra) { CPU.GPR[rt].Reset(); CPU.GPR[rt]._u32[0] = CPU.GetChannelCount(ra); } - virtual void SF(OP_REG rt, OP_REG ra, OP_REG rb) + void SF(u32 rt, u32 ra, u32 rb) { CPU.GPR[rt]._u32[0] = CPU.GPR[rb]._u32[0] + ~CPU.GPR[ra]._u32[0] + 1; CPU.GPR[rt]._u32[1] = CPU.GPR[rb]._u32[1] + ~CPU.GPR[ra]._u32[1] + 1; CPU.GPR[rt]._u32[2] = CPU.GPR[rb]._u32[2] + ~CPU.GPR[ra]._u32[2] + 1; CPU.GPR[rt]._u32[3] = CPU.GPR[rb]._u32[3] + ~CPU.GPR[ra]._u32[3] + 1; } - virtual void OR(OP_REG rt, OP_REG ra, OP_REG rb) + void OR(u32 rt, u32 ra, u32 rb) { CPU.GPR[rt]._u32[0] = CPU.GPR[ra]._u32[0] | CPU.GPR[rb]._u32[0]; CPU.GPR[rt]._u32[1] = CPU.GPR[ra]._u32[1] | CPU.GPR[rb]._u32[1]; CPU.GPR[rt]._u32[2] = CPU.GPR[ra]._u32[2] | CPU.GPR[rb]._u32[2]; CPU.GPR[rt]._u32[3] = CPU.GPR[ra]._u32[3] | CPU.GPR[rb]._u32[3]; } - virtual void BG(OP_REG rt, OP_REG ra, OP_REG rb) + void BG(u32 rt, u32 ra, u32 rb) { CPU.GPR[rt]._u32[0] = CPU.GPR[ra]._u32[0] > CPU.GPR[rb]._u32[0] ? 0 : 1; CPU.GPR[rt]._u32[1] = CPU.GPR[ra]._u32[1] > CPU.GPR[rb]._u32[1] ? 0 : 1; CPU.GPR[rt]._u32[2] = CPU.GPR[ra]._u32[2] > CPU.GPR[rb]._u32[2] ? 0 : 1; CPU.GPR[rt]._u32[3] = CPU.GPR[ra]._u32[3] > CPU.GPR[rb]._u32[3] ? 0 : 1; } - virtual void SFH(OP_REG rt, OP_REG ra, OP_REG rb) + void SFH(u32 rt, u32 ra, u32 rb) { for (int h = 0; h < 8; h++) CPU.GPR[rt]._u16[h] = CPU.GPR[rb]._u16[h] - CPU.GPR[ra]._u16[h]; } - virtual void NOR(OP_REG rt, OP_REG ra, OP_REG rb) + void NOR(u32 rt, u32 ra, u32 rb) { CPU.GPR[rt]._u32[0] = ~(CPU.GPR[ra]._u32[0] | CPU.GPR[rb]._u32[0]); CPU.GPR[rt]._u32[1] = ~(CPU.GPR[ra]._u32[1] | CPU.GPR[rb]._u32[1]); CPU.GPR[rt]._u32[2] = ~(CPU.GPR[ra]._u32[2] | CPU.GPR[rb]._u32[2]); CPU.GPR[rt]._u32[3] = ~(CPU.GPR[ra]._u32[3] | CPU.GPR[rb]._u32[3]); } - virtual void ABSDB(OP_REG rt, OP_REG ra, OP_REG rb) + void ABSDB(u32 rt, u32 ra, u32 rb) { for (int b = 0; b < 16; b++) CPU.GPR[rt]._u8[b] = CPU.GPR[rb]._u8[b] > CPU.GPR[ra]._u8[b] ? CPU.GPR[rb]._u8[b] - CPU.GPR[ra]._u8[b] : CPU.GPR[ra]._u8[b] - CPU.GPR[rb]._u8[b]; } - virtual void ROT(OP_REG rt, OP_REG ra, OP_REG rb) + void ROT(u32 rt, u32 ra, u32 rb) { CPU.GPR[rt]._u32[0] = (CPU.GPR[ra]._u32[0] << (CPU.GPR[rb]._u32[0] & 0x1f)) | (CPU.GPR[ra]._u32[0] >> (32 - (CPU.GPR[rb]._u32[0] & 0x1f))); CPU.GPR[rt]._u32[1] = (CPU.GPR[ra]._u32[1] << (CPU.GPR[rb]._u32[1] & 0x1f)) | (CPU.GPR[ra]._u32[1] >> (32 - (CPU.GPR[rb]._u32[1] & 0x1f))); CPU.GPR[rt]._u32[2] = (CPU.GPR[ra]._u32[2] << (CPU.GPR[rb]._u32[2] & 0x1f)) | (CPU.GPR[ra]._u32[2] >> (32 - (CPU.GPR[rb]._u32[2] & 0x1f))); CPU.GPR[rt]._u32[3] = (CPU.GPR[ra]._u32[3] << (CPU.GPR[rb]._u32[3] & 0x1f)) | (CPU.GPR[ra]._u32[3] >> (32 - (CPU.GPR[rb]._u32[3] & 0x1f))); } - virtual void ROTM(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTM(u32 rt, u32 ra, u32 rb) { CPU.GPR[rt]._u32[0] = ((0 - CPU.GPR[rb]._u32[0]) % 64) < 32 ? CPU.GPR[ra]._u32[0] >> ((0 - CPU.GPR[rb]._u32[0]) % 64) : 0; CPU.GPR[rt]._u32[1] = ((0 - CPU.GPR[rb]._u32[1]) % 64) < 32 ? CPU.GPR[ra]._u32[1] >> ((0 - CPU.GPR[rb]._u32[1]) % 64) : 0; CPU.GPR[rt]._u32[2] = ((0 - CPU.GPR[rb]._u32[2]) % 64) < 32 ? CPU.GPR[ra]._u32[2] >> ((0 - CPU.GPR[rb]._u32[2]) % 64) : 0; CPU.GPR[rt]._u32[3] = ((0 - CPU.GPR[rb]._u32[3]) % 64) < 32 ? CPU.GPR[ra]._u32[3] >> ((0 - CPU.GPR[rb]._u32[3]) % 64) : 0; } - virtual void ROTMA(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTMA(u32 rt, u32 ra, u32 rb) { CPU.GPR[rt]._i32[0] = ((0 - CPU.GPR[rb]._i32[0]) % 64) < 32 ? CPU.GPR[ra]._i32[0] >> ((0 - CPU.GPR[rb]._i32[0]) % 64) : CPU.GPR[ra]._i32[0] >> 31; CPU.GPR[rt]._i32[1] = ((0 - CPU.GPR[rb]._i32[1]) % 64) < 32 ? CPU.GPR[ra]._i32[1] >> ((0 - CPU.GPR[rb]._i32[1]) % 64) : CPU.GPR[ra]._i32[1] >> 31; CPU.GPR[rt]._i32[2] = ((0 - CPU.GPR[rb]._i32[2]) % 64) < 32 ? CPU.GPR[ra]._i32[2] >> ((0 - CPU.GPR[rb]._i32[2]) % 64) : CPU.GPR[ra]._i32[2] >> 31; CPU.GPR[rt]._i32[3] = ((0 - CPU.GPR[rb]._i32[3]) % 64) < 32 ? CPU.GPR[ra]._i32[3] >> ((0 - CPU.GPR[rb]._i32[3]) % 64) : CPU.GPR[ra]._i32[3] >> 31; } - virtual void SHL(OP_REG rt, OP_REG ra, OP_REG rb) + void SHL(u32 rt, u32 ra, u32 rb) { CPU.GPR[rt]._u32[0] = (CPU.GPR[rb]._u32[0] & 0x3f) > 31 ? 0 : CPU.GPR[ra]._u32[0] << (CPU.GPR[rb]._u32[0] & 0x3f); CPU.GPR[rt]._u32[1] = (CPU.GPR[rb]._u32[1] & 0x3f) > 31 ? 0 : CPU.GPR[ra]._u32[1] << (CPU.GPR[rb]._u32[1] & 0x3f); CPU.GPR[rt]._u32[2] = (CPU.GPR[rb]._u32[2] & 0x3f) > 31 ? 0 : CPU.GPR[ra]._u32[2] << (CPU.GPR[rb]._u32[2] & 0x3f); CPU.GPR[rt]._u32[3] = (CPU.GPR[rb]._u32[3] & 0x3f) > 31 ? 0 : CPU.GPR[ra]._u32[3] << (CPU.GPR[rb]._u32[3] & 0x3f); } - virtual void ROTH(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTH(u32 rt, u32 ra, u32 rb) { for (int h = 0; h < 8; h++) CPU.GPR[rt]._u16[h] = (CPU.GPR[ra]._u16[h] << (CPU.GPR[rb]._u16[h] & 0xf)) | (CPU.GPR[ra]._u16[h] >> (16 - (CPU.GPR[rb]._u32[h] & 0xf))); } - virtual void ROTHM(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTHM(u32 rt, u32 ra, u32 rb) { for (int h = 0; h < 8; h++) CPU.GPR[rt]._u16[h] = ((0 - CPU.GPR[rb]._u16[h]) % 32) < 16 ? CPU.GPR[ra]._u16[h] >> ((0 - CPU.GPR[rb]._u16[h]) % 32) : 0; } - virtual void ROTMAH(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTMAH(u32 rt, u32 ra, u32 rb) { for (int h = 0; h < 8; h++) CPU.GPR[rt]._i16[h] = ((0 - CPU.GPR[rb]._i16[h]) % 32) < 16 ? CPU.GPR[ra]._i16[h] >> ((0 - CPU.GPR[rb]._i16[h]) % 32) : CPU.GPR[ra]._i16[h] >> 15; } - virtual void SHLH(OP_REG rt, OP_REG ra, OP_REG rb) + void SHLH(u32 rt, u32 ra, u32 rb) { for (int h = 0; h < 8; h++) CPU.GPR[rt]._u16[h] = (CPU.GPR[rb]._u16[h] & 0x1f) > 15 ? 0 : CPU.GPR[ra]._u16[h] << (CPU.GPR[rb]._u16[h] & 0x3f); } - virtual void ROTI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void ROTI(u32 rt, u32 ra, s32 i7) { const int nRot = i7 & 0x1f; CPU.GPR[rt]._u32[0] = (CPU.GPR[ra]._u32[0] << nRot) | (CPU.GPR[ra]._u32[0] >> (32 - nRot)); @@ -148,7 +147,7 @@ private: CPU.GPR[rt]._u32[2] = (CPU.GPR[ra]._u32[2] << nRot) | (CPU.GPR[ra]._u32[2] >> (32 - nRot)); CPU.GPR[rt]._u32[3] = (CPU.GPR[ra]._u32[3] << nRot) | (CPU.GPR[ra]._u32[3] >> (32 - nRot)); } - virtual void ROTMI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void ROTMI(u32 rt, u32 ra, s32 i7) { const int nRot = (0 - i7) % 64; CPU.GPR[rt]._u32[0] = nRot < 32 ? CPU.GPR[ra]._u32[0] >> nRot : 0; @@ -156,7 +155,7 @@ private: CPU.GPR[rt]._u32[2] = nRot < 32 ? CPU.GPR[ra]._u32[2] >> nRot : 0; CPU.GPR[rt]._u32[3] = nRot < 32 ? CPU.GPR[ra]._u32[3] >> nRot : 0; } - virtual void ROTMAI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void ROTMAI(u32 rt, u32 ra, s32 i7) { const int nRot = (0 - i7) % 64; CPU.GPR[rt]._i32[0] = nRot < 32 ? CPU.GPR[ra]._i32[0] >> nRot : CPU.GPR[ra]._i32[0] >> 31; @@ -164,7 +163,7 @@ private: CPU.GPR[rt]._i32[2] = nRot < 32 ? CPU.GPR[ra]._i32[2] >> nRot : CPU.GPR[ra]._i32[2] >> 31; CPU.GPR[rt]._i32[3] = nRot < 32 ? CPU.GPR[ra]._i32[3] >> nRot : CPU.GPR[ra]._i32[3] >> 31; } - virtual void SHLI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void SHLI(u32 rt, u32 ra, s32 i7) { const u32 s = i7 & 0x3f; @@ -181,133 +180,133 @@ private: CPU.GPR[rt]._u32[j] = r; } } - virtual void ROTHI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void ROTHI(u32 rt, u32 ra, s32 i7) { const int nRot = i7 & 0xf; for (int h = 0; h < 8; h++) CPU.GPR[rt]._u16[h] = (CPU.GPR[ra]._u16[h] << nRot) | (CPU.GPR[ra]._u16[h] >> (16 - nRot)); } - virtual void ROTHMI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void ROTHMI(u32 rt, u32 ra, s32 i7) { const int nRot = (0 - i7) % 32; for (int h = 0; h < 8; h++) CPU.GPR[rt]._u16[h] = nRot < 16 ? CPU.GPR[ra]._u16[h] >> nRot : 0; } - virtual void ROTMAHI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void ROTMAHI(u32 rt, u32 ra, s32 i7) { const int nRot = (0 - i7) % 32; for (int h = 0; h < 8; h++) CPU.GPR[rt]._i16[h] = nRot < 16 ? CPU.GPR[ra]._i16[h] >> nRot : CPU.GPR[ra]._i16[h] >> 15; } - virtual void SHLHI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void SHLHI(u32 rt, u32 ra, s32 i7) { const int nRot = i7 & 0x1f; for (int h = 0; h < 8; h++) CPU.GPR[rt]._u16[0] = nRot > 15 ? 0 : CPU.GPR[ra]._u16[0] << nRot; } - virtual void A(OP_REG rt, OP_REG ra, OP_REG rb) + void A(u32 rt, u32 ra, u32 rb) { CPU.GPR[rt]._u32[0] = CPU.GPR[ra]._u32[0] + CPU.GPR[rb]._u32[0]; CPU.GPR[rt]._u32[1] = CPU.GPR[ra]._u32[1] + CPU.GPR[rb]._u32[1]; CPU.GPR[rt]._u32[2] = CPU.GPR[ra]._u32[2] + CPU.GPR[rb]._u32[2]; CPU.GPR[rt]._u32[3] = CPU.GPR[ra]._u32[3] + CPU.GPR[rb]._u32[3]; } - virtual void AND(OP_REG rt, OP_REG ra, OP_REG rb) + void AND(u32 rt, u32 ra, u32 rb) { CPU.GPR[rt]._u32[0] = CPU.GPR[ra]._u32[0] & CPU.GPR[rb]._u32[0]; CPU.GPR[rt]._u32[1] = CPU.GPR[ra]._u32[1] & CPU.GPR[rb]._u32[1]; CPU.GPR[rt]._u32[2] = CPU.GPR[ra]._u32[2] & CPU.GPR[rb]._u32[2]; CPU.GPR[rt]._u32[3] = CPU.GPR[ra]._u32[3] & CPU.GPR[rb]._u32[3]; } - virtual void CG(OP_REG rt, OP_REG ra, OP_REG rb) + void CG(u32 rt, u32 ra, u32 rb) { CPU.GPR[rt]._u32[0] = ((CPU.GPR[ra]._u32[0] + CPU.GPR[rb]._u32[0]) < CPU.GPR[ra]._u32[0]) ? 1 : 0; CPU.GPR[rt]._u32[1] = ((CPU.GPR[ra]._u32[1] + CPU.GPR[rb]._u32[1]) < CPU.GPR[ra]._u32[1]) ? 1 : 0; CPU.GPR[rt]._u32[2] = ((CPU.GPR[ra]._u32[2] + CPU.GPR[rb]._u32[2]) < CPU.GPR[ra]._u32[2]) ? 1 : 0; CPU.GPR[rt]._u32[3] = ((CPU.GPR[ra]._u32[3] + CPU.GPR[rb]._u32[3]) < CPU.GPR[ra]._u32[3]) ? 1 : 0; } - virtual void AH(OP_REG rt, OP_REG ra, OP_REG rb) + void AH(u32 rt, u32 ra, u32 rb) { for (int h = 0; h < 8; h++) CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._u16[h] + CPU.GPR[rb]._u16[h]; } - virtual void NAND(OP_REG rt, OP_REG ra, OP_REG rb) + void NAND(u32 rt, u32 ra, u32 rb) { CPU.GPR[rt]._u32[0] = ~(CPU.GPR[ra]._u32[0] & CPU.GPR[rb]._u32[0]); CPU.GPR[rt]._u32[1] = ~(CPU.GPR[ra]._u32[1] & CPU.GPR[rb]._u32[1]); CPU.GPR[rt]._u32[2] = ~(CPU.GPR[ra]._u32[2] & CPU.GPR[rb]._u32[2]); CPU.GPR[rt]._u32[3] = ~(CPU.GPR[ra]._u32[3] & CPU.GPR[rb]._u32[3]); } - virtual void AVGB(OP_REG rt, OP_REG ra, OP_REG rb) + void AVGB(u32 rt, u32 ra, u32 rb) { for (int b = 0; b < 16; b++) CPU.GPR[rt]._u8[b] = (CPU.GPR[ra]._u8[b] + CPU.GPR[rb]._u8[b] + 1) >> 1; } - virtual void MTSPR(OP_REG rt, OP_REG sa) + void MTSPR(u32 rt, u32 sa) { - // TODO + UNIMPLEMENTED(); } - virtual void WRCH(OP_REG ra, OP_REG rt) + void WRCH(u32 ra, u32 rt) { CPU.WriteChannel(ra, CPU.GPR[rt]); } - virtual void BIZ(OP_REG rt, OP_REG ra) + void BIZ(u32 rt, u32 ra) { if(CPU.GPR[rt]._u32[0] == 0) CPU.SetBranch(CPU.GPR[ra]._u32[0] & 0xfffffffc); } - virtual void BINZ(OP_REG rt, OP_REG ra) + void BINZ(u32 rt, u32 ra) { if(CPU.GPR[rt]._u32[0] != 0) CPU.SetBranch(CPU.GPR[ra]._u32[0] & 0xfffffffc); } - virtual void BIHZ(OP_REG rt, OP_REG ra) + void BIHZ(u32 rt, u32 ra) { if(CPU.GPR[rt]._u16[0] == 0) CPU.SetBranch(CPU.GPR[ra]._u32[0] & 0xfffffffc); } - virtual void BIHNZ(OP_REG rt, OP_REG ra) + void BIHNZ(u32 rt, u32 ra) { if(CPU.GPR[rt]._u16[0] != 0) CPU.SetBranch(CPU.GPR[ra]._u32[0] & 0xfffffffc); } - virtual void STOPD(OP_REG rc, OP_REG ra, OP_REG rb) + void STOPD(u32 rc, u32 ra, u32 rb) { Emu.Pause(); } - virtual void STQX(OP_REG rt, OP_REG ra, OP_REG rb) + void STQX(u32 rt, u32 ra, u32 rb) { CPU.LSA = CPU.GPR[ra]._u32[0] + CPU.GPR[rb]._u32[0]; CPU.WriteLSA128(CPU.GPR[rt]._u128); } - virtual void BI(OP_REG ra) + void BI(u32 ra) { CPU.SetBranch(CPU.GPR[ra]._u32[0] & 0xfffffffc); } - virtual void BISL(OP_REG rt, OP_REG ra) + void BISL(u32 rt, u32 ra) { CPU.SetBranch(CPU.GPR[ra]._u32[0] & 0xfffffffc); CPU.GPR[rt].Reset(); CPU.GPR[rt]._u32[0] = CPU.PC + 4; } - virtual void IRET(OP_REG ra) + void IRET(u32 ra) { - // TODO + UNIMPLEMENTED(); // SetBranch(SRR0); } - virtual void BISLED(OP_REG rt, OP_REG ra) + void BISLED(u32 rt, u32 ra) { - // TODO + UNIMPLEMENTED(); } - virtual void HBR(OP_REG p, OP_REG ro, OP_REG ra) + void HBR(u32 p, u32 ro, u32 ra) { CPU.SetBranch(CPU.GPR[ra]._u32[0]); } - virtual void GB(OP_REG rt, OP_REG ra) + void GB(u32 rt, u32 ra) { CPU.GPR[rt].Reset(); CPU.GPR[rt]._u32[0] = (CPU.GPR[ra]._u32[0] & 1) | @@ -315,56 +314,56 @@ private: ((CPU.GPR[ra]._u32[2] & 1) << 2) | ((CPU.GPR[ra]._u32[3] & 1) << 3); } - virtual void GBH(OP_REG rt, OP_REG ra) + void GBH(u32 rt, u32 ra) { CPU.GPR[rt].Reset(); for (int h = 0; h < 8; h++) CPU.GPR[rt]._u32[0] |= (CPU.GPR[ra]._u16[h] & 1) << h; } - virtual void GBB(OP_REG rt, OP_REG ra) + void GBB(u32 rt, u32 ra) { CPU.GPR[rt].Reset(); for (int b = 0; b < 16; b++) CPU.GPR[rt]._u32[0] |= (CPU.GPR[ra]._u8[b] & 1) << b; } - virtual void FSM(OP_REG rt, OP_REG ra) + void FSM(u32 rt, u32 ra) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._u32[w] = (CPU.GPR[ra]._u32[0] & (8 >> w)) ? ~0 : 0; } - virtual void FSMH(OP_REG rt, OP_REG ra) + void FSMH(u32 rt, u32 ra) { for (int h = 0; h < 8; h++) CPU.GPR[rt]._u16[h] = (CPU.GPR[ra]._u32[0] & (128 >> h)) ? ~0 : 0; } - virtual void FSMB(OP_REG rt, OP_REG ra) + void FSMB(u32 rt, u32 ra) { for (int b = 0; b < 16; b++) CPU.GPR[rt]._u8[b] = (CPU.GPR[ra]._u32[0] & (32768 >> b)) ? ~0 : 0; } - virtual void FREST(OP_REG rt, OP_REG ra) + void FREST(u32 rt, u32 ra) { - // TODO + UNIMPLEMENTED(); } - virtual void FRSQEST(OP_REG rt, OP_REG ra) + void FRSQEST(u32 rt, u32 ra) { - // TODO + UNIMPLEMENTED(); } - virtual void LQX(OP_REG rt, OP_REG ra, OP_REG rb) + void LQX(u32 rt, u32 ra, u32 rb) { CPU.LSA = CPU.GPR[ra]._u32[0] + CPU.GPR[rb]._u32[0]; CPU.GPR[rt]._u128 = CPU.ReadLSA128(); } - virtual void ROTQBYBI(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTQBYBI(u32 rt, u32 ra, u32 rb) { const int nShift = (CPU.GPR[rb]._u32[0] >> 3) & 0xf; for (int b = 0; b < 8; b++) CPU.GPR[rt]._u8[b] = nShift == 0 ? CPU.GPR[ra]._u8[b] : (CPU.GPR[ra]._u8[b] << nShift) | (CPU.GPR[ra]._u8[b] >> (16 - nShift)); } - virtual void ROTQMBYBI(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTQMBYBI(u32 rt, u32 ra, u32 rb) { const int nShift = ((0 - CPU.GPR[rb]._u32[0]) >> 3) & 0x1f; @@ -376,7 +375,7 @@ private: CPU.GPR[rt]._u8[b] = 0; } } - virtual void SHLQBYBI(OP_REG rt, OP_REG ra, OP_REG rb) + void SHLQBYBI(u32 rt, u32 ra, u32 rb) { const int nShift = (CPU.GPR[rb]._u32[0] >> 3) & 0x1f; @@ -388,34 +387,34 @@ private: CPU.GPR[rt]._u8[b] = 0; } } - virtual void CBX(OP_REG rt, OP_REG ra, OP_REG rb) + void CBX(u32 rt, u32 ra, u32 rb) { int n = (CPU.GPR[rb]._u32[0] + CPU.GPR[ra]._u32[0]) & 0xf; for (int b = 0; b < 16; b++) CPU.GPR[rt]._u8[b] = b == n ? 3 : b | 0x10; } - virtual void CHX(OP_REG rt, OP_REG ra, OP_REG rb) + void CHX(u32 rt, u32 ra, u32 rb) { int n = ((CPU.GPR[rb]._u32[0] + CPU.GPR[ra]._u32[0]) & 0xf) >> 1; for (int h = 0; h < 8; h++) CPU.GPR[rt]._u16[h] = h == n ? 0x0203 : (h * 2 * 0x0101 + 0x1011); } - virtual void CWX(OP_REG rt, OP_REG ra, OP_REG rb) + void CWX(u32 rt, u32 ra, u32 rb) { const u32 t = ((CPU.GPR[ra]._u32[0] + CPU.GPR[rb]._u32[0]) & 0xc) / 4; for(u32 i=0; i<16; ++i) CPU.GPR[rt]._i8[i] = 0x10 + i; CPU.GPR[rt]._u32[t] = 0x10203; } - virtual void CDX(OP_REG rt, OP_REG ra, OP_REG rb) + void CDX(u32 rt, u32 ra, u32 rb) { int n = ((CPU.GPR[rb]._u32[0] + CPU.GPR[ra]._u32[0]) & 0x8) >> 2; for (int w = 0; w < 4; w++) CPU.GPR[rt]._u32[w] = (w == n) ? 0x00010203 : (w == (n + 1)) ? 0x04050607 : (0x01010101 * (w * 4) + 0x10111213); } - virtual void ROTQBI(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTQBI(u32 rt, u32 ra, u32 rb) { int nShift = CPU.GPR[rb]._u32[0] & 0x7; @@ -424,7 +423,7 @@ private: CPU.GPR[rt]._u32[2] = (CPU.GPR[ra]._u32[2] << nShift) | (CPU.GPR[ra]._u32[3] >> (32 - nShift)); CPU.GPR[rt]._u32[3] = (CPU.GPR[ra]._u32[3] << nShift) | (CPU.GPR[ra]._u32[0] >> (32 - nShift)); } - virtual void ROTQMBI(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTQMBI(u32 rt, u32 ra, u32 rb) { int nShift = (0 - CPU.GPR[rb]._u32[0]) % 8; @@ -433,7 +432,7 @@ private: CPU.GPR[rt]._u32[2] = (CPU.GPR[ra]._u32[2] >> nShift) | (CPU.GPR[ra]._u32[1] << (32 - nShift)); CPU.GPR[rt]._u32[3] = (CPU.GPR[ra]._u32[3] >> nShift) | (CPU.GPR[ra]._u32[2] << (32 - nShift)); } - virtual void SHLQBI(OP_REG rt, OP_REG ra, OP_REG rb) + void SHLQBI(u32 rt, u32 ra, u32 rb) { const int nShift = CPU.GPR[rb]._u32[0] & 0x7; @@ -442,7 +441,7 @@ private: CPU.GPR[rt]._u32[2] = (CPU.GPR[ra]._u32[2] << nShift) | (CPU.GPR[ra]._u32[3] >> (32 - nShift)); CPU.GPR[rt]._u32[3] = CPU.GPR[ra]._u32[3] << nShift; } - virtual void ROTQBY(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTQBY(u32 rt, u32 ra, u32 rb) { const s32 s = CPU.GPR[rb]._u8[0] & 0xf; @@ -458,7 +457,7 @@ private: } } } - virtual void ROTQMBY(OP_REG rt, OP_REG ra, OP_REG rb) + void ROTQMBY(u32 rt, u32 ra, u32 rb) { const int nShift = (0 - CPU.GPR[rb]._u32[0]) % 32; @@ -468,7 +467,7 @@ private: else CPU.GPR[rt]._u8[b] = 0; } - virtual void SHLQBY(OP_REG rt, OP_REG ra, OP_REG rb) + void SHLQBY(u32 rt, u32 ra, u32 rb) { const int nShift = CPU.GPR[rb]._u32[0] & 0x1f; @@ -478,13 +477,13 @@ private: else CPU.GPR[rt]._u8[b] = 0; } - virtual void ORX(OP_REG rt, OP_REG ra) + void ORX(u32 rt, u32 ra) { CPU.GPR[rt].Reset(); CPU.GPR[rt]._u32[0] = CPU.GPR[ra]._u32[0] | CPU.GPR[ra]._u32[1] | CPU.GPR[ra]._u32[2] | CPU.GPR[ra]._u32[3]; } - virtual void CBD(OP_REG rt, OP_REG ra, OP_sIMM i7) + void CBD(u32 rt, u32 ra, s32 i7) { const int n = (CPU.GPR[ra]._u32[0] + i7) & 0xf; @@ -494,14 +493,14 @@ private: else CPU.GPR[rt]._u8[b] = b | 0x10; } - virtual void CHD(OP_REG rt, OP_REG ra, OP_sIMM i7) + void CHD(u32 rt, u32 ra, s32 i7) { int n = ((CPU.GPR[ra]._u32[0] + i7) & 0xf) >> 1; for (int h = 0; h < 8; h++) CPU.GPR[rt]._u16[h] = h == n ? 0x0203 : (h * 2 * 0x0101 + 0x1011); } - virtual void CWD(OP_REG rt, OP_REG ra, OP_sIMM i7) + void CWD(u32 rt, u32 ra, s32 i7) { const int t = ((CPU.GPR[ra]._u32[0] + i7) & 0xf) >> 2; @@ -510,7 +509,7 @@ private: CPU.GPR[rt]._u32[t] = 0x10203; } - virtual void CDD(OP_REG rt, OP_REG ra, OP_sIMM i7) + void CDD(u32 rt, u32 ra, s32 i7) { const int t = ((CPU.GPR[ra]._u32[0] + i7) & 0xf) >> 3; @@ -519,7 +518,7 @@ private: CPU.GPR[rt]._u64[t] = (u64)0x0001020304050607; } - virtual void ROTQBII(OP_REG rt, OP_REG ra, OP_sIMM i7) + void ROTQBII(u32 rt, u32 ra, s32 i7) { int nShift = i7 & 0x7; @@ -528,7 +527,7 @@ private: CPU.GPR[rt]._u32[2] = (CPU.GPR[ra]._u32[2] << nShift) | (CPU.GPR[ra]._u32[3] >> (32 - nShift)); CPU.GPR[rt]._u32[3] = (CPU.GPR[ra]._u32[3] << nShift) | (CPU.GPR[ra]._u32[0] >> (32 - nShift)); } - virtual void ROTQMBII(OP_REG rt, OP_REG ra, OP_sIMM i7) + void ROTQMBII(u32 rt, u32 ra, s32 i7) { int nShift = (0 - i7) % 8; @@ -537,7 +536,7 @@ private: CPU.GPR[rt]._u32[2] = (CPU.GPR[ra]._u32[2] >> nShift) | (CPU.GPR[ra]._u32[1] << (32 - nShift)); CPU.GPR[rt]._u32[3] = (CPU.GPR[ra]._u32[3] >> nShift) | (CPU.GPR[ra]._u32[2] << (32 - nShift)); } - virtual void SHLQBII(OP_REG rt, OP_REG ra, OP_sIMM i7) + void SHLQBII(u32 rt, u32 ra, s32 i7) { const int nShift = i7 & 0x7; @@ -546,7 +545,7 @@ private: CPU.GPR[rt]._u32[2] = (CPU.GPR[ra]._u32[2] << nShift) | (CPU.GPR[ra]._u32[3] >> (32 - nShift)); CPU.GPR[rt]._u32[3] = CPU.GPR[ra]._u32[3] << nShift; } - virtual void ROTQBYI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void ROTQBYI(u32 rt, u32 ra, s32 i7) { const u16 s = i7 & 0xf; @@ -562,7 +561,7 @@ private: } } } - virtual void ROTQMBYI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void ROTQMBYI(u32 rt, u32 ra, s32 i7) { const int nShift = (0 - i7) % 32; @@ -572,7 +571,7 @@ private: else CPU.GPR[rt]._u8[b] = 0; } - virtual void SHLQBYI(OP_REG rt, OP_REG ra, OP_sIMM i7) + void SHLQBYI(u32 rt, u32 ra, s32 i7) { const u16 s = i7 & 0x1f; @@ -583,35 +582,35 @@ private: CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._u8[b + s]; } } - virtual void NOP(OP_REG rt) + void NOP(u32 rt) { } - virtual void CGT(OP_REG rt, OP_REG ra, OP_REG rb) + void CGT(u32 rt, u32 ra, u32 rb) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._i32[w] > CPU.GPR[rb]._i32[w] ? 0xffffffff : 0; } - virtual void XOR(OP_REG rt, OP_REG ra, OP_REG rb) + void XOR(u32 rt, u32 ra, u32 rb) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._u32[w] ^ CPU.GPR[rb]._u32[w]; } - virtual void CGTH(OP_REG rt, OP_REG ra, OP_REG rb) + void CGTH(u32 rt, u32 ra, u32 rb) { for (int h = 0; h < 8; h++) CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._i16[h] > CPU.GPR[rb]._i16[h] ? 0xffff : 0; } - virtual void EQV(OP_REG rt, OP_REG ra, OP_REG rb) + void EQV(u32 rt, u32 ra, u32 rb) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._u32[w] = (CPU.GPR[ra]._u32[w] & CPU.GPR[rb]._u32[w]) | ~(CPU.GPR[ra]._u32[w] | CPU.GPR[rb]._u32[w]); } - virtual void CGTB(OP_REG rt, OP_REG ra, OP_REG rb) + void CGTB(u32 rt, u32 ra, u32 rb) { for (int b = 0; b < 16; b++) CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._i8[b] > CPU.GPR[rb]._i8[b] ? 0xff : 0; } - virtual void SUMB(OP_REG rt, OP_REG ra, OP_REG rb) + void SUMB(u32 rt, u32 ra, u32 rb) { for (int w = 0; w < 4; w++) { @@ -619,11 +618,11 @@ private: CPU.GPR[rt]._u16[w*2 + 1] = CPU.GPR[rb]._u8[w*4] + CPU.GPR[rb]._u8[w*4 + 1] + CPU.GPR[rb]._u8[w*4 + 2] + CPU.GPR[rb]._u8[w*4 + 3]; } } - virtual void HGT(OP_REG rt, OP_REG ra, OP_REG rb) + void HGT(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } - virtual void CLZ(OP_REG rt, OP_REG ra) + void CLZ(u32 rt, u32 ra) { for (int w = 0; w < 4; w++) { @@ -636,17 +635,17 @@ private: CPU.GPR[rt]._u32[w] = nPos; } } - virtual void XSWD(OP_REG rt, OP_REG ra) + void XSWD(u32 rt, u32 ra) { CPU.GPR[rt]._i64[0] = (s64)CPU.GPR[ra]._i32[1]; CPU.GPR[rt]._i64[1] = (s64)CPU.GPR[ra]._i32[3]; } - virtual void XSHW(OP_REG rt, OP_REG ra) + void XSHW(u32 rt, u32 ra) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._i32[w] = (s32)CPU.GPR[ra]._i16[w*2 + 1]; } - virtual void CNTB(OP_REG rt, OP_REG ra) + void CNTB(u32 rt, u32 ra) { CPU.GPR[rt].Reset(); @@ -654,124 +653,124 @@ private: for (int i = 0; i < 8; i++) CPU.GPR[rt]._u8[b] += (CPU.GPR[ra]._u8[b] & (1 << i)) ? 1 : 0; } - virtual void XSBH(OP_REG rt, OP_REG ra) + void XSBH(u32 rt, u32 ra) { for (int h = 0; h < 8; h++) CPU.GPR[rt]._i16[h] = (s16)CPU.GPR[ra]._i8[h*2 + 1]; } - virtual void CLGT(OP_REG rt, OP_REG ra, OP_REG rb) + void CLGT(u32 rt, u32 ra, u32 rb) { for(u32 i = 0; i < 4; ++i) { CPU.GPR[rt]._u32[i] = (CPU.GPR[ra]._u32[i] > CPU.GPR[rb]._u32[i]) ? 0xffffffff : 0x00000000; } } - virtual void ANDC(OP_REG rt, OP_REG ra, OP_REG rb) + void ANDC(u32 rt, u32 ra, u32 rb) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._u32[w] & (~CPU.GPR[rb]._u32[w]); } - virtual void FCGT(OP_REG rt, OP_REG ra, OP_REG rb) + void FCGT(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } - virtual void DFCGT(OP_REG rt, OP_REG ra, OP_REG rb) + void DFCGT(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } - virtual void FA(OP_REG rt, OP_REG ra, OP_REG rb) + void FA(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } - virtual void FS(OP_REG rt, OP_REG ra, OP_REG rb) + void FS(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } - virtual void FM(OP_REG rt, OP_REG ra, OP_REG rb) + void FM(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } - virtual void CLGTH(OP_REG rt, OP_REG ra, OP_REG rb) + void CLGTH(u32 rt, u32 ra, u32 rb) { for (int h = 0; h < 8; h++) CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._u16[h] > CPU.GPR[rb]._u16[h] ? 0xffff : 0; } - virtual void ORC(OP_REG rt, OP_REG ra, OP_REG rb) + void ORC(u32 rt, u32 ra, u32 rb) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._u32[w] | (~CPU.GPR[rb]._u32[w]); } - virtual void FCMGT(OP_REG rt, OP_REG ra, OP_REG rb) + void FCMGT(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } - virtual void DFCMGT(OP_REG rt, OP_REG ra, OP_REG rb) + void DFCMGT(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } - virtual void DFA(OP_REG rt, OP_REG ra, OP_REG rb) + void DFA(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } - virtual void DFS(OP_REG rt, OP_REG ra, OP_REG rb) + void DFS(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } - virtual void DFM(OP_REG rt, OP_REG ra, OP_REG rb) + void DFM(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } - virtual void CLGTB(OP_REG rt, OP_REG ra, OP_REG rb) + void CLGTB(u32 rt, u32 ra, u32 rb) { for (int b = 0; b < 16; b++) CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._u8[b] > CPU.GPR[rb]._u8[b] ? 0xff : 0; } - virtual void HLGT(OP_REG rt, OP_REG ra, OP_REG rb) + void HLGT(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } - virtual void DFMA(OP_REG rt, OP_REG ra, OP_REG rb) + void DFMA(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } - virtual void DFMS(OP_REG rt, OP_REG ra, OP_REG rb) + void DFMS(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } - virtual void DFNMS(OP_REG rt, OP_REG ra, OP_REG rb) + void DFNMS(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } - virtual void DFNMA(OP_REG rt, OP_REG ra, OP_REG rb) + void DFNMA(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } - virtual void CEQ(OP_REG rt, OP_REG ra, OP_REG rb) + void CEQ(u32 rt, u32 ra, u32 rb) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._i32[w] == CPU.GPR[rb]._i32[w] ? 0xffffffff : 0; } - virtual void MPYHHU(OP_REG rt, OP_REG ra, OP_REG rb) + void MPYHHU(u32 rt, u32 ra, u32 rb) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._u16[w*2] * CPU.GPR[rb]._u16[w*2]; } - virtual void ADDX(OP_REG rt, OP_REG ra, OP_REG rb) + void ADDX(u32 rt, u32 ra, u32 rb) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._u32[w] + CPU.GPR[rb]._u32[w] + (CPU.GPR[rt]._u32[w] & 1); } - virtual void SFX(OP_REG rt, OP_REG ra, OP_REG rb) + void SFX(u32 rt, u32 ra, u32 rb) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._u32[w] = CPU.GPR[rb]._u32[w] - CPU.GPR[ra]._u32[w] - (1 - (CPU.GPR[rt]._u32[w] & 1)); } - virtual void CGX(OP_REG rt, OP_REG ra, OP_REG rb) + void CGX(u32 rt, u32 ra, u32 rb) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._u32[w] = (CPU.GPR[ra]._u32[w] + CPU.GPR[rb]._u32[w] + (CPU.GPR[rt]._u32[w] & 1)) < CPU.GPR[ra]._u32[w] ? 1 : 0; } - virtual void BGX(OP_REG rt, OP_REG ra, OP_REG rb) + void BGX(u32 rt, u32 ra, u32 rb) { s64 nResult; @@ -781,151 +780,151 @@ private: CPU.GPR[rt]._u32[w] = nResult < 0 ? 0 : 1; } } - virtual void MPYHHA(OP_REG rt, OP_REG ra, OP_REG rb) + void MPYHHA(u32 rt, u32 ra, u32 rb) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._i32[w] += CPU.GPR[ra]._i16[w*2] * CPU.GPR[rb]._i16[w*2]; } - virtual void MPYHHAU(OP_REG rt, OP_REG ra, OP_REG rb) + void MPYHHAU(u32 rt, u32 ra, u32 rb) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._u32[w] += CPU.GPR[ra]._u16[w*2] * CPU.GPR[rb]._u16[w*2]; } - virtual void FSCRRD(OP_REG rt) + void FSCRRD(u32 rt) { - // TODO + UNIMPLEMENTED(); } - virtual void FESD(OP_REG rt, OP_REG ra) + void FESD(u32 rt, u32 ra) { - // TODO + UNIMPLEMENTED(); } - virtual void FRDS(OP_REG rt, OP_REG ra) + void FRDS(u32 rt, u32 ra) { - // TODO + UNIMPLEMENTED(); } - virtual void FSCRWR(OP_REG rt, OP_REG ra) + void FSCRWR(u32 rt, u32 ra) { - // TODO + UNIMPLEMENTED(); } - virtual void DFTSV(OP_REG rt, OP_REG ra, OP_sIMM i7) + void DFTSV(u32 rt, u32 ra, s32 i7) { - // TODO + UNIMPLEMENTED(); } - virtual void FCEQ(OP_REG rt, OP_REG ra, OP_REG rb) + void FCEQ(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } - virtual void DFCEQ(OP_REG rt, OP_REG ra, OP_REG rb) + void DFCEQ(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } - virtual void MPY(OP_REG rt, OP_REG ra, OP_REG rb) + void MPY(u32 rt, u32 ra, u32 rb) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._i32[w] = CPU.GPR[ra]._i16[w*2 + 1] * CPU.GPR[rb]._i16[w*2 + 1]; } - virtual void MPYH(OP_REG rt, OP_REG ra, OP_REG rb) + void MPYH(u32 rt, u32 ra, u32 rb) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._i32[w] = ((CPU.GPR[ra]._i32[w] >> 16) * (CPU.GPR[rb]._i32[w] & 0xffff)) << 16; } - virtual void MPYHH(OP_REG rt, OP_REG ra, OP_REG rb) + void MPYHH(u32 rt, u32 ra, u32 rb) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._i32[w] = CPU.GPR[ra]._i16[w*2] * CPU.GPR[rb]._i16[w*2]; } - virtual void MPYS(OP_REG rt, OP_REG ra, OP_REG rb) + void MPYS(u32 rt, u32 ra, u32 rb) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._i32[w] = (CPU.GPR[ra]._i16[w*2 + 1] * CPU.GPR[rb]._i16[w*2 + 1]) >> 16; } - virtual void CEQH(OP_REG rt, OP_REG ra, OP_REG rb) + void CEQH(u32 rt, u32 ra, u32 rb) { for (int h = 0; h < 8; h++) CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._u16[h] == CPU.GPR[rb]._u16[h] ? 0xffff : 0; } - virtual void FCMEQ(OP_REG rt, OP_REG ra, OP_REG rb) + void FCMEQ(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } - virtual void DFCMEQ(OP_REG rt, OP_REG ra, OP_REG rb) + void DFCMEQ(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } - virtual void MPYU(OP_REG rt, OP_REG ra, OP_REG rb) + void MPYU(u32 rt, u32 ra, u32 rb) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._u16[w*2 + 1] * CPU.GPR[rb]._u16[w*2 + 1]; } - virtual void CEQB(OP_REG rt, OP_REG ra, OP_REG rb) + void CEQB(u32 rt, u32 ra, u32 rb) { for (int b = 0; b < 16; b++) CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._u8[b] == CPU.GPR[rb]._u8[b] ? 0xff : 0; } - virtual void FI(OP_REG rt, OP_REG ra, OP_REG rb) + void FI(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } - virtual void HEQ(OP_REG rt, OP_REG ra, OP_REG rb) + void HEQ(u32 rt, u32 ra, u32 rb) { - // TODO + UNIMPLEMENTED(); } //0 - 9 - virtual void CFLTS(OP_REG rt, OP_REG ra, OP_sIMM i8) + void CFLTS(u32 rt, u32 ra, s32 i8) { - // TODO + UNIMPLEMENTED(); } - virtual void CFLTU(OP_REG rt, OP_REG ra, OP_sIMM i8) + void CFLTU(u32 rt, u32 ra, s32 i8) { - // TODO + UNIMPLEMENTED(); } - virtual void CSFLT(OP_REG rt, OP_REG ra, OP_sIMM i8) + void CSFLT(u32 rt, u32 ra, s32 i8) { - // TODO + UNIMPLEMENTED(); } - virtual void CUFLT(OP_REG rt, OP_REG ra, OP_sIMM i8) + void CUFLT(u32 rt, u32 ra, s32 i8) { - // TODO + UNIMPLEMENTED(); } //0 - 8 - virtual void BRZ(OP_REG rt, OP_sIMM i16) + void BRZ(u32 rt, s32 i16) { if(!CPU.GPR[rt]._u32[0]) CPU.SetBranch(branchTarget(CPU.PC, i16)); } - virtual void STQA(OP_REG rt, OP_sIMM i16) + void STQA(u32 rt, s32 i16) { CPU.LSA = i16 << 2; CPU.WriteLSA128(CPU.GPR[rt]._u128); } - virtual void BRNZ(OP_REG rt, OP_sIMM i16) + void BRNZ(u32 rt, s32 i16) { if(CPU.GPR[rt]._u32[0] != 0) CPU.SetBranch(branchTarget(CPU.PC, i16)); } - virtual void BRHZ(OP_REG rt, OP_sIMM i16) + void BRHZ(u32 rt, s32 i16) { if(!CPU.GPR[rt]._u16[0]) CPU.SetBranch(branchTarget(CPU.PC, i16)); } - virtual void BRHNZ(OP_REG rt, OP_sIMM i16) + void BRHNZ(u32 rt, s32 i16) { if(CPU.GPR[rt]._u16[0]) CPU.SetBranch(branchTarget(CPU.PC, i16)); } - virtual void STQR(OP_REG rt, OP_sIMM i16) + void STQR(u32 rt, s32 i16) { CPU.LSA = branchTarget(CPU.PC, i16); CPU.WriteLSA128(CPU.GPR[rt]._u128); } - virtual void BRA(OP_sIMM i16) + void BRA(s32 i16) { CPU.SetBranch(i16 << 2); } - virtual void LQA(OP_REG rt, OP_sIMM i16) + void LQA(u32 rt, s32 i16) { CPU.LSA = i16 << 2; if(!Memory.IsGoodAddr(CPU.LSA)) @@ -936,17 +935,17 @@ private: CPU.GPR[rt]._u128 = CPU.ReadLSA128(); } - virtual void BRASL(OP_REG rt, OP_sIMM i16) + void BRASL(u32 rt, s32 i16) { CPU.GPR[rt].Reset(); CPU.GPR[rt]._u32[0] = CPU.PC + 4; CPU.SetBranch(i16 << 2); } - virtual void BR(OP_sIMM i16) + void BR(s32 i16) { CPU.SetBranch(branchTarget(CPU.PC, i16)); } - virtual void FSMBI(OP_REG rt, OP_sIMM i16) + void FSMBI(u32 rt, s32 i16) { const u32 s = i16; @@ -962,13 +961,13 @@ private: } } } - virtual void BRSL(OP_REG rt, OP_sIMM i16) + void BRSL(u32 rt, s32 i16) { CPU.GPR[rt].Reset(); CPU.GPR[rt]._u32[0] = CPU.PC + 4; CPU.SetBranch(branchTarget(CPU.PC, i16)); } - virtual void LQR(OP_REG rt, OP_sIMM i16) + void LQR(u32 rt, s32 i16) { CPU.LSA = branchTarget(CPU.PC, i16); if(!Memory.IsGoodAddr(CPU.LSA)) @@ -979,24 +978,24 @@ private: CPU.GPR[rt]._u128 = CPU.ReadLSA128(); } - virtual void IL(OP_REG rt, OP_sIMM i16) + void IL(u32 rt, s32 i16) { CPU.GPR[rt]._u32[0] = i16; CPU.GPR[rt]._u32[1] = i16; CPU.GPR[rt]._u32[2] = i16; CPU.GPR[rt]._u32[3] = i16; } - virtual void ILHU(OP_REG rt, OP_sIMM i16) + void ILHU(u32 rt, s32 i16) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._u16[w*2] = i16; } - virtual void ILH(OP_REG rt, OP_sIMM i16) + void ILH(u32 rt, s32 i16) { for (int h = 0; h < 8; h++) CPU.GPR[rt]._u16[h] = i16; } - virtual void IOHL(OP_REG rt, OP_sIMM i16) + void IOHL(u32 rt, s32 i16) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._u32[w] |= i16; @@ -1004,174 +1003,176 @@ private: //0 - 7 - virtual void ORI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void ORI(u32 rt, u32 ra, s32 i10) { for(u32 i = 0; i < 4; ++i) { CPU.GPR[rt]._u32[i] = CPU.GPR[ra]._u32[i] | i10; } } - virtual void ORHI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void ORHI(u32 rt, u32 ra, s32 i10) { for (int h = 0; h < 8; h++) CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._u16[h] | i10; } - virtual void ORBI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void ORBI(u32 rt, u32 ra, s32 i10) { for (int b = 0; b < 16; b++) CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._u8[b] | (i10 & 0xff); } - virtual void SFI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void SFI(u32 rt, u32 ra, s32 i10) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._i32[w] = i10 - CPU.GPR[ra]._i32[w]; } - virtual void SFHI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void SFHI(u32 rt, u32 ra, s32 i10) { for (int h = 0; h < 8; h++) CPU.GPR[rt]._i16[h] = i10 - CPU.GPR[ra]._i16[h]; } - virtual void ANDI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void ANDI(u32 rt, u32 ra, s32 i10) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._u32[w] & i10; } - virtual void ANDHI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void ANDHI(u32 rt, u32 ra, s32 i10) { for (int h = 0; h < 8; h++) CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._u16[h] & i10; } - virtual void ANDBI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void ANDBI(u32 rt, u32 ra, s32 i10) { for (int b = 0; b < 16; b++) CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._u8[b] & (i10 & 0xff); } - virtual void AI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void AI(u32 rt, u32 ra, s32 i10) { for(u32 i = 0; i < 4; ++i) { CPU.GPR[rt]._u32[i] = CPU.GPR[ra]._u32[i] + i10; } } - virtual void AHI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void AHI(u32 rt, u32 ra, s32 i10) { for(u32 i = 0; i < 8; ++i) { CPU.GPR[rt]._u16[i] = CPU.GPR[ra]._u16[i] + i10; } } - virtual void STQD(OP_REG rt, OP_sIMM i10, OP_REG ra) + void STQD(u32 rt, s32 i10, u32 ra) { CPU.LSA = branchTarget(0, i10 + CPU.GPR[ra]._u32[0]); CPU.WriteLSA128(CPU.GPR[rt]._u128); } - virtual void LQD(OP_REG rt, OP_sIMM i10, OP_REG ra) + void LQD(u32 rt, s32 i10, u32 ra) { CPU.LSA = branchTarget(0, i10 + CPU.GPR[ra]._u32[0]); CPU.GPR[rt]._u128 = CPU.ReadLSA128(); } - virtual void XORI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void XORI(u32 rt, u32 ra, s32 i10) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._u32[w] ^ i10; } - virtual void XORHI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void XORHI(u32 rt, u32 ra, s32 i10) { for (int h = 0; h < 8; h++) CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._u16[h] ^ i10; } - virtual void XORBI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void XORBI(u32 rt, u32 ra, s32 i10) { for (int b = 0; b < 16; b++) CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._u8[b] ^ (i10 & 0xff); } - virtual void CGTI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void CGTI(u32 rt, u32 ra, s32 i10) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._i32[w] > i10 ? 0xffffffff : 0; } - virtual void CGTHI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void CGTHI(u32 rt, u32 ra, s32 i10) { for (int h = 0; h < 8; h++) CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._i16[h] > i10 ? 0xffff : 0; } - virtual void CGTBI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void CGTBI(u32 rt, u32 ra, s32 i10) { for (int b = 0; b < 16; b++) CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._i8[b] > (s8)(i10 & 0xff) ? 0xff : 0; } - virtual void HGTI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void HGTI(u32 rt, u32 ra, s32 i10) { - // TODO + UNIMPLEMENTED(); } - virtual void CLGTI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void CLGTI(u32 rt, u32 ra, s32 i10) { for(u32 i = 0; i < 4; ++i) { CPU.GPR[rt]._u32[i] = (CPU.GPR[rt]._u32[i] > (u32)i10) ? 0xffffffff : 0x00000000; } } - virtual void CLGTHI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void CLGTHI(u32 rt, u32 ra, s32 i10) { for(u32 i = 0; i < 8; ++i) { CPU.GPR[rt]._u16[i] = (CPU.GPR[rt]._u16[i] > (u16)i10) ? 0xffff : 0x0000; } } - virtual void CLGTBI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void CLGTBI(u32 rt, u32 ra, s32 i10) { for (int b = 0; b < 16; b++) CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._u8[b] > (u8)(i10 & 0xff) ? 0xff : 0; } - virtual void HLGTI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void HLGTI(u32 rt, u32 ra, s32 i10) { - // TODO + UNIMPLEMENTED(); } - virtual void MPYI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void MPYI(u32 rt, u32 ra, s32 i10) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._i32[w] = CPU.GPR[rt]._i16[w*2 + 1] * i10; } - virtual void MPYUI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void MPYUI(u32 rt, u32 ra, s32 i10) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._u32[w] = CPU.GPR[rt]._u16[w*2 + 1] * (u16)(i10 & 0xffff); } - virtual void CEQI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void CEQI(u32 rt, u32 ra, s32 i10) { for(u32 i = 0; i < 4; ++i) { CPU.GPR[rt]._u32[i] = (CPU.GPR[rt]._u32[i] == (u32)i10) ? 0xffffffff : 0x00000000; } } - virtual void CEQHI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void CEQHI(u32 rt, u32 ra, s32 i10) { for (int h = 0; h < 8; h++) CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._i16[h] == (s16)i10 ? 0xffff : 0; } - virtual void CEQBI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void CEQBI(u32 rt, u32 ra, s32 i10) { for (int b = 0; b < 16; b++) CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._u8[b] == (u8)(i10 & 0xff) ? 0xff : 0; } - virtual void HEQI(OP_REG rt, OP_REG ra, OP_sIMM i10) + void HEQI(u32 rt, u32 ra, s32 i10) { - // TODO + UNIMPLEMENTED(); } //0 - 6 - virtual void HBRA(OP_sIMM ro, OP_sIMM i16) + void HBRA(s32 ro, s32 i16) { - // TODO + UNIMPLEMENTED(); + UNIMPLEMENTED(); } - virtual void HBRR(OP_sIMM ro, OP_sIMM i16) + void HBRR(s32 ro, s32 i16) { + UNIMPLEMENTED(); //CHECK ME //CPU.GPR[0]._u64[0] = branchTarget(CPU.PC, i16); //CPU.SetBranch(branchTarget(CPU.PC, ro)); } - virtual void ILA(OP_REG rt, OP_sIMM i18) + void ILA(u32 rt, s32 i18) { CPU.GPR[rt]._u32[0] = i18; CPU.GPR[rt]._u32[1] = i18; @@ -1180,7 +1181,7 @@ private: } //0 - 3 - virtual void SELB(OP_REG rt, OP_REG ra, OP_REG rb, OP_REG rc) + void SELB(u32 rt, u32 ra, u32 rb, u32 rc) { for(u32 i = 0; i < 4; ++i) { @@ -1195,31 +1196,31 @@ private: ); */ } - virtual void SHUFB(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt) + void SHUFB(u32 rc, u32 ra, u32 rb, u32 rt) { ConLog.Warning("SHUFB"); } - virtual void MPYA(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt) + void MPYA(u32 rc, u32 ra, u32 rb, u32 rt) { for (int w = 0; w < 4; w++) CPU.GPR[rt]._i32[w] = CPU.GPR[ra]._i16[w*2 + 1] * CPU.GPR[rb]._i16[w*2 + 1] + CPU.GPR[rc]._i32[w]; } - virtual void FNMS(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt) + void FNMS(u32 rc, u32 ra, u32 rb, u32 rt) { - // TODO + UNIMPLEMENTED(); } - virtual void FMA(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt) + void FMA(u32 rc, u32 ra, u32 rb, u32 rt) { - // TODO + UNIMPLEMENTED(); } - virtual void FMS(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt) + void FMS(u32 rc, u32 ra, u32 rb, u32 rt) { - // TODO + UNIMPLEMENTED(); } - virtual void UNK(const s32 code, const s32 opcode, const s32 gcode) + void UNK(u32 code, u32 opcode, u32 gcode) { - UNK(wxString::Format("Unknown/Illegal opcode! (0x%08x)", code)); + UNK(wxString::Format("Unknown/Illegal opcode! (0x%08x, 0x%x, 0x%x)", code, opcode, gcode)); } void UNK(const wxString& err) @@ -1229,6 +1230,3 @@ private: for(uint i=0; i<128; ++i) ConLog.Write("r%d = 0x%s", i, CPU.GPR[i].ToString()); } }; - -#undef START_OPCODES_GROUP -#undef END_OPCODES_GROUP \ No newline at end of file diff --git a/rpcs3/Emu/Cell/SPUOpcodes.h b/rpcs3/Emu/Cell/SPUOpcodes.h index f9446a82a0..1b56e9281b 100644 --- a/rpcs3/Emu/Cell/SPUOpcodes.h +++ b/rpcs3/Emu/Cell/SPUOpcodes.h @@ -1,13 +1,5 @@ #pragma once -#define OP_REG u32 -#define OP_sIMM s32 -#define OP_uIMM u32 -#define START_OPCODES_GROUP(x) /*x*/ -#define ADD_OPCODE(name, regs) virtual void(##name##)##regs##=0 -#define ADD_NULL_OPCODE(name) virtual void(##name##)()=0 -#define END_OPCODES_GROUP(x) /*x*/ - namespace SPU_opcodes { enum SPU_0_10_Opcodes @@ -245,220 +237,215 @@ public: virtual void Exit()=0; //0 - 10 - ADD_OPCODE(STOP,(OP_uIMM code)); - ADD_OPCODE(LNOP,()); - ADD_OPCODE(SYNC, (OP_uIMM Cbit)); - ADD_OPCODE(DSYNC, ()); - ADD_OPCODE(MFSPR,(OP_REG rt, OP_REG sa)); - ADD_OPCODE(RDCH,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(RCHCNT,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(SF,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(OR,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(BG,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(SFH,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(NOR,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(ABSDB,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(ROT,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(ROTM,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(ROTMA,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(SHL,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(ROTH,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(ROTHM,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(ROTMAH,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(SHLH,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(ROTI,(OP_REG rt, OP_REG ra, OP_sIMM i7)); - ADD_OPCODE(ROTMI,(OP_REG rt, OP_REG ra, OP_sIMM i7)); - ADD_OPCODE(ROTMAI,(OP_REG rt, OP_REG ra, OP_sIMM i7)); - ADD_OPCODE(SHLI,(OP_REG rt, OP_REG ra, OP_sIMM i7)); - ADD_OPCODE(ROTHI,(OP_REG rt, OP_REG ra, OP_sIMM i7)); - ADD_OPCODE(ROTHMI,(OP_REG rt, OP_REG ra, OP_sIMM i7)); - ADD_OPCODE(ROTMAHI,(OP_REG rt, OP_REG ra, OP_sIMM i7)); - ADD_OPCODE(SHLHI,(OP_REG rt, OP_REG ra, OP_sIMM i7)); - ADD_OPCODE(A,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(AND,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(CG,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(AH,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(NAND,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(AVGB,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(MTSPR,(OP_REG rt, OP_REG sa)); - ADD_OPCODE(WRCH,(OP_REG ra, OP_REG rt)); - ADD_OPCODE(BIZ,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(BINZ,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(BIHZ,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(BIHNZ,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(STOPD,(OP_REG rc, OP_REG ra, OP_REG rb)); - ADD_OPCODE(STQX,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(BI,(OP_REG ra)); - ADD_OPCODE(BISL,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(IRET,(OP_REG ra)); - ADD_OPCODE(BISLED,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(HBR,(OP_REG p, OP_REG ro, OP_REG ra)); - ADD_OPCODE(GB,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(GBH,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(GBB,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(FSM,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(FSMH,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(FSMB,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(FREST,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(FRSQEST,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(LQX,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(ROTQBYBI,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(ROTQMBYBI,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(SHLQBYBI,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(CBX,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(CHX,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(CWX,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(CDX,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(ROTQBI,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(ROTQMBI,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(SHLQBI,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(ROTQBY,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(ROTQMBY,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(SHLQBY,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(ORX,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(CBD,(OP_REG rt, OP_REG ra, OP_sIMM i7)); - ADD_OPCODE(CHD,(OP_REG rt, OP_REG ra, OP_sIMM i7)); - ADD_OPCODE(CWD,(OP_REG rt, OP_REG ra, OP_sIMM i7)); - ADD_OPCODE(CDD,(OP_REG rt, OP_REG ra, OP_sIMM i7)); - ADD_OPCODE(ROTQBII,(OP_REG rt, OP_REG ra, OP_sIMM i7)); - ADD_OPCODE(ROTQMBII,(OP_REG rt, OP_REG ra, OP_sIMM i7)); - ADD_OPCODE(SHLQBII,(OP_REG rt, OP_REG ra, OP_sIMM i7)); - ADD_OPCODE(ROTQBYI,(OP_REG rt, OP_REG ra, OP_sIMM i7)); - ADD_OPCODE(ROTQMBYI,(OP_REG rt, OP_REG ra, OP_sIMM i7)); - ADD_OPCODE(SHLQBYI,(OP_REG rt, OP_REG ra, OP_sIMM i7)); - ADD_OPCODE(NOP,(OP_REG rt)); - ADD_OPCODE(CGT,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(XOR,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(CGTH,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(EQV,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(CGTB,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(SUMB,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(HGT,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(CLZ,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(XSWD,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(XSHW,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(CNTB,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(XSBH,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(CLGT,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(ANDC,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(FCGT,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(DFCGT,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(FA,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(FS,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(FM,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(CLGTH,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(ORC,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(FCMGT,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(DFCMGT,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(DFA,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(DFS,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(DFM,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(CLGTB,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(HLGT,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(DFMA,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(DFMS,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(DFNMS,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(DFNMA,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(CEQ,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(MPYHHU,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(ADDX,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(SFX,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(CGX,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(BGX,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(MPYHHA,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(MPYHHAU,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(FSCRRD,(OP_REG rt)); - ADD_OPCODE(FESD,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(FRDS,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(FSCRWR,(OP_REG rt, OP_REG ra)); - ADD_OPCODE(DFTSV,(OP_REG rt, OP_REG ra, OP_sIMM i7)); - ADD_OPCODE(FCEQ,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(DFCEQ,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(MPY,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(MPYH,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(MPYHH,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(MPYS,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(CEQH,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(FCMEQ,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(DFCMEQ,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(MPYU,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(CEQB,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(FI,(OP_REG rt, OP_REG ra, OP_REG rb)); - ADD_OPCODE(HEQ,(OP_REG rt, OP_REG ra, OP_REG rb)); + virtual void STOP(u32 code) = 0; + virtual void LNOP() = 0; + virtual void SYNC(u32 Cbit) = 0; + virtual void DSYNC() = 0; + virtual void MFSPR(u32 rt, u32 sa) = 0; + virtual void RDCH(u32 rt, u32 ra) = 0; + virtual void RCHCNT(u32 rt, u32 ra) = 0; + virtual void SF(u32 rt, u32 ra, u32 rb) = 0; + virtual void OR(u32 rt, u32 ra, u32 rb) = 0; + virtual void BG(u32 rt, u32 ra, u32 rb) = 0; + virtual void SFH(u32 rt, u32 ra, u32 rb) = 0; + virtual void NOR(u32 rt, u32 ra, u32 rb) = 0; + virtual void ABSDB(u32 rt, u32 ra, u32 rb) = 0; + virtual void ROT(u32 rt, u32 ra, u32 rb) = 0; + virtual void ROTM(u32 rt, u32 ra, u32 rb) = 0; + virtual void ROTMA(u32 rt, u32 ra, u32 rb) = 0; + virtual void SHL(u32 rt, u32 ra, u32 rb) = 0; + virtual void ROTH(u32 rt, u32 ra, u32 rb) = 0; + virtual void ROTHM(u32 rt, u32 ra, u32 rb) = 0; + virtual void ROTMAH(u32 rt, u32 ra, u32 rb) = 0; + virtual void SHLH(u32 rt, u32 ra, u32 rb) = 0; + virtual void ROTI(u32 rt, u32 ra, s32 i7) = 0; + virtual void ROTMI(u32 rt, u32 ra, s32 i7) = 0; + virtual void ROTMAI(u32 rt, u32 ra, s32 i7) = 0; + virtual void SHLI(u32 rt, u32 ra, s32 i7) = 0; + virtual void ROTHI(u32 rt, u32 ra, s32 i7) = 0; + virtual void ROTHMI(u32 rt, u32 ra, s32 i7) = 0; + virtual void ROTMAHI(u32 rt, u32 ra, s32 i7) = 0; + virtual void SHLHI(u32 rt, u32 ra, s32 i7) = 0; + virtual void A(u32 rt, u32 ra, u32 rb) = 0; + virtual void AND(u32 rt, u32 ra, u32 rb) = 0; + virtual void CG(u32 rt, u32 ra, u32 rb) = 0; + virtual void AH(u32 rt, u32 ra, u32 rb) = 0; + virtual void NAND(u32 rt, u32 ra, u32 rb) = 0; + virtual void AVGB(u32 rt, u32 ra, u32 rb) = 0; + virtual void MTSPR(u32 rt, u32 sa) = 0; + virtual void WRCH(u32 ra, u32 rt) = 0; + virtual void BIZ(u32 rt, u32 ra) = 0; + virtual void BINZ(u32 rt, u32 ra) = 0; + virtual void BIHZ(u32 rt, u32 ra) = 0; + virtual void BIHNZ(u32 rt, u32 ra) = 0; + virtual void STOPD(u32 rc, u32 ra, u32 rb) = 0; + virtual void STQX(u32 rt, u32 ra, u32 rb) = 0; + virtual void BI(u32 ra) = 0; + virtual void BISL(u32 rt, u32 ra) = 0; + virtual void IRET(u32 ra) = 0; + virtual void BISLED(u32 rt, u32 ra) = 0; + virtual void HBR(u32 p, u32 ro, u32 ra) = 0; + virtual void GB(u32 rt, u32 ra) = 0; + virtual void GBH(u32 rt, u32 ra) = 0; + virtual void GBB(u32 rt, u32 ra) = 0; + virtual void FSM(u32 rt, u32 ra) = 0; + virtual void FSMH(u32 rt, u32 ra) = 0; + virtual void FSMB(u32 rt, u32 ra) = 0; + virtual void FREST(u32 rt, u32 ra) = 0; + virtual void FRSQEST(u32 rt, u32 ra) = 0; + virtual void LQX(u32 rt, u32 ra, u32 rb) = 0; + virtual void ROTQBYBI(u32 rt, u32 ra, u32 rb) = 0; + virtual void ROTQMBYBI(u32 rt, u32 ra, u32 rb) = 0; + virtual void SHLQBYBI(u32 rt, u32 ra, u32 rb) = 0; + virtual void CBX(u32 rt, u32 ra, u32 rb) = 0; + virtual void CHX(u32 rt, u32 ra, u32 rb) = 0; + virtual void CWX(u32 rt, u32 ra, u32 rb) = 0; + virtual void CDX(u32 rt, u32 ra, u32 rb) = 0; + virtual void ROTQBI(u32 rt, u32 ra, u32 rb) = 0; + virtual void ROTQMBI(u32 rt, u32 ra, u32 rb) = 0; + virtual void SHLQBI(u32 rt, u32 ra, u32 rb) = 0; + virtual void ROTQBY(u32 rt, u32 ra, u32 rb) = 0; + virtual void ROTQMBY(u32 rt, u32 ra, u32 rb) = 0; + virtual void SHLQBY(u32 rt, u32 ra, u32 rb) = 0; + virtual void ORX(u32 rt, u32 ra) = 0; + virtual void CBD(u32 rt, u32 ra, s32 i7) = 0; + virtual void CHD(u32 rt, u32 ra, s32 i7) = 0; + virtual void CWD(u32 rt, u32 ra, s32 i7) = 0; + virtual void CDD(u32 rt, u32 ra, s32 i7) = 0; + virtual void ROTQBII(u32 rt, u32 ra, s32 i7) = 0; + virtual void ROTQMBII(u32 rt, u32 ra, s32 i7) = 0; + virtual void SHLQBII(u32 rt, u32 ra, s32 i7) = 0; + virtual void ROTQBYI(u32 rt, u32 ra, s32 i7) = 0; + virtual void ROTQMBYI(u32 rt, u32 ra, s32 i7) = 0; + virtual void SHLQBYI(u32 rt, u32 ra, s32 i7) = 0; + virtual void NOP(u32 rt) = 0; + virtual void CGT(u32 rt, u32 ra, u32 rb) = 0; + virtual void XOR(u32 rt, u32 ra, u32 rb) = 0; + virtual void CGTH(u32 rt, u32 ra, u32 rb) = 0; + virtual void EQV(u32 rt, u32 ra, u32 rb) = 0; + virtual void CGTB(u32 rt, u32 ra, u32 rb) = 0; + virtual void SUMB(u32 rt, u32 ra, u32 rb) = 0; + virtual void HGT(u32 rt, u32 ra, u32 rb) = 0; + virtual void CLZ(u32 rt, u32 ra) = 0; + virtual void XSWD(u32 rt, u32 ra) = 0; + virtual void XSHW(u32 rt, u32 ra) = 0; + virtual void CNTB(u32 rt, u32 ra) = 0; + virtual void XSBH(u32 rt, u32 ra) = 0; + virtual void CLGT(u32 rt, u32 ra, u32 rb) = 0; + virtual void ANDC(u32 rt, u32 ra, u32 rb) = 0; + virtual void FCGT(u32 rt, u32 ra, u32 rb) = 0; + virtual void DFCGT(u32 rt, u32 ra, u32 rb) = 0; + virtual void FA(u32 rt, u32 ra, u32 rb) = 0; + virtual void FS(u32 rt, u32 ra, u32 rb) = 0; + virtual void FM(u32 rt, u32 ra, u32 rb) = 0; + virtual void CLGTH(u32 rt, u32 ra, u32 rb) = 0; + virtual void ORC(u32 rt, u32 ra, u32 rb) = 0; + virtual void FCMGT(u32 rt, u32 ra, u32 rb) = 0; + virtual void DFCMGT(u32 rt, u32 ra, u32 rb) = 0; + virtual void DFA(u32 rt, u32 ra, u32 rb) = 0; + virtual void DFS(u32 rt, u32 ra, u32 rb) = 0; + virtual void DFM(u32 rt, u32 ra, u32 rb) = 0; + virtual void CLGTB(u32 rt, u32 ra, u32 rb) = 0; + virtual void HLGT(u32 rt, u32 ra, u32 rb) = 0; + virtual void DFMA(u32 rt, u32 ra, u32 rb) = 0; + virtual void DFMS(u32 rt, u32 ra, u32 rb) = 0; + virtual void DFNMS(u32 rt, u32 ra, u32 rb) = 0; + virtual void DFNMA(u32 rt, u32 ra, u32 rb) = 0; + virtual void CEQ(u32 rt, u32 ra, u32 rb) = 0; + virtual void MPYHHU(u32 rt, u32 ra, u32 rb) = 0; + virtual void ADDX(u32 rt, u32 ra, u32 rb) = 0; + virtual void SFX(u32 rt, u32 ra, u32 rb) = 0; + virtual void CGX(u32 rt, u32 ra, u32 rb) = 0; + virtual void BGX(u32 rt, u32 ra, u32 rb) = 0; + virtual void MPYHHA(u32 rt, u32 ra, u32 rb) = 0; + virtual void MPYHHAU(u32 rt, u32 ra, u32 rb) = 0; + virtual void FSCRRD(u32 rt) = 0; + virtual void FESD(u32 rt, u32 ra) = 0; + virtual void FRDS(u32 rt, u32 ra) = 0; + virtual void FSCRWR(u32 rt, u32 ra) = 0; + virtual void DFTSV(u32 rt, u32 ra, s32 i7) = 0; + virtual void FCEQ(u32 rt, u32 ra, u32 rb) = 0; + virtual void DFCEQ(u32 rt, u32 ra, u32 rb) = 0; + virtual void MPY(u32 rt, u32 ra, u32 rb) = 0; + virtual void MPYH(u32 rt, u32 ra, u32 rb) = 0; + virtual void MPYHH(u32 rt, u32 ra, u32 rb) = 0; + virtual void MPYS(u32 rt, u32 ra, u32 rb) = 0; + virtual void CEQH(u32 rt, u32 ra, u32 rb) = 0; + virtual void FCMEQ(u32 rt, u32 ra, u32 rb) = 0; + virtual void DFCMEQ(u32 rt, u32 ra, u32 rb) = 0; + virtual void MPYU(u32 rt, u32 ra, u32 rb) = 0; + virtual void CEQB(u32 rt, u32 ra, u32 rb) = 0; + virtual void FI(u32 rt, u32 ra, u32 rb) = 0; + virtual void HEQ(u32 rt, u32 ra, u32 rb) = 0; //0 - 9 - ADD_OPCODE(CFLTS,(OP_REG rt, OP_REG ra, OP_sIMM i8)); - ADD_OPCODE(CFLTU,(OP_REG rt, OP_REG ra, OP_sIMM i8)); - ADD_OPCODE(CSFLT,(OP_REG rt, OP_REG ra, OP_sIMM i8)); - ADD_OPCODE(CUFLT,(OP_REG rt, OP_REG ra, OP_sIMM i8)); + virtual void CFLTS(u32 rt, u32 ra, s32 i8) = 0; + virtual void CFLTU(u32 rt, u32 ra, s32 i8) = 0; + virtual void CSFLT(u32 rt, u32 ra, s32 i8) = 0; + virtual void CUFLT(u32 rt, u32 ra, s32 i8) = 0; //0 - 8 - ADD_OPCODE(BRZ,(OP_REG rt, OP_sIMM i16)); - ADD_OPCODE(STQA,(OP_REG rt, OP_sIMM i16)); - ADD_OPCODE(BRNZ,(OP_REG rt, OP_sIMM i16)); - ADD_OPCODE(BRHZ,(OP_REG rt, OP_sIMM i16)); - ADD_OPCODE(BRHNZ,(OP_REG rt, OP_sIMM i16)); - ADD_OPCODE(STQR,(OP_REG rt, OP_sIMM i16)); - ADD_OPCODE(BRA,(OP_sIMM i16)); - ADD_OPCODE(LQA,(OP_REG rt, OP_sIMM i16)); - ADD_OPCODE(BRASL,(OP_REG rt, OP_sIMM i16)); - ADD_OPCODE(BR,(OP_sIMM i16)); - ADD_OPCODE(FSMBI,(OP_REG rt, OP_sIMM i16)); - ADD_OPCODE(BRSL,(OP_REG rt, OP_sIMM i16)); - ADD_OPCODE(LQR,(OP_REG rt, OP_sIMM i16)); - ADD_OPCODE(IL,(OP_REG rt, OP_sIMM i16)); - ADD_OPCODE(ILHU,(OP_REG rt, OP_sIMM i16)); - ADD_OPCODE(ILH,(OP_REG rt, OP_sIMM i16)); - ADD_OPCODE(IOHL,(OP_REG rt, OP_sIMM i16)); + virtual void BRZ(u32 rt, s32 i16) = 0; + virtual void STQA(u32 rt, s32 i16) = 0; + virtual void BRNZ(u32 rt, s32 i16) = 0; + virtual void BRHZ(u32 rt, s32 i16) = 0; + virtual void BRHNZ(u32 rt, s32 i16) = 0; + virtual void STQR(u32 rt, s32 i16) = 0; + virtual void BRA(s32 i16) = 0; + virtual void LQA(u32 rt, s32 i16) = 0; + virtual void BRASL(u32 rt, s32 i16) = 0; + virtual void BR(s32 i16) = 0; + virtual void FSMBI(u32 rt, s32 i16) = 0; + virtual void BRSL(u32 rt, s32 i16) = 0; + virtual void LQR(u32 rt, s32 i16) = 0; + virtual void IL(u32 rt, s32 i16) = 0; + virtual void ILHU(u32 rt, s32 i16) = 0; + virtual void ILH(u32 rt, s32 i16) = 0; + virtual void IOHL(u32 rt, s32 i16) = 0; //0 - 7 - ADD_OPCODE(ORI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(ORHI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(ORBI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(SFI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(SFHI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(ANDI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(ANDHI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(ANDBI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(AI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(AHI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(STQD,(OP_REG rt, OP_sIMM i10, OP_REG ra)); - ADD_OPCODE(LQD,(OP_REG rt, OP_sIMM i10, OP_REG ra)); - ADD_OPCODE(XORI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(XORHI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(XORBI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(CGTI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(CGTHI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(CGTBI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(HGTI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(CLGTI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(CLGTHI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(CLGTBI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(HLGTI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(MPYI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(MPYUI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(CEQI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(CEQHI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(CEQBI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); - ADD_OPCODE(HEQI,(OP_REG rt, OP_REG ra, OP_sIMM i10)); + virtual void ORI(u32 rt, u32 ra, s32 i10) = 0; + virtual void ORHI(u32 rt, u32 ra, s32 i10) = 0; + virtual void ORBI(u32 rt, u32 ra, s32 i10) = 0; + virtual void SFI(u32 rt, u32 ra, s32 i10) = 0; + virtual void SFHI(u32 rt, u32 ra, s32 i10) = 0; + virtual void ANDI(u32 rt, u32 ra, s32 i10) = 0; + virtual void ANDHI(u32 rt, u32 ra, s32 i10) = 0; + virtual void ANDBI(u32 rt, u32 ra, s32 i10) = 0; + virtual void AI(u32 rt, u32 ra, s32 i10) = 0; + virtual void AHI(u32 rt, u32 ra, s32 i10) = 0; + virtual void STQD(u32 rt, s32 i10, u32 ra) = 0; + virtual void LQD(u32 rt, s32 i10, u32 ra) = 0; + virtual void XORI(u32 rt, u32 ra, s32 i10) = 0; + virtual void XORHI(u32 rt, u32 ra, s32 i10) = 0; + virtual void XORBI(u32 rt, u32 ra, s32 i10) = 0; + virtual void CGTI(u32 rt, u32 ra, s32 i10) = 0; + virtual void CGTHI(u32 rt, u32 ra, s32 i10) = 0; + virtual void CGTBI(u32 rt, u32 ra, s32 i10) = 0; + virtual void HGTI(u32 rt, u32 ra, s32 i10) = 0; + virtual void CLGTI(u32 rt, u32 ra, s32 i10) = 0; + virtual void CLGTHI(u32 rt, u32 ra, s32 i10) = 0; + virtual void CLGTBI(u32 rt, u32 ra, s32 i10) = 0; + virtual void HLGTI(u32 rt, u32 ra, s32 i10) = 0; + virtual void MPYI(u32 rt, u32 ra, s32 i10) = 0; + virtual void MPYUI(u32 rt, u32 ra, s32 i10) = 0; + virtual void CEQI(u32 rt, u32 ra, s32 i10) = 0; + virtual void CEQHI(u32 rt, u32 ra, s32 i10) = 0; + virtual void CEQBI(u32 rt, u32 ra, s32 i10) = 0; + virtual void HEQI(u32 rt, u32 ra, s32 i10) = 0; //0 - 6 - ADD_OPCODE(HBRA,(OP_sIMM ro, OP_sIMM i16)); - ADD_OPCODE(HBRR,(OP_sIMM ro, OP_sIMM i16)); - ADD_OPCODE(ILA,(OP_REG rt, OP_sIMM i18)); + virtual void HBRA(s32 ro, s32 i16) = 0; + virtual void HBRR(s32 ro, s32 i16) = 0; + virtual void ILA(u32 rt, s32 i18) = 0; //0 - 3 - ADD_OPCODE(SELB,(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt)); - ADD_OPCODE(SHUFB,(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt)); - ADD_OPCODE(MPYA,(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt)); - ADD_OPCODE(FNMS,(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt)); - ADD_OPCODE(FMA,(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt)); - ADD_OPCODE(FMS,(OP_REG rc, OP_REG ra, OP_REG rb, OP_REG rt)); + virtual void SELB(u32 rc, u32 ra, u32 rb, u32 rt) = 0; + virtual void SHUFB(u32 rc, u32 ra, u32 rb, u32 rt) = 0; + virtual void MPYA(u32 rc, u32 ra, u32 rb, u32 rt) = 0; + virtual void FNMS(u32 rc, u32 ra, u32 rb, u32 rt) = 0; + virtual void FMA(u32 rc, u32 ra, u32 rb, u32 rt) = 0; + virtual void FMS(u32 rc, u32 ra, u32 rb, u32 rt) = 0; - ADD_OPCODE(UNK,(const s32 code, const s32 opcode, const s32 gcode)); + virtual void UNK(u32 code, u32 opcode, u32 gcode) = 0; }; - -#undef START_OPCODES_GROUP -#undef ADD_OPCODE -#undef ADD_NULL_OPCODE -#undef END_OPCODES_GROUP \ No newline at end of file diff --git a/rpcs3/Gui/CompilerELF.cpp b/rpcs3/Gui/CompilerELF.cpp index 4da6cb1e21..5cc0c44804 100644 --- a/rpcs3/Gui/CompilerELF.cpp +++ b/rpcs3/Gui/CompilerELF.cpp @@ -97,7 +97,7 @@ CompilerELF::CompilerELF(wxWindow* parent) " addi r11, r0, sys_tty_write\n" " sc 2\n" " cmpi cr7, 0, r3, 0\n" - " bc 0x04, 28, exit_err, 0, 0\n" + " bc 0x04, 30, exit_err, 0, 0\n" "\n" "exit_ok:\n" " addi r3, r0, 0\n" diff --git a/rpcs3/Gui/InterpreterDisAsm.cpp b/rpcs3/Gui/InterpreterDisAsm.cpp index 9b951d4592..bdf9a1e4de 100644 --- a/rpcs3/Gui/InterpreterDisAsm.cpp +++ b/rpcs3/Gui/InterpreterDisAsm.cpp @@ -1,11 +1,11 @@ #include "stdafx.h" #include "InterpreterDisAsm.h" -static const int show_lines = 30; +//static const int show_lines = 30; -u32 FixPc(const u32 pc) +u32 InterpreterDisAsmFrame::CentrePc(const u32 pc) const { - return pc - ((show_lines/2)*4); + return pc - ((m_item_count / 2) * 4); } InterpreterDisAsmFrame::InterpreterDisAsmFrame(wxWindow* parent, PPCThread* cpu) @@ -13,6 +13,7 @@ InterpreterDisAsmFrame::InterpreterDisAsmFrame(wxWindow* parent, PPCThread* cpu) , ThreadBase(false, "DisAsmFrame Thread") , CPU(*cpu) , PC(0) + , m_item_count(30) { if(CPU.IsSPU()) { @@ -64,8 +65,7 @@ InterpreterDisAsmFrame::InterpreterDisAsmFrame(wxWindow* parent, PPCThread* cpu) Layout(); m_list->InsertColumn(0, "ASM"); - - for(uint i=0; iInsertItem(m_list->GetItemCount(), wxEmptyString); } @@ -77,7 +77,7 @@ InterpreterDisAsmFrame::InterpreterDisAsmFrame(wxWindow* parent, PPCThread* cpu) Connect(m_btn_run->GetId(), wxEVT_COMMAND_BUTTON_CLICKED, wxCommandEventHandler(InterpreterDisAsmFrame::DoRun)); Connect(m_btn_pause->GetId(), wxEVT_COMMAND_BUTTON_CLICKED, wxCommandEventHandler(InterpreterDisAsmFrame::DoPause)); Connect(m_list->GetId(), wxEVT_COMMAND_LIST_ITEM_ACTIVATED, wxListEventHandler(InterpreterDisAsmFrame::DClick)); - //Connect(wxEVT_SIZE, wxSizeEventHandler(InterpreterDisAsmFrame::OnResize)); + Connect(wxEVT_SIZE, wxSizeEventHandler(InterpreterDisAsmFrame::OnResize)); m_app_connector.Connect(m_list->GetId(), wxEVT_MOUSEWHEEL, wxMouseEventHandler(InterpreterDisAsmFrame::MouseWheel), (wxObject*)0, this); m_app_connector.Connect(wxEVT_KEY_DOWN, wxKeyEventHandler(InterpreterDisAsmFrame::OnKeyDown), (wxObject*)0, this); @@ -110,16 +110,50 @@ void InterpreterDisAsmFrame::OnKeyDown(wxKeyEvent& event) { switch(event.GetKeyCode()) { - case WXK_PAGEUP: ShowAddr( PC - (show_lines * 2) * 4 ); return; + case WXK_PAGEUP: ShowAddr( PC - (m_item_count * 2) * 4 ); return; case WXK_PAGEDOWN: ShowAddr( PC ); return; - case WXK_UP: ShowAddr( PC - (show_lines + 1) * 4 ); return; - case WXK_DOWN: ShowAddr( PC - (show_lines - 1) * 4 ); return; + case WXK_UP: ShowAddr( PC - (m_item_count + 1) * 4 ); return; + case WXK_DOWN: ShowAddr( PC - (m_item_count - 1) * 4 ); return; } } event.Skip(); } +void InterpreterDisAsmFrame::OnResize(wxSizeEvent& event) +{ + event.Skip(); + + if(0) + { + if(!m_list->GetItemCount()) + { + m_list->InsertItem(m_list->GetItemCount(), wxEmptyString); + } + + int size = 0; + m_list->DeleteAllItems(); + int item = 0; + while(size < m_list->GetSize().GetHeight()) + { + item = m_list->GetItemCount(); + m_list->InsertItem(item, wxEmptyString); + wxRect rect; + m_list->GetItemRect(item, rect); + + size = rect.GetBottom(); + } + + if(item) + { + m_list->DeleteItem(--item); + } + + m_item_count = item; + ShowAddr(PC); + } +} + void InterpreterDisAsmFrame::DoUpdate() { Show_PC(wxCommandEvent()); @@ -130,7 +164,7 @@ void InterpreterDisAsmFrame::ShowAddr(const u64 addr) { PC = addr; m_list->Freeze(); - for(uint i=0; iGetLabel(), "%llx", &pc); remove_markedPC.AddCpy(Emu.GetMarkedPoints().AddCpy(pc)); - ShowAddr(FixPc(pc)); + ShowAddr(CentrePc(pc)); } } void InterpreterDisAsmFrame::Show_PC(wxCommandEvent& WXUNUSED(event)) { - ShowAddr(FixPc(CPU.PC)); + ShowAddr(CentrePc(CPU.PC)); } extern bool dump_enable; void InterpreterDisAsmFrame::DoRun(wxCommandEvent& WXUNUSED(event)) { if(CPU.IsPaused()) CPU.Resume(); - if(Emu.IsPaused()) Emu.Resume(); - CPU.Exec(); + if(!Emu.IsPaused()) + { + CPU.Exec(); + } + //ThreadBase::Start(); } @@ -319,7 +356,7 @@ void InterpreterDisAsmFrame::DClick(wxListEvent& event) long i = m_list->GetFirstSelected(); if(i < 0) return; - const u64 start_pc = PC - show_lines*4; + const u64 start_pc = PC - m_item_count*4; const u64 pc = start_pc + i*4; //ConLog.Write("pc=0x%llx", pc); @@ -341,7 +378,7 @@ void InterpreterDisAsmFrame::MouseWheel(wxMouseEvent& event) { const int value = (event.m_wheelRotation / event.m_wheelDelta); - ShowAddr( PC - (event.ControlDown() ? show_lines * (value + 1) : show_lines + value) * 4); + ShowAddr( PC - (event.ControlDown() ? m_item_count * (value + 1) : m_item_count + value) * 4); event.Skip(); } diff --git a/rpcs3/Gui/InterpreterDisAsm.h b/rpcs3/Gui/InterpreterDisAsm.h index a3ebe3df7f..57d3846fcb 100644 --- a/rpcs3/Gui/InterpreterDisAsm.h +++ b/rpcs3/Gui/InterpreterDisAsm.h @@ -19,6 +19,7 @@ class InterpreterDisAsmFrame wxButton* m_btn_run; wxButton* m_btn_pause; AppConnector m_app_connector; + u32 m_item_count; public: PPCThread& CPU; @@ -27,7 +28,10 @@ public: InterpreterDisAsmFrame(wxWindow* parent, PPCThread* cpu); ~InterpreterDisAsmFrame(); + u32 CentrePc(const u32 pc) const; + void OnKeyDown(wxKeyEvent& event); + void OnResize(wxSizeEvent& event); void DoUpdate(); void ShowAddr(const u64 addr); void WriteRegs();