mirror of https://github.com/RPCS3/rpcs3.git
Nekotekina
parent
43a61d0ab9
commit
82433d946e
|
|
@ -1,5 +1,182 @@
|
|||
#pragma once
|
||||
|
||||
union u128
|
||||
{
|
||||
struct
|
||||
{
|
||||
u64 hi;
|
||||
u64 lo;
|
||||
};
|
||||
|
||||
u64 _u64[2];
|
||||
s64 _s64[2];
|
||||
u32 _u32[4];
|
||||
s32 _s32[4];
|
||||
u16 _u16[8];
|
||||
s16 _s16[8];
|
||||
u8 _u8[16];
|
||||
s8 _s8[16];
|
||||
float _f[4];
|
||||
double _d[2];
|
||||
|
||||
class bit_array_128
|
||||
{
|
||||
u64 data[2];
|
||||
|
||||
public:
|
||||
class bit_element
|
||||
{
|
||||
u64& data;
|
||||
const u64 mask;
|
||||
|
||||
public:
|
||||
bit_element(u64& data, const u64 mask)
|
||||
: data(data)
|
||||
, mask(mask)
|
||||
{
|
||||
}
|
||||
|
||||
__forceinline operator bool() const
|
||||
{
|
||||
return (data & mask) != 0;
|
||||
}
|
||||
|
||||
__forceinline bit_element& operator = (const bool right)
|
||||
{
|
||||
if (right)
|
||||
{
|
||||
data |= mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
data &= ~mask;
|
||||
}
|
||||
return *this;
|
||||
}
|
||||
|
||||
__forceinline bit_element& operator = (const bit_element& right)
|
||||
{
|
||||
if (right)
|
||||
{
|
||||
data |= mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
data &= ~mask;
|
||||
}
|
||||
return *this;
|
||||
}
|
||||
};
|
||||
|
||||
bit_element operator [] (u32 index)
|
||||
{
|
||||
assert(index < 128);
|
||||
return bit_element(data[index / 64], 1ull << (index % 64));
|
||||
}
|
||||
|
||||
const bool operator [] (u32 index) const
|
||||
{
|
||||
assert(index < 128);
|
||||
return (data[index / 64] & (1ull << (index % 64))) != 0;
|
||||
}
|
||||
|
||||
} _bit;
|
||||
|
||||
//operator u64() const { return _u64[0]; }
|
||||
//operator u32() const { return _u32[0]; }
|
||||
//operator u16() const { return _u16[0]; }
|
||||
//operator u8() const { return _u8[0]; }
|
||||
|
||||
//operator bool() const { return _u64[0] != 0 || _u64[1] != 0; }
|
||||
|
||||
static u128 from128(u64 hi, u64 lo)
|
||||
{
|
||||
u128 ret = { hi, lo };
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u128 from64(u64 src)
|
||||
{
|
||||
u128 ret = { 0, src };
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u128 from32(u32 src)
|
||||
{
|
||||
u128 ret;
|
||||
ret._u32[0] = src;
|
||||
ret._u32[1] = 0;
|
||||
ret._u32[2] = 0;
|
||||
ret._u32[3] = 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u128 fromBit(u32 bit)
|
||||
{
|
||||
u128 ret;
|
||||
ret._bit[bit] = true;
|
||||
return ret;
|
||||
}
|
||||
|
||||
void setBit(u32 bit)
|
||||
{
|
||||
_bit[bit] = true;
|
||||
}
|
||||
|
||||
bool operator == (const u128& right) const
|
||||
{
|
||||
return (lo == right.lo) && (hi == right.hi);
|
||||
}
|
||||
|
||||
bool operator != (const u128& right) const
|
||||
{
|
||||
return (lo != right.lo) || (hi != right.hi);
|
||||
}
|
||||
|
||||
u128 operator | (const u128& right) const
|
||||
{
|
||||
return from128(hi | right.hi, lo | right.lo);
|
||||
}
|
||||
|
||||
u128 operator & (const u128& right) const
|
||||
{
|
||||
return from128(hi & right.hi, lo & right.lo);
|
||||
}
|
||||
|
||||
u128 operator ^ (const u128& right) const
|
||||
{
|
||||
return from128(hi ^ right.hi, lo ^ right.lo);
|
||||
}
|
||||
|
||||
u128 operator ~ () const
|
||||
{
|
||||
return from128(~hi, ~lo);
|
||||
}
|
||||
|
||||
void clear()
|
||||
{
|
||||
hi = lo = 0;
|
||||
}
|
||||
|
||||
std::string to_hex() const
|
||||
{
|
||||
return fmt::Format("%08x%08x%08x%08x", _u32[3], _u32[2], _u32[1], _u32[0]);
|
||||
}
|
||||
|
||||
std::string to_xyzw() const
|
||||
{
|
||||
return fmt::Format("x: %g y: %g z: %g w: %g", _f[3], _f[2], _f[1], _f[0]);
|
||||
}
|
||||
|
||||
static __forceinline u128 byteswap(const u128 val)
|
||||
{
|
||||
u128 ret;
|
||||
ret.lo = _byteswap_uint64(val.hi);
|
||||
ret.hi = _byteswap_uint64(val.lo);
|
||||
return ret;
|
||||
}
|
||||
};
|
||||
|
||||
#define re16(val) _byteswap_ushort(val)
|
||||
#define re32(val) _byteswap_ulong(val)
|
||||
#define re64(val) _byteswap_uint64(val)
|
||||
|
|
|
|||
|
|
@ -169,7 +169,7 @@ private:
|
|||
|
||||
void MFVSCR(u32 vd) //nf
|
||||
{
|
||||
CPU.VPR[vd].Clear();
|
||||
CPU.VPR[vd].clear();
|
||||
CPU.VPR[vd]._u32[0] = CPU.VSCR.VSCR;
|
||||
}
|
||||
void MTVSCR(u32 vb)
|
||||
|
|
@ -965,8 +965,8 @@ private:
|
|||
}
|
||||
void VMRGHB(u32 vd, u32 va, u32 vb)
|
||||
{
|
||||
VPR_reg VA = CPU.VPR[va];
|
||||
VPR_reg VB = CPU.VPR[vb];
|
||||
u128 VA = CPU.VPR[va];
|
||||
u128 VB = CPU.VPR[vb];
|
||||
for (uint h = 0; h < 8; h++)
|
||||
{
|
||||
CPU.VPR[vd]._u8[15 - h*2] = VA._u8[15 - h];
|
||||
|
|
@ -975,8 +975,8 @@ private:
|
|||
}
|
||||
void VMRGHH(u32 vd, u32 va, u32 vb)
|
||||
{
|
||||
VPR_reg VA = CPU.VPR[va];
|
||||
VPR_reg VB = CPU.VPR[vb];
|
||||
u128 VA = CPU.VPR[va];
|
||||
u128 VB = CPU.VPR[vb];
|
||||
for (uint w = 0; w < 4; w++)
|
||||
{
|
||||
CPU.VPR[vd]._u16[7 - w*2] = VA._u16[7 - w];
|
||||
|
|
@ -985,8 +985,8 @@ private:
|
|||
}
|
||||
void VMRGHW(u32 vd, u32 va, u32 vb)
|
||||
{
|
||||
VPR_reg VA = CPU.VPR[va];
|
||||
VPR_reg VB = CPU.VPR[vb];
|
||||
u128 VA = CPU.VPR[va];
|
||||
u128 VB = CPU.VPR[vb];
|
||||
for (uint d = 0; d < 2; d++)
|
||||
{
|
||||
CPU.VPR[vd]._u32[3 - d*2] = VA._u32[3 - d];
|
||||
|
|
@ -1578,7 +1578,7 @@ private:
|
|||
{
|
||||
u8 nShift = (CPU.VPR[vb]._u8[0] >> 3) & 0xf;
|
||||
|
||||
CPU.VPR[vd].Clear();
|
||||
CPU.VPR[vd].clear();
|
||||
|
||||
for (u8 b = 0; b < 16 - nShift; b++)
|
||||
{
|
||||
|
|
@ -1711,7 +1711,7 @@ private:
|
|||
{
|
||||
u8 nShift = (CPU.VPR[vb]._u8[0] >> 3) & 0xf;
|
||||
|
||||
CPU.VPR[vd].Clear();
|
||||
CPU.VPR[vd].clear();
|
||||
|
||||
for (u8 b = 0; b < 16 - nShift; b++)
|
||||
{
|
||||
|
|
@ -1867,7 +1867,7 @@ private:
|
|||
}
|
||||
void VSUMSWS(u32 vd, u32 va, u32 vb)
|
||||
{
|
||||
CPU.VPR[vd].Clear();
|
||||
CPU.VPR[vd].clear();
|
||||
|
||||
s64 sum = CPU.VPR[vb]._s32[3];
|
||||
|
||||
|
|
@ -2301,7 +2301,7 @@ private:
|
|||
//const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb];
|
||||
//CPU.VPR[vd].Clear();
|
||||
//CPU.VPR[vd]._u8[addr & 0xf] = vm::read8(addr);
|
||||
CPU.VPR[vd]._u128 = vm::read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL);
|
||||
CPU.VPR[vd] = vm::read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL);
|
||||
}
|
||||
void SUBFC(u32 rd, u32 ra, u32 rb, u32 oe, bool rc)
|
||||
{
|
||||
|
|
@ -2450,7 +2450,7 @@ private:
|
|||
//const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~1ULL;
|
||||
//CPU.VPR[vd].Clear();
|
||||
//(u16&)CPU.VPR[vd]._u8[addr & 0xf] = vm::read16(addr);
|
||||
CPU.VPR[vd]._u128 = vm::read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL);
|
||||
CPU.VPR[vd] = vm::read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL);
|
||||
}
|
||||
void SUBF(u32 rd, u32 ra, u32 rb, u32 oe, bool rc)
|
||||
{
|
||||
|
|
@ -2500,7 +2500,7 @@ private:
|
|||
//const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~3ULL;
|
||||
//CPU.VPR[vd].Clear();
|
||||
//(u32&)CPU.VPR[vd]._u8[addr & 0xf] = vm::read32(addr);
|
||||
CPU.VPR[vd]._u128 = vm::read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL);
|
||||
CPU.VPR[vd] = vm::read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL);
|
||||
}
|
||||
void MULHD(u32 rd, u32 ra, u32 rb, bool rc)
|
||||
{
|
||||
|
|
@ -2531,7 +2531,7 @@ private:
|
|||
}
|
||||
void LVX(u32 vd, u32 ra, u32 rb)
|
||||
{
|
||||
CPU.VPR[vd]._u128 = vm::read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL);
|
||||
CPU.VPR[vd] = vm::read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL);
|
||||
}
|
||||
void NEG(u32 rd, u32 ra, u32 oe, bool rc)
|
||||
{
|
||||
|
|
@ -2707,7 +2707,7 @@ private:
|
|||
}
|
||||
void STVX(u32 vs, u32 ra, u32 rb)
|
||||
{
|
||||
vm::write128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL, CPU.VPR[vs]._u128);
|
||||
vm::write128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL, CPU.VPR[vs]);
|
||||
}
|
||||
void SUBFME(u32 rd, u32 ra, u32 oe, bool rc)
|
||||
{
|
||||
|
|
@ -2805,7 +2805,7 @@ private:
|
|||
}
|
||||
void LVXL(u32 vd, u32 ra, u32 rb)
|
||||
{
|
||||
CPU.VPR[vd]._u128 = vm::read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL);
|
||||
CPU.VPR[vd] = vm::read128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL);
|
||||
}
|
||||
void MFTB(u32 rd, u32 spr)
|
||||
{
|
||||
|
|
@ -2906,7 +2906,7 @@ private:
|
|||
}
|
||||
void STVXL(u32 vs, u32 ra, u32 rb)
|
||||
{
|
||||
vm::write128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL, CPU.VPR[vs]._u128);
|
||||
vm::write128((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~0xfULL, CPU.VPR[vs]);
|
||||
}
|
||||
void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc)
|
||||
{
|
||||
|
|
@ -2947,7 +2947,7 @@ private:
|
|||
const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb];
|
||||
const u8 eb = addr & 0xf;
|
||||
|
||||
CPU.VPR[vd].Clear();
|
||||
CPU.VPR[vd].clear();
|
||||
for (u32 i = 0; i < 16 - eb; ++i) CPU.VPR[vd]._u8[15 - i] = vm::read8(addr + i);
|
||||
}
|
||||
void LDBRX(u32 rd, u32 ra, u32 rb)
|
||||
|
|
@ -2990,7 +2990,7 @@ private:
|
|||
const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb];
|
||||
const u8 eb = addr & 0xf;
|
||||
|
||||
CPU.VPR[vd].Clear();
|
||||
CPU.VPR[vd].clear();
|
||||
for (u32 i = 16 - eb; i < 16; ++i) CPU.VPR[vd]._u8[15 - i] = vm::read8(addr + i - 16);
|
||||
}
|
||||
void LSWI(u32 rd, u32 ra, u32 nb)
|
||||
|
|
@ -3117,7 +3117,7 @@ private:
|
|||
const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb];
|
||||
const u8 eb = addr & 0xf;
|
||||
|
||||
CPU.VPR[vd].Clear();
|
||||
CPU.VPR[vd].clear();
|
||||
for (u32 i = 0; i < 16 - eb; ++i) CPU.VPR[vd]._u8[15 - i] = vm::read8(addr + i);
|
||||
}
|
||||
void LHBRX(u32 rd, u32 ra, u32 rb)
|
||||
|
|
@ -3163,7 +3163,7 @@ private:
|
|||
const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb];
|
||||
const u8 eb = addr & 0xf;
|
||||
|
||||
CPU.VPR[vd].Clear();
|
||||
CPU.VPR[vd].clear();
|
||||
for (u32 i = 16 - eb; i < 16; ++i) CPU.VPR[vd]._u8[15 - i] = vm::read8(addr + i - 16);
|
||||
}
|
||||
void DSS(u32 strm, u32 a)
|
||||
|
|
@ -3993,7 +3993,7 @@ private:
|
|||
|
||||
for(uint i=0; i<32; ++i) LOG_NOTICE(PPU, "r%d = 0x%llx", i, CPU.GPR[i]);
|
||||
for(uint i=0; i<32; ++i) LOG_NOTICE(PPU, "f%d = %llf", i, CPU.FPR[i]);
|
||||
for(uint i=0; i<32; ++i) LOG_NOTICE(PPU, "v%d = 0x%s [%s]", i, CPU.VPR[i].ToString(true).c_str(), CPU.VPR[i].ToString().c_str());
|
||||
for(uint i=0; i<32; ++i) LOG_NOTICE(PPU, "v%d = 0x%s [%s]", i, CPU.VPR[i].to_hex().c_str(), CPU.VPR[i].to_xyzw().c_str());
|
||||
LOG_NOTICE(PPU, "CR = 0x%08x", CPU.CR);
|
||||
LOG_NOTICE(PPU, "LR = 0x%llx", CPU.LR);
|
||||
LOG_NOTICE(PPU, "CTR = 0x%llx", CPU.CTR);
|
||||
|
|
|
|||
|
|
@ -468,57 +468,6 @@ struct FPRdouble
|
|||
static int Cmp(PPCdouble a, PPCdouble b);
|
||||
};
|
||||
|
||||
union VPR_reg
|
||||
{
|
||||
u128 _u128;
|
||||
u64 _u64[2];
|
||||
s64 _s64[2];
|
||||
u32 _u32[4];
|
||||
s32 _s32[4];
|
||||
u16 _u16[8];
|
||||
s16 _s16[8];
|
||||
u8 _u8[16];
|
||||
s8 _s8[16];
|
||||
float _f[4];
|
||||
double _d[2];
|
||||
|
||||
VPR_reg() { Clear(); }
|
||||
|
||||
std::string ToString(bool hex = false) const
|
||||
{
|
||||
if(hex) return fmt::Format("%08x%08x%08x%08x", _u32[3], _u32[2], _u32[1], _u32[0]);
|
||||
|
||||
return fmt::Format("x: %g y: %g z: %g w: %g", _f[3], _f[2], _f[1], _f[0]);
|
||||
}
|
||||
|
||||
u8 GetBit(u8 bit)
|
||||
{
|
||||
if(bit < 64) return (_u64[0] >> bit) & 0x1;
|
||||
|
||||
return (_u64[1] >> (bit - 64)) & 0x1;
|
||||
}
|
||||
|
||||
void SetBit(u8 bit, u8 value)
|
||||
{
|
||||
if(bit < 64)
|
||||
{
|
||||
_u64[0] &= ~(1 << bit);
|
||||
_u64[0] |= (value & 0x1) << bit;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
bit -= 64;
|
||||
|
||||
_u64[1] &= ~(1 << bit);
|
||||
_u64[1] |= (value & 0x1) << bit;
|
||||
}
|
||||
|
||||
void Clear() { _u64[1] = _u64[0] = 0; }
|
||||
};
|
||||
|
||||
static const s32 MAX_INT_VALUE = 0x7fffffff;
|
||||
|
||||
class PPUThread : public PPCThread
|
||||
{
|
||||
public:
|
||||
|
|
@ -528,7 +477,7 @@ public:
|
|||
PPCdouble FPR[32]; //Floating Point Register
|
||||
FPSCRhdr FPSCR; //Floating Point Status and Control Register
|
||||
u64 GPR[32]; //General-Purpose Register
|
||||
VPR_reg VPR[32];
|
||||
u128 VPR[32];
|
||||
u32 vpcr;
|
||||
|
||||
CRhdr CR; //Condition Register
|
||||
|
|
@ -741,7 +690,7 @@ public:
|
|||
|
||||
for(uint i=0; i<32; ++i) ret += fmt::Format("GPR[%d] = 0x%llx\n", i, GPR[i]);
|
||||
for(uint i=0; i<32; ++i) ret += fmt::Format("FPR[%d] = %.6G\n", i, (double)FPR[i]);
|
||||
for(uint i=0; i<32; ++i) ret += fmt::Format("VPR[%d] = 0x%s [%s]\n", i, (const char*)VPR[i].ToString(true).c_str(), (const char*)VPR[i].ToString().c_str());
|
||||
for(uint i=0; i<32; ++i) ret += fmt::Format("VPR[%d] = 0x%s [%s]\n", i, VPR[i].to_hex().c_str(), VPR[i].to_xyzw().c_str());
|
||||
ret += fmt::Format("CR = 0x%08x\n", CR.CR);
|
||||
ret += fmt::Format("LR = 0x%llx\n", LR);
|
||||
ret += fmt::Format("CTR = 0x%llx\n", CTR);
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@ private:
|
|||
}
|
||||
void RCHCNT(u32 rt, u32 ra)
|
||||
{
|
||||
CPU.GPR[rt].Reset();
|
||||
CPU.GPR[rt].clear();
|
||||
CPU.GPR[rt]._u32[3] = CPU.GetChannelCount(ra);
|
||||
}
|
||||
void SF(u32 rt, u32 ra, u32 rb)
|
||||
|
|
@ -112,10 +112,10 @@ private:
|
|||
}
|
||||
void ROTMA(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
CPU.GPR[rt]._i32[0] = ((0 - CPU.GPR[rb]._u32[0]) & 0x3f) < 32 ? CPU.GPR[ra]._i32[0] >> ((0 - CPU.GPR[rb]._u32[0]) & 0x3f) : CPU.GPR[ra]._i32[0] >> 31;
|
||||
CPU.GPR[rt]._i32[1] = ((0 - CPU.GPR[rb]._u32[1]) & 0x3f) < 32 ? CPU.GPR[ra]._i32[1] >> ((0 - CPU.GPR[rb]._u32[1]) & 0x3f) : CPU.GPR[ra]._i32[1] >> 31;
|
||||
CPU.GPR[rt]._i32[2] = ((0 - CPU.GPR[rb]._u32[2]) & 0x3f) < 32 ? CPU.GPR[ra]._i32[2] >> ((0 - CPU.GPR[rb]._u32[2]) & 0x3f) : CPU.GPR[ra]._i32[2] >> 31;
|
||||
CPU.GPR[rt]._i32[3] = ((0 - CPU.GPR[rb]._u32[3]) & 0x3f) < 32 ? CPU.GPR[ra]._i32[3] >> ((0 - CPU.GPR[rb]._u32[3]) & 0x3f) : CPU.GPR[ra]._i32[3] >> 31;
|
||||
CPU.GPR[rt]._s32[0] = ((0 - CPU.GPR[rb]._u32[0]) & 0x3f) < 32 ? CPU.GPR[ra]._s32[0] >> ((0 - CPU.GPR[rb]._u32[0]) & 0x3f) : CPU.GPR[ra]._s32[0] >> 31;
|
||||
CPU.GPR[rt]._s32[1] = ((0 - CPU.GPR[rb]._u32[1]) & 0x3f) < 32 ? CPU.GPR[ra]._s32[1] >> ((0 - CPU.GPR[rb]._u32[1]) & 0x3f) : CPU.GPR[ra]._s32[1] >> 31;
|
||||
CPU.GPR[rt]._s32[2] = ((0 - CPU.GPR[rb]._u32[2]) & 0x3f) < 32 ? CPU.GPR[ra]._s32[2] >> ((0 - CPU.GPR[rb]._u32[2]) & 0x3f) : CPU.GPR[ra]._s32[2] >> 31;
|
||||
CPU.GPR[rt]._s32[3] = ((0 - CPU.GPR[rb]._u32[3]) & 0x3f) < 32 ? CPU.GPR[ra]._s32[3] >> ((0 - CPU.GPR[rb]._u32[3]) & 0x3f) : CPU.GPR[ra]._s32[3] >> 31;
|
||||
}
|
||||
void SHL(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
|
|
@ -137,7 +137,7 @@ private:
|
|||
void ROTMAH(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
for (int h = 0; h < 8; h++)
|
||||
CPU.GPR[rt]._i16[h] = ((0 - CPU.GPR[rb]._u16[h]) & 0x1f) < 16 ? CPU.GPR[ra]._i16[h] >> ((0 - CPU.GPR[rb]._u16[h]) & 0x1f) : CPU.GPR[ra]._i16[h] >> 15;
|
||||
CPU.GPR[rt]._s16[h] = ((0 - CPU.GPR[rb]._u16[h]) & 0x1f) < 16 ? CPU.GPR[ra]._s16[h] >> ((0 - CPU.GPR[rb]._u16[h]) & 0x1f) : CPU.GPR[ra]._s16[h] >> 15;
|
||||
}
|
||||
void SHLH(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
|
|
@ -163,10 +163,10 @@ private:
|
|||
void ROTMAI(u32 rt, u32 ra, s32 i7)
|
||||
{
|
||||
const int nRot = (0 - i7) & 0x3f;
|
||||
CPU.GPR[rt]._i32[0] = nRot < 32 ? CPU.GPR[ra]._i32[0] >> nRot : CPU.GPR[ra]._i32[0] >> 31;
|
||||
CPU.GPR[rt]._i32[1] = nRot < 32 ? CPU.GPR[ra]._i32[1] >> nRot : CPU.GPR[ra]._i32[1] >> 31;
|
||||
CPU.GPR[rt]._i32[2] = nRot < 32 ? CPU.GPR[ra]._i32[2] >> nRot : CPU.GPR[ra]._i32[2] >> 31;
|
||||
CPU.GPR[rt]._i32[3] = nRot < 32 ? CPU.GPR[ra]._i32[3] >> nRot : CPU.GPR[ra]._i32[3] >> 31;
|
||||
CPU.GPR[rt]._s32[0] = nRot < 32 ? CPU.GPR[ra]._s32[0] >> nRot : CPU.GPR[ra]._s32[0] >> 31;
|
||||
CPU.GPR[rt]._s32[1] = nRot < 32 ? CPU.GPR[ra]._s32[1] >> nRot : CPU.GPR[ra]._s32[1] >> 31;
|
||||
CPU.GPR[rt]._s32[2] = nRot < 32 ? CPU.GPR[ra]._s32[2] >> nRot : CPU.GPR[ra]._s32[2] >> 31;
|
||||
CPU.GPR[rt]._s32[3] = nRot < 32 ? CPU.GPR[ra]._s32[3] >> nRot : CPU.GPR[ra]._s32[3] >> 31;
|
||||
}
|
||||
void SHLI(u32 rt, u32 ra, s32 i7)
|
||||
{
|
||||
|
|
@ -194,7 +194,7 @@ private:
|
|||
const int nRot = (0 - i7) & 0x1f;
|
||||
|
||||
for (int h = 0; h < 8; h++)
|
||||
CPU.GPR[rt]._i16[h] = nRot < 16 ? CPU.GPR[ra]._i16[h] >> nRot : CPU.GPR[ra]._i16[h] >> 15;
|
||||
CPU.GPR[rt]._s16[h] = nRot < 16 ? CPU.GPR[ra]._s16[h] >> nRot : CPU.GPR[ra]._s16[h] >> 15;
|
||||
}
|
||||
void SHLHI(u32 rt, u32 ra, s32 i7)
|
||||
{
|
||||
|
|
@ -333,7 +333,7 @@ private:
|
|||
{
|
||||
u32 lsa = (CPU.GPR[ra]._u32[3] + CPU.GPR[rb]._u32[3]) & 0x3fff0;
|
||||
|
||||
CPU.WriteLS128(lsa, CPU.GPR[rt]._u128);
|
||||
CPU.WriteLS128(lsa, CPU.GPR[rt]);
|
||||
}
|
||||
void BI(u32 intr, u32 ra)
|
||||
{
|
||||
|
|
@ -356,7 +356,7 @@ private:
|
|||
}
|
||||
|
||||
u64 target = branchTarget(CPU.GPR[ra]._u32[3], 0);
|
||||
CPU.GPR[rt].Reset();
|
||||
CPU.GPR[rt].clear();
|
||||
CPU.GPR[rt]._u32[3] = (u32)CPU.PC + 4;
|
||||
LOG5_OPCODE("branch (0x%llx)", target);
|
||||
CPU.SetBranch(target);
|
||||
|
|
@ -436,28 +436,28 @@ private:
|
|||
|
||||
u32 lsa = (a + b) & 0x3fff0;
|
||||
|
||||
CPU.GPR[rt]._u128 = CPU.ReadLS128(lsa);
|
||||
CPU.GPR[rt] = CPU.ReadLS128(lsa);
|
||||
}
|
||||
void ROTQBYBI(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
const int s = (CPU.GPR[rb]._u32[3] >> 3) & 0xf;
|
||||
const SPU_GPR_hdr temp = CPU.GPR[ra];
|
||||
const u128 temp = CPU.GPR[ra];
|
||||
for (int b = 0; b < 16; b++)
|
||||
CPU.GPR[rt]._u8[b] = temp._u8[(b - s) & 0xf];
|
||||
}
|
||||
void ROTQMBYBI(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
const int s = (0 - (CPU.GPR[rb]._u32[3] >> 3)) & 0x1f;
|
||||
const SPU_GPR_hdr temp = CPU.GPR[ra];
|
||||
CPU.GPR[rt].Reset();
|
||||
const u128 temp = CPU.GPR[ra];
|
||||
CPU.GPR[rt].clear();
|
||||
for (int b = 0; b < 16 - s; b++)
|
||||
CPU.GPR[rt]._u8[b] = temp._u8[b + s];
|
||||
}
|
||||
void SHLQBYBI(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
const int s = (CPU.GPR[rb]._u32[3] >> 3) & 0x1f;
|
||||
const SPU_GPR_hdr temp = CPU.GPR[ra];
|
||||
CPU.GPR[rt].Reset();
|
||||
const u128 temp = CPU.GPR[ra];
|
||||
CPU.GPR[rt].clear();
|
||||
for (int b = s; b < 16; b++)
|
||||
CPU.GPR[rt]._u8[b] = temp._u8[b - s];
|
||||
}
|
||||
|
|
@ -498,7 +498,7 @@ private:
|
|||
const int t = CPU.GPR[rb]._u32[3] & 0x7;
|
||||
if (t) // not an optimization, it fixes shifts
|
||||
{
|
||||
const SPU_GPR_hdr temp = CPU.GPR[ra];
|
||||
const u128 temp = CPU.GPR[ra];
|
||||
CPU.GPR[rt]._u32[0] = (temp._u32[0] << t) | (temp._u32[3] >> (32 - t));
|
||||
CPU.GPR[rt]._u32[1] = (temp._u32[1] << t) | (temp._u32[0] >> (32 - t));
|
||||
CPU.GPR[rt]._u32[2] = (temp._u32[2] << t) | (temp._u32[1] >> (32 - t));
|
||||
|
|
@ -514,7 +514,7 @@ private:
|
|||
const int t = (0 - CPU.GPR[rb]._u32[3]) & 0x7;
|
||||
if (t) // not an optimization, it fixes shifts
|
||||
{
|
||||
const SPU_GPR_hdr temp = CPU.GPR[ra];
|
||||
const u128 temp = CPU.GPR[ra];
|
||||
CPU.GPR[rt]._u32[0] = (temp._u32[0] >> t) | (temp._u32[1] << (32 - t));
|
||||
CPU.GPR[rt]._u32[1] = (temp._u32[1] >> t) | (temp._u32[2] << (32 - t));
|
||||
CPU.GPR[rt]._u32[2] = (temp._u32[2] >> t) | (temp._u32[3] << (32 - t));
|
||||
|
|
@ -530,7 +530,7 @@ private:
|
|||
const int t = CPU.GPR[rb]._u32[3] & 0x7;
|
||||
if (t) // not an optimization, it fixes shifts
|
||||
{
|
||||
const SPU_GPR_hdr temp = CPU.GPR[ra];
|
||||
const u128 temp = CPU.GPR[ra];
|
||||
CPU.GPR[rt]._u32[0] = (temp._u32[0] << t);
|
||||
CPU.GPR[rt]._u32[1] = (temp._u32[1] << t) | (temp._u32[0] >> (32 - t));
|
||||
CPU.GPR[rt]._u32[2] = (temp._u32[2] << t) | (temp._u32[1] >> (32 - t));
|
||||
|
|
@ -544,23 +544,23 @@ private:
|
|||
void ROTQBY(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
const int s = CPU.GPR[rb]._u32[3] & 0xf;
|
||||
const SPU_GPR_hdr temp = CPU.GPR[ra];
|
||||
const u128 temp = CPU.GPR[ra];
|
||||
for (int b = 0; b < 16; ++b)
|
||||
CPU.GPR[rt]._u8[b] = temp._u8[(b - s) & 0xf];
|
||||
}
|
||||
void ROTQMBY(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
const int s = (0 - CPU.GPR[rb]._u32[3]) & 0x1f;
|
||||
const SPU_GPR_hdr temp = CPU.GPR[ra];
|
||||
CPU.GPR[rt].Reset();
|
||||
const u128 temp = CPU.GPR[ra];
|
||||
CPU.GPR[rt].clear();
|
||||
for (int b = 0; b < 16 - s; b++)
|
||||
CPU.GPR[rt]._u8[b] = temp._u8[b + s];
|
||||
}
|
||||
void SHLQBY(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
const int s = CPU.GPR[rb]._u32[3] & 0x1f;
|
||||
const SPU_GPR_hdr temp = CPU.GPR[ra];
|
||||
CPU.GPR[rt].Reset();
|
||||
const u128 temp = CPU.GPR[ra];
|
||||
CPU.GPR[rt].clear();
|
||||
for (int b = s; b < 16; b++)
|
||||
CPU.GPR[rt]._u8[b] = temp._u8[b - s];
|
||||
}
|
||||
|
|
@ -607,7 +607,7 @@ private:
|
|||
const int s = i7 & 0x7;
|
||||
if (s) // not an optimization, it fixes shifts
|
||||
{
|
||||
const SPU_GPR_hdr temp = CPU.GPR[ra];
|
||||
const u128 temp = CPU.GPR[ra];
|
||||
CPU.GPR[rt]._u32[0] = (temp._u32[0] << s) | (temp._u32[3] >> (32 - s));
|
||||
CPU.GPR[rt]._u32[1] = (temp._u32[1] << s) | (temp._u32[0] >> (32 - s));
|
||||
CPU.GPR[rt]._u32[2] = (temp._u32[2] << s) | (temp._u32[1] >> (32 - s));
|
||||
|
|
@ -623,7 +623,7 @@ private:
|
|||
const int s = (0 - i7) & 0x7;
|
||||
if (s) // not an optimization, it fixes shifts
|
||||
{
|
||||
const SPU_GPR_hdr temp = CPU.GPR[ra];
|
||||
const u128 temp = CPU.GPR[ra];
|
||||
CPU.GPR[rt]._u32[0] = (temp._u32[0] >> s) | (temp._u32[1] << (32 - s));
|
||||
CPU.GPR[rt]._u32[1] = (temp._u32[1] >> s) | (temp._u32[2] << (32 - s));
|
||||
CPU.GPR[rt]._u32[2] = (temp._u32[2] >> s) | (temp._u32[3] << (32 - s));
|
||||
|
|
@ -639,7 +639,7 @@ private:
|
|||
const int s = i7 & 0x7;
|
||||
if (s) // not an optimization, it fixes shifts
|
||||
{
|
||||
const SPU_GPR_hdr temp = CPU.GPR[ra];
|
||||
const u128 temp = CPU.GPR[ra];
|
||||
CPU.GPR[rt]._u32[0] = (temp._u32[0] << s);
|
||||
CPU.GPR[rt]._u32[1] = (temp._u32[1] << s) | (temp._u32[0] >> (32 - s));
|
||||
CPU.GPR[rt]._u32[2] = (temp._u32[2] << s) | (temp._u32[1] >> (32 - s));
|
||||
|
|
@ -653,23 +653,23 @@ private:
|
|||
void ROTQBYI(u32 rt, u32 ra, s32 i7)
|
||||
{
|
||||
const int s = i7 & 0xf;
|
||||
const SPU_GPR_hdr temp = CPU.GPR[ra];
|
||||
const u128 temp = CPU.GPR[ra];
|
||||
for (int b = 0; b < 16; b++)
|
||||
CPU.GPR[rt]._u8[b] = temp._u8[(b - s) & 0xf];
|
||||
}
|
||||
void ROTQMBYI(u32 rt, u32 ra, s32 i7)
|
||||
{
|
||||
const int s = (0 - i7) & 0x1f;
|
||||
const SPU_GPR_hdr temp = CPU.GPR[ra];
|
||||
CPU.GPR[rt].Reset();
|
||||
const u128 temp = CPU.GPR[ra];
|
||||
CPU.GPR[rt].clear();
|
||||
for (int b = 0; b < 16 - s; b++)
|
||||
CPU.GPR[rt]._u8[b] = temp._u8[b + s];
|
||||
}
|
||||
void SHLQBYI(u32 rt, u32 ra, s32 i7)
|
||||
{
|
||||
const int s = i7 & 0x1f;
|
||||
const SPU_GPR_hdr temp = CPU.GPR[ra];
|
||||
CPU.GPR[rt].Reset();
|
||||
const u128 temp = CPU.GPR[ra];
|
||||
CPU.GPR[rt].clear();
|
||||
for (int b = s; b < 16; b++)
|
||||
CPU.GPR[rt]._u8[b] = temp._u8[b - s];
|
||||
}
|
||||
|
|
@ -679,7 +679,7 @@ private:
|
|||
void CGT(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
for (int w = 0; w < 4; w++)
|
||||
CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._i32[w] > CPU.GPR[rb]._i32[w] ? 0xffffffff : 0;
|
||||
CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._s32[w] > CPU.GPR[rb]._s32[w] ? 0xffffffff : 0;
|
||||
}
|
||||
void XOR(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
|
|
@ -689,7 +689,7 @@ private:
|
|||
void CGTH(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
for (int h = 0; h < 8; h++)
|
||||
CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._i16[h] > CPU.GPR[rb]._i16[h] ? 0xffff : 0;
|
||||
CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._s16[h] > CPU.GPR[rb]._s16[h] ? 0xffff : 0;
|
||||
}
|
||||
void EQV(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
|
|
@ -699,12 +699,12 @@ private:
|
|||
void CGTB(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
for (int b = 0; b < 16; b++)
|
||||
CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._i8[b] > CPU.GPR[rb]._i8[b] ? 0xff : 0;
|
||||
CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._s8[b] > CPU.GPR[rb]._s8[b] ? 0xff : 0;
|
||||
}
|
||||
void SUMB(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
const SPU_GPR_hdr _a = CPU.GPR[ra];
|
||||
const SPU_GPR_hdr _b = CPU.GPR[rb];
|
||||
const u128 _a = CPU.GPR[ra];
|
||||
const u128 _b = CPU.GPR[rb];
|
||||
for (int w = 0; w < 4; w++)
|
||||
{
|
||||
CPU.GPR[rt]._u16[w*2] = _a._u8[w*4] + _a._u8[w*4 + 1] + _a._u8[w*4 + 2] + _a._u8[w*4 + 3];
|
||||
|
|
@ -714,7 +714,7 @@ private:
|
|||
//HGT uses signed values. HLGT uses unsigned values
|
||||
void HGT(u32 rt, s32 ra, s32 rb)
|
||||
{
|
||||
if (CPU.GPR[ra]._i32[3] > CPU.GPR[rb]._i32[3])
|
||||
if (CPU.GPR[ra]._s32[3] > CPU.GPR[rb]._s32[3])
|
||||
{
|
||||
CPU.SPU.Status.SetValue(SPU_STATUS_STOPPED_BY_HALT);
|
||||
CPU.Stop();
|
||||
|
|
@ -735,18 +735,18 @@ private:
|
|||
}
|
||||
void XSWD(u32 rt, u32 ra)
|
||||
{
|
||||
CPU.GPR[rt]._i64[0] = (s64)CPU.GPR[ra]._i32[0];
|
||||
CPU.GPR[rt]._i64[1] = (s64)CPU.GPR[ra]._i32[2];
|
||||
CPU.GPR[rt]._s64[0] = (s64)CPU.GPR[ra]._s32[0];
|
||||
CPU.GPR[rt]._s64[1] = (s64)CPU.GPR[ra]._s32[2];
|
||||
}
|
||||
void XSHW(u32 rt, u32 ra)
|
||||
{
|
||||
for (int w = 0; w < 4; w++)
|
||||
CPU.GPR[rt]._i32[w] = (s32)CPU.GPR[ra]._i16[w*2];
|
||||
CPU.GPR[rt]._s32[w] = (s32)CPU.GPR[ra]._s16[w*2];
|
||||
}
|
||||
void CNTB(u32 rt, u32 ra)
|
||||
{
|
||||
const SPU_GPR_hdr temp = CPU.GPR[ra];
|
||||
CPU.GPR[rt].Reset();
|
||||
const u128 temp = CPU.GPR[ra];
|
||||
CPU.GPR[rt].clear();
|
||||
for (int b = 0; b < 16; b++)
|
||||
for (int i = 0; i < 8; i++)
|
||||
CPU.GPR[rt]._u8[b] += (temp._u8[b] & (1 << i)) ? 1 : 0;
|
||||
|
|
@ -754,7 +754,7 @@ private:
|
|||
void XSBH(u32 rt, u32 ra)
|
||||
{
|
||||
for (int h = 0; h < 8; h++)
|
||||
CPU.GPR[rt]._i16[h] = (s16)CPU.GPR[ra]._i8[h*2];
|
||||
CPU.GPR[rt]._s16[h] = (s16)CPU.GPR[ra]._s8[h*2];
|
||||
}
|
||||
void CLGT(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
|
|
@ -875,7 +875,7 @@ private:
|
|||
void CEQ(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
for (int w = 0; w < 4; w++)
|
||||
CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._i32[w] == CPU.GPR[rb]._i32[w] ? 0xffffffff : 0;
|
||||
CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._s32[w] == CPU.GPR[rb]._s32[w] ? 0xffffffff : 0;
|
||||
}
|
||||
void MPYHHU(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
|
|
@ -912,7 +912,7 @@ private:
|
|||
void MPYHHA(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
for (int w = 0; w < 4; w++)
|
||||
CPU.GPR[rt]._i32[w] += CPU.GPR[ra]._i16[w*2+1] * CPU.GPR[rb]._i16[w*2+1];
|
||||
CPU.GPR[rt]._s32[w] += CPU.GPR[ra]._s16[w*2+1] * CPU.GPR[rb]._s16[w*2+1];
|
||||
}
|
||||
void MPYHHAU(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
|
|
@ -924,7 +924,7 @@ private:
|
|||
void FSCRRD(u32 rt)
|
||||
{
|
||||
// TODO (rarely used)
|
||||
CPU.GPR[rt].Reset();
|
||||
CPU.GPR[rt].clear();
|
||||
}
|
||||
void FESD(u32 rt, u32 ra)
|
||||
{
|
||||
|
|
@ -941,9 +941,9 @@ private:
|
|||
void FSCRWR(u32 rt, u32 ra)
|
||||
{
|
||||
// TODO (rarely used)
|
||||
if (CPU.GPR[ra]._u128)
|
||||
if (CPU.GPR[ra]._u64[0] || CPU.GPR[ra]._u64[1])
|
||||
{
|
||||
LOG_ERROR(SPU, "FSCRWR(%d,%d): value = %s", rt, ra, CPU.GPR[ra].ToString().c_str());
|
||||
LOG_ERROR(SPU, "FSCRWR(%d,%d): value = %s", rt, ra, CPU.GPR[ra].to_hex().c_str());
|
||||
UNIMPLEMENTED();
|
||||
}
|
||||
}
|
||||
|
|
@ -965,22 +965,22 @@ private:
|
|||
void MPY(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
for (int w = 0; w < 4; w++)
|
||||
CPU.GPR[rt]._i32[w] = CPU.GPR[ra]._i16[w*2] * CPU.GPR[rb]._i16[w*2];
|
||||
CPU.GPR[rt]._s32[w] = CPU.GPR[ra]._s16[w*2] * CPU.GPR[rb]._s16[w*2];
|
||||
}
|
||||
void MPYH(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
for (int w = 0; w < 4; w++)
|
||||
CPU.GPR[rt]._i32[w] = (CPU.GPR[ra]._i16[w*2+1] * CPU.GPR[rb]._i16[w*2]) << 16;
|
||||
CPU.GPR[rt]._s32[w] = (CPU.GPR[ra]._s16[w*2+1] * CPU.GPR[rb]._s16[w*2]) << 16;
|
||||
}
|
||||
void MPYHH(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
for (int w = 0; w < 4; w++)
|
||||
CPU.GPR[rt]._i32[w] = CPU.GPR[ra]._i16[w*2+1] * CPU.GPR[rb]._i16[w*2+1];
|
||||
CPU.GPR[rt]._s32[w] = CPU.GPR[ra]._s16[w*2+1] * CPU.GPR[rb]._s16[w*2+1];
|
||||
}
|
||||
void MPYS(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
for (int w = 0; w < 4; w++)
|
||||
CPU.GPR[rt]._i32[w] = (CPU.GPR[ra]._i16[w*2] * CPU.GPR[rb]._i16[w*2]) >> 16;
|
||||
CPU.GPR[rt]._s32[w] = (CPU.GPR[ra]._s16[w*2] * CPU.GPR[rb]._s16[w*2]) >> 16;
|
||||
}
|
||||
void CEQH(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
|
|
@ -1016,7 +1016,7 @@ private:
|
|||
}
|
||||
void HEQ(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
if (CPU.GPR[ra]._i32[3] == CPU.GPR[rb]._i32[3])
|
||||
if (CPU.GPR[ra]._s32[3] == CPU.GPR[rb]._s32[3])
|
||||
{
|
||||
CPU.SPU.Status.SetValue(SPU_STATUS_STOPPED_BY_HALT);
|
||||
CPU.Stop();
|
||||
|
|
@ -1041,7 +1041,7 @@ private:
|
|||
else if (CPU.GPR[rt]._f[i] < -pow(2, 31))
|
||||
CPU.GPR[rt]._u32[i] = 0x80000000;
|
||||
else
|
||||
CPU.GPR[rt]._i32[i] = (s32)CPU.GPR[rt]._f[i]; //trunc
|
||||
CPU.GPR[rt]._s32[i] = (s32)CPU.GPR[rt]._f[i]; //trunc
|
||||
}
|
||||
}
|
||||
void CFLTU(u32 rt, u32 ra, s32 i8)
|
||||
|
|
@ -1072,7 +1072,7 @@ private:
|
|||
const u32 scale = 155 - (i8 & 0xff); //unsigned immediate
|
||||
for (int i = 0; i < 4; i++)
|
||||
{
|
||||
CPU.GPR[rt]._f[i] = (float)CPU.GPR[ra]._i32[i];
|
||||
CPU.GPR[rt]._f[i] = (float)CPU.GPR[ra]._s32[i];
|
||||
|
||||
u32 exp = ((CPU.GPR[rt]._u32[i] >> 23) & 0xff) - scale;
|
||||
|
||||
|
|
@ -1115,7 +1115,7 @@ private:
|
|||
{
|
||||
u32 lsa = (i16 << 2) & 0x3fff0;
|
||||
|
||||
CPU.WriteLS128(lsa, CPU.GPR[rt]._u128);
|
||||
CPU.WriteLS128(lsa, CPU.GPR[rt]);
|
||||
}
|
||||
void BRNZ(u32 rt, s32 i16)
|
||||
{
|
||||
|
|
@ -1160,7 +1160,7 @@ private:
|
|||
{
|
||||
u32 lsa = branchTarget(CPU.PC, i16) & 0x3fff0;
|
||||
|
||||
CPU.WriteLS128(lsa, CPU.GPR[rt]._u128);
|
||||
CPU.WriteLS128(lsa, CPU.GPR[rt]);
|
||||
}
|
||||
void BRA(s32 i16)
|
||||
{
|
||||
|
|
@ -1172,12 +1172,12 @@ private:
|
|||
{
|
||||
u32 lsa = (i16 << 2) & 0x3fff0;
|
||||
|
||||
CPU.GPR[rt]._u128 = CPU.ReadLS128(lsa);
|
||||
CPU.GPR[rt] = CPU.ReadLS128(lsa);
|
||||
}
|
||||
void BRASL(u32 rt, s32 i16)
|
||||
{
|
||||
u64 target = branchTarget(0, i16);
|
||||
CPU.GPR[rt].Reset();
|
||||
CPU.GPR[rt].clear();
|
||||
CPU.GPR[rt]._u32[3] = (u32)CPU.PC + 4;
|
||||
LOG5_OPCODE("branch (0x%llx)", target);
|
||||
CPU.SetBranch(target);
|
||||
|
|
@ -1207,7 +1207,7 @@ private:
|
|||
void BRSL(u32 rt, s32 i16)
|
||||
{
|
||||
u64 target = branchTarget(CPU.PC, i16);
|
||||
CPU.GPR[rt].Reset();
|
||||
CPU.GPR[rt].clear();
|
||||
CPU.GPR[rt]._u32[3] = (u32)CPU.PC + 4;
|
||||
LOG5_OPCODE("branch (0x%llx)", target);
|
||||
CPU.SetBranch(target);
|
||||
|
|
@ -1216,29 +1216,29 @@ private:
|
|||
{
|
||||
u32 lsa = branchTarget(CPU.PC, i16) & 0x3fff0;
|
||||
|
||||
CPU.GPR[rt]._u128 = CPU.ReadLS128(lsa);
|
||||
CPU.GPR[rt] = CPU.ReadLS128(lsa);
|
||||
}
|
||||
void IL(u32 rt, s32 i16)
|
||||
{
|
||||
CPU.GPR[rt]._i32[0] =
|
||||
CPU.GPR[rt]._i32[1] =
|
||||
CPU.GPR[rt]._i32[2] =
|
||||
CPU.GPR[rt]._i32[3] = i16;
|
||||
CPU.GPR[rt]._s32[0] =
|
||||
CPU.GPR[rt]._s32[1] =
|
||||
CPU.GPR[rt]._s32[2] =
|
||||
CPU.GPR[rt]._s32[3] = i16;
|
||||
}
|
||||
void ILHU(u32 rt, s32 i16)
|
||||
{
|
||||
for (int w = 0; w < 4; w++)
|
||||
CPU.GPR[rt]._i32[w] = i16 << 16;
|
||||
CPU.GPR[rt]._s32[w] = i16 << 16;
|
||||
}
|
||||
void ILH(u32 rt, s32 i16)
|
||||
{
|
||||
for (int h = 0; h < 8; h++)
|
||||
CPU.GPR[rt]._i16[h] = i16;
|
||||
CPU.GPR[rt]._s16[h] = i16;
|
||||
}
|
||||
void IOHL(u32 rt, s32 i16)
|
||||
{
|
||||
for (int w = 0; w < 4; w++)
|
||||
CPU.GPR[rt]._i32[w] |= (i16 & 0xFFFF);
|
||||
CPU.GPR[rt]._s32[w] |= (i16 & 0xFFFF);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1246,101 +1246,101 @@ private:
|
|||
void ORI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
for(u32 i = 0; i < 4; ++i)
|
||||
CPU.GPR[rt]._i32[i] = CPU.GPR[ra]._i32[i] | i10;
|
||||
CPU.GPR[rt]._s32[i] = CPU.GPR[ra]._s32[i] | i10;
|
||||
}
|
||||
void ORHI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
for (int h = 0; h < 8; h++)
|
||||
CPU.GPR[rt]._i16[h] = CPU.GPR[ra]._i16[h] | i10;
|
||||
CPU.GPR[rt]._s16[h] = CPU.GPR[ra]._s16[h] | i10;
|
||||
}
|
||||
void ORBI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
for (int b = 0; b < 16; b++)
|
||||
CPU.GPR[rt]._i8[b] = CPU.GPR[ra]._i8[b] | i10;
|
||||
CPU.GPR[rt]._s8[b] = CPU.GPR[ra]._s8[b] | i10;
|
||||
}
|
||||
void SFI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
for (int w = 0; w < 4; w++)
|
||||
CPU.GPR[rt]._i32[w] = i10 - CPU.GPR[ra]._i32[w];
|
||||
CPU.GPR[rt]._s32[w] = i10 - CPU.GPR[ra]._s32[w];
|
||||
}
|
||||
void SFHI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
for (int h = 0; h < 8; h++)
|
||||
CPU.GPR[rt]._i16[h] = i10 - CPU.GPR[ra]._i16[h];
|
||||
CPU.GPR[rt]._s16[h] = i10 - CPU.GPR[ra]._s16[h];
|
||||
}
|
||||
void ANDI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
for (int w = 0; w < 4; w++)
|
||||
CPU.GPR[rt]._i32[w] = CPU.GPR[ra]._i32[w] & i10;
|
||||
CPU.GPR[rt]._s32[w] = CPU.GPR[ra]._s32[w] & i10;
|
||||
}
|
||||
void ANDHI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
for (int h = 0; h < 8; h++)
|
||||
CPU.GPR[rt]._i16[h] = CPU.GPR[ra]._i16[h] & i10;
|
||||
CPU.GPR[rt]._s16[h] = CPU.GPR[ra]._s16[h] & i10;
|
||||
}
|
||||
void ANDBI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
for (int b = 0; b < 16; b++)
|
||||
CPU.GPR[rt]._i8[b] = CPU.GPR[ra]._i8[b] & i10;
|
||||
CPU.GPR[rt]._s8[b] = CPU.GPR[ra]._s8[b] & i10;
|
||||
}
|
||||
void AI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
CPU.GPR[rt]._i32[0] = CPU.GPR[ra]._i32[0] + i10;
|
||||
CPU.GPR[rt]._i32[1] = CPU.GPR[ra]._i32[1] + i10;
|
||||
CPU.GPR[rt]._i32[2] = CPU.GPR[ra]._i32[2] + i10;
|
||||
CPU.GPR[rt]._i32[3] = CPU.GPR[ra]._i32[3] + i10;
|
||||
CPU.GPR[rt]._s32[0] = CPU.GPR[ra]._s32[0] + i10;
|
||||
CPU.GPR[rt]._s32[1] = CPU.GPR[ra]._s32[1] + i10;
|
||||
CPU.GPR[rt]._s32[2] = CPU.GPR[ra]._s32[2] + i10;
|
||||
CPU.GPR[rt]._s32[3] = CPU.GPR[ra]._s32[3] + i10;
|
||||
}
|
||||
void AHI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
for(u32 h = 0; h < 8; ++h)
|
||||
CPU.GPR[rt]._i16[h] = CPU.GPR[ra]._i16[h] + i10;
|
||||
CPU.GPR[rt]._s16[h] = CPU.GPR[ra]._s16[h] + i10;
|
||||
}
|
||||
void STQD(u32 rt, s32 i10, u32 ra) //i10 is shifted left by 4 while decoding
|
||||
{
|
||||
const u32 lsa = (CPU.GPR[ra]._i32[3] + i10) & 0x3fff0;
|
||||
const u32 lsa = (CPU.GPR[ra]._s32[3] + i10) & 0x3fff0;
|
||||
|
||||
//LOG_NOTICE(Log::SPU, "STQD(lsa=0x%x): GPR[%d] (0x%llx%llx)", lsa, rt, CPU.GPR[rt]._u64[1], CPU.GPR[rt]._u64[0]);
|
||||
CPU.WriteLS128(lsa, CPU.GPR[rt]._u128);
|
||||
CPU.WriteLS128(lsa, CPU.GPR[rt]);
|
||||
}
|
||||
void LQD(u32 rt, s32 i10, u32 ra) //i10 is shifted left by 4 while decoding
|
||||
{
|
||||
const u32 lsa = (CPU.GPR[ra]._i32[3] + i10) & 0x3fff0;
|
||||
const u32 lsa = (CPU.GPR[ra]._s32[3] + i10) & 0x3fff0;
|
||||
|
||||
CPU.GPR[rt]._u128 = CPU.ReadLS128(lsa);
|
||||
CPU.GPR[rt] = CPU.ReadLS128(lsa);
|
||||
}
|
||||
void XORI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
for (int w = 0; w < 4; w++)
|
||||
CPU.GPR[rt]._i32[w] = CPU.GPR[ra]._i32[w] ^ i10;
|
||||
CPU.GPR[rt]._s32[w] = CPU.GPR[ra]._s32[w] ^ i10;
|
||||
}
|
||||
void XORHI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
for (int h = 0; h < 8; h++)
|
||||
CPU.GPR[rt]._i16[h] = CPU.GPR[ra]._i16[h] ^ i10;
|
||||
CPU.GPR[rt]._s16[h] = CPU.GPR[ra]._s16[h] ^ i10;
|
||||
}
|
||||
void XORBI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
for (int b = 0; b < 16; b++)
|
||||
CPU.GPR[rt]._i8[b] = CPU.GPR[ra]._i8[b] ^ i10;
|
||||
CPU.GPR[rt]._s8[b] = CPU.GPR[ra]._s8[b] ^ i10;
|
||||
}
|
||||
void CGTI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
for (int w = 0; w < 4; w++)
|
||||
CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._i32[w] > i10 ? 0xffffffff : 0;
|
||||
CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._s32[w] > i10 ? 0xffffffff : 0;
|
||||
}
|
||||
void CGTHI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
for (int h = 0; h < 8; h++)
|
||||
CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._i16[h] > i10 ? 0xffff : 0;
|
||||
CPU.GPR[rt]._u16[h] = CPU.GPR[ra]._s16[h] > i10 ? 0xffff : 0;
|
||||
}
|
||||
void CGTBI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
for (int b = 0; b < 16; b++)
|
||||
CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._i8[b] > (s8)(i10 & 0xff) ? 0xff : 0;
|
||||
CPU.GPR[rt]._u8[b] = CPU.GPR[ra]._s8[b] > (s8)(i10 & 0xff) ? 0xff : 0;
|
||||
}
|
||||
void HGTI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
if (CPU.GPR[ra]._i32[3] > i10)
|
||||
if (CPU.GPR[ra]._s32[3] > i10)
|
||||
{
|
||||
CPU.SPU.Status.SetValue(SPU_STATUS_STOPPED_BY_HALT);
|
||||
CPU.Stop();
|
||||
|
|
@ -1376,7 +1376,7 @@ private:
|
|||
void MPYI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
for (int w = 0; w < 4; w++)
|
||||
CPU.GPR[rt]._i32[w] = CPU.GPR[ra]._i16[w*2] * i10;
|
||||
CPU.GPR[rt]._s32[w] = CPU.GPR[ra]._s16[w*2] * i10;
|
||||
}
|
||||
void MPYUI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
|
|
@ -1386,21 +1386,21 @@ private:
|
|||
void CEQI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
for(u32 i = 0; i < 4; ++i)
|
||||
CPU.GPR[rt]._u32[i] = (CPU.GPR[ra]._i32[i] == i10) ? 0xffffffff : 0x00000000;
|
||||
CPU.GPR[rt]._u32[i] = (CPU.GPR[ra]._s32[i] == i10) ? 0xffffffff : 0x00000000;
|
||||
}
|
||||
void CEQHI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
for (int h = 0; h < 8; h++)
|
||||
CPU.GPR[rt]._u16[h] = (CPU.GPR[ra]._i16[h] == (s16)i10) ? 0xffff : 0;
|
||||
CPU.GPR[rt]._u16[h] = (CPU.GPR[ra]._s16[h] == (s16)i10) ? 0xffff : 0;
|
||||
}
|
||||
void CEQBI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
for (int b = 0; b < 16; b++)
|
||||
CPU.GPR[rt]._i8[b] = (CPU.GPR[ra]._i8[b] == (s8)(i10 & 0xff)) ? 0xff : 0;
|
||||
CPU.GPR[rt]._s8[b] = (CPU.GPR[ra]._s8[b] == (s8)(i10 & 0xff)) ? 0xff : 0;
|
||||
}
|
||||
void HEQI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
if (CPU.GPR[ra]._i32[3] == i10)
|
||||
if (CPU.GPR[ra]._s32[3] == i10)
|
||||
{
|
||||
CPU.SPU.Status.SetValue(SPU_STATUS_STOPPED_BY_HALT);
|
||||
CPU.Stop();
|
||||
|
|
@ -1435,8 +1435,8 @@ private:
|
|||
}
|
||||
void SHUFB(u32 rt, u32 ra, u32 rb, u32 rc)
|
||||
{
|
||||
const SPU_GPR_hdr _a = CPU.GPR[ra];
|
||||
const SPU_GPR_hdr _b = CPU.GPR[rb];
|
||||
const u128 _a = CPU.GPR[ra];
|
||||
const u128 _b = CPU.GPR[rb];
|
||||
for (int i = 0; i < 16; i++)
|
||||
{
|
||||
u8 b = CPU.GPR[rc]._u8[i];
|
||||
|
|
@ -1464,7 +1464,7 @@ private:
|
|||
void MPYA(u32 rt, u32 ra, u32 rb, u32 rc)
|
||||
{
|
||||
for (int w = 0; w < 4; w++)
|
||||
CPU.GPR[rt]._i32[w] = CPU.GPR[ra]._i16[w*2] * CPU.GPR[rb]._i16[w*2] + CPU.GPR[rc]._i32[w];
|
||||
CPU.GPR[rt]._s32[w] = CPU.GPR[ra]._s16[w*2] * CPU.GPR[rb]._s16[w*2] + CPU.GPR[rc]._s32[w];
|
||||
}
|
||||
void FNMS(u32 rt, u32 ra, u32 rb, u32 rc)
|
||||
{
|
||||
|
|
@ -1500,6 +1500,6 @@ private:
|
|||
{
|
||||
LOG_ERROR(Log::SPU, err + fmt::Format(" #pc: 0x%x", CPU.PC));
|
||||
Emu.Pause();
|
||||
for(uint i=0; i<128; ++i) LOG_NOTICE(Log::SPU, "r%d = 0x%s", i, CPU.GPR[i].ToString().c_str());
|
||||
for(uint i=0; i<128; ++i) LOG_NOTICE(Log::SPU, "r%d = 0x%s", i, CPU.GPR[i].to_hex().c_str());
|
||||
}
|
||||
};
|
||||
|
|
|
|||
|
|
@ -483,7 +483,7 @@ private:
|
|||
{
|
||||
c.mov(cpu_qword(PC), (u32)CPU.PC);
|
||||
WRAPPER_BEGIN(rt, ra, yy, zz);
|
||||
CPU.GPR[rt].Reset();
|
||||
CPU.GPR[rt].clear();
|
||||
CPU.GPR[rt]._u32[3] = CPU.GetChannelCount(ra);
|
||||
WRAPPER_END(rt, ra, 0, 0);
|
||||
// TODO
|
||||
|
|
@ -1945,8 +1945,8 @@ private:
|
|||
//HGT uses signed values. HLGT uses unsigned values
|
||||
void HGT(u32 rt, s32 ra, s32 rb)
|
||||
{
|
||||
c.mov(*addr, cpu_dword(GPR[ra]._i32[3]));
|
||||
c.cmp(*addr, cpu_dword(GPR[rb]._i32[3]));
|
||||
c.mov(*addr, cpu_dword(GPR[ra]._s32[3]));
|
||||
c.cmp(*addr, cpu_dword(GPR[rb]._s32[3]));
|
||||
c.mov(*addr, 0);
|
||||
c.setg(addr->r8());
|
||||
c.neg(*addr);
|
||||
|
|
@ -1970,10 +1970,10 @@ private:
|
|||
}
|
||||
void XSWD(u32 rt, u32 ra)
|
||||
{
|
||||
c.movsxd(*qw0, cpu_dword(GPR[ra]._i32[0]));
|
||||
c.movsxd(*qw1, cpu_dword(GPR[ra]._i32[2]));
|
||||
c.mov(cpu_qword(GPR[rt]._i64[0]), *qw0);
|
||||
c.mov(cpu_qword(GPR[rt]._i64[1]), *qw1);
|
||||
c.movsxd(*qw0, cpu_dword(GPR[ra]._s32[0]));
|
||||
c.movsxd(*qw1, cpu_dword(GPR[ra]._s32[2]));
|
||||
c.mov(cpu_qword(GPR[rt]._s64[0]), *qw0);
|
||||
c.mov(cpu_qword(GPR[rt]._s64[1]), *qw1);
|
||||
XmmInvalidate(rt);
|
||||
LOG_OPCODE();
|
||||
}
|
||||
|
|
@ -2660,8 +2660,8 @@ private:
|
|||
}
|
||||
void HEQ(u32 rt, u32 ra, u32 rb)
|
||||
{
|
||||
c.mov(*addr, cpu_dword(GPR[ra]._i32[3]));
|
||||
c.cmp(*addr, cpu_dword(GPR[rb]._i32[3]));
|
||||
c.mov(*addr, cpu_dword(GPR[ra]._s32[3]));
|
||||
c.cmp(*addr, cpu_dword(GPR[rb]._s32[3]));
|
||||
c.mov(*addr, 0);
|
||||
c.sete(addr->r8());
|
||||
c.neg(*addr);
|
||||
|
|
@ -3322,7 +3322,7 @@ private:
|
|||
}
|
||||
void HGTI(u32 rt, u32 ra, s32 i10)
|
||||
{
|
||||
c.mov(*addr, cpu_dword(GPR[ra]._i32[3]));
|
||||
c.mov(*addr, cpu_dword(GPR[ra]._s32[3]));
|
||||
c.cmp(*addr, i10);
|
||||
c.mov(*addr, 0);
|
||||
c.setg(addr->r8());
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@ void SPUThread::DoReset()
|
|||
PPCThread::DoReset();
|
||||
|
||||
//reset regs
|
||||
memset(GPR, 0, sizeof(SPU_GPR_hdr) * 128);
|
||||
memset(GPR, 0, sizeof(u128) * 128);
|
||||
}
|
||||
|
||||
void SPUThread::InitRegs()
|
||||
|
|
@ -533,7 +533,7 @@ u32 SPUThread::GetChannelCount(u32 ch)
|
|||
}
|
||||
}
|
||||
|
||||
void SPUThread::WriteChannel(u32 ch, const SPU_GPR_hdr& r)
|
||||
void SPUThread::WriteChannel(u32 ch, const u128& r)
|
||||
{
|
||||
const u32 v = r._u32[3];
|
||||
|
||||
|
|
@ -861,9 +861,9 @@ void SPUThread::WriteChannel(u32 ch, const SPU_GPR_hdr& r)
|
|||
if (Emu.IsStopped()) LOG_WARNING(Log::SPU, "%s(%s) aborted", __FUNCTION__, spu_ch_name[ch]);
|
||||
}
|
||||
|
||||
void SPUThread::ReadChannel(SPU_GPR_hdr& r, u32 ch)
|
||||
void SPUThread::ReadChannel(u128& r, u32 ch)
|
||||
{
|
||||
r.Reset();
|
||||
r.clear();
|
||||
u32& v = r._u32[3];
|
||||
|
||||
switch (ch)
|
||||
|
|
|
|||
|
|
@ -191,36 +191,6 @@ public:
|
|||
|
||||
};
|
||||
|
||||
union SPU_GPR_hdr
|
||||
{
|
||||
u32 _u32[4];
|
||||
float _f[4];
|
||||
u128 _u128;
|
||||
__m128 _m128;
|
||||
__m128i _m128i;
|
||||
u64 _u64[2];
|
||||
s64 _i64[2];
|
||||
s32 _i32[4];
|
||||
u16 _u16[8];
|
||||
s16 _i16[8];
|
||||
u8 _u8[16];
|
||||
s8 _i8[16];
|
||||
double _d[2];
|
||||
|
||||
|
||||
SPU_GPR_hdr() {}
|
||||
|
||||
std::string ToString() const
|
||||
{
|
||||
return fmt::Format("%08x%08x%08x%08x", _u32[3], _u32[2], _u32[1], _u32[0]);
|
||||
}
|
||||
|
||||
void Reset()
|
||||
{
|
||||
memset(this, 0, sizeof(*this));
|
||||
}
|
||||
};
|
||||
|
||||
union SPU_SNRConfig_hdr
|
||||
{
|
||||
u64 value;
|
||||
|
|
@ -243,7 +213,7 @@ struct SpuGroupInfo;
|
|||
class SPUThread : public PPCThread
|
||||
{
|
||||
public:
|
||||
SPU_GPR_hdr GPR[128]; // General-Purpose Registers
|
||||
u128 GPR[128]; // General-Purpose Registers
|
||||
//FPSCR FPSCR;
|
||||
SPU_SNRConfig_hdr cfg; // Signal Notification Registers Configuration (OR-mode enabled: 0x1 for SNR1, 0x2 for SNR2)
|
||||
|
||||
|
|
@ -515,9 +485,9 @@ public:
|
|||
|
||||
u32 GetChannelCount(u32 ch);
|
||||
|
||||
void WriteChannel(u32 ch, const SPU_GPR_hdr& r);
|
||||
void WriteChannel(u32 ch, const u128& r);
|
||||
|
||||
void ReadChannel(SPU_GPR_hdr& r, u32 ch);
|
||||
void ReadChannel(u128& r, u32 ch);
|
||||
|
||||
void StopAndSignal(u32 code);
|
||||
|
||||
|
|
@ -541,7 +511,7 @@ public:
|
|||
{
|
||||
std::string ret = "Registers:\n=========\n";
|
||||
|
||||
for(uint i=0; i<128; ++i) ret += fmt::Format("GPR[%d] = 0x%s\n", i, GPR[i].ToString().c_str());
|
||||
for(uint i=0; i<128; ++i) ret += fmt::Format("GPR[%d] = 0x%s\n", i, GPR[i].to_hex().c_str());
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
102
rpcs3/stdafx.h
102
rpcs3/stdafx.h
|
|
@ -47,108 +47,6 @@ typedef int16_t s16;
|
|||
typedef int32_t s32;
|
||||
typedef int64_t s64;
|
||||
|
||||
union u128
|
||||
{
|
||||
struct
|
||||
{
|
||||
u64 hi;
|
||||
u64 lo;
|
||||
};
|
||||
|
||||
u64 _u64[2];
|
||||
u32 _u32[4];
|
||||
u16 _u16[8];
|
||||
u8 _u8[16];
|
||||
|
||||
operator u64() const { return _u64[0]; }
|
||||
operator u32() const { return _u32[0]; }
|
||||
operator u16() const { return _u16[0]; }
|
||||
operator u8() const { return _u8[0]; }
|
||||
|
||||
operator bool() const { return _u64[0] != 0 || _u64[1] != 0; }
|
||||
|
||||
static u128 From128(u64 hi, u64 lo)
|
||||
{
|
||||
u128 ret = { hi, lo };
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u128 From64(u64 src)
|
||||
{
|
||||
u128 ret = { 0, src };
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u128 From32(u32 src)
|
||||
{
|
||||
u128 ret;
|
||||
ret._u32[0] = src;
|
||||
ret._u32[1] = 0;
|
||||
ret._u32[2] = 0;
|
||||
ret._u32[3] = 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u128 FromBit(u32 bit)
|
||||
{
|
||||
u128 ret;
|
||||
if (bit < 64)
|
||||
{
|
||||
ret.hi = 0;
|
||||
ret.lo = (u64)1 << bit;
|
||||
}
|
||||
else if (bit < 128)
|
||||
{
|
||||
ret.hi = (u64)1 << (bit - 64);
|
||||
ret.lo = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
ret.hi = 0;
|
||||
ret.lo = 0;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool operator == (const u128& right) const
|
||||
{
|
||||
return (lo == right.lo) && (hi == right.hi);
|
||||
}
|
||||
|
||||
bool operator != (const u128& right) const
|
||||
{
|
||||
return (lo != right.lo) || (hi != right.hi);
|
||||
}
|
||||
|
||||
u128 operator | (const u128& right) const
|
||||
{
|
||||
return From128(hi | right.hi, lo | right.lo);
|
||||
}
|
||||
|
||||
u128 operator & (const u128& right) const
|
||||
{
|
||||
return From128(hi & right.hi, lo & right.lo);
|
||||
}
|
||||
|
||||
u128 operator ^ (const u128& right) const
|
||||
{
|
||||
return From128(hi ^ right.hi, lo ^ right.lo);
|
||||
}
|
||||
|
||||
u128 operator ~ () const
|
||||
{
|
||||
return From128(~hi, ~lo);
|
||||
}
|
||||
|
||||
static __forceinline u128 byteswap(const u128 val)
|
||||
{
|
||||
u128 ret;
|
||||
ret.lo = _byteswap_uint64(val.hi);
|
||||
ret.hi = _byteswap_uint64(val.lo);
|
||||
return ret;
|
||||
}
|
||||
};
|
||||
|
||||
#define AlignAddr(addr, align) (((addr) + ((align) - 1)) & ~((align) - 1))
|
||||
|
||||
#include "Utilities/StrFmt.h"
|
||||
|
|
|
|||
Loading…
Reference in New Issue