mirror of https://github.com/RPCS3/rpcs3.git
parent
39dadad534
commit
712c04b2ad
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@ -321,7 +321,7 @@ std::vector<ppu_function> ppu_analyse(const std::vector<std::pair<u32, u32>>& se
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if (func.addr)
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if (func.addr)
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{
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{
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// Update TOC (TODO: this doesn't work well)
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// Update TOC (TODO: this doesn't work well, must update TOC recursively)
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if (func.toc == 0 || toc == -1)
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if (func.toc == 0 || toc == -1)
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{
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{
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func.toc = toc;
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func.toc = toc;
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@ -592,6 +592,8 @@ std::vector<ppu_function> ppu_analyse(const std::vector<std::pair<u32, u32>>& se
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func.size = 0x4;
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func.size = 0x4;
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func.blocks.emplace(func.addr, func.size);
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func.blocks.emplace(func.addr, func.size);
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func.attr += new_func.attr & ppu_attr::no_return;
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func.attr += new_func.attr & ppu_attr::no_return;
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func.called_from.emplace(target);
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func.gate_target = target;
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continue;
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continue;
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}
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}
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}
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}
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@ -620,7 +622,9 @@ std::vector<ppu_function> ppu_analyse(const std::vector<std::pair<u32, u32>>& se
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func.size = 0x10;
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func.size = 0x10;
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func.blocks.emplace(func.addr, func.size);
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func.blocks.emplace(func.addr, func.size);
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func.attr += new_func.attr & ppu_attr::no_return;
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func.attr += new_func.attr & ppu_attr::no_return;
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func.called_from.emplace(target);
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func.gate_target = target;
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continue;
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continue;
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}
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}
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}
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}
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@ -909,6 +913,7 @@ std::vector<ppu_function> ppu_analyse(const std::vector<std::pair<u32, u32>>& se
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{
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{
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if (target < func.addr || target >= func.addr + func.size)
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if (target < func.addr || target >= func.addr + func.size)
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{
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{
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func.called_from.emplace(target);
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add_func(target, func.toc, func.addr);
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add_func(target, func.toc, func.addr);
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}
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}
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}
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}
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@ -1,6 +1,7 @@
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#pragma once
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#pragma once
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#include <map>
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#include <map>
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#include <set>
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#include "Utilities/BitSet.h"
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#include "Utilities/BitSet.h"
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#include "Utilities/BEType.h"
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#include "Utilities/BEType.h"
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@ -14,17 +15,22 @@ enum class ppu_attr : u32
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no_size,
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no_size,
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uses_r0,
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uses_r0,
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entry_point,
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entry_point,
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complex_stack,
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};
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};
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// PPU Function Information
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// PPU Function Information
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struct ppu_function
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struct ppu_function
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{
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{
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u32 addr{};
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u32 addr = 0;
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u32 toc{};
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u32 toc = 0;
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u32 size{};
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u32 size = 0;
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bitset_t<ppu_attr> attr{};
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bitset_t<ppu_attr> attr{};
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u32 stack_frame = 0;
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u32 gate_target = 0;
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std::map<u32, u32> blocks; // Basic blocks: addr -> size
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std::map<u32, u32> blocks; // Basic blocks: addr -> size
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std::set<u32> called_from; // Set of called functions
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};
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};
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// Aux
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// Aux
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@ -448,6 +454,423 @@ struct ppu_itype
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}
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}
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};
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};
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// PPU Instruction Flags
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struct ppu_iflag
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{
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// Various flags (TODO)
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enum : u32
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{
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write_rd = 1 << 0,
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write_ra = 1 << 1,
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read_ra = 1 << 2,
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read_rb = 1 << 3,
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read_rs = 1 << 4,
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write_vd = 1 << 5,
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read_va = 1 << 6,
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read_vb = 1 << 7,
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read_vc = 1 << 8,
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read_vs = 1 << 9,
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write_frd = 1 << 10,
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read_fra = 1 << 11,
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read_frb = 1 << 12,
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read_frc = 1 << 13,
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read_frs = 1 << 14,
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rw_all = 1 << 15,
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};
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enum flags : u32
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{
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UNK = 0,
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MFVSCR = 0,
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MTVSCR = 0,
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VADDCUW = 0,
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VADDFP = 0,
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VADDSBS = 0,
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VADDSHS = 0,
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VADDSWS = 0,
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VADDUBM = 0,
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VADDUBS = 0,
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VADDUHM = 0,
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VADDUHS = 0,
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VADDUWM = 0,
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VADDUWS = 0,
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VAND = 0,
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VANDC = 0,
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VAVGSB = 0,
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VAVGSH = 0,
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VAVGSW = 0,
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VAVGUB = 0,
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VAVGUH = 0,
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VAVGUW = 0,
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VCFSX = 0,
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VCFUX = 0,
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VCMPBFP = 0,
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VCMPEQFP = 0,
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VCMPEQUB = 0,
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VCMPEQUH = 0,
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VCMPEQUW = 0,
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VCMPGEFP = 0,
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VCMPGTFP = 0,
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VCMPGTSB = 0,
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VCMPGTSH = 0,
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VCMPGTSW = 0,
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VCMPGTUB = 0,
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VCMPGTUH = 0,
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VCMPGTUW = 0,
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VCTSXS = 0,
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VCTUXS = 0,
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VEXPTEFP = 0,
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VLOGEFP = 0,
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VMADDFP = 0,
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VMAXFP = 0,
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VMAXSB = 0,
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VMAXSH = 0,
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VMAXSW = 0,
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VMAXUB = 0,
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VMAXUH = 0,
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VMAXUW = 0,
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VMHADDSHS = 0,
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VMHRADDSHS = 0,
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VMINFP = 0,
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VMINSB = 0,
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VMINSH = 0,
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VMINSW = 0,
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VMINUB = 0,
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VMINUH = 0,
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VMINUW = 0,
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VMLADDUHM = 0,
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VMRGHB = 0,
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VMRGHH = 0,
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VMRGHW = 0,
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VMRGLB = 0,
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VMRGLH = 0,
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VMRGLW = 0,
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VMSUMMBM = 0,
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VMSUMSHM = 0,
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VMSUMSHS = 0,
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VMSUMUBM = 0,
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VMSUMUHM = 0,
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VMSUMUHS = 0,
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VMULESB = 0,
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VMULESH = 0,
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VMULEUB = 0,
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VMULEUH = 0,
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VMULOSB = 0,
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VMULOSH = 0,
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VMULOUB = 0,
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VMULOUH = 0,
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VNMSUBFP = 0,
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VNOR = 0,
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VOR = 0,
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VPERM = 0,
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VPKPX = 0,
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VPKSHSS = 0,
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VPKSHUS = 0,
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VPKSWSS = 0,
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VPKSWUS = 0,
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VPKUHUM = 0,
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VPKUHUS = 0,
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VPKUWUM = 0,
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VPKUWUS = 0,
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VREFP = 0,
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VRFIM = 0,
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VRFIN = 0,
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VRFIP = 0,
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VRFIZ = 0,
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VRLB = 0,
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VRLH = 0,
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VRLW = 0,
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VRSQRTEFP = 0,
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VSEL = 0,
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VSL = 0,
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VSLB = 0,
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VSLDOI = 0,
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VSLH = 0,
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VSLO = 0,
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VSLW = 0,
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VSPLTB = 0,
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VSPLTH = 0,
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VSPLTISB = 0,
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VSPLTISH = 0,
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VSPLTISW = 0,
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VSPLTW = 0,
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VSR = 0,
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VSRAB = 0,
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VSRAH = 0,
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VSRAW = 0,
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VSRB = 0,
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VSRH = 0,
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VSRO = 0,
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VSRW = 0,
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VSUBCUW = 0,
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VSUBFP = 0,
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VSUBSBS = 0,
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VSUBSHS = 0,
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VSUBSWS = 0,
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VSUBUBM = 0,
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VSUBUBS = 0,
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VSUBUHM = 0,
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VSUBUHS = 0,
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VSUBUWM = 0,
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VSUBUWS = 0,
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VSUMSWS = 0,
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VSUM2SWS = 0,
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VSUM4SBS = 0,
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VSUM4SHS = 0,
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VSUM4UBS = 0,
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VUPKHPX = 0,
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VUPKHSB = 0,
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VUPKHSH = 0,
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VUPKLPX = 0,
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VUPKLSB = 0,
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VUPKLSH = 0,
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VXOR = 0,
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TDI = read_ra,
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TWI = read_ra,
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MULLI = read_ra,
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SUBFIC = read_ra,
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CMPLI = read_ra,
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CMPI = read_ra,
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ADDIC = read_ra,
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ADDI = read_ra,
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ADDIS = read_ra,
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BC = 0,
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HACK = 0,
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SC = 0,
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B = 0,
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MCRF = 0,
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BCLR = 0,
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CRNOR = 0,
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CRANDC = 0,
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ISYNC = 0,
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CRXOR = 0,
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CRNAND = 0,
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CRAND = 0,
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CREQV = 0,
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CRORC = 0,
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CROR = 0,
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BCCTR = 0,
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RLWIMI = read_ra | read_rs,
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RLWINM = read_rs,
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RLWNM = read_rs | read_rb,
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ORI = read_rs,
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ORIS = read_rs,
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XORI = read_rs,
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XORIS = read_rs,
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ANDI = read_rs,
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ANDIS = read_rs,
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RLDICL = read_rs,
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RLDICR = read_rs,
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RLDIC = read_rs,
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RLDIMI = read_ra | read_rs,
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RLDCL = read_rs | read_rb,
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RLDCR = read_rs | read_rb,
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CMP = read_ra | read_rb,
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TW = read_ra | read_rb,
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LVSL = read_ra | read_rb,
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LVEBX = read_ra | read_rb,
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SUBFC = read_ra | read_rb,
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ADDC = read_ra | read_rb,
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MULHDU = read_ra | read_rb,
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MULHWU = read_ra | read_rb,
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MFOCRF = 0,
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LWARX = read_ra | read_rb,
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LDX = read_ra | read_rb,
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LWZX = read_ra | read_rb,
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SLW = read_rs | read_rb,
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CNTLZW = read_rs,
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SLD = read_rs | read_rb,
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AND = read_rs | read_rb,
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CMPL = read_ra | read_rb,
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LVSR = read_ra | read_rb,
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LVEHX = read_ra | read_rb,
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SUBF = read_ra | read_rb,
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LDUX = read_ra | read_rb,
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DCBST = 0,
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LWZUX = read_ra | read_rb,
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CNTLZD = read_rs,
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ANDC = read_rs | read_rb,
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TD = read_ra | read_rb,
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LVEWX = read_ra | read_rb,
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MULHD = read_ra | read_rb,
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MULHW = read_ra | read_rb,
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LDARX = read_ra | read_rb,
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DCBF = 0,
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LBZX = read_ra | read_rb,
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LVX = read_ra | read_rb,
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NEG = read_ra,
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LBZUX = read_ra | read_rb,
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NOR = read_rs | read_rb,
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STVEBX = read_ra | read_rb,
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SUBFE = read_ra | read_rb,
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ADDE = read_ra | read_rb,
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MTOCRF = read_rs,
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STDX = read_rs | read_ra | read_rb,
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STWCX = read_rs | read_ra | read_rb,
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STWX = read_rs | read_ra | read_rb,
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STVEHX = read_ra | read_rb,
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STDUX = read_rs | read_ra | read_rb,
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STWUX = read_rs | read_ra | read_rb,
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STVEWX = read_ra | read_rb,
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SUBFZE = read_ra,
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ADDZE = read_ra,
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STDCX = read_rs | read_ra | read_rb,
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STBX = read_rs | read_ra | read_rb,
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STVX = read_ra | read_rb,
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SUBFME = read_ra,
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MULLD = read_ra | read_rb,
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ADDME = read_ra | read_rb,
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MULLW = read_ra | read_rb,
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DCBTST = 0,
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STBUX = read_rs | read_ra | read_rb,
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ADD = read_ra | read_rb,
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DCBT = 0,
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LHZX = read_ra | read_rb,
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EQV = read_rs | read_rb,
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ECIWX = read_ra | read_rb,
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LHZUX = read_ra | read_rb,
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XOR = read_rs | read_rb,
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MFSPR = 0,
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LWAX = read_ra | read_rb,
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DST = 0,
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LHAX = read_ra | read_rb,
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LVXL = LVX,
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MFTB = MFSPR,
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LWAUX = read_ra | read_rb,
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DSTST = 0,
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LHAUX = read_ra | read_rb,
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STHX = read_rs | read_ra | read_rb,
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ORC = read_rs | read_rb,
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ECOWX = read_rs | read_ra | read_rb,
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STHUX = read_rs | read_ra | read_rb,
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OR = read_rs | read_rb,
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DIVDU = read_ra | read_rb,
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DIVWU = read_ra | read_rb,
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MTSPR = read_rs,
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DCBI = 0,
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NAND = read_rs | read_rb,
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STVXL = STVX,
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DIVD = read_ra | read_rb,
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DIVW = read_ra | read_rb,
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LVLX = read_ra | read_rb,
|
||||||
|
LDBRX = read_ra | read_rb,
|
||||||
|
LSWX = read_ra | read_rb | rw_all,
|
||||||
|
LWBRX = read_ra | read_rb,
|
||||||
|
LFSX = read_ra | read_rb,
|
||||||
|
SRW = read_rs | read_rb,
|
||||||
|
SRD = read_rs | read_rb,
|
||||||
|
LVRX = read_ra | read_rb,
|
||||||
|
LSWI = rw_all,
|
||||||
|
LFSUX = read_ra | read_rb,
|
||||||
|
SYNC = 0,
|
||||||
|
LFDX = read_ra | read_rb,
|
||||||
|
LFDUX = read_ra | read_rb,
|
||||||
|
STVLX = read_ra | read_rb,
|
||||||
|
STDBRX = read_rs | read_ra | read_rb,
|
||||||
|
STSWX = rw_all,
|
||||||
|
STWBRX = read_rs | read_ra | read_rb,
|
||||||
|
STFSX = read_ra | read_rb,
|
||||||
|
STVRX = read_ra | read_rb,
|
||||||
|
STFSUX = read_ra | read_rb,
|
||||||
|
STSWI = rw_all,
|
||||||
|
STFDX = read_ra | read_rb,
|
||||||
|
STFDUX = read_ra | read_rb,
|
||||||
|
LVLXL = LVLX,
|
||||||
|
LHBRX = read_ra | read_rb,
|
||||||
|
SRAW = read_rs | read_rb,
|
||||||
|
SRAD = read_rs | read_rb,
|
||||||
|
LVRXL = LVRX,
|
||||||
|
DSS = 0,
|
||||||
|
SRAWI = read_rs,
|
||||||
|
SRADI = read_rs,
|
||||||
|
EIEIO = 0,
|
||||||
|
STVLXL = STVLX,
|
||||||
|
STHBRX = read_rs | read_ra | read_rb,
|
||||||
|
EXTSH = read_rs,
|
||||||
|
STVRXL = STVRX,
|
||||||
|
EXTSB = read_rs,
|
||||||
|
STFIWX = read_ra | read_rb,
|
||||||
|
EXTSW = read_rs,
|
||||||
|
ICBI = 0,
|
||||||
|
DCBZ = read_ra | read_rb,
|
||||||
|
LWZ = read_ra,
|
||||||
|
LWZU = read_ra,
|
||||||
|
LBZ = read_ra,
|
||||||
|
LBZU = read_ra,
|
||||||
|
STW = read_rs | read_ra,
|
||||||
|
STWU = read_rs | read_ra,
|
||||||
|
STB = read_rs | read_ra,
|
||||||
|
STBU = read_rs | read_ra,
|
||||||
|
LHZ = read_ra,
|
||||||
|
LHZU = read_ra,
|
||||||
|
LHA = read_ra,
|
||||||
|
LHAU = read_ra,
|
||||||
|
STH = read_rs | read_ra,
|
||||||
|
STHU = read_rs | read_ra,
|
||||||
|
LMW = rw_all,
|
||||||
|
STMW = rw_all,
|
||||||
|
LFS = read_ra,
|
||||||
|
LFSU = read_ra,
|
||||||
|
LFD = read_ra,
|
||||||
|
LFDU = read_ra,
|
||||||
|
STFS = read_ra,
|
||||||
|
STFSU = read_ra,
|
||||||
|
STFD = read_ra,
|
||||||
|
STFDU = read_ra,
|
||||||
|
LD = read_ra,
|
||||||
|
LDU = read_ra,
|
||||||
|
LWA = read_ra,
|
||||||
|
STD = read_rs | read_ra,
|
||||||
|
STDU = read_rs | read_ra,
|
||||||
|
FDIVS = 0,
|
||||||
|
FSUBS = 0,
|
||||||
|
FADDS = 0,
|
||||||
|
FSQRTS = 0,
|
||||||
|
FRES = 0,
|
||||||
|
FMULS = 0,
|
||||||
|
FMADDS = 0,
|
||||||
|
FMSUBS = 0,
|
||||||
|
FNMSUBS = 0,
|
||||||
|
FNMADDS = 0,
|
||||||
|
MTFSB1 = 0,
|
||||||
|
MCRFS = 0,
|
||||||
|
MTFSB0 = 0,
|
||||||
|
MTFSFI = 0,
|
||||||
|
MFFS = 0,
|
||||||
|
MTFSF = 0,
|
||||||
|
FCMPU = 0,
|
||||||
|
FRSP = 0,
|
||||||
|
FCTIW = 0,
|
||||||
|
FCTIWZ = 0,
|
||||||
|
FDIV = 0,
|
||||||
|
FSUB = 0,
|
||||||
|
FADD = 0,
|
||||||
|
FSQRT = 0,
|
||||||
|
FSEL = 0,
|
||||||
|
FMUL = 0,
|
||||||
|
FRSQRTE = 0,
|
||||||
|
FMSUB = 0,
|
||||||
|
FMADD = 0,
|
||||||
|
FNMSUB = 0,
|
||||||
|
FNMADD = 0,
|
||||||
|
FCMPO = 0,
|
||||||
|
FNEG = 0,
|
||||||
|
FMR = 0,
|
||||||
|
FNABS = 0,
|
||||||
|
FABS = 0,
|
||||||
|
FCTID = 0,
|
||||||
|
FCTIDZ = 0,
|
||||||
|
FCFID = 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
// Enable address-of operator for ppu_decoder<>
|
||||||
|
friend constexpr flags operator &(flags value)
|
||||||
|
{
|
||||||
|
return value;
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
// Encode instruction name: 6 bits per character (0x20..0x5f), max 10
|
// Encode instruction name: 6 bits per character (0x20..0x5f), max 10
|
||||||
static constexpr u64 ppu_iname_encode(const char* ptr, u64 value = 0)
|
static constexpr u64 ppu_iname_encode(const char* ptr, u64 value = 0)
|
||||||
{
|
{
|
||||||
|
|
Loading…
Reference in New Issue