diff --git a/rpcs3/Emu/ARMv7/ARMv7Callback.h b/rpcs3/Emu/ARMv7/ARMv7Callback.h index a1ddd72593..4455284084 100644 --- a/rpcs3/Emu/ARMv7/ARMv7Callback.h +++ b/rpcs3/Emu/ARMv7/ARMv7Callback.h @@ -1,17 +1,17 @@ #pragma once -#include "Emu/Memory/Memory.h" -#include "Emu/ARMv7/PSVFuncList.h" + +#include "ARMv7Function.h" namespace vm { template - force_inline RT _ptr_base::operator()(ARMv7Thread& context, T... args) const + force_inline RT _ptr_base::operator()(ARMv7Thread& cpu, T... args) const { - return psv_func_detail::func_caller::call(context, VM_CAST(this->addr()), args...); + return arm_func_detail::func_caller::call(cpu, vm::cast(this->addr(), HERE), args...); } } -template inline RT cb_call(ARMv7Thread& context, u32 addr, T... args) +template inline RT cb_call(ARMv7Thread& cpu, u32 addr, T... args) { - return psv_func_detail::func_caller::call(context, addr, args...); + return arm_func_detail::func_caller::call(cpu, addr, args...); } diff --git a/rpcs3/Emu/ARMv7/ARMv7Context.h b/rpcs3/Emu/ARMv7/ARMv7Context.h deleted file mode 100644 index 3de2c17bc4..0000000000 --- a/rpcs3/Emu/ARMv7/ARMv7Context.h +++ /dev/null @@ -1,324 +0,0 @@ -#pragma once - -#include "Emu/Memory/Memory.h" - -enum ARMv7InstructionSet -{ - ARM, - Thumb, - Jazelle, - ThumbEE -}; - -enum armv7_debug_flags : u32 -{ - DF_DISASM = 1 << 0, - DF_PRINT = 1 << 1, - DF_NO_EXE = 1 << 2, -}; - -struct ARMv7Context -{ - union - { - u32 GPR[15]; - - struct - { - u32 pad[13]; - - union - { - u32 SP; - - struct { u16 SP_main, SP_process; }; - }; - - u32 LR; - - union - { - struct - { - u32 reserved0 : 16; - u32 GE : 4; - u32 reserved1 : 4; - u32 dummy : 3; - u32 Q : 1; // Set to 1 if an SSAT or USAT instruction changes (saturates) the input value for the signed or unsigned range of the result - u32 V : 1; // Overflow condition code flag - u32 C : 1; // Carry condition code flag - u32 Z : 1; // Zero condition code flag - u32 N : 1; // Negative condition code flag - }; - - u32 APSR; - - } APSR; - }; - - struct - { - u64 GPR_D[8]; - }; - }; - - union - { - struct - { - u32 dummy : 24; - u32 exception : 8; - }; - - u32 IPSR; - - } IPSR; - - ARMv7InstructionSet ISET; - - union - { - struct - { - u8 shift_state : 5; - u8 cond_base : 3; - }; - - struct - { - u8 check_state : 4; - u8 condition : 4; - }; - - u8 IT; - - u32 advance() - { - const u32 res = check_state ? condition : 0xe /* always true */; - - shift_state <<= 1; - if (!check_state) - { - IT = 0; // clear - } - - return res; - } - - operator bool() const - { - return check_state != 0; - } - - } ITSTATE; - - u32 TLS; - - struct perf_counter - { - u32 event; - u32 value; - }; - - std::array counters; - - u32 PC; - s32 prio; - u32 stack_addr; - u32 stack_size; - u32 hle_func; // current function ID - - u32 debug; - std::string debug_str; - - void write_pc(u32 value, u32 size) - { - ISET = value & 1 ? Thumb : ARM; - PC = (value & ~1) - size; - } - - u32 read_pc() - { - return ISET == ARM ? PC + 8 : PC + 4; - } - - u32 get_stack_arg(u32 pos) - { - return vm::psv::read32(SP + sizeof(u32) * (pos - 5)); - } - - void fast_call(u32 addr); - - void write_gpr(u32 n, u32 value, u32 size) - { - assert(n < 16); - - if (n < 15) - { - GPR[n] = value; - } - else - { - write_pc(value, size); - } - } - - u32 read_gpr(u32 n) - { - assert(n < 16); - - if (n < 15) - { - return GPR[n]; - } - - return read_pc(); - } - - // function for processing va_args in printf-like functions - u32 get_next_gpr_arg(u32& g_count, u32& f_count, u32& v_count) - { - assert(!f_count && !v_count); // not supported - - if (g_count < 4) - { - return GPR[g_count++]; - } - else - { - return get_stack_arg(g_count++); - } - } - - template - never_inline void fmt_debug_str(const char* fmt, T... args) - { - debug_str = fmt::format(fmt, args...); - } -}; - -template::value> -struct cast_armv7_gpr -{ - static_assert(is_enum, "Invalid type for cast_armv7_gpr"); - - force_inline static u32 to_gpr(const T& value) - { - return cast_armv7_gpr>::to_gpr(static_cast>(value)); - } - - force_inline static T from_gpr(const u32 reg) - { - return static_cast(cast_armv7_gpr>::from_gpr(reg)); - } -}; - -template<> -struct cast_armv7_gpr -{ - force_inline static u32 to_gpr(const u8& value) - { - return value; - } - - force_inline static u8 from_gpr(const u32 reg) - { - return static_cast(reg); - } -}; - -template<> -struct cast_armv7_gpr -{ - force_inline static u32 to_gpr(const u16& value) - { - return value; - } - - force_inline static u16 from_gpr(const u32 reg) - { - return static_cast(reg); - } -}; - -template<> -struct cast_armv7_gpr -{ - force_inline static u32 to_gpr(const u32& value) - { - return value; - } - - force_inline static u32 from_gpr(const u32 reg) - { - return reg; - } -}; - -template<> -struct cast_armv7_gpr -{ - force_inline static u32 to_gpr(const s8& value) - { - return value; - } - - force_inline static s8 from_gpr(const u32 reg) - { - return static_cast(reg); - } -}; - -template<> -struct cast_armv7_gpr -{ - force_inline static u32 to_gpr(const s16& value) - { - return value; - } - - force_inline static s16 from_gpr(const u32 reg) - { - return static_cast(reg); - } -}; - -template<> -struct cast_armv7_gpr -{ - force_inline static u32 to_gpr(const s32& value) - { - return value; - } - - force_inline static s32 from_gpr(const u32 reg) - { - return static_cast(reg); - } -}; - -template<> -struct cast_armv7_gpr -{ - force_inline static u32 to_gpr(const b8& value) - { - return value; - } - - force_inline static b8 from_gpr(const u32& reg) - { - return reg != 0; - } -}; - -template -force_inline u32 cast_to_armv7_gpr(const T& value) -{ - return cast_armv7_gpr::to_gpr(value); -} - -template -force_inline T cast_from_armv7_gpr(const u32 reg) -{ - return cast_armv7_gpr::from_gpr(reg); -} diff --git a/rpcs3/Emu/ARMv7/ARMv7Decoder.cpp b/rpcs3/Emu/ARMv7/ARMv7Decoder.cpp deleted file mode 100644 index 005c7a2e38..0000000000 --- a/rpcs3/Emu/ARMv7/ARMv7Decoder.cpp +++ /dev/null @@ -1,1371 +0,0 @@ -#include "stdafx.h" -#include "Emu/Memory/Memory.h" -#include "ARMv7Thread.h" -#include "ARMv7Interpreter.h" -#include "ARMv7Opcodes.h" -#include "ARMv7Decoder.h" - -struct ARMv7_opcode_t -{ - u32 mask; - u32 code; - u32 length; // 2 or 4 - const char* name; - ARMv7_encoding type; - void(*func)(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - bool(*skip)(u32 code); -}; - -// single 16-bit value -#define ARMv7_OP2(mask, code, type, name, ...) { (u32)((mask) << 16), (u32)((code) << 16), 2, #name "_" #type, type, ARMv7_instrs::name, __VA_ARGS__ } -// two 16-bit values -#define ARMv7_OP4(mask0, mask1, code0, code1, type, name, ...) { (u32)((mask0) << 16) | (mask1), (u32)((code0) << 16) | (code1), 4, #name "_" #type, type, ARMv7_instrs::name, __VA_ARGS__ } - -#define SKIP_IF(cond) [](u32 c) -> bool { return cond; } - -#define BF(start, end) ((c << (31 - (end))) >> ((start) + 31 - (end))) -#define BT(pos) ((c >> (pos)) & 1) - -const ARMv7_opcode_t ARMv7_opcode_table[] = -{ - ARMv7_OP4(0xffff, 0x0000, 0xf870, 0x0000, T1, HACK, nullptr), // "Undefined" Thumb opcode used - ARMv7_OP4(0x0ff0, 0x00f0, 0x0070, 0x0090, A1, HACK), // "Undefined" ARM opcode used - - ARMv7_OP4(0xfbe0, 0x8000, 0xf140, 0x0000, T1, ADC_IMM, nullptr), - ARMv7_OP4(0x0fe0, 0x0000, 0x02a0, 0x0000, A1, ADC_IMM), - ARMv7_OP2(0xffc0, 0x4140, T1, ADC_REG, nullptr), - ARMv7_OP4(0xffe0, 0x8000, 0xeb40, 0x0000, T2, ADC_REG, nullptr), - ARMv7_OP4(0x0fe0, 0x0010, 0x00a0, 0x0000, A1, ADC_REG), - ARMv7_OP4(0x0fe0, 0x0090, 0x00a0, 0x0010, A1, ADC_RSR), - - ARMv7_OP2(0xfe00, 0x1c00, T1, ADD_IMM, nullptr), - ARMv7_OP2(0xf800, 0x3000, T2, ADD_IMM, nullptr), - ARMv7_OP4(0xfbe0, 0x8000, 0xf100, 0x0000, T3, ADD_IMM, SKIP_IF( (BF(8, 11) == 15 && BT(20)) || BF(16, 19) == 13 )), - ARMv7_OP4(0xfbf0, 0x8000, 0xf200, 0x0000, T4, ADD_IMM, SKIP_IF( (BF(16, 19) & 13) == 13 )), - ARMv7_OP4(0x0fe0, 0x0000, 0x0280, 0x0000, A1, ADD_IMM), - ARMv7_OP2(0xfe00, 0x1800, T1, ADD_REG, nullptr), - ARMv7_OP2(0xff00, 0x4400, T2, ADD_REG, SKIP_IF( (c & 0x87) == 0x85 || BF(3, 6) == 13 )), - ARMv7_OP4(0xffe0, 0x8000, 0xeb00, 0x0000, T3, ADD_REG, SKIP_IF( (BF(8, 11) == 15 && BT(20)) || BF(16, 19) == 13 )), - ARMv7_OP4(0x0fe0, 0x0010, 0x0080, 0x0000, A1, ADD_REG), - ARMv7_OP4(0x0fe0, 0x0090, 0x0080, 0x0010, A1, ADD_RSR), - ARMv7_OP2(0xf800, 0xa800, T1, ADD_SPI, nullptr), - ARMv7_OP2(0xff80, 0xb000, T2, ADD_SPI, nullptr), - ARMv7_OP4(0xfbef, 0x8000, 0xf10d, 0x0000, T3, ADD_SPI, SKIP_IF( BF(8, 11) == 15 && BT(20) )), - ARMv7_OP4(0xfbff, 0x8000, 0xf20d, 0x0000, T4, ADD_SPI, nullptr), - ARMv7_OP4(0x0fef, 0x0000, 0x028d, 0x0000, A1, ADD_SPI), - ARMv7_OP2(0xff78, 0x4468, T1, ADD_SPR, nullptr), - ARMv7_OP2(0xff87, 0x4485, T2, ADD_SPR, SKIP_IF( BF(3, 6) == 13 )), - ARMv7_OP4(0xffef, 0x8000, 0xeb0d, 0x0000, T3, ADD_SPR, nullptr), - ARMv7_OP4(0x0fef, 0x0010, 0x008d, 0x0000, A1, ADD_SPR), - - ARMv7_OP2(0xf800, 0xa000, T1, ADR, nullptr), - ARMv7_OP4(0xfbff, 0x8000, 0xf2af, 0x0000, T2, ADR, nullptr), - ARMv7_OP4(0xfbff, 0x8000, 0xf20f, 0x0000, T3, ADR, nullptr), - ARMv7_OP4(0x0fff, 0x0000, 0x028f, 0x0000, A1, ADR), - ARMv7_OP4(0x0fff, 0x0000, 0x024f, 0x0000, A2, ADR), - - ARMv7_OP4(0xfbe0, 0x8000, 0xf000, 0x0000, T1, AND_IMM, SKIP_IF( BF(8, 11) == 15 && BT(20) )), - ARMv7_OP4(0x0fe0, 0x0000, 0x0200, 0x0000, A1, AND_IMM), - ARMv7_OP2(0xffc0, 0x4000, T1, AND_REG, nullptr), - ARMv7_OP4(0xffe0, 0x8000, 0xea00, 0x0000, T2, AND_REG, SKIP_IF( BF(8, 11) == 15 && BT(20) )), - ARMv7_OP4(0x0fe0, 0x0010, 0x0000, 0x0000, A1, AND_REG), - ARMv7_OP4(0x0fe0, 0x0090, 0x0000, 0x0010, A1, AND_RSR), - - ARMv7_OP2(0xf800, 0x1000, T1, ASR_IMM, nullptr), - ARMv7_OP4(0xffef, 0x8030, 0xea4f, 0x0020, T2, ASR_IMM, nullptr), - ARMv7_OP4(0x0fef, 0x0070, 0x01a0, 0x0040, A1, ASR_IMM), - ARMv7_OP2(0xffc0, 0x4100, T1, ASR_REG, nullptr), - ARMv7_OP4(0xffe0, 0xf0f0, 0xfa40, 0xf000, T2, ASR_REG, nullptr), - ARMv7_OP4(0x0fef, 0x00f0, 0x01a0, 0x0050, A1, ASR_REG), - - ARMv7_OP2(0xf000, 0xd000, T1, B, SKIP_IF( BF(9, 11) == 0x7 )), - ARMv7_OP2(0xf800, 0xe000, T2, B, nullptr), - ARMv7_OP4(0xf800, 0xd000, 0xf000, 0x8000, T3, B, SKIP_IF( BF(23, 25) == 0x7 )), - ARMv7_OP4(0xf800, 0xd000, 0xf000, 0x9000, T4, B, nullptr), - ARMv7_OP4(0x0f00, 0x0000, 0x0a00, 0x0000, A1, B), - - ARMv7_OP4(0xffff, 0x8020, 0xf36f, 0x0000, T1, BFC, nullptr), - ARMv7_OP4(0x0fe0, 0x007f, 0x07c0, 0x001f, A1, BFC), - - ARMv7_OP4(0xfff0, 0x8020, 0xf360, 0x0000, T1, BFI, SKIP_IF( BF(16, 19) == 15 )), - ARMv7_OP4(0x0fe0, 0x0070, 0x07c0, 0x0010, A1, BFI), - - ARMv7_OP4(0xfbe0, 0x8000, 0xf020, 0x0000, T1, BIC_IMM, nullptr), - ARMv7_OP4(0x0fe0, 0x0000, 0x03c0, 0x0000, A1, BIC_IMM), - ARMv7_OP2(0xffc0, 0x4380, T1, BIC_REG, nullptr), - ARMv7_OP4(0xffe0, 0x8000, 0xea20, 0x0000, T2, BIC_REG, nullptr), - ARMv7_OP4(0x0fe0, 0x0010, 0x01c0, 0x0000, A1, BIC_REG), - ARMv7_OP4(0x0fe0, 0x0090, 0x01c0, 0x0010, A1, BIC_RSR), - - ARMv7_OP2(0xff00, 0xbe00, T1, BKPT, nullptr), - ARMv7_OP4(0x0ff0, 0x00f0, 0x0120, 0x0070, A1, BKPT), - - ARMv7_OP4(0xf800, 0xd000, 0xf000, 0xd000, T1, BL, nullptr), - ARMv7_OP4(0x0f00, 0x0000, 0x0b00, 0x0000, A1, BL), - ARMv7_OP2(0xff80, 0x4780, T1, BLX, nullptr), - ARMv7_OP4(0xf800, 0xc001, 0xf000, 0xc000, T2, BLX, nullptr), - ARMv7_OP4(0x0fff, 0xfff0, 0x012f, 0xff30, A1, BLX), - ARMv7_OP4(0xfe00, 0x0000, 0xfa00, 0x0000, A2, BLX), - - ARMv7_OP2(0xff87, 0x4700, T1, BX, nullptr), - ARMv7_OP4(0x0fff, 0xfff0, 0x012f, 0xff10, A1, BX), - - ARMv7_OP2(0xf500, 0xb100, T1, CB_Z, nullptr), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfab0, 0xf080, T1, CLZ, nullptr), - ARMv7_OP4(0x0fff, 0x0ff0, 0x016f, 0x0f10, A1, CLZ), - - ARMv7_OP4(0xfbf0, 0x8f00, 0xf110, 0x0f00, T1, CMN_IMM, nullptr), - ARMv7_OP4(0x0ff0, 0xf000, 0x0370, 0x0000, A1, CMN_IMM), - ARMv7_OP2(0xffc0, 0x42c0, T1, CMN_REG, nullptr), - ARMv7_OP4(0xfff0, 0x8f00, 0xeb10, 0x0f00, T2, CMN_REG, nullptr), - ARMv7_OP4(0x0ff0, 0xf010, 0x0170, 0x0000, A1, CMN_REG), - ARMv7_OP4(0x0ff0, 0xf090, 0x0170, 0x0010, A1, CMN_RSR), - - ARMv7_OP2(0xf800, 0x2800, T1, CMP_IMM, nullptr), - ARMv7_OP4(0xfbf0, 0x8f00, 0xf1b0, 0x0f00, T2, CMP_IMM, nullptr), - ARMv7_OP4(0x0ff0, 0xf000, 0x0350, 0x0000, A1, CMP_IMM), - ARMv7_OP2(0xffc0, 0x4280, T1, CMP_REG, nullptr), - ARMv7_OP2(0xff00, 0x4500, T2, CMP_REG, nullptr), - ARMv7_OP4(0xfff0, 0x8f00, 0xebb0, 0x0f00, T3, CMP_REG, nullptr), - ARMv7_OP4(0x0ff0, 0xf010, 0x0150, 0x0000, A1, CMP_REG), - ARMv7_OP4(0x0ff0, 0xf090, 0x0150, 0x0010, A1, CMP_RSR), - - ARMv7_OP4(0xffff, 0xfff0, 0xf3af, 0x80f0, T1, DBG, nullptr), - ARMv7_OP4(0x0fff, 0xfff0, 0x0320, 0xf0f0, A1, DBG), - - ARMv7_OP4(0xffff, 0xfff0, 0xf3bf, 0x8f50, T1, DMB, nullptr), - ARMv7_OP4(0xffff, 0xfff0, 0xf57f, 0xf050, A1, DMB), - - ARMv7_OP4(0xffff, 0xfff0, 0xf3bf, 0x8f40, T1, DSB, nullptr), - ARMv7_OP4(0xffff, 0xfff0, 0xf57f, 0xf040, A1, DSB), - - ARMv7_OP4(0xfbe0, 0x8000, 0xf080, 0x0000, T1, EOR_IMM, SKIP_IF( BF(8, 11) == 15 && BT(20) )), - ARMv7_OP4(0x0fe0, 0x0000, 0x0220, 0x0000, A1, EOR_IMM), - ARMv7_OP2(0xffc0, 0x4040, T1, EOR_REG, nullptr), - ARMv7_OP4(0xffe0, 0x8000, 0xea80, 0x0000, T2, EOR_REG, SKIP_IF( BF(8, 11) == 15 && BT(20) )), - ARMv7_OP4(0x0fe0, 0x0010, 0x0020, 0x0000, A1, EOR_REG), - ARMv7_OP4(0x0fe0, 0x0090, 0x0020, 0x0010, A1, EOR_RSR), - - ARMv7_OP2(0xff00, 0xbf00, T1, IT, SKIP_IF( BF(0, 3) == 0 )), - - ARMv7_OP2(0xf800, 0xc800, T1, LDM, nullptr), - ARMv7_OP4(0xffd0, 0x2000, 0xe890, 0x0000, T2, LDM, SKIP_IF( BT(21) && BF(16, 19) == 13 )), - ARMv7_OP4(0x0fd0, 0x0000, 0x0890, 0x0000, A1, LDM), - ARMv7_OP4(0x0fd0, 0x0000, 0x0810, 0x0000, A1, LDMDA), - ARMv7_OP4(0xffd0, 0x2000, 0xe910, 0x0000, T1, LDMDB, nullptr), - ARMv7_OP4(0x0fd0, 0x0000, 0x0910, 0x0000, A1, LDMDB), - ARMv7_OP4(0x0fd0, 0x0000, 0x0990, 0x0000, A1, LDMIB), - - ARMv7_OP2(0xf800, 0x6800, T1, LDR_IMM, nullptr), - ARMv7_OP2(0xf800, 0x9800, T2, LDR_IMM, nullptr), - ARMv7_OP4(0xfff0, 0x0000, 0xf8d0, 0x0000, T3, LDR_IMM, SKIP_IF( BF(16, 19) == 15 )), - ARMv7_OP4(0xfff0, 0x0800, 0xf850, 0x0800, T4, LDR_IMM, SKIP_IF( BF(16, 19) == 15 || BF(8, 10) == 6 || (c & 0xf07ff) == 0xd0304 || (c & 0x500) == 0 )), - ARMv7_OP4(0x0e50, 0x0000, 0x0410, 0x0000, A1, LDR_IMM), - ARMv7_OP2(0xf800, 0x4800, T1, LDR_LIT, nullptr), - ARMv7_OP4(0xff7f, 0x0000, 0xf85f, 0x0000, T2, LDR_LIT, nullptr), - ARMv7_OP4(0x0f7f, 0x0000, 0x051f, 0x0000, A1, LDR_LIT), - ARMv7_OP2(0xfe00, 0x5800, T1, LDR_REG, nullptr), - ARMv7_OP4(0xfff0, 0x0fc0, 0xf850, 0x0000, T2, LDR_REG, SKIP_IF( BF(16, 19) == 15 )), - ARMv7_OP4(0x0e50, 0x0010, 0x0610, 0x0000, A1, LDR_REG), - - ARMv7_OP2(0xf800, 0x7800, T1, LDRB_IMM), - ARMv7_OP4(0xfff0, 0x0000, 0xf890, 0x0000, T2, LDRB_IMM), - ARMv7_OP4(0xfff0, 0x0800, 0xf810, 0x0800, T3, LDRB_IMM), - ARMv7_OP4(0x0e50, 0x0000, 0x0450, 0x0000, A1, LDRB_IMM), - ARMv7_OP4(0xff7f, 0x0000, 0xf81f, 0x0000, T1, LDRB_LIT), - ARMv7_OP4(0x0f7f, 0x0000, 0x055f, 0x0000, A1, LDRB_LIT), - ARMv7_OP2(0xfe00, 0x5c00, T1, LDRB_REG), - ARMv7_OP4(0xfff0, 0x0fc0, 0xf810, 0x0000, T2, LDRB_REG), - ARMv7_OP4(0x0e50, 0x0010, 0x0650, 0x0000, A1, LDRB_REG), - - ARMv7_OP4(0xfe50, 0x0000, 0xe850, 0x0000, T1, LDRD_IMM, SKIP_IF( (!BT(21) && !BT(24)) || BF(16, 19) == 15 )), - ARMv7_OP4(0x0e50, 0x00f0, 0x0040, 0x00d0, A1, LDRD_IMM), - ARMv7_OP4(0xfe7f, 0x0000, 0xe85f, 0x0000, T1, LDRD_LIT), - ARMv7_OP4(0x0f7f, 0x00f0, 0x014f, 0x00d0, A1, LDRD_LIT), - ARMv7_OP4(0x0e50, 0x0ff0, 0x0000, 0x00d0, A1, LDRD_REG), - - ARMv7_OP4(0xfff0, 0x0f00, 0xe850, 0x0f00, T1, LDREX), - ARMv7_OP4(0x0ff0, 0x0fff, 0x0190, 0x0f9f, A1, LDREX), - ARMv7_OP4(0xfff0, 0x0fff, 0xe8d0, 0x0f4f, T1, LDREXB), - ARMv7_OP4(0x0ff0, 0x0fff, 0x01d0, 0x0f9f, A1, LDREXB), - ARMv7_OP4(0xfff0, 0x00ff, 0xe8d0, 0x007f, T1, LDREXD), - ARMv7_OP4(0x0ff0, 0x0fff, 0x01b0, 0x0f9f, A1, LDREXD), - ARMv7_OP4(0xfff0, 0x0fff, 0xe8d0, 0x0f5f, T1, LDREXH), - ARMv7_OP4(0x0ff0, 0x0fff, 0x01f0, 0x0f9f, A1, LDREXH), - - ARMv7_OP2(0xf800, 0x8800, T1, LDRH_IMM), - ARMv7_OP4(0xfff0, 0x0000, 0xf8b0, 0x0000, T2, LDRH_IMM), - ARMv7_OP4(0xfff0, 0x0800, 0xf830, 0x0800, T3, LDRH_IMM), - ARMv7_OP4(0x0e50, 0x00f0, 0x0050, 0x00b0, A1, LDRH_IMM), - ARMv7_OP4(0xff7f, 0x0000, 0xf83f, 0x0000, T1, LDRH_LIT), - ARMv7_OP4(0x0f7f, 0x00f0, 0x015f, 0x00b0, A1, LDRH_LIT), - ARMv7_OP2(0xfe00, 0x5a00, T1, LDRH_REG), - ARMv7_OP4(0xfff0, 0x0fc0, 0xf830, 0x0000, T2, LDRH_REG), - ARMv7_OP4(0x0e50, 0x0ff0, 0x0010, 0x00b0, A1, LDRH_REG), - - ARMv7_OP4(0xfff0, 0x0000, 0xf990, 0x0000, T1, LDRSB_IMM), - ARMv7_OP4(0xfff0, 0x0800, 0xf910, 0x0800, T2, LDRSB_IMM), - ARMv7_OP4(0x0e50, 0x00f0, 0x0050, 0x00d0, A1, LDRSB_IMM), - ARMv7_OP4(0xff7f, 0x0000, 0xf91f, 0x0000, T1, LDRSB_LIT), - ARMv7_OP4(0x0f7f, 0x00f0, 0x015f, 0x00d0, A1, LDRSB_LIT), - ARMv7_OP2(0xfe00, 0x5600, T1, LDRSB_REG), - ARMv7_OP4(0xfff0, 0x0fc0, 0xf910, 0x0000, T2, LDRSB_REG), - ARMv7_OP4(0x0e50, 0x0ff0, 0x0010, 0x00d0, A1, LDRSB_REG), - - ARMv7_OP4(0xfff0, 0x0000, 0xf9b0, 0x0000, T1, LDRSH_IMM), - ARMv7_OP4(0xfff0, 0x0800, 0xf930, 0x0800, T2, LDRSH_IMM), - ARMv7_OP4(0x0e50, 0x00f0, 0x0050, 0x00f0, A1, LDRSH_IMM), - ARMv7_OP4(0xff7f, 0x0000, 0xf93f, 0x0000, T1, LDRSH_LIT), - ARMv7_OP4(0x0f7f, 0x00f0, 0x015f, 0x00f0, A1, LDRSH_LIT), - ARMv7_OP2(0xfe00, 0x5e00, T1, LDRSH_REG), - ARMv7_OP4(0xfff0, 0x0fc0, 0xf930, 0x0000, T2, LDRSH_REG), - ARMv7_OP4(0x0e50, 0x0ff0, 0x0010, 0x00f0, A1, LDRSH_REG), - - ARMv7_OP2(0xf800, 0x0000, T1, LSL_IMM), - ARMv7_OP4(0xffef, 0x8030, 0xea4f, 0x0000, T2, LSL_IMM), - ARMv7_OP4(0x0fef, 0x0070, 0x01a0, 0x0000, A1, LSL_IMM), - ARMv7_OP2(0xffc0, 0x4080, T1, LSL_REG), - ARMv7_OP4(0xffe0, 0xf0f0, 0xfa00, 0xf000, T2, LSL_REG), - ARMv7_OP4(0x0fef, 0x00f0, 0x01a0, 0x0010, A1, LSL_REG), - - ARMv7_OP2(0xf800, 0x0800, T1, LSR_IMM), - ARMv7_OP4(0xffef, 0x8030, 0xea4f, 0x0010, T2, LSR_IMM), - ARMv7_OP4(0x0fef, 0x0030, 0x01a0, 0x0020, A1, LSR_IMM), - ARMv7_OP2(0xffc0, 0x40c0, T1, LSR_REG), - ARMv7_OP4(0xffe0, 0xf0f0, 0xfa20, 0xf000, T2, LSR_REG), - ARMv7_OP4(0x0fef, 0x00f0, 0x01a0, 0x0030, A1, LSR_REG), - - ARMv7_OP4(0xfff0, 0x00f0, 0xfb00, 0x0000, T1, MLA, SKIP_IF( BF(12, 15) == 15 )), - ARMv7_OP4(0x0fe0, 0x00f0, 0x0020, 0x0090, A1, MLA), - - ARMv7_OP4(0xfff0, 0x00f0, 0xfb00, 0x0010, T1, MLS), - ARMv7_OP4(0x0ff0, 0x00f0, 0x0060, 0x0090, A1, MLS), - - ARMv7_OP2(0xf800, 0x2000, T1, MOV_IMM), - ARMv7_OP4(0xfbef, 0x8000, 0xf04f, 0x0000, T2, MOV_IMM), - ARMv7_OP4(0xfbf0, 0x8000, 0xf240, 0x0000, T3, MOV_IMM), - ARMv7_OP4(0x0fef, 0x0000, 0x03a0, 0x0000, A1, MOV_IMM), - ARMv7_OP4(0x0ff0, 0x0000, 0x0300, 0x0000, A2, MOV_IMM), - ARMv7_OP2(0xff00, 0x4600, T1, MOV_REG), - ARMv7_OP2(0xffc0, 0x0000, T2, MOV_REG), - ARMv7_OP4(0xffef, 0xf0f0, 0xea4f, 0x0000, T3, MOV_REG), - ARMv7_OP4(0x0fef, 0x0ff0, 0x01a0, 0x0000, A1, MOV_REG), - - ARMv7_OP4(0xfbf0, 0x8000, 0xf2c0, 0x0000, T1, MOVT), - ARMv7_OP4(0x0ff0, 0x0000, 0x0340, 0x0000, A1, MOVT), - - ARMv7_OP4(0xff10, 0x0010, 0xee10, 0x0010, T1, MRC_), - ARMv7_OP4(0x0f10, 0x0010, 0x0e10, 0x0010, A1, MRC_), - ARMv7_OP4(0xff10, 0x0010, 0xfe10, 0x0010, T2, MRC_), - ARMv7_OP4(0xff10, 0x0010, 0xfe10, 0x0010, A2, MRC_), - - ARMv7_OP4(0xffff, 0xf0ff, 0xf3ef, 0x8000, T1, MRS), - ARMv7_OP4(0x0fff, 0x0fff, 0x010f, 0x0000, A1, MRS), - - ARMv7_OP4(0x0ff3, 0xf000, 0x0320, 0xf000, A1, MSR_IMM), - ARMv7_OP4(0xfff0, 0xf3ff, 0xf380, 0x8000, T1, MSR_REG), - ARMv7_OP4(0x0ff3, 0xfff0, 0x0120, 0xf000, A1, MSR_REG), - - ARMv7_OP2(0xffc0, 0x4340, T1, MUL), - ARMv7_OP4(0xfff0, 0xf0f0, 0xfb00, 0xf000, T2, MUL), - ARMv7_OP4(0x0fe0, 0xf0f0, 0x0000, 0x0090, A1, MUL), - - ARMv7_OP4(0xfbef, 0x8000, 0xf06f, 0x0000, T1, MVN_IMM), - ARMv7_OP4(0x0fef, 0x0000, 0x03e0, 0x0000, A1, MVN_IMM), - ARMv7_OP2(0xffc0, 0x43c0, T1, MVN_REG), - ARMv7_OP4(0xffef, 0x8000, 0xea6f, 0x0000, T2, MVN_REG), - ARMv7_OP4(0xffef, 0x0010, 0x01e0, 0x0000, A1, MVN_REG), - ARMv7_OP4(0x0fef, 0x0090, 0x01e0, 0x0010, A1, MVN_RSR), - - ARMv7_OP2(0xffff, 0xbf00, T1, NOP), - ARMv7_OP4(0xffff, 0xffff, 0xf3af, 0x8000, T2, NOP), - ARMv7_OP4(0x0fff, 0xffff, 0x0320, 0xf000, A1, NOP), - - ARMv7_OP4(0xfbe0, 0x8000, 0xf060, 0x0000, T1, ORN_IMM), - ARMv7_OP4(0xffe0, 0x8000, 0xea60, 0x0000, T1, ORN_REG), - - ARMv7_OP4(0xfbe0, 0x8000, 0xf040, 0x0000, T1, ORR_IMM), - ARMv7_OP4(0x0fe0, 0x0000, 0x0380, 0x0000, A1, ORR_IMM), - ARMv7_OP2(0xffc0, 0x4300, T1, ORR_REG), - ARMv7_OP4(0xffe0, 0x8000, 0xea40, 0x0000, T2, ORR_REG, SKIP_IF( BF(16, 19) == 15 )), - ARMv7_OP4(0x0fe0, 0x0010, 0x0180, 0x0000, A1, ORR_REG), - ARMv7_OP4(0x0fe0, 0x0090, 0x0180, 0x0010, A1, ORR_RSR), - - ARMv7_OP4(0xfff0, 0x8010, 0xeac0, 0x0000, T1, PKH), - ARMv7_OP4(0x0ff0, 0x0030, 0x0680, 0x0010, A1, PKH), - - ARMv7_OP2(0xfe00, 0xbc00, T1, POP), - ARMv7_OP4(0xffff, 0x0000, 0xe8bd, 0x0000, T2, POP), - ARMv7_OP4(0xffff, 0x0fff, 0xf85d, 0x0b04, T3, POP), - ARMv7_OP4(0x0fff, 0x0000, 0x08bd, 0x0000, A1, POP), - ARMv7_OP4(0x0fff, 0x0fff, 0x049d, 0x0004, A2, POP), - - ARMv7_OP2(0xfe00, 0xb400, T1, PUSH), - ARMv7_OP4(0xffff, 0x0000, 0xe92d, 0x0000, T2, PUSH), // had an error in arch ref - ARMv7_OP4(0xffff, 0x0fff, 0xf84d, 0x0d04, T3, PUSH), - ARMv7_OP4(0x0fff, 0x0000, 0x092d, 0x0000, A1, PUSH), - ARMv7_OP4(0x0fff, 0x0fff, 0x052d, 0x0004, A2, PUSH), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf080, T1, QADD), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0100, 0x0050, A1, QADD), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf010, T1, QADD16), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0620, 0x0f10, A1, QADD16), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf010, T1, QADD8), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0620, 0x0f90, A1, QADD8), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfaa0, 0xf010, T1, QASX), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0620, 0x0f30, A1, QASX), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf090, T1, QDADD), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0140, 0x0050, A1, QDADD), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf0b0, T1, QDSUB), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0160, 0x0050, A1, QDSUB), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfae0, 0xf010, T1, QSAX), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0620, 0x0f50, A1, QSAX), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf0a0, T1, QSUB), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0120, 0x0050, A1, QSUB), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfad0, 0xf010, T1, QSUB16), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0620, 0x0f70, A1, QSUB16), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfac0, 0xf010, T1, QSUB8), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0620, 0x0ff0, A1, QSUB8), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf0a0, T1, RBIT), - ARMv7_OP4(0x0fff, 0x0ff0, 0x06ff, 0x0f30, A1, RBIT), - - ARMv7_OP2(0xffc0, 0xba00, T1, REV), - ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf080, T2, REV), - ARMv7_OP4(0x0fff, 0x0ff0, 0x06bf, 0x0f30, A1, REV), - - ARMv7_OP2(0xffc0, 0xba40, T1, REV16), - ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf090, T2, REV16), - ARMv7_OP4(0x0fff, 0x0ff0, 0x06bf, 0x0fb0, A1, REV16), - - ARMv7_OP2(0xffc0, 0xbac0, T1, REVSH), - ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf0b0, T2, REVSH), - ARMv7_OP4(0x0fff, 0x0ff0, 0x06ff, 0x0fb0, A1, REVSH), - - ARMv7_OP4(0xffef, 0x8030, 0xea4f, 0x0030, T1, ROR_IMM), - ARMv7_OP4(0x0fef, 0x0070, 0x01a0, 0x0060, A1, ROR_IMM), - ARMv7_OP2(0xffc0, 0x41c0, T1, ROR_REG), - ARMv7_OP4(0xffe0, 0xf0f0, 0xfa60, 0xf000, T2, ROR_REG), - ARMv7_OP4(0x0fef, 0x00f0, 0x01a0, 0x0070, A1, ROR_REG), - ARMv7_OP4(0xffef, 0xf0f0, 0xea4f, 0x0030, T1, RRX), - ARMv7_OP4(0x0fef, 0x0ff0, 0x01a0, 0x0060, A1, RRX), - - ARMv7_OP2(0xffc0, 0x4240, T1, RSB_IMM), - ARMv7_OP4(0xfbe0, 0x8000, 0xf1c0, 0x0000, T2, RSB_IMM), - ARMv7_OP4(0x0fe0, 0x0000, 0x0260, 0x0000, A1, RSB_IMM), - ARMv7_OP4(0xffe0, 0x8000, 0xebc0, 0x0000, T1, RSB_REG), - ARMv7_OP4(0x0fe0, 0x0010, 0x0060, 0x0000, A1, RSB_REG), - ARMv7_OP4(0x0fe0, 0x0090, 0x0060, 0x0010, A1, RSB_RSR), - - ARMv7_OP4(0x0fe0, 0x0000, 0x02e0, 0x0000, A1, RSC_IMM), - ARMv7_OP4(0x0fe0, 0x0010, 0x00e0, 0x0000, A1, RSC_REG), - ARMv7_OP4(0x0fe0, 0x0090, 0x00e0, 0x0010, A1, RSC_RSR), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf000, T1, SADD16), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0610, 0x0f10, A1, SADD16), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf000, T1, SADD8), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0610, 0x0f90, A1, SADD8), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfaa0, 0xf000, T1, SASX), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0610, 0x0f30, A1, SASX), - - ARMv7_OP4(0xfbe0, 0x8000, 0xf160, 0x0000, T1, SBC_IMM), - ARMv7_OP4(0x0fe0, 0x0000, 0x02c0, 0x0000, A1, SBC_IMM), - ARMv7_OP2(0xffc0, 0x4180, T1, SBC_REG), - ARMv7_OP4(0xffe0, 0x8000, 0xeb60, 0x0000, T2, SBC_REG), - ARMv7_OP4(0x0fe0, 0x0010, 0x00c0, 0x0000, A1, SBC_REG), - ARMv7_OP4(0x0fe0, 0x0090, 0x00c0, 0x0010, A1, SBC_RSR), - - ARMv7_OP4(0xfff0, 0x8020, 0xf340, 0x0000, T1, SBFX), - ARMv7_OP4(0x0fe0, 0x0070, 0x07a0, 0x0050, A1, SBFX), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfb90, 0xf0f0, T1, SDIV), // ??? - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfaa0, 0xf080, T1, SEL), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0680, 0x0fb0, A1, SEL), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf020, T1, SHADD16), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0630, 0x0f10, A1, SHADD16), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf020, T1, SHADD8), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0630, 0x0f90, A1, SHADD8), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfaa0, 0xf020, T1, SHASX), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0630, 0x0f30, A1, SHASX), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfae0, 0xf020, T1, SHSAX), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0630, 0x0f50, A1, SHSAX), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfad0, 0xf020, T1, SHSUB16), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0630, 0x0f70, A1, SHSUB16), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfac0, 0xf020, T1, SHSUB8), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0630, 0x0ff0, A1, SHSUB8), - - ARMv7_OP4(0xfff0, 0x00c0, 0xfb10, 0x0000, T1, SMLA__), - ARMv7_OP4(0x0ff0, 0x0090, 0x0100, 0x0080, A1, SMLA__), - - ARMv7_OP4(0xfff0, 0x00e0, 0xfb20, 0x0000, T1, SMLAD), - ARMv7_OP4(0x0ff0, 0x00d0, 0x0700, 0x0010, A1, SMLAD), - - ARMv7_OP4(0xfff0, 0x00f0, 0xfbc0, 0x0000, T1, SMLAL), - ARMv7_OP4(0x0fe0, 0x00f0, 0x00e0, 0x0090, A1, SMLAL), - - ARMv7_OP4(0xfff0, 0x00c0, 0xfbc0, 0x0080, T1, SMLAL__), - ARMv7_OP4(0x0ff0, 0x0090, 0x0140, 0x0080, A1, SMLAL__), - - ARMv7_OP4(0xfff0, 0x00e0, 0xfbc0, 0x00c0, T1, SMLALD), - ARMv7_OP4(0x0ff0, 0x00d0, 0x0740, 0x0010, A1, SMLALD), - - ARMv7_OP4(0xfff0, 0x00e0, 0xfb30, 0x0000, T1, SMLAW_), - ARMv7_OP4(0x0ff0, 0x00b0, 0x0120, 0x0080, A1, SMLAW_), - - ARMv7_OP4(0xfff0, 0x00e0, 0xfb40, 0x0000, T1, SMLSD), - ARMv7_OP4(0x0ff0, 0x00d0, 0x0700, 0x0050, A1, SMLSD), - - ARMv7_OP4(0xfff0, 0x00e0, 0xfbd0, 0x00c0, T1, SMLSLD), - ARMv7_OP4(0x0ff0, 0x00d0, 0x0740, 0x0050, A1, SMLSLD), - - ARMv7_OP4(0xfff0, 0x00e0, 0xfb50, 0x0000, T1, SMMLA), - ARMv7_OP4(0x0ff0, 0x00d0, 0x0750, 0x0010, A1, SMMLA), - - ARMv7_OP4(0xfff0, 0x00e0, 0xfb60, 0x0000, T1, SMMLS), - ARMv7_OP4(0x0ff0, 0x00d0, 0x0750, 0x00d0, A1, SMMLS), - - ARMv7_OP4(0xfff0, 0xf0e0, 0xfb50, 0xf000, T1, SMMUL), - ARMv7_OP4(0x0ff0, 0xf0d0, 0x0750, 0xf010, A1, SMMUL), - - ARMv7_OP4(0xfff0, 0xf0e0, 0xfb20, 0xf000, T1, SMUAD), - ARMv7_OP4(0x0ff0, 0xf0d0, 0x0700, 0xf010, A1, SMUAD), - - ARMv7_OP4(0xfff0, 0xf0c0, 0xfb10, 0xf000, T1, SMUL__), - ARMv7_OP4(0x0ff0, 0xf090, 0x0160, 0x0080, A1, SMUL__), - - ARMv7_OP4(0xfff0, 0x00f0, 0xfb80, 0x0000, T1, SMULL), - ARMv7_OP4(0x0fe0, 0x00f0, 0x00c0, 0x0090, A1, SMULL), - - ARMv7_OP4(0xfff0, 0xf0e0, 0xfb30, 0xf000, T1, SMULW_), - ARMv7_OP4(0x0ff0, 0xf0b0, 0x0120, 0x00a0, A1, SMULW_), - - ARMv7_OP4(0xfff0, 0xf0e0, 0xfb40, 0xf000, T1, SMUSD), - ARMv7_OP4(0x0ff0, 0xf0d0, 0x0700, 0xf050, A1, SMUSD), - - ARMv7_OP4(0xffd0, 0x8020, 0xf300, 0x0000, T1, SSAT), - ARMv7_OP4(0x0fe0, 0x0030, 0x06a0, 0x0010, A1, SSAT), - - ARMv7_OP4(0xfff0, 0xf0e0, 0xf320, 0x0000, T1, SSAT16), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x06a0, 0x0f30, A1, SSAT16), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfae0, 0xf000, T1, SSAX), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0610, 0x0f50, A1, SSAX), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfad0, 0xf000, T1, SSUB16), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0610, 0x0f70, A1, SSUB16), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfac0, 0xf000, T1, SSUB8), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0610, 0x0ff0, A1, SSUB8), - - ARMv7_OP2(0xf800, 0xc000, T1, STM), - ARMv7_OP4(0xffd0, 0xa000, 0xe880, 0x0000, T2, STM), - ARMv7_OP4(0x0fd0, 0x0000, 0x0880, 0x0000, A1, STM), - ARMv7_OP4(0x0fd0, 0x0000, 0x0800, 0x0000, A1, STMDA), - ARMv7_OP4(0xffd0, 0xa000, 0xe900, 0x0000, T1, STMDB), - ARMv7_OP4(0x0fd0, 0x0000, 0x0900, 0x0000, A1, STMDB), - ARMv7_OP4(0x0fd0, 0x0000, 0x0980, 0x0000, A1, STMIB), - - ARMv7_OP2(0xf800, 0x6000, T1, STR_IMM), - ARMv7_OP2(0xf800, 0x9000, T2, STR_IMM), - ARMv7_OP4(0xfff0, 0x0000, 0xf8c0, 0x0000, T3, STR_IMM), - ARMv7_OP4(0xfff0, 0x0800, 0xf840, 0x0800, T4, STR_IMM), - ARMv7_OP4(0x0e50, 0x0000, 0x0400, 0x0000, A1, STR_IMM), - ARMv7_OP2(0xfe00, 0x5000, T1, STR_REG), - ARMv7_OP4(0xfff0, 0x0fc0, 0xf840, 0x0000, T2, STR_REG), - ARMv7_OP4(0x0e50, 0x0010, 0x0600, 0x0000, A1, STR_REG), - - ARMv7_OP2(0xf800, 0x7000, T1, STRB_IMM), - ARMv7_OP4(0xfff0, 0x0000, 0xf880, 0x0000, T2, STRB_IMM), - ARMv7_OP4(0xfff0, 0x0800, 0xf800, 0x0800, T3, STRB_IMM), - ARMv7_OP4(0x0e50, 0x0000, 0x0440, 0x0000, A1, STRB_IMM), - ARMv7_OP2(0xfe00, 0x5400, T1, STRB_REG), - ARMv7_OP4(0xfff0, 0x0fc0, 0xf800, 0x0000, T2, STRB_REG), - ARMv7_OP4(0x0e50, 0x0010, 0x0640, 0x0000, A1, STRB_REG), - - ARMv7_OP4(0xfe50, 0x0000, 0xe840, 0x0000, T1, STRD_IMM, SKIP_IF( !BT(21) && !BT(24) )), - ARMv7_OP4(0x0e50, 0x00f0, 0x0040, 0x00f0, A1, STRD_IMM), - ARMv7_OP4(0x0e50, 0x0ff0, 0x0000, 0x00f0, A1, STRD_REG), - - ARMv7_OP4(0xfff0, 0x0000, 0xe840, 0x0000, T1, STREX), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0180, 0x0f90, A1, STREX), - ARMv7_OP4(0xfff0, 0x0ff0, 0xe8c0, 0x0f40, T1, STREXB), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x01c0, 0x0f90, A1, STREXB), - ARMv7_OP4(0xfff0, 0x00f0, 0xe8c0, 0x0070, T1, STREXD), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x01a0, 0x0f90, A1, STREXD), - ARMv7_OP4(0xfff0, 0x0ff0, 0xe8c0, 0x0f50, T1, STREXH), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x01e0, 0x0f90, A1, STREXH), - - ARMv7_OP2(0xf800, 0x8000, T1, STRH_IMM), - ARMv7_OP4(0xfff0, 0x0000, 0xf8a0, 0x0000, T2, STRH_IMM), - ARMv7_OP4(0xfff0, 0x0800, 0xf820, 0x0800, T3, STRH_IMM), - ARMv7_OP4(0x0e50, 0x00f0, 0x0040, 0x00b0, A1, STRH_IMM), - ARMv7_OP2(0xfe00, 0x5200, T1, STRH_REG), - ARMv7_OP4(0xfff0, 0x0fc0, 0xf820, 0x0000, T2, STRH_REG), - ARMv7_OP4(0x0e50, 0x0ff0, 0x0000, 0x00b0, A1, STRH_REG), - - ARMv7_OP2(0xfe00, 0x1e00, T1, SUB_IMM), - ARMv7_OP2(0xf800, 0x3800, T2, SUB_IMM), - ARMv7_OP4(0xfbe0, 0x8000, 0xf1a0, 0x0000, T3, SUB_IMM, SKIP_IF( (BF(8, 11) == 15 && BT(20)) || BF(16, 19) == 13 )), - ARMv7_OP4(0xfbf0, 0x8000, 0xf2a0, 0x0000, T4, SUB_IMM), - ARMv7_OP4(0x0fe0, 0x0000, 0x0240, 0x0000, A1, SUB_IMM), - ARMv7_OP2(0xfe00, 0x1a00, T1, SUB_REG), - ARMv7_OP4(0xffe0, 0x8000, 0xeba0, 0x0000, T2, SUB_REG, SKIP_IF( (BF(8, 11) == 15 && BT(20)) || BF(16, 19) == 13 )), - ARMv7_OP4(0x0fe0, 0x0010, 0x0040, 0x0000, A1, SUB_REG), - ARMv7_OP4(0x0fe0, 0x0090, 0x0040, 0x0010, A1, SUB_RSR), - ARMv7_OP2(0xff80, 0xb080, T1, SUB_SPI), - ARMv7_OP4(0xfbef, 0x8000, 0xf1ad, 0x0000, T2, SUB_SPI), - ARMv7_OP4(0xfbff, 0x8000, 0xf2ad, 0x0000, T3, SUB_SPI), - ARMv7_OP4(0x0fef, 0x0000, 0x024d, 0x0000, A1, SUB_SPI), - ARMv7_OP4(0xffef, 0x8000, 0xebad, 0x0000, T1, SUB_SPR), - ARMv7_OP4(0x0fef, 0x0010, 0x004d, 0x0000, A1, SUB_SPR), - - ARMv7_OP2(0xff00, 0xdf00, T1, SVC), - ARMv7_OP4(0x0f00, 0x0000, 0x0f00, 0x0000, A1, SVC), - - ARMv7_OP4(0xfff0, 0xf0c0, 0xfa40, 0xf080, T1, SXTAB), - ARMv7_OP4(0x0ff0, 0x03f0, 0x06a0, 0x0070, A1, SXTAB), - - ARMv7_OP4(0xfff0, 0xf0c0, 0xfa20, 0xf080, T1, SXTAB16), - ARMv7_OP4(0x0ff0, 0x03f0, 0x0680, 0x0070, A1, SXTAB16), - - ARMv7_OP4(0xfff0, 0xf0c0, 0xfa00, 0xf080, T1, SXTAH), - ARMv7_OP4(0x0ff0, 0x03f0, 0x06b0, 0x0070, A1, SXTAH), - - ARMv7_OP2(0xffc0, 0xb240, T1, SXTB), - ARMv7_OP4(0xffff, 0xf0c0, 0xfa4f, 0xf080, T2, SXTB), - ARMv7_OP4(0x0fff, 0x03f0, 0x06af, 0x0070, A1, SXTB), - - ARMv7_OP4(0xffff, 0xf0c0, 0xfa2f, 0xf080, T1, SXTB16), - ARMv7_OP4(0x0fff, 0x03f0, 0x068f, 0x0070, A1, SXTB16), - - ARMv7_OP2(0xffc0, 0xb200, T1, SXTH), - ARMv7_OP4(0xffff, 0xf0c0, 0xfa0f, 0xf080, T2, SXTH), - ARMv7_OP4(0x0fff, 0x03f0, 0x06bf, 0x0070, A1, SXTH), - - ARMv7_OP4(0xfff0, 0xffe0, 0xe8d0, 0xf000, T1, TB_), - - ARMv7_OP4(0xfbf0, 0x8f00, 0xf090, 0x0f00, T1, TEQ_IMM), - ARMv7_OP4(0x0ff0, 0xf000, 0x0330, 0x0000, A1, TEQ_IMM), - ARMv7_OP4(0xfff0, 0x8f00, 0xea90, 0x0f00, T1, TEQ_REG), - ARMv7_OP4(0x0ff0, 0xf010, 0x0130, 0x0000, A1, TEQ_REG), - ARMv7_OP4(0x0ff0, 0xf090, 0x0130, 0x0010, A1, TEQ_RSR), - - ARMv7_OP4(0xfbf0, 0x8f00, 0xf010, 0x0f00, T1, TST_IMM), - ARMv7_OP4(0x0ff0, 0xf000, 0x0310, 0x0000, A1, TST_IMM), - ARMv7_OP2(0xffc0, 0x4200, T1, TST_REG), - ARMv7_OP4(0xfff0, 0x8f00, 0xea10, 0x0f00, T2, TST_REG), - ARMv7_OP4(0x0ff0, 0xf010, 0x0110, 0x0000, A1, TST_REG), - ARMv7_OP4(0x0ff0, 0xf090, 0x0110, 0x0010, A1, TST_RSR), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf040, T1, UADD16), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0650, 0x0f10, A1, UADD16), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf040, T1, UADD8), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0650, 0x0f90, A1, UADD8), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfaa0, 0xf040, T1, UASX), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0650, 0x0f30, A1, UASX), - - ARMv7_OP4(0xfff0, 0x8020, 0xf3c0, 0x0000, T1, UBFX), - ARMv7_OP4(0x0fe0, 0x0070, 0x07e0, 0x0050, A1, UBFX), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfbb0, 0xf0f0, T1, UDIV), // ??? - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf060, T1, UHADD16), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0670, 0x0f10, A1, UHADD16), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf060, T1, UHADD8), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0670, 0x0f90, A1, UHADD8), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfaa0, 0xf060, T1, UHASX), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0670, 0x0f30, A1, UHASX), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfae0, 0xf060, T1, UHSAX), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0670, 0x0f50, A1, UHSAX), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfad0, 0xf060, T1, UHSUB16), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0670, 0x0f70, A1, UHSUB16), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfac0, 0xf060, T1, UHSUB8), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0670, 0x0ff0, A1, UHSUB8), - - ARMv7_OP4(0xfff0, 0x00f0, 0xfbe0, 0x0060, T1, UMAAL), - ARMv7_OP4(0x0ff0, 0x00f0, 0x0040, 0x0090, A1, UMAAL), - - ARMv7_OP4(0xfff0, 0x00f0, 0xfbe0, 0x0000, T1, UMLAL), - ARMv7_OP4(0x0fe0, 0x00f0, 0x00a0, 0x0090, A1, UMLAL), - - ARMv7_OP4(0xfff0, 0x00f0, 0xfba0, 0x0000, T1, UMULL), - ARMv7_OP4(0x0fe0, 0x00f0, 0x0080, 0x0090, A1, UMULL), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf050, T1, UQADD16), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0660, 0x0f10, A1, UQADD16), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf050, T1, UQADD8), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0660, 0x0f90, A1, UQADD8), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfaa0, 0xf050, T1, UQASX), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0660, 0x0f30, A1, UQASX), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfae0, 0xf050, T1, UQSAX), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0660, 0x0f50, A1, UQSAX), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfad0, 0xf050, T1, UQSUB16), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0660, 0x0f70, A1, UQSUB16), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfac0, 0xf050, T1, UQSUB8), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0660, 0x0ff0, A1, UQSUB8), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfb70, 0xf000, T1, USAD8), - ARMv7_OP4(0x0ff0, 0xf0f0, 0x0780, 0xf010, A1, USAD8), - - ARMv7_OP4(0xfff0, 0x00f0, 0xfb70, 0x0000, T1, USADA8), - ARMv7_OP4(0x0ff0, 0x00f0, 0x0780, 0x0010, A1, USADA8), - - ARMv7_OP4(0xffd0, 0x8020, 0xf380, 0x0000, T1, USAT), - ARMv7_OP4(0x0fe0, 0x0030, 0x06e0, 0x0010, A1, USAT), - - ARMv7_OP4(0xfff0, 0xf0e0, 0xf3a0, 0x0000, T1, USAT16), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x06e0, 0x0f30, A1, USAT16), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfae0, 0xf040, T1, USAX), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0650, 0x0f50, A1, USAX), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfad0, 0xf040, T1, USUB16), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0650, 0x0f70, A1, USUB16), - - ARMv7_OP4(0xfff0, 0xf0f0, 0xfac0, 0xf040, T1, USUB8), - ARMv7_OP4(0x0ff0, 0x0ff0, 0x0650, 0x0ff0, A1, USUB8), - - ARMv7_OP4(0xfff0, 0xf0c0, 0xfa50, 0xf080, T1, UXTAB, SKIP_IF( BF(16, 19) == 15 )), - ARMv7_OP4(0x0ff0, 0x03f0, 0x06e0, 0x0070, A1, UXTAB, SKIP_IF( BF(16, 19) == 15 )), - - ARMv7_OP4(0xfff0, 0xf0c0, 0xfa30, 0xf080, T1, UXTAB16), - ARMv7_OP4(0x0ff0, 0x03f0, 0x06c0, 0x0070, A1, UXTAB16), - - ARMv7_OP4(0xfff0, 0xf0c0, 0xfa10, 0xf080, T1, UXTAH), - ARMv7_OP4(0x0ff0, 0x03f0, 0x06f0, 0x0070, A1, UXTAH), - - ARMv7_OP2(0xffc0, 0xb2c0, T1, UXTB), - ARMv7_OP4(0xffff, 0xf0c0, 0xfa5f, 0xf080, T2, UXTB), - ARMv7_OP4(0x0fff, 0x03f0, 0x06ef, 0x0070, A1, UXTB), - - ARMv7_OP4(0xffff, 0xf0c0, 0xfa3f, 0xf080, T1, UXTB16), - ARMv7_OP4(0x0fff, 0x03f0, 0x06cf, 0x0070, A1, UXTB16), - - ARMv7_OP2(0xffc0, 0xb280, T1, UXTH), - ARMv7_OP4(0xffff, 0xf0c0, 0xfa1f, 0xf080, T2, UXTH), - ARMv7_OP4(0x0fff, 0x03f0, 0x06ff, 0x0070, A1, UXTH), - - ARMv7_OP4(0xef80, 0x0f10, 0xef00, 0x0710, T1, VABA_), - ARMv7_OP4(0xfe80, 0x0f10, 0xf200, 0x0710, A1, VABA_), - ARMv7_OP4(0xef80, 0x0f50, 0xef80, 0x0500, T2, VABA_), - ARMv7_OP4(0xfe80, 0x0f50, 0xf280, 0x0500, A2, VABA_), - - ARMv7_OP4(0xef80, 0x0f10, 0xef00, 0x0700, T1, VABD_), - ARMv7_OP4(0xfe80, 0x0f10, 0xf200, 0x0700, A1, VABD_), - ARMv7_OP4(0xef80, 0x0f50, 0xef80, 0x0700, T2, VABD_), - ARMv7_OP4(0xfe80, 0x0f50, 0xf280, 0x0700, A2, VABD_), - - ARMv7_OP4(0xffa0, 0x0f10, 0xff20, 0x0d00, T1, VABD_FP), - ARMv7_OP4(0xffa0, 0x0f10, 0xf320, 0x0d00, A1, VABD_FP), - - ARMv7_OP4(0xffb3, 0x0b90, 0xffb1, 0x0300, T1, VABS), - ARMv7_OP4(0xffb3, 0x0b90, 0xf3b1, 0x0300, A1, VABS), - ARMv7_OP4(0xffbf, 0x0ed0, 0xeeb0, 0x0ac0, T2, VABS), - ARMv7_OP4(0x0fbf, 0x0ed0, 0x0eb0, 0x0ac0, A2, VABS), - - ARMv7_OP4(0xff80, 0x0f10, 0xff00, 0x0e10, T1, VAC__), - ARMv7_OP4(0xff80, 0x0f10, 0xf300, 0x0e10, A1, VAC__), - - ARMv7_OP4(0xff80, 0x0f10, 0xef00, 0x0800, T1, VADD), - ARMv7_OP4(0xff80, 0x0f10, 0xf200, 0x0800, A1, VADD), - - ARMv7_OP4(0xffa0, 0x0f10, 0xef00, 0x0d00, T1, VADD_FP), - ARMv7_OP4(0xffa0, 0x0f10, 0xf200, 0x0d00, A1, VADD_FP), - ARMv7_OP4(0xffb0, 0x0e50, 0xee30, 0x0a00, T2, VADD_FP), - ARMv7_OP4(0x0fb0, 0x0e50, 0x0e30, 0x0a00, A2, VADD_FP), - - ARMv7_OP4(0xff80, 0x0f50, 0xef80, 0x0400, T1, VADDHN), - ARMv7_OP4(0xff80, 0x0f50, 0xf280, 0x0400, A1, VADDHN), - - ARMv7_OP4(0xef80, 0x0e50, 0xef80, 0x0000, T1, VADD_), - ARMv7_OP4(0xfe80, 0x0e50, 0xf280, 0x0000, A1, VADD_), - - ARMv7_OP4(0xffb0, 0x0f10, 0xef00, 0x0110, T1, VAND), - ARMv7_OP4(0xffb0, 0x0f10, 0xf200, 0x0110, A1, VAND), - - ARMv7_OP4(0xefb8, 0x00b0, 0xef80, 0x0030, T1, VBIC_IMM), - ARMv7_OP4(0xfeb0, 0x00b0, 0xf280, 0x0030, A1, VBIC_IMM), - - ARMv7_OP4(0xffb0, 0x0f10, 0xef10, 0x0110, T1, VBIC_REG), - ARMv7_OP4(0xffb0, 0x0f10, 0xf210, 0x0110, A1, VBIC_REG), - - ARMv7_OP4(0xff80, 0x0f10, 0xff00, 0x0110, T1, VB__), - ARMv7_OP4(0xff80, 0x0f10, 0xf300, 0x0110, A1, VB__), - - ARMv7_OP4(0xff80, 0x0f10, 0xff00, 0x0810, T1, VCEQ_REG), - ARMv7_OP4(0xff80, 0x0f10, 0xf300, 0x0810, A1, VCEQ_REG), - ARMv7_OP4(0xffa0, 0x0f10, 0xef00, 0x0e00, T2, VCEQ_REG), - ARMv7_OP4(0xffa0, 0x0f10, 0xf200, 0x0e00, A2, VCEQ_REG), - - ARMv7_OP4(0xffb3, 0x0b90, 0xffb1, 0x0100, T1, VCEQ_ZERO), - ARMv7_OP4(0xffb3, 0x0b90, 0xf3b1, 0x0100, A1, VCEQ_ZERO), - - ARMv7_OP4(0xef80, 0x0f10, 0xef00, 0x0310, T1, VCGE_REG), - ARMv7_OP4(0xfe80, 0x0f10, 0xf200, 0x0310, A1, VCGE_REG), - ARMv7_OP4(0xffa0, 0x0f10, 0xff00, 0x0e00, T2, VCGE_REG), - ARMv7_OP4(0xffa0, 0x0f10, 0xf300, 0x0e00, A2, VCGE_REG), - - ARMv7_OP4(0xffb3, 0x0b90, 0xffb1, 0x0080, T1, VCGE_ZERO), - ARMv7_OP4(0xffb3, 0x0b90, 0xf3b1, 0x0080, A1, VCGE_ZERO), - - ARMv7_OP4(0xef80, 0x0f10, 0xef00, 0x0300, T1, VCGT_REG), - ARMv7_OP4(0xfe80, 0x0f10, 0xf200, 0x0300, A1, VCGT_REG), - ARMv7_OP4(0xffa0, 0x0f10, 0xff20, 0x0e00, T2, VCGT_REG), - ARMv7_OP4(0xffa0, 0x0f10, 0xf320, 0x0e00, A2, VCGT_REG), - - ARMv7_OP4(0xffb3, 0x0b90, 0xffb1, 0x0000, T1, VCGT_ZERO), - ARMv7_OP4(0xffb3, 0x0b90, 0xf3b1, 0x0000, A1, VCGT_ZERO), - - ARMv7_OP4(0xffb3, 0x0b90, 0xffb1, 0x0180, T1, VCLE_ZERO), - ARMv7_OP4(0xffb3, 0x0b90, 0xf3b1, 0x0180, A1, VCLE_ZERO), - - ARMv7_OP4(0xffb3, 0x0f90, 0xffb0, 0x0400, T1, VCLS), - ARMv7_OP4(0xffb3, 0x0f90, 0xf3b0, 0x0400, A1, VCLS), - - ARMv7_OP4(0xffb3, 0x0b90, 0xffb1, 0x0200, T1, VCLT_ZERO), - ARMv7_OP4(0xffb3, 0x0b90, 0xf3b1, 0x0200, A1, VCLT_ZERO), - - ARMv7_OP4(0xffb3, 0x0f90, 0xffb0, 0x0480, T1, VCLZ), - ARMv7_OP4(0xffb3, 0x0f90, 0xf3b0, 0x0480, A1, VCLZ), - - ARMv7_OP4(0xffbf, 0x0e50, 0xeeb4, 0x0a40, T1, VCMP_), - ARMv7_OP4(0x0fbf, 0x0e50, 0x0eb4, 0x0a40, A1, VCMP_), - ARMv7_OP4(0xffbf, 0x0e7f, 0xeeb5, 0x0a40, T2, VCMP_), - ARMv7_OP4(0x0fbf, 0x0e7f, 0x0eb5, 0x0a40, A2, VCMP_), - - ARMv7_OP4(0xffb3, 0x0f90, 0xffb0, 0x0500, T1, VCNT), - ARMv7_OP4(0xffb3, 0x0f90, 0xf3b0, 0x0500, A1, VCNT), - - ARMv7_OP4(0xffb3, 0x0e10, 0xffb3, 0x0600, T1, VCVT_FIA), - ARMv7_OP4(0xffb3, 0x0e10, 0xf3b3, 0x0600, A1, VCVT_FIA), - - ARMv7_OP4(0xffb8, 0x0e50, 0xeeb8, 0x0a40, T1, VCVT_FIF), - ARMv7_OP4(0x0fb8, 0x0e50, 0x0eb8, 0x0a40, A1, VCVT_FIF), - - ARMv7_OP4(0xef80, 0x0e90, 0xef80, 0x0e10, T1, VCVT_FFA), - ARMv7_OP4(0xfe80, 0x0e90, 0xf280, 0x0e10, A1, VCVT_FFA), - - ARMv7_OP4(0xffba, 0x0e50, 0xeeba, 0x0a40, T1, VCVT_FFF), - ARMv7_OP4(0x0fba, 0x0e50, 0x0eba, 0x0a40, A1, VCVT_FFF), - - ARMv7_OP4(0xffbf, 0x0ed0, 0xeeb7, 0x0ac0, T1, VCVT_DF), - ARMv7_OP4(0x0fbf, 0x0ed0, 0x0eb7, 0x0ac0, A1, VCVT_DF), - - ARMv7_OP4(0xffb3, 0x0ed0, 0xffb2, 0x0600, T1, VCVT_HFA), - ARMv7_OP4(0xffb3, 0x0ed0, 0xf3b2, 0x0600, A1, VCVT_HFA), - - ARMv7_OP4(0xffbe, 0x0f50, 0xeeb2, 0x0a40, T1, VCVT_HFF), - ARMv7_OP4(0x0fbe, 0x0f50, 0x0eb2, 0x0a40, A1, VCVT_HFF), - - ARMv7_OP4(0xffb0, 0x0e50, 0xee80, 0x0a00, T1, VDIV), - ARMv7_OP4(0x0fb0, 0x0e50, 0x0e80, 0x0a00, A1, VDIV), - - ARMv7_OP4(0xffb0, 0x0f90, 0xffb0, 0x0c00, T1, VDUP_S), - ARMv7_OP4(0xffb0, 0x0f90, 0xf3b0, 0x0c00, A1, VDUP_S), - - ARMv7_OP4(0xff90, 0x0f5f, 0xee80, 0x0b10, T1, VDUP_R), - ARMv7_OP4(0x0f90, 0x0f5f, 0x0e80, 0x0b10, A1, VDUP_R), - - ARMv7_OP4(0xffb0, 0x0f10, 0xff00, 0x0110, T1, VEOR), - ARMv7_OP4(0xffb0, 0x0f10, 0xf300, 0x0110, A1, VEOR), - - ARMv7_OP4(0xffb0, 0x0010, 0xefb0, 0x0000, T1, VEXT), - ARMv7_OP4(0xffb0, 0x0010, 0xf2b0, 0x0000, A1, VEXT), - - ARMv7_OP4(0xef80, 0x0b10, 0xef00, 0x0000, T1, VHADDSUB), - ARMv7_OP4(0xfe80, 0x0b10, 0xf200, 0x0000, A1, VHADDSUB), - - ARMv7_OP4(0xffb0, 0x0000, 0xf920, 0x0000, T1, VLD__MS), // VLD1, VLD2, VLD3, VLD4 - ARMv7_OP4(0xffb0, 0x0000, 0xf420, 0x0000, A1, VLD__MS), - - ARMv7_OP4(0xffb0, 0x0f00, 0xf9a0, 0x0c00, T1, VLD1_SAL), - ARMv7_OP4(0xffb0, 0x0f00, 0xf4a0, 0x0c00, A1, VLD1_SAL), - - ARMv7_OP4(0xffb0, 0x0300, 0xf9a0, 0x0000, T1, VLD1_SL), - ARMv7_OP4(0xffb0, 0x0300, 0xf4a0, 0x0000, A1, VLD1_SL), - - ARMv7_OP4(0xffb0, 0x0f00, 0xf9a0, 0x0d00, T1, VLD2_SAL), - ARMv7_OP4(0xffb0, 0x0f00, 0xf4a0, 0x0d00, A1, VLD2_SAL), - - ARMv7_OP4(0xffb0, 0x0300, 0xf9a0, 0x0100, T1, VLD2_SL), - ARMv7_OP4(0xffb0, 0x0300, 0xf4a0, 0x0100, A1, VLD2_SL), - - ARMv7_OP4(0xffb0, 0x0f00, 0xf9a0, 0x0e00, T1, VLD3_SAL), - ARMv7_OP4(0xffb0, 0x0f00, 0xf4a0, 0x0e00, A1, VLD3_SAL), - - ARMv7_OP4(0xffb0, 0x0300, 0xf9a0, 0x0200, T1, VLD3_SL), - ARMv7_OP4(0xffb0, 0x0300, 0xf4a0, 0x0200, A1, VLD3_SL), - - ARMv7_OP4(0xffb0, 0x0f00, 0xf9a0, 0x0f00, T1, VLD4_SAL), - ARMv7_OP4(0xffb0, 0x0f00, 0xf4a0, 0x0f00, A1, VLD4_SAL), - - ARMv7_OP4(0xffb0, 0x0300, 0xf9a0, 0x0300, T1, VLD4_SL), - ARMv7_OP4(0xffb0, 0x0300, 0xf4a0, 0x0300, A1, VLD4_SL), - - ARMv7_OP4(0xfe10, 0x0f00, 0xec10, 0x0b00, T1, VLDM), - ARMv7_OP4(0x0e10, 0x0f00, 0x0c10, 0x0b00, A1, VLDM), - ARMv7_OP4(0xfe10, 0x0f00, 0xec10, 0x0a00, T2, VLDM), - ARMv7_OP4(0x0e10, 0x0f00, 0x0c10, 0x0a00, A2, VLDM), - - ARMv7_OP4(0xff30, 0x0f00, 0xed10, 0x0b00, T1, VLDR), - ARMv7_OP4(0x0f30, 0x0f00, 0x0d10, 0x0b00, A1, VLDR), - ARMv7_OP4(0xff30, 0x0f00, 0xed10, 0x0a00, T2, VLDR), - ARMv7_OP4(0x0f30, 0x0f00, 0x0d10, 0x0a00, A2, VLDR), - - ARMv7_OP4(0xef80, 0x0f00, 0xef00, 0x0600, T1, VMAXMIN), - ARMv7_OP4(0xfe80, 0x0f00, 0xf200, 0x0600, A1, VMAXMIN), - - ARMv7_OP4(0xff80, 0x0f10, 0xef00, 0x0f00, T1, VMAXMIN_FP), - ARMv7_OP4(0xff80, 0x0f10, 0xf200, 0x0f00, A1, VMAXMIN_FP), - - ARMv7_OP4(0xef80, 0x0f10, 0xef00, 0x0900, T1, VML__), - ARMv7_OP4(0xfe80, 0x0f10, 0xf200, 0x0900, A1, VML__), - ARMv7_OP4(0xef80, 0x0d50, 0xef80, 0x0800, T2, VML__), - ARMv7_OP4(0xfe80, 0x0d50, 0xf280, 0x0800, A2, VML__), - - ARMv7_OP4(0xff80, 0x0f10, 0xef00, 0x0d10, T1, VML__FP), - ARMv7_OP4(0xff80, 0x0f10, 0xf200, 0x0d10, A1, VML__FP), - ARMv7_OP4(0xffb0, 0x0e10, 0xee00, 0x0a00, T2, VML__FP), - ARMv7_OP4(0x0fb0, 0x0e10, 0x0e00, 0x0a00, A2, VML__FP), - - ARMv7_OP4(0xef80, 0x0a50, 0xef80, 0x0040, T1, VML__S), - ARMv7_OP4(0xfe80, 0x0a50, 0xf280, 0x0040, A1, VML__S), - ARMv7_OP4(0xef80, 0x0b50, 0xef80, 0x0240, T2, VML__S), - ARMv7_OP4(0xfe80, 0x0b50, 0xf280, 0x0240, A2, VML__S), - - ARMv7_OP4(0xefb8, 0x0090, 0xef80, 0x0010, T1, VMOV_IMM), - ARMv7_OP4(0xfeb8, 0x0090, 0xf280, 0x0010, A1, VMOV_IMM), - ARMv7_OP4(0xffb0, 0x0ef0, 0xeeb0, 0x0a00, T2, VMOV_IMM), - ARMv7_OP4(0x0fb0, 0x0ef0, 0x0eb0, 0x0a00, A2, VMOV_IMM), - - ARMv7_OP4(0xffb0, 0x0f10, 0xef20, 0x0110, T1, VMOV_REG), - ARMv7_OP4(0xffb0, 0x0f10, 0xf220, 0x0110, A1, VMOV_REG), - ARMv7_OP4(0xffbf, 0x0ed0, 0xeeb0, 0x0a40, T2, VMOV_REG), - ARMv7_OP4(0x0fbf, 0x0ed0, 0x0eb0, 0x0a40, A2, VMOV_REG), - - ARMv7_OP4(0xff90, 0x0f1f, 0xee00, 0x0b10, T1, VMOV_RS), - ARMv7_OP4(0x0f90, 0x0f1f, 0x0e00, 0x0b10, A1, VMOV_RS), - - ARMv7_OP4(0xff10, 0x0f1f, 0xee10, 0x0b10, T1, VMOV_SR), - ARMv7_OP4(0x0f10, 0x0f1f, 0x0e10, 0x0b10, A1, VMOV_SR), - - ARMv7_OP4(0xffe0, 0x0f7f, 0xee00, 0x0a10, T1, VMOV_RF), - ARMv7_OP4(0x0fe0, 0x0f7f, 0x0e00, 0x0a10, A1, VMOV_RF), - - ARMv7_OP4(0xffe0, 0x0fd0, 0xec40, 0x0a10, T1, VMOV_2RF), - ARMv7_OP4(0x0fe0, 0x0fd0, 0x0c40, 0x0a10, A1, VMOV_2RF), - - ARMv7_OP4(0xffe0, 0x0fd0, 0xec40, 0x0b10, T1, VMOV_2RD), - ARMv7_OP4(0x0fe0, 0x0fd0, 0x0c40, 0x0b10, A1, VMOV_2RD), - - ARMv7_OP4(0xef87, 0x0fd0, 0xef80, 0x0a10, T1, VMOVL), - ARMv7_OP4(0xfe87, 0x0fd0, 0xf280, 0x0a10, A1, VMOVL), - - ARMv7_OP4(0xffb3, 0x0fd0, 0xffb2, 0x0200, T1, VMOVN), - ARMv7_OP4(0xffb3, 0x0fd0, 0xf3b2, 0x0200, A1, VMOVN), - - ARMv7_OP4(0xffff, 0x0fff, 0xeef1, 0x0a10, T1, VMRS), - ARMv7_OP4(0x0fff, 0x0fff, 0x0ef1, 0x0a10, A1, VMRS), - - ARMv7_OP4(0xffff, 0x0fff, 0xeee1, 0x0a10, T1, VMSR), - ARMv7_OP4(0x0fff, 0x0fff, 0x0ee1, 0x0a10, A1, VMSR), - - ARMv7_OP4(0xef80, 0x0f10, 0xef00, 0x0910, T1, VMUL_), - ARMv7_OP4(0xfe80, 0x0f10, 0xf200, 0x0910, A1, VMUL_), - ARMv7_OP4(0xef80, 0x0d50, 0xef80, 0x0c00, T2, VMUL_), - ARMv7_OP4(0xfe80, 0x0d50, 0xf280, 0x0c00, A2, VMUL_), - - ARMv7_OP4(0xffa0, 0x0f10, 0xff00, 0x0d10, T1, VMUL_FP), - ARMv7_OP4(0xffa0, 0x0f10, 0xf300, 0x0d10, A1, VMUL_FP), - ARMv7_OP4(0xffb0, 0x0e50, 0xee20, 0x0a00, T2, VMUL_FP), - ARMv7_OP4(0x0fb0, 0x0e50, 0x0e20, 0x0a00, A2, VMUL_FP), - - ARMv7_OP4(0xef80, 0x0e50, 0xef80, 0x0840, T1, VMUL_S), - ARMv7_OP4(0xfe80, 0x0e50, 0xf280, 0x0840, A1, VMUL_S), - ARMv7_OP4(0xef80, 0x0f50, 0xef80, 0x0a40, T2, VMUL_S), - ARMv7_OP4(0xfe80, 0x0f50, 0xf280, 0x0a40, A2, VMUL_S), - - ARMv7_OP4(0xefb8, 0x00b0, 0xef80, 0x0030, T1, VMVN_IMM), - ARMv7_OP4(0xfeb8, 0x00b0, 0xf280, 0x0030, A1, VMVN_IMM), - - ARMv7_OP4(0xffb3, 0x0f90, 0xffb0, 0x0580, T1, VMVN_REG), - ARMv7_OP4(0xffb3, 0x0f90, 0xf3b0, 0x0580, A1, VMVN_REG), - - ARMv7_OP4(0xffb3, 0x0b90, 0xffb1, 0x0380, T1, VNEG), - ARMv7_OP4(0xffb3, 0x0b90, 0xf3b1, 0x0380, A1, VNEG), - ARMv7_OP4(0xffbf, 0x0ed0, 0xeeb1, 0x0a40, T2, VNEG), - ARMv7_OP4(0x0fbf, 0x0ed0, 0x0eb1, 0x0a40, A2, VNEG), - - ARMv7_OP4(0xffb0, 0x0e10, 0xee10, 0x0a00, T1, VNM__), - ARMv7_OP4(0x0fb0, 0x0e10, 0x0e10, 0x0a00, A1, VNM__), - ARMv7_OP4(0xffb0, 0x0e50, 0xee20, 0x0a40, T2, VNM__), - ARMv7_OP4(0x0fb0, 0x0e50, 0x0e20, 0x0a40, A2, VNM__), - - ARMv7_OP4(0xffb0, 0x0f10, 0xef30, 0x0110, T1, VORN_REG), - ARMv7_OP4(0xffb0, 0x0f10, 0xf230, 0x0110, A1, VORN_REG), - - ARMv7_OP4(0xefb8, 0x00b0, 0xef80, 0x0010, T1, VORR_IMM), - ARMv7_OP4(0xfeb8, 0x00b0, 0xf280, 0x0010, A1, VORR_IMM), - - ARMv7_OP4(0xffb0, 0x0f10, 0xef20, 0x0110, T1, VORR_REG), - ARMv7_OP4(0xffb0, 0x0f10, 0xf220, 0x0110, A1, VORR_REG), - - ARMv7_OP4(0xffb3, 0x0f10, 0xffb0, 0x0600, T1, VPADAL), - ARMv7_OP4(0xffb3, 0x0f10, 0xf3b0, 0x0600, A1, VPADAL), - - ARMv7_OP4(0xff80, 0x0f10, 0xef00, 0x0b10, T1, VPADD), - ARMv7_OP4(0xff80, 0x0f10, 0xf200, 0x0b10, A1, VPADD), - - ARMv7_OP4(0xffa0, 0x0f10, 0xff00, 0x0d00, T1, VPADD_FP), - ARMv7_OP4(0xffa0, 0x0f10, 0xf300, 0x0d00, A1, VPADD_FP), - - ARMv7_OP4(0xffb3, 0x0f10, 0xffb0, 0x0200, T1, VPADDL), - ARMv7_OP4(0xffb3, 0x0f10, 0xf3b0, 0x0200, A1, VPADDL), - - ARMv7_OP4(0xef80, 0x0f00, 0xef00, 0x0a00, T1, VPMAXMIN), - ARMv7_OP4(0xfe80, 0x0f00, 0xf200, 0x0a00, A1, VPMAXMIN), - - ARMv7_OP4(0xff80, 0x0f10, 0xff00, 0x0f00, T1, VPMAXMIN_FP), - ARMv7_OP4(0xff80, 0x0f10, 0xf300, 0x0f00, A1, VPMAXMIN_FP), - - ARMv7_OP4(0xffbf, 0x0f00, 0xecbd, 0x0b00, T1, VPOP), - ARMv7_OP4(0x0fbf, 0x0f00, 0x0cbd, 0x0b00, A1, VPOP), - ARMv7_OP4(0xffbf, 0x0f00, 0xecbd, 0x0a00, T2, VPOP), - ARMv7_OP4(0x0fbf, 0x0f00, 0x0cbd, 0x0a00, A2, VPOP), - - ARMv7_OP4(0xffbf, 0x0f00, 0xed2d, 0x0b00, T1, VPUSH), - ARMv7_OP4(0x0fbf, 0x0f00, 0x0d2d, 0x0b00, A1, VPUSH), - ARMv7_OP4(0xffbf, 0x0f00, 0xed2d, 0x0a00, T2, VPUSH), - ARMv7_OP4(0x0fbf, 0x0f00, 0x0d2d, 0x0a00, A2, VPUSH), - - // TODO: VQ* instructions - - ARMv7_OP4(0xff80, 0x0f50, 0xff80, 0x0400, T1, VRADDHN), - ARMv7_OP4(0xff80, 0x0f50, 0xf380, 0x0400, A1, VRADDHN), - - ARMv7_OP4(0xffb3, 0x0e90, 0xffb3, 0x0400, T1, VRECPE), - ARMv7_OP4(0xffb3, 0x0e90, 0xf3b3, 0x0400, A1, VRECPE), - - ARMv7_OP4(0xffa0, 0x0f10, 0xef00, 0x0f10, T1, VRECPS), - ARMv7_OP4(0xffa0, 0x0f10, 0xf200, 0x0f10, A1, VRECPS), - - ARMv7_OP4(0xffb3, 0x0e10, 0xffb0, 0x0000, T1, VREV__), - ARMv7_OP4(0xffb3, 0x0e10, 0xf3b0, 0x0000, A1, VREV__), - - ARMv7_OP4(0xef80, 0x0f10, 0xef00, 0x0100, T1, VRHADD), - ARMv7_OP4(0xfe80, 0x0f10, 0xf200, 0x0100, A1, VRHADD), - - ARMv7_OP4(0xef80, 0x0f10, 0xef00, 0x0500, T1, VRSHL), - ARMv7_OP4(0xfe80, 0x0f10, 0xf200, 0x0500, A1, VRSHL), - - ARMv7_OP4(0xef80, 0x0f10, 0xef80, 0x0210, T1, VRSHR), - ARMv7_OP4(0xfe80, 0x0f10, 0xf280, 0x0210, A1, VRSHR), - - ARMv7_OP4(0xff80, 0x0fd0, 0xef80, 0x0850, T1, VRSHRN), - ARMv7_OP4(0xff80, 0x0fd0, 0xf280, 0x0850, A1, VRSHRN), - - ARMv7_OP4(0xffb3, 0x0e90, 0xffb3, 0x0480, T1, VRSQRTE), - ARMv7_OP4(0xffb3, 0x0e90, 0xf3b3, 0x0480, A1, VRSQRTE), - - ARMv7_OP4(0xffa0, 0x0f10, 0xef20, 0x0f10, T1, VRSQRTS), - ARMv7_OP4(0xffa0, 0x0f10, 0xf220, 0x0f10, A1, VRSQRTS), - - ARMv7_OP4(0xef80, 0x0f10, 0xef80, 0x0310, T1, VRSRA), - ARMv7_OP4(0xfe80, 0x0f10, 0xf280, 0x0310, A1, VRSRA), - - ARMv7_OP4(0xff80, 0x0f50, 0xff80, 0x0600, T1, VRSUBHN), - ARMv7_OP4(0xff80, 0x0f50, 0xf380, 0x0600, A1, VRSUBHN), - - ARMv7_OP4(0xff80, 0x0f10, 0xef80, 0x0510, T1, VSHL_IMM), - ARMv7_OP4(0xff80, 0x0f10, 0xf280, 0x0510, A1, VSHL_IMM), - - ARMv7_OP4(0xef80, 0x0f10, 0xef00, 0x0400, T1, VSHL_REG), - ARMv7_OP4(0xfe80, 0x0f10, 0xf200, 0x0400, A1, VSHL_REG), - - ARMv7_OP4(0xef80, 0x0fd0, 0xef80, 0x0a10, T1, VSHLL), - ARMv7_OP4(0xfe80, 0x0fd0, 0xf280, 0x0a10, A1, VSHLL), - ARMv7_OP4(0xffb3, 0x0fd0, 0xffb2, 0x0300, T2, VSHLL), - ARMv7_OP4(0xffb3, 0x0fd0, 0xf3b2, 0x0300, A2, VSHLL), - - ARMv7_OP4(0xef80, 0x0f10, 0xef80, 0x0010, T1, VSHR), - ARMv7_OP4(0xfe80, 0x0f10, 0xf280, 0x0010, A1, VSHR), - - ARMv7_OP4(0xff80, 0x0fd0, 0xef80, 0x0810, T1, VSHRN), - ARMv7_OP4(0xff80, 0x0fd0, 0xf280, 0x0810, A1, VSHRN), - - ARMv7_OP4(0xff80, 0x0f10, 0xff80, 0x0510, T1, VSLI), - ARMv7_OP4(0xff80, 0x0f10, 0xf380, 0x0510, A1, VSLI), - - ARMv7_OP4(0xffbf, 0x0ed0, 0xeeb1, 0x0ac0, T1, VSQRT), - ARMv7_OP4(0x0fbf, 0x0ed0, 0x0eb1, 0x0ac0, A1, VSQRT), - - ARMv7_OP4(0xef80, 0x0f10, 0xef80, 0x0110, T1, VSRA), - ARMv7_OP4(0xfe80, 0x0f10, 0xf280, 0x0110, A1, VSRA), - - ARMv7_OP4(0xff80, 0x0f10, 0xff80, 0x0410, T1, VSRI), - ARMv7_OP4(0xff80, 0x0f10, 0xf380, 0x0410, A1, VSRI), - - ARMv7_OP4(0xffb0, 0x0000, 0xf900, 0x0000, T1, VST__MS), // VST1, VST2, VST3, VST4 - ARMv7_OP4(0xffb0, 0x0000, 0xf400, 0x0000, A1, VST__MS), - - ARMv7_OP4(0xffb0, 0x0300, 0xf980, 0x0000, T1, VST1_SL), - ARMv7_OP4(0xffb0, 0x0300, 0xf480, 0x0000, A1, VST1_SL), - - ARMv7_OP4(0xffb0, 0x0300, 0xf980, 0x0100, T1, VST2_SL), - ARMv7_OP4(0xffb0, 0x0300, 0xf480, 0x0100, A1, VST2_SL), - - ARMv7_OP4(0xffb0, 0x0300, 0xf980, 0x0200, T1, VST3_SL), - ARMv7_OP4(0xffb0, 0x0300, 0xf480, 0x0200, A1, VST3_SL), - - ARMv7_OP4(0xffb0, 0x0300, 0xf980, 0x0300, T1, VST4_SL), - ARMv7_OP4(0xffb0, 0x0300, 0xf480, 0x0300, A1, VST4_SL), - - ARMv7_OP4(0xfe10, 0x0f00, 0xec00, 0x0b00, T1, VSTM), - ARMv7_OP4(0x0e10, 0x0f00, 0x0c00, 0x0b00, A1, VSTM), - ARMv7_OP4(0xfe10, 0x0f00, 0xec00, 0x0a00, T2, VSTM), - ARMv7_OP4(0x0e10, 0x0f00, 0x0c00, 0x0a00, A2, VSTM), - - ARMv7_OP4(0xff30, 0x0f00, 0xed00, 0x0b00, T1, VSTR), - ARMv7_OP4(0x0f30, 0x0f00, 0x0d00, 0x0b00, A1, VSTR), - ARMv7_OP4(0xff30, 0x0f00, 0xed00, 0x0a00, T2, VSTR), - ARMv7_OP4(0x0f30, 0x0f00, 0x0d00, 0x0a00, A2, VSTR), - - ARMv7_OP4(0xff80, 0x0f10, 0xff00, 0x0800, T1, VSUB), - ARMv7_OP4(0xff80, 0x0f10, 0xf300, 0x0800, A1, VSUB), - - ARMv7_OP4(0xffa0, 0x0f10, 0xef20, 0x0d00, T1, VSUB_FP), - ARMv7_OP4(0xffa0, 0x0f10, 0xf220, 0x0d00, A1, VSUB_FP), - ARMv7_OP4(0xffb0, 0x0e50, 0xee30, 0x0a40, T2, VSUB_FP), - ARMv7_OP4(0x0fb0, 0x0e50, 0x0e30, 0x0a40, A2, VSUB_FP), - - ARMv7_OP4(0xff80, 0x0f50, 0xef80, 0x0600, T1, VSUBHN), - ARMv7_OP4(0xff80, 0x0f50, 0xf280, 0x0600, A1, VSUBHN), - - ARMv7_OP4(0xef80, 0x0e50, 0xef80, 0x0200, T1, VSUB_), - ARMv7_OP4(0xfe80, 0x0e50, 0xf280, 0x0200, A1, VSUB_), - - ARMv7_OP4(0xffb3, 0x0f90, 0xffb2, 0x0000, T1, VSWP), - ARMv7_OP4(0xffb3, 0x0f90, 0xf3b2, 0x0000, A1, VSWP), - - ARMv7_OP4(0xffb0, 0x0c10, 0xffb0, 0x0800, T1, VTB_), - ARMv7_OP4(0xffb0, 0x0c10, 0xf3b0, 0x0800, A1, VTB_), - - ARMv7_OP4(0xffb3, 0x0f90, 0xffb2, 0x0080, T1, VTRN), - ARMv7_OP4(0xffb3, 0x0f90, 0xf3b2, 0x0080, A1, VTRN), - - ARMv7_OP4(0xff80, 0x0f10, 0xef00, 0x0810, T1, VTST), - ARMv7_OP4(0xff80, 0x0f10, 0xf200, 0x0810, A1, VTST), - - ARMv7_OP4(0xffb3, 0x0f90, 0xffb2, 0x0100, T1, VUZP), - ARMv7_OP4(0xffb3, 0x0f90, 0xf3b2, 0x0100, A1, VUZP), - - ARMv7_OP4(0xffb3, 0x0f90, 0xffb2, 0x0180, T1, VZIP), - ARMv7_OP4(0xffb3, 0x0f90, 0xf3b2, 0x0180, A1, VZIP), - - ARMv7_OP2(0xffff, 0xbf20, T1, WFE), - ARMv7_OP4(0xffff, 0xffff, 0xf3af, 0x8002, T2, WFE), - ARMv7_OP4(0x0fff, 0xffff, 0x0320, 0xf002, A1, WFE), - ARMv7_OP2(0xffff, 0xbf30, T1, WFI), - ARMv7_OP4(0xffff, 0xffff, 0xf3af, 0x8003, T2, WFI), - ARMv7_OP4(0x0fff, 0xffff, 0x0320, 0xf003, A1, WFI), - ARMv7_OP2(0xffff, 0xbf10, T1, YIELD), - ARMv7_OP4(0xffff, 0xffff, 0xf3af, 0x8001, T2, YIELD), - ARMv7_OP4(0x0fff, 0xffff, 0x0320, 0xf001, A1, YIELD), -}; - -#undef ARMv7_OP2 -#undef ARMv7_OP4 -#undef SKIP_IF -#undef BF -#undef BT - -struct ARMv7_op2_table_t -{ - const ARMv7_opcode_t* data[0x10000]; - u32 null_ops; - - ARMv7_op2_table_t() - { - std::vector t2; - - for (auto& opcode : ARMv7_opcode_table) - { - if (opcode.length == 2) - { - if (opcode.code & ~opcode.mask) - { - LOG_ERROR(ARMv7, "%s: wrong opcode mask (mask=0x%04x, code=0x%04x)", opcode.name, opcode.mask >> 16, opcode.code >> 16); - } - - t2.push_back(&opcode); - } - } - - null_ops = 0x10000; - - for (u32 i = 0; i < 0x10000; i++) - { - data[i] = nullptr; - - for (auto& opcode : t2) - { - if (((i << 16) & opcode->mask) == opcode->code && (!opcode->skip || !opcode->skip(i))) - { - data[i] = opcode; - null_ops--; - break; - } - } - } - } - -} g_op2t; - -struct ARMv7_op4t_table_t -{ - std::vector table; - - ARMv7_op4t_table_t() - { - for (auto& opcode : ARMv7_opcode_table) - { - if (opcode.length == 4 && opcode.type < A1) - { - if (opcode.code & ~opcode.mask) - { - LOG_ERROR(ARMv7, "%s: wrong opcode mask (mask=0x%04x 0x%04x, code=0x%04x 0x%04x)", opcode.name, opcode.mask >> 16, (u16)opcode.mask, opcode.code >> 16, (u16)opcode.code); - } - - table.push_back(&opcode); - } - } - } - - const ARMv7_opcode_t* HACK() - { - for (auto& opcode : table) - { - if (opcode->func == ARMv7_instrs::HACK) - { - return opcode; - } - } - - throw EXCEPTION("HACK instruction not found"); - } - -} g_op4t; - -struct ARMv7_op4arm_table_t -{ - std::vector table; - - ARMv7_op4arm_table_t() - { - for (auto& opcode : ARMv7_opcode_table) - { - if (opcode.type >= A1) - { - if (opcode.code & ~opcode.mask) - { - LOG_ERROR(ARMv7, "%s: wrong opcode mask (mask=0x%08x, code=0x%08x)", opcode.name, opcode.mask, opcode.code); - } - - table.push_back(&opcode); - } - } - } - -} g_op4arm; - -std::unordered_map g_opct; - -void armv7_decoder_initialize(u32 addr, u32 end_addr, bool dump) -{ - // 1. Find every 4-byte Thumb instruction and cache it - // 2. If some instruction is not recognized, print the error - // 3. Possibly print disasm - - //g_opct.clear(); - //g_opct.reserve(end_addr - addr); - - const auto hack = g_op4t.HACK(); - - while (addr < end_addr) - { - ARMv7Code code = {}; - code.code0 = vm::psv::read16(addr); - - auto found = g_op2t.data[code.code0]; - - if (!found) - { - code.code1 = code.code0; - code.code0 = vm::psv::read16(addr + 2); - - auto op = g_opct.find(code.data); - if (op != g_opct.end()) - { - found = op->second; - } - } - - if (!found) - { - for (auto opcode : g_op4t.table) - { - if ((code.data & opcode->mask) == opcode->code && (!opcode->skip || !opcode->skip(code.data))) - { - g_opct[code.data] = (found = opcode); - break; - } - } - } - - if (!found) - { - LOG_ERROR(ARMv7, "Unknown instruction found at address 0x%08x: %04x %04x", addr, code.code1, code.code0); - addr += 4; - continue; - } - - // Proceed with found: - - if (dump) - { - if (found->length == 2) - { - LOG_NOTICE(ARMv7, "0x%08x: %04x %s", addr, code.code0, found->name); - } - else - { - LOG_NOTICE(ARMv7, "0x%08x: %04x %04x %s", addr, code.code1, code.code0, found->name); - } - } - - if (found->func == ARMv7_instrs::BLX && found->type == T2) - { - const u32 s = (code.data >> 26) & 0x1; - const u32 i1 = (code.data >> 13) & 0x1 ^ s ^ 1; - const u32 i2 = (code.data >> 11) & 0x1 ^ s ^ 1; - const u32 target = (addr + 4 & ~3) + sign<25, u32>(s << 24 | i2 << 23 | i1 << 22 | (code.data & 0x3ff0000) >> 4 | (code.data & 0x7ff) << 1); - - const u32 instr = vm::check_addr(target, 4) ? vm::psv::read32(target).value() : 0; - - // possibly a call to imported function: - if (target >= end_addr && ((target - end_addr) % 16) == 0 && (instr & 0xfff000f0) == 0xe0700090) - { - // replace BLX with "HACK" instruction directly (in Thumb form), it can help to see where it was called from - const u32 index = (instr & 0xfff00) >> 4 | (instr & 0xf); - vm::psv::write32(addr, 0xf870 | index << 16); - g_opct[0xf8700000 | index] = hack; - } - else - { - LOG_ERROR(ARMv7, "Unrecognized BLX call found at adddress 0x%08x (target=0x%08x)", addr, target); - } - } - - //if (found->func == ARMv7_instrs::IT) - //{ - // LOG_ERROR(ARMv7, "IT instruction found at address 0x%08x", addr); - //} - - addr += found->length; - } - - LOG_NOTICE(ARMv7, "armv7_decoder_initialize() finished, g_opct.size() = %lld, g_op2t.null_ops=0x%x", (u64)g_opct.size(), g_op2t.null_ops); -} - -u32 ARMv7Decoder::DecodeMemory(const u32 address) -{ - ARMv7Code code = {}; - - if (m_ctx.ISET == Thumb) - { - code.code0 = vm::psv::read16(address); - - if (auto opcode = g_op2t.data[code.code0]) - { - (*opcode->func)(m_ctx, code, opcode->type); - return 2; - } - - code.code1 = code.code0; - code.code0 = vm::psv::read16(address + 2); - - auto op = g_opct.find(code.data); - if (op != g_opct.end()) - { - (*op->second->func)(m_ctx, code, op->second->type); - return 4; - } - - //for (auto opcode : g_op4t.table) - //{ - // if ((code.data & opcode->mask) == opcode->code && (!opcode->skip || !opcode->skip(code.data))) - // { - // (*opcode->func)(m_ctx, code, opcode->type); - // return 4; - // } - //} - } - else if (m_ctx.ISET == ARM) - { - code.data = vm::psv::read32(address); - - for (auto opcode : g_op4arm.table) - { - if ((code.data & opcode->mask) == opcode->code && (!opcode->skip || !opcode->skip(code.data))) - { - (*opcode->func)(m_ctx, code, opcode->type); - return 4; - } - } - } - else - { - throw EXCEPTION("Invalid instruction set"); - } - - ARMv7_instrs::UNK(m_ctx, code); - return 4; - - // "group" decoding algorithm (temporarily disabled) - - //execute_main_group(&m_thr); - //// LOG_NOTICE(ARMv7, "%s, %d \n\n", m_thr.m_last_instr_name, m_thr.m_last_instr_size); - //m_thr.m_last_instr_name = "Unknown"; - //return m_thr.m_last_instr_size; -} diff --git a/rpcs3/Emu/ARMv7/ARMv7Decoder.h b/rpcs3/Emu/ARMv7/ARMv7Decoder.h deleted file mode 100644 index 229f74014b..0000000000 --- a/rpcs3/Emu/ARMv7/ARMv7Decoder.h +++ /dev/null @@ -1,18 +0,0 @@ -#pragma once -#include "Emu/CPU/CPUDecoder.h" - -struct ARMv7Context; - -class ARMv7Decoder : public CPUDecoder -{ - ARMv7Context& m_ctx; - -public: - ARMv7Decoder(ARMv7Context& context) : m_ctx(context) - { - } - - virtual u32 DecodeMemory(const u32 address); -}; - -void armv7_decoder_initialize(u32 addr, u32 end_addr, bool dump = false); diff --git a/rpcs3/Emu/ARMv7/ARMv7DisAsm.cpp b/rpcs3/Emu/ARMv7/ARMv7DisAsm.cpp index a9524d664b..f7cd9178cd 100644 --- a/rpcs3/Emu/ARMv7/ARMv7DisAsm.cpp +++ b/rpcs3/Emu/ARMv7/ARMv7DisAsm.cpp @@ -1,1123 +1,3758 @@ #include "stdafx.h" -#if 0 +#include "ARMv7Opcodes.h" #include "ARMv7DisAsm.h" -void ARMv7DisAsm::UNK(const u32 data) +using namespace arm_code::arm_encoding_alias; + +const arm_decoder s_arm_disasm; + +template +static const char* fmt_encoding() { - Write("Unknown/illegal opcode"); + switch (type) + { + case T1: return "T1"; + case T2: return "T2"; + case T3: return "T3"; + case T4: return "T4"; + case A1: return "A1"; + case A2: return "A2"; + } + + return nullptr; } -void ARMv7DisAsm::NULL_OP(const u32 data, const ARMv7_encoding type) +static const char* fmt_cond(u32 cond) { - Write("Illegal opcode (null)"); + switch (cond) + { + case 0: return "eq"; + case 1: return "ne"; + case 2: return "cs"; + case 3: return "cc"; + case 4: return "mi"; + case 5: return "pl"; + case 6: return "vs"; + case 7: return "vc"; + case 8: return "hi"; + case 9: return "ls"; + case 10: return "ge"; + case 11: return "lt"; + case 12: return "gt"; + case 13: return "le"; + case 14: return "al"; + case 15: return ""; + default: return "??"; + } } -void ARMv7DisAsm::HACK(const u32 data, const ARMv7_encoding type) +static const char* fmt_it(u32 state) { - Write(__FUNCTION__); + switch (state & ~0x10) + { + case 0x8: return ""; + + case 0x4: return state & 0x10 ? "e" : "t"; + case 0xc: return state & 0x10 ? "t" : "e"; + + case 0x2: return state & 0x10 ? "ee" : "tt"; + case 0x6: return state & 0x10 ? "et" : "te"; + case 0xa: return state & 0x10 ? "te" : "et"; + case 0xe: return state & 0x10 ? "tt" : "ee"; + + case 0x1: return state & 0x10 ? "eee" : "ttt"; + case 0x3: return state & 0x10 ? "eet" : "tte"; + case 0x5: return state & 0x10 ? "ete" : "tet"; + case 0x7: return state & 0x10 ? "ett" : "tee"; + case 0x9: return state & 0x10 ? "tee" : "ett"; + case 0xb: return state & 0x10 ? "tet" : "ete"; + case 0xd: return state & 0x10 ? "tte" : "eet"; + case 0xf: return state & 0x10 ? "ttt" : "eee"; + + default: return "???"; + } } -void ARMv7DisAsm::ADC_IMM(const u32 data, const ARMv7_encoding type) +static const char* fmt_reg(u32 reg) { - Write(__FUNCTION__); + switch (reg) + { + case 0: return "r0"; + case 1: return "r1"; + case 2: return "r2"; + case 3: return "r3"; + case 4: return "r4"; + case 5: return "r5"; + case 6: return "r6"; + case 7: return "r7"; + case 8: return "r8"; + case 9: return "r9"; + case 10: return "r10"; + case 11: return "r11"; + case 12: return "r12"; + case 13: return "sp"; + case 14: return "lr"; + case 15: return "pc"; + default: return "r???"; + } } -void ARMv7DisAsm::ADC_REG(const u32 data, const ARMv7_encoding type) +static std::string fmt_shift(u32 type, u32 amount) { - Write(__FUNCTION__); + Expects(type != arm_code::SRType_RRX || amount == 1); + Expects(amount <= 32); + + if (amount) + { + switch (type) + { + case arm_code::SRType_LSL: return ",lsl #" + fmt::to_udec(amount); + case arm_code::SRType_LSR: return ",lsr #" + fmt::to_udec(amount); + case arm_code::SRType_ASR: return ",asr #" + fmt::to_udec(amount); + case arm_code::SRType_ROR: return ",ror #" + fmt::to_udec(amount); + case arm_code::SRType_RRX: return ",rrx"; + default: return ",?????"; + } + } + + return{}; } -void ARMv7DisAsm::ADC_RSR(const u32 data, const ARMv7_encoding type) +static std::string fmt_reg_list(u32 reg_list) { - Write(__FUNCTION__); + std::vector> lines; + + for (u32 i = 0; i < 13; i++) + { + if (reg_list & (1 << i)) + { + if (lines.size() && lines.rbegin()->second == i - 1) + { + lines.rbegin()->second = i; + } + else + { + lines.push_back({ i, i }); + } + } + } + + if (reg_list & 0x2000) lines.push_back({ 13, 13 }); // sp + if (reg_list & 0x4000) lines.push_back({ 14, 14 }); // lr + if (reg_list & 0x8000) lines.push_back({ 15, 15 }); // pc + + std::string result; + + if (reg_list >> 16) result = "???"; // invalid bits + + for (auto& line : lines) + { + if (!result.empty()) + { + result += ","; + } + + if (line.first == line.second) + { + result += fmt_reg(line.first); + } + else + { + result += fmt_reg(line.first); + result += '-'; + result += fmt_reg(line.second); + } + } + + return result; +} + +static std::string fmt_mem_imm(u32 reg, u32 imm, u32 index, u32 add, u32 wback) +{ + if (index) + { + return fmt::format("[%s,#%s0x%X]%s", fmt_reg(reg), add ? "" : "-", imm, wback ? "!" : ""); + } + else + { + return fmt::format("[%s],#%s0x%X%s", fmt_reg(reg), add ? "" : "-", imm, wback ? "" : "???"); + } +} + +static std::string fmt_mem_reg(u32 n, u32 m, u32 index, u32 add, u32 wback, u32 shift_t = 0, u32 shift_n = 0) +{ + if (index) + { + return fmt::format("[%s,%s%s%s]%s", fmt_reg(n), add ? "" : "-", fmt_reg(m), fmt_shift(shift_t, shift_n), wback ? "!" : ""); + } + else + { + return fmt::format("[%s],%s%s%s%s", fmt_reg(n), add ? "" : "-", fmt_reg(m), fmt_shift(shift_t, shift_n), wback ? "" : "???"); + } +} + +u32 ARMv7DisAsm::disasm(u32 pc) +{ + const u16 op16 = *(le_t*)(offset + pc); + const u32 cond = -1; // TODO + + if (const auto func16 = s_arm_disasm.decode_thumb(op16)) + { + (this->*func16)(op16, cond); + return 2; + } + else + { + const u32 op32 = (op16 << 16) | *(le_t*)(offset + pc + 2); + (this->*s_arm_disasm.decode_thumb(op32))(op32, cond); + return 4; + } +} + +void ARMv7DisAsm::Write(const std::string& value) +{ + switch (m_mode) + { + case CPUDisAsm_DumpMode: + last_opcode = fmt::format("\t%08x:\t", dump_pc); + break; + + case CPUDisAsm_InterpreterMode: + last_opcode = fmt::format("[%08x] ", dump_pc); + break; + + case CPUDisAsm_CompilerElfMode: + last_opcode = value + "\n"; + return; + } + + const u16 op16 = *(le_t*)(offset + dump_pc); + + // TODO: ARM + if (false) + { + const u32 op_arm = *(le_t*)(offset + dump_pc); + + last_opcode += fmt::format("%08x ", op_arm); + } + else if (arm_op_thumb_is_32(op16)) + { + const u16 op_second = *(le_t*)(offset + dump_pc + 2); + + last_opcode += fmt::format("%04x %04x ", op16, op_second); + } + else + { + last_opcode += fmt::format("%04x ", op16); + } + + auto str = value; + const auto found = str.find_first_of(' '); + if (found < 10) str.insert(str.begin() + found, 10 - found, ' '); + + switch (m_mode) + { + case CPUDisAsm_DumpMode: + last_opcode += fmt::format("\t%s\n", str); + break; + + case CPUDisAsm_InterpreterMode: + last_opcode += fmt::format(": %s", str); + break; + } +} + +#define ARG(arg, ...) const u32 arg = args::arg::extract(__VA_ARGS__); + +void ARMv7DisAsm::UNK(const u32 op, const u32 cond) +{ + // TODO: ARM + if (false) + { + write("Unknown/Illegal opcode: 0x%08X (ARM)", op); + } + else if (op > 0xffff) + { + write("Unknown/Illegal opcode: 0x%04X 0x%04X (Thumb)", op >> 16, op & 0xffff); + } + else + { + write("Unknown/Illegal opcode: 0x%04X (Thumb)", op); + } + +} + +template +void ARMv7DisAsm::HACK(const u32 op, const u32 cond) +{ + using args = arm_code::hack; + ARG(index, op); + + write("hack%s %d", fmt_cond(cond), index); +} + +template +void ARMv7DisAsm::MRC_(const u32 op, const u32 cond) +{ + using args = arm_code::mrc; + ARG(t, op); + ARG(cp, op); + ARG(opc1, op); + ARG(opc2, op); + ARG(cn, op); + ARG(cm, op); + + write("mrc%s p%d,%d,r%d,c%d,c%d,%d", fmt_cond(cond), cp, opc1, t, cn, cm, opc2); } -void ARMv7DisAsm::ADD_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::ADC_IMM(const u32 op, const u32 cond) { - Write(__FUNCTION__); + using args = arm_code::adc_imm; + ARG(d, op); + ARG(n, op); + ARG(imm32, op); + ARG(set_flags, op, cond); + + write("adc%s%s %s,%s,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), imm32); } -void ARMv7DisAsm::ADD_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::ADC_REG(const u32 op, const u32 cond) { - Write(__FUNCTION__); + using args = arm_code::adc_reg; + ARG(d, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); + + write("adc%s%s %s,%s,%s%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), fmt_reg(m), fmt_shift(shift_t, shift_n)); } -void ARMv7DisAsm::ADD_RSR(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::ADC_RSR(const u32 op, const u32 cond) { - Write(__FUNCTION__); -} - -void ARMv7DisAsm::ADD_SPI(const u32 data, const ARMv7_encoding type) -{ - Write(__FUNCTION__); -} - -void ARMv7DisAsm::ADD_SPR(const u32 data, const ARMv7_encoding type) -{ - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::ADR(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::ADD_IMM(const u32 op, const u32 cond) { - Write(__FUNCTION__); + using args = arm_code::add_imm; + ARG(d, op); + ARG(n, op); + ARG(imm32, op); + ARG(set_flags, op, cond); + + write("add%s%s %s,%s,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), imm32); +} + +template +void ARMv7DisAsm::ADD_REG(const u32 op, const u32 cond) +{ + using args = arm_code::add_reg; + ARG(d, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); + + write("add%s%s %s,%s,%s%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), fmt_reg(m), fmt_shift(shift_t, shift_n)); +} + +template +void ARMv7DisAsm::ADD_RSR(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::ADD_SPI(const u32 op, const u32 cond) +{ + using args = arm_code::add_spi; + ARG(d, op); + ARG(imm32, op); + ARG(set_flags, op, cond); + + write("add%s%s %s,sp,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), imm32); +} + +template +void ARMv7DisAsm::ADD_SPR(const u32 op, const u32 cond) +{ + using args = arm_code::add_spr; + ARG(d, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); + + write("add%s%s %s,sp,%s%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(m), fmt_shift(shift_t, shift_n)); } -void ARMv7DisAsm::AND_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::ADR(const u32 op, const u32 cond) { - Write(__FUNCTION__); -} + using args = arm_code::adr; + ARG(d, op); + ARG(i, op); -void ARMv7DisAsm::AND_REG(const u32 data, const ARMv7_encoding type) -{ - Write(__FUNCTION__); -} - -void ARMv7DisAsm::AND_RSR(const u32 data, const ARMv7_encoding type) -{ - Write(__FUNCTION__); + write("adr%s r%d, 0x%08X", fmt_cond(cond), d, (DisAsmBranchTarget(0) & ~3) + i); } -void ARMv7DisAsm::ASR_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::AND_IMM(const u32 op, const u32 cond) { - Write(__FUNCTION__); + using args = arm_code::and_imm; + ARG(d, op); + ARG(n, op); + ARG(imm32, op); + ARG(set_flags, op, cond); + + write("and%s%s %s,%s,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), imm32); } -void ARMv7DisAsm::ASR_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::AND_REG(const u32 op, const u32 cond) { - Write(__FUNCTION__); + using args = arm_code::and_reg; + ARG(d, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); + + write("and%s%s %s,%s,%s%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), fmt_reg(m), fmt_shift(shift_t, shift_n)); +} + +template +void ARMv7DisAsm::AND_RSR(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::B(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::ASR_IMM(const u32 op, const u32 cond) { - Write(__FUNCTION__); - //if ((cond & 0xe) == 0xe) + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::ASR_REG(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::B(const u32 op, const u32 cond) +{ + using args = arm_code::b; + ARG(imm32, op); + + write("b%s 0x%08X", fmt_cond(cond), DisAsmBranchTarget(imm32)); +} + + +template +void ARMv7DisAsm::BFC(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::BFI(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::BIC_IMM(const u32 op, const u32 cond) +{ + using args = arm_code::bic_imm; + ARG(d, op); + ARG(n, op); + ARG(imm32, op); + ARG(set_flags, op, cond); + + write("bic%s%s %s,%s,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), imm32); +} + +template +void ARMv7DisAsm::BIC_REG(const u32 op, const u32 cond) +{ + using args = arm_code::bic_reg; + ARG(d, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); + + write("bic%s%s %s,%s,%s%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), fmt_reg(m), fmt_shift(shift_t, shift_n)); +} + +template +void ARMv7DisAsm::BIC_RSR(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::BKPT(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::BL(const u32 op, const u32 cond) +{ + using args = arm_code::bl; + ARG(imm32, op); + ARG(to_arm); + + write("bl%s%s 0x%08X", (to_arm != 0) != (type >= A1) ? "x" : "", fmt_cond(cond), DisAsmBranchTarget(imm32)); +} + +template +void ARMv7DisAsm::BLX(const u32 op, const u32 cond) +{ + using args = arm_code::blx; + ARG(m, op); + + write("blx%s %s", fmt_cond(cond), fmt_reg(m)); +} + +template +void ARMv7DisAsm::BX(const u32 op, const u32 cond) +{ + using args = arm_code::bx; + ARG(m, op); + + write("bx%s %s", fmt_cond(cond), fmt_reg(m)); +} + + +template +void ARMv7DisAsm::CB_Z(const u32 op, const u32 cond) +{ + using args = arm_code::cb_z; + ARG(n, op); + ARG(imm32, op); + ARG(nonzero, op); + + write("cb%sz 0x%08X", nonzero ? "n" : "", DisAsmBranchTarget(imm32)); +} + + +template +void ARMv7DisAsm::CLZ(const u32 op, const u32 cond) +{ + using args = arm_code::clz; + ARG(d, op); + ARG(m, op); + + write("clz%s %s,%s", fmt_cond(cond), fmt_reg(d), fmt_reg(m)); +} + + +template +void ARMv7DisAsm::CMN_IMM(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::CMN_REG(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::CMN_RSR(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::CMP_IMM(const u32 op, const u32 cond) +{ + using args = arm_code::cmp_imm; + ARG(n, op); + ARG(imm32, op); + + write("cmp%s %s,#0x%X", fmt_cond(cond), fmt_reg(n), imm32); +} + +template +void ARMv7DisAsm::CMP_REG(const u32 op, const u32 cond) +{ + using args = arm_code::cmp_reg; + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + + write("cmp%s %s,%s%s", fmt_cond(cond), fmt_reg(n), fmt_reg(m), fmt_shift(shift_t, shift_n)); +} + +template +void ARMv7DisAsm::CMP_RSR(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::DBG(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::DMB(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::DSB(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::EOR_IMM(const u32 op, const u32 cond) +{ + using args = arm_code::eor_imm; + ARG(d, op); + ARG(n, op); + ARG(imm32, op); + ARG(set_flags, op, cond); + + write("eor%s%s %s,%s,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), imm32); +} + +template +void ARMv7DisAsm::EOR_REG(const u32 op, const u32 cond) +{ + using args = arm_code::eor_reg; + ARG(d, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); + + write("eor%s%s %s,%s,%s%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), fmt_reg(m), fmt_shift(shift_t, shift_n)); +} + +template +void ARMv7DisAsm::EOR_RSR(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::IT(const u32 op, const u32 cond) +{ + static_assert(type == T1, "IT"); + + const u32 mask = (op & 0xf); + const u32 first = (op & 0xf0) >> 4; + + write("IT%s %s", fmt_it(mask), fmt_cond(first)); +} + + +template +void ARMv7DisAsm::LDM(const u32 op, const u32 cond) +{ + using args = arm_code::ldm; + ARG(n, op); + ARG(registers, op); + ARG(wback, op); + + write("ldm%s %s%s,{%s}", fmt_cond(cond), fmt_reg(n), wback ? "!" : "", fmt_reg_list(registers)); +} + +template +void ARMv7DisAsm::LDMDA(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::LDMDB(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::LDMIB(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::LDR_IMM(const u32 op, const u32 cond) +{ + using args = arm_code::ldr_imm; + ARG(t, op); + ARG(n, op); + ARG(imm32, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); + + write("ldr%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_imm(n, imm32, index, add, wback)); +} + +template +void ARMv7DisAsm::LDR_LIT(const u32 op, const u32 cond) +{ + using args = arm_code::ldr_lit; + ARG(t, op); + ARG(imm32, op); + ARG(add, op); + + const u32 base = DisAsmBranchTarget(0) & ~3; + const u32 addr = add ? base + imm32 : base - imm32; + + write("ldr%s %s,0x%08X", fmt_cond(cond), fmt_reg(t), addr); +} + +template +void ARMv7DisAsm::LDR_REG(const u32 op, const u32 cond) +{ + using args = arm_code::ldr_reg; + ARG(t, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); + + write("ldr%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_reg(n, m, index, add, wback, shift_t, shift_n)); +} + + +template +void ARMv7DisAsm::LDRB_IMM(const u32 op, const u32 cond) +{ + using args = arm_code::ldrb_imm; + ARG(t, op); + ARG(n, op); + ARG(imm32, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); + + write("ldrb%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_imm(n, imm32, index, add, wback)); +} + +template +void ARMv7DisAsm::LDRB_LIT(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::LDRB_REG(const u32 op, const u32 cond) +{ + using args = arm_code::ldrb_reg; + ARG(t, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); + + write("ldrb%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_reg(n, m, index, add, wback, shift_t, shift_n)); +} + + +template +void ARMv7DisAsm::LDRD_IMM(const u32 op, const u32 cond) +{ + using args = arm_code::ldrd_imm; + ARG(t, op); + ARG(t2, op); + ARG(n, op); + ARG(imm32, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); + + write("ldrd%s %s,%s,%s", fmt_cond(cond), fmt_reg(t), fmt_reg(t2), fmt_mem_imm(n, imm32, index, add, wback)); +} + +template +void ARMv7DisAsm::LDRD_LIT(const u32 op, const u32 cond) +{ + using args = arm_code::ldrd_lit; + ARG(t, op); + ARG(t2, op); + ARG(imm32, op); + ARG(add, op); + + const u32 base = DisAsmBranchTarget(0) & ~3; + const u32 addr = add ? base + imm32 : base - imm32; + + write("ldrd%s %s,%s,0x%08X", fmt_cond(cond), fmt_reg(t), fmt_reg(t2), addr); +} + +template +void ARMv7DisAsm::LDRD_REG(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::LDRH_IMM(const u32 op, const u32 cond) +{ + using args = arm_code::ldrh_imm; + ARG(t, op); + ARG(n, op); + ARG(imm32, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); + + write("ldrh%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_imm(n, imm32, index, add, wback)); +} + +template +void ARMv7DisAsm::LDRH_LIT(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::LDRH_REG(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::LDRSB_IMM(const u32 op, const u32 cond) +{ + using args = arm_code::ldrsb_imm; + ARG(t, op); + ARG(n, op); + ARG(imm32, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); + + write("ldrsb%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_imm(n, imm32, index, add, wback)); +} + +template +void ARMv7DisAsm::LDRSB_LIT(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::LDRSB_REG(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::LDRSH_IMM(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::LDRSH_LIT(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::LDRSH_REG(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::LDREX(const u32 op, const u32 cond) +{ + using args = arm_code::ldrex; + ARG(t, op); + ARG(n, op); + ARG(imm32, op); + + write("ldrex%s %s,[%s,#0x%X]", fmt_cond(cond), fmt_reg(t), fmt_reg(n), imm32); +} + +template +void ARMv7DisAsm::LDREXB(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::LDREXD(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::LDREXH(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::LSL_IMM(const u32 op, const u32 cond) +{ + using args = arm_code::lsl_imm; + ARG(d, op); + ARG(m, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); + + write("lsl%s%s %s,%s,#%d", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(m), shift_n); +} + +template +void ARMv7DisAsm::LSL_REG(const u32 op, const u32 cond) +{ + using args = arm_code::lsl_reg; + ARG(d, op); + ARG(n, op); + ARG(m, op); + ARG(set_flags, op, cond); + + write("lsl%s%s %s,%s,%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), fmt_reg(m)); +} + + +template +void ARMv7DisAsm::LSR_IMM(const u32 op, const u32 cond) +{ + using args = arm_code::lsr_imm; + ARG(d, op); + ARG(m, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); + + write("lsr%s%s %s,%s,#%d", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(m), shift_n); +} + +template +void ARMv7DisAsm::LSR_REG(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::MLA(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::MLS(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::MOV_IMM(const u32 op, const u32 cond) +{ + using args = arm_code::mov_imm; + ARG(d, op); + ARG(imm32, op); + ARG(set_flags, op, cond); + + //switch (type) //{ - // Write(fmt::format("b 0x%x", DisAsmBranchTarget(imm) + intstr_size)); - //} - //else - //{ - // Write(fmt::format("b[%s] 0x%x", g_arm_cond_name[cond], DisAsmBranchTarget(imm) + intstr_size)); + //case T3: + //case A2: write("movw%s%s %s,#0x%04X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), imm32); break; + //default: write("mov%s%s %s,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), imm32); //} } +template +void ARMv7DisAsm::MOV_REG(const u32 op, const u32 cond) +{ + using args = arm_code::mov_reg; + ARG(d, op); + ARG(m, op); + ARG(set_flags, op, cond); + + write("mov%s%s %s,%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(m)); +} + +template +void ARMv7DisAsm::MOVT(const u32 op, const u32 cond) +{ + using args = arm_code::movt; + ARG(d, op); + ARG(imm16, op); + + write("movt%s %s,#0x%04X", fmt_cond(cond), fmt_reg(d), imm16); +} + + +template +void ARMv7DisAsm::MRS(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::MSR_IMM(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::MSR_REG(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::MUL(const u32 op, const u32 cond) +{ + using args = arm_code::mul; + ARG(d, op); + ARG(n, op); + ARG(m, op); + ARG(set_flags, op, cond); + + write("mul%s%s %s,%s,%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), fmt_reg(m)); +} + + +template +void ARMv7DisAsm::MVN_IMM(const u32 op, const u32 cond) +{ + using args = arm_code::mvn_imm; + ARG(d, op); + ARG(imm32, op); + ARG(set_flags, op, cond); + + write("mvn%s%s %s,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), imm32); +} + +template +void ARMv7DisAsm::MVN_REG(const u32 op, const u32 cond) +{ + using args = arm_code::mvn_reg; + ARG(d, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); + + write("mvn%s%s %s,%s%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(m), fmt_shift(shift_t, shift_n)); +} + +template +void ARMv7DisAsm::MVN_RSR(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::NOP(const u32 op, const u32 cond) +{ + write("nop%s", fmt_cond(cond)); +} + + +template +void ARMv7DisAsm::ORN_IMM(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::ORN_REG(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::ORR_IMM(const u32 op, const u32 cond) +{ + using args = arm_code::orr_imm; + ARG(d, op); + ARG(n, op); + ARG(imm32, op); + ARG(set_flags, op, cond); + + write("orr%s%s %s,%s,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), imm32); +} + +template +void ARMv7DisAsm::ORR_REG(const u32 op, const u32 cond) +{ + using args = arm_code::orr_reg; + ARG(d, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); + + write("orr%s%s %s,%s,%s%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), fmt_reg(m), fmt_shift(shift_t, shift_n)); +} + +template +void ARMv7DisAsm::ORR_RSR(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::PKH(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::POP(const u32 op, const u32 cond) +{ + const u32 registers = arm_code::pop::registers::extract(op); + + write("pop%s {%s}", fmt_cond(cond), fmt_reg_list(registers)); +} + +template +void ARMv7DisAsm::PUSH(const u32 op, const u32 cond) +{ + const u32 registers = arm_code::push::registers::extract(op); + + write("push%s {%s}", fmt_cond(cond), fmt_reg_list(registers)); +} + + +template +void ARMv7DisAsm::QADD(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::QADD16(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::QADD8(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::QASX(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::QDADD(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::QDSUB(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::QSAX(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::QSUB(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::QSUB16(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::QSUB8(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::RBIT(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::REV(const u32 op, const u32 cond) +{ + using args = arm_code::rev; + ARG(d, op); + ARG(m, op); + + write("rev%s %s,%s", fmt_cond(cond), fmt_reg(d), fmt_reg(m)); +} + +template +void ARMv7DisAsm::REV16(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::REVSH(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::ROR_IMM(const u32 op, const u32 cond) +{ + using args = arm_code::ror_imm; + ARG(d, op); + ARG(m, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); + + write("ror%s%s %s,%s,#%d", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(m), shift_n); +} + +template +void ARMv7DisAsm::ROR_REG(const u32 op, const u32 cond) +{ + using args = arm_code::ror_reg; + ARG(d, op); + ARG(n, op); + ARG(m, op); + ARG(set_flags, op, cond); + + write("ror%s%s %s,%s,%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), fmt_reg(m)); +} + + +template +void ARMv7DisAsm::RRX(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::RSB_IMM(const u32 op, const u32 cond) +{ + using args = arm_code::rsb_imm; + ARG(d, op); + ARG(n, op); + ARG(imm32, op); + ARG(set_flags, op, cond); + + write("rsb%s%s %s,%s,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), imm32); +} + +template +void ARMv7DisAsm::RSB_REG(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::RSB_RSR(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::RSC_IMM(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::RSC_REG(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::RSC_RSR(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::SADD16(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::BFC(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SADD8(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::BFI(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SASX(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::BIC_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SBC_IMM(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::BIC_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SBC_REG(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::BIC_RSR(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SBC_RSR(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::BKPT(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SBFX(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::BL(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SDIV(const u32 op, const u32 cond) { - Write(__FUNCTION__); - //Write(fmt::format("bl 0x%x", DisAsmBranchTarget(imm) + intstr_size)); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::BLX(const u32 data, const ARMv7_encoding type) + +template +void ARMv7DisAsm::SEL(const u32 op, const u32 cond) { - Write(__FUNCTION__); - //Write(fmt::format("bl 0x%x", DisAsmBranchTarget(imm) + intstr_size)); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::BX(const u32 data, const ARMv7_encoding type) + +template +void ARMv7DisAsm::SHADD16(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::SHADD8(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::CB_Z(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SHASX(const u32 op, const u32 cond) { - Write(__FUNCTION__); - //Write(fmt::format("cbz 0x%x,%s", DisAsmBranchTarget(imm) + intstr_size, g_arm_reg_name[rn])); - //Write(fmt::format("cbnz 0x%x,%s", DisAsmBranchTarget(imm) + intstr_size, g_arm_reg_name[rn])); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::SHSAX(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::SHSUB16(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::CLZ(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SHSUB8(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::CMN_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SMLA__(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::CMN_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SMLAD(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::CMN_RSR(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SMLAL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::SMLAL__(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::CMP_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SMLALD(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::CMP_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SMLAW_(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::CMP_RSR(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SMLSD(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::SMLSLD(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::EOR_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SMMLA(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::EOR_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SMMLS(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::EOR_RSR(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SMMUL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::SMUAD(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::SMUL__(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::IT(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SMULL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::SMULW_(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::LDM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SMUSD(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::LDMDA(const u32 data, const ARMv7_encoding type) + +template +void ARMv7DisAsm::SSAT(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::LDMDB(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SSAT16(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::LDMIB(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SSAX(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::SSUB16(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::LDR_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SSUB8(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::LDR_LIT(const u32 data, const ARMv7_encoding type) + +template +void ARMv7DisAsm::STM(const u32 op, const u32 cond) { - Write(__FUNCTION__); + using args = arm_code::stm; + ARG(n, op); + ARG(registers, op); + ARG(wback, op); + + write("stm%s %s%s,{%s}", fmt_cond(cond), fmt_reg(n), wback ? "!" : "", fmt_reg_list(registers)); } -void ARMv7DisAsm::LDR_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::STMDA(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::STMDB(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::LDRB_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::STMIB(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::LDRB_LIT(const u32 data, const ARMv7_encoding type) + +template +void ARMv7DisAsm::STR_IMM(const u32 op, const u32 cond) { - Write(__FUNCTION__); + using args = arm_code::str_imm; + ARG(t, op); + ARG(n, op); + ARG(imm32, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); + + write("str%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_imm(n, imm32, index, add, wback)); } -void ARMv7DisAsm::LDRB_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::STR_REG(const u32 op, const u32 cond) { - Write(__FUNCTION__); + using args = arm_code::str_reg; + ARG(t, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); + + write("str%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_reg(n, m, index, add, wback, shift_t, shift_n)); } -void ARMv7DisAsm::LDRD_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::STRB_IMM(const u32 op, const u32 cond) { - Write(__FUNCTION__); + using args = arm_code::strb_imm; + ARG(t, op); + ARG(n, op); + ARG(imm32, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); + + write("strb%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_imm(n, imm32, index, add, wback)); } -void ARMv7DisAsm::LDRD_LIT(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::STRB_REG(const u32 op, const u32 cond) +{ + using args = arm_code::strb_reg; + ARG(t, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); + + write("strb%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_reg(n, m, index, add, wback, shift_t, shift_n)); +} + + +template +void ARMv7DisAsm::STRD_IMM(const u32 op, const u32 cond) { - Write(__FUNCTION__); + using args = arm_code::strd_imm; + ARG(t, op); + ARG(t2, op); + ARG(n, op); + ARG(imm32, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); + + write("strd%s %s,%s,%s", fmt_cond(cond), fmt_reg(t), fmt_reg(t2), fmt_mem_imm(n, imm32, index, add, wback)); } -void ARMv7DisAsm::LDRD_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::STRD_REG(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::LDRH_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::STRH_IMM(const u32 op, const u32 cond) { - Write(__FUNCTION__); + using args = arm_code::strh_imm; + ARG(t, op); + ARG(n, op); + ARG(imm32, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); + + write("strh%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_imm(n, imm32, index, add, wback)); } -void ARMv7DisAsm::LDRH_LIT(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::STRH_REG(const u32 op, const u32 cond) { - Write(__FUNCTION__); + using args = arm_code::strh_reg; + ARG(t, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); + + write("strh%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_reg(n, m, index, add, wback, shift_t, shift_n)); } -void ARMv7DisAsm::LDRH_REG(const u32 data, const ARMv7_encoding type) + +template +void ARMv7DisAsm::STREX(const u32 op, const u32 cond) { - Write(__FUNCTION__); + using args = arm_code::strex; + ARG(d, op); + ARG(t, op); + ARG(n, op); + ARG(imm32, op); + + write("strex%s %s,%s,[%s,#0x%x]", fmt_cond(cond), fmt_reg(d), fmt_reg(t), fmt_reg(n), imm32); } +template +void ARMv7DisAsm::STREXB(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::LDRSB_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::STREXD(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::LDRSB_LIT(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::STREXH(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::LDRSB_REG(const u32 data, const ARMv7_encoding type) + +template +void ARMv7DisAsm::SUB_IMM(const u32 op, const u32 cond) { - Write(__FUNCTION__); + using args = arm_code::sub_imm; + ARG(d, op); + ARG(n, op); + ARG(imm32, op); + ARG(set_flags, op, cond); + + write("sub%s%s %s,%s,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), imm32); } +template +void ARMv7DisAsm::SUB_REG(const u32 op, const u32 cond) +{ + using args = arm_code::sub_reg; + ARG(d, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); + + write("sub%s%s %s,%s,%s%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), fmt_reg(m), fmt_shift(shift_t, shift_n)); +} -void ARMv7DisAsm::LDRSH_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SUB_RSR(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::LDRSH_LIT(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SUB_SPI(const u32 op, const u32 cond) { - Write(__FUNCTION__); + using args = arm_code::sub_spi; + ARG(d, op); + ARG(imm32, op); + ARG(set_flags, op, cond); + + write("sub%s%s %s,sp,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), imm32); } -void ARMv7DisAsm::LDRSH_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SUB_SPR(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::LSL_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SVC(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::LSL_REG(const u32 data, const ARMv7_encoding type) + +template +void ARMv7DisAsm::SXTAB(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::SXTAB16(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::LSR_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SXTAH(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::LSR_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SXTB(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::SXTB16(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::MLA(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::SXTH(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::MLS(const u32 data, const ARMv7_encoding type) + +template +void ARMv7DisAsm::TB_(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::MOV_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::TEQ_IMM(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::MOV_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::TEQ_REG(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::MOVT(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::TEQ_RSR(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::MRS(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::TST_IMM(const u32 op, const u32 cond) +{ + using args = arm_code::tst_imm; + ARG(n, op); + ARG(imm32, op); + + write("tst%s %s,#0x%X", fmt_cond(cond), fmt_reg(n), imm32); +} + +template +void ARMv7DisAsm::TST_REG(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::MSR_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::TST_RSR(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + + +template +void ARMv7DisAsm::UADD16(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::MSR_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::UADD8(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::UASX(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::MUL(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::UBFX(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::UDIV(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::MVN_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::UHADD16(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::MVN_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::UHADD8(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::MVN_RSR(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::UHASX(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::UHSAX(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::NOP(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::UHSUB16(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::UHSUB8(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::ORN_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::UMAAL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::ORN_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::UMLAL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::UMULL(const u32 op, const u32 cond) +{ + using args = arm_code::umull; + ARG(d0, op); + ARG(d1, op); + ARG(n, op); + ARG(m, op); + ARG(set_flags, op, cond); + + write("umull%s%s %s,%s,%s,%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d0), fmt_reg(d1), fmt_reg(n), fmt_reg(m)); +} -void ARMv7DisAsm::ORR_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::UQADD16(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::ORR_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::UQADD8(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::ORR_RSR(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::UQASX(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::UQSAX(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::PKH(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::UQSUB16(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::UQSUB8(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::POP(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::USAD8(const u32 op, const u32 cond) { - Write(__FUNCTION__); - //Write(fmt::format("pop {%s}", GetRegsListString(regs_list).c_str())); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::PUSH(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::USADA8(const u32 op, const u32 cond) { - Write(__FUNCTION__); - //Write(fmt::format("push {%s}", GetRegsListString(regs_list).c_str())); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::USAT(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::QADD(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::USAT16(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::QADD16(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::USAX(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::QADD8(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::USUB16(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::QASX(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::USUB8(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::QDADD(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::UXTAB(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::QDSUB(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::UXTAB16(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::QSAX(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::UXTAH(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::QSUB(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::UXTB(const u32 op, const u32 cond) { - Write(__FUNCTION__); + using args = arm_code::uxtb; + ARG(d, op); + ARG(m, op); + ARG(rotation, op); + + write("uxtb%s %s,%s%s", fmt_cond(cond), fmt_reg(d), fmt_reg(m), fmt_shift(arm_code::SRType_ROR, rotation)); } -void ARMv7DisAsm::QSUB16(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::UXTB16(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::QSUB8(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::UXTH(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::RBIT(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VABA_(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::REV(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VABD_(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::REV16(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VABD_FP(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::REVSH(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VABS(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VAC__(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::ROR_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VADD(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::ROR_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VADD_FP(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VADDHN(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::RRX(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VADD_(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VAND(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} + +template +void ARMv7DisAsm::VBIC_IMM(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::RSB_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VBIC_REG(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::RSB_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VB__(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::RSB_RSR(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VCEQ_REG(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VCEQ_ZERO(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::RSC_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VCGE_REG(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::RSC_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VCGE_ZERO(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::RSC_RSR(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VCGT_REG(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VCGT_ZERO(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::SADD16(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VCLE_ZERO(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SADD8(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VCLS(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SASX(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VCLT_ZERO(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VCLZ(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::SBC_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VCMP_(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SBC_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VCNT(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SBC_RSR(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VCVT_FIA(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VCVT_FIF(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::SBFX(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VCVT_FFA(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VCVT_FFF(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::SDIV(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VCVT_DF(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VCVT_HFA(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::SEL(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VCVT_HFF(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VDIV(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::SHADD16(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VDUP_S(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SHADD8(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VDUP_R(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SHASX(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VEOR(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SHSAX(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VEXT(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SHSUB16(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VHADDSUB(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SHSUB8(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VLD__MS(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VLD1_SL(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::SMLA__(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VLD1_SAL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SMLAD(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VLD2_SL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SMLAL(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VLD2_SAL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SMLAL__(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VLD3_SL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SMLALD(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VLD3_SAL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SMLAW_(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VLD4_SL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SMLSD(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VLD4_SAL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SMLSLD(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VLDM(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SMMLA(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VLDR(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SMMLS(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VMAXMIN(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SMMUL(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VMAXMIN_FP(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SMUAD(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VML__(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SMUL__(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VML__FP(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SMULL(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VML__S(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SMULW_(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VMOV_IMM(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SMUSD(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VMOV_REG(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VMOV_RS(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::SSAT(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VMOV_SR(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SSAT16(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VMOV_RF(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SSAX(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VMOV_2RF(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SSUB16(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VMOV_2RD(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SSUB8(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VMOVL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VMOVN(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::STM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VMRS(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::STMDA(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VMSR(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::STMDB(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VMUL_(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::STMIB(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VMUL_FP(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VMUL_S(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::STR_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VMVN_IMM(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::STR_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VMVN_REG(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VNEG(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::STRB_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VNM__(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::STRB_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VORN_REG(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VORR_IMM(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::STRD_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VORR_REG(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::STRD_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VPADAL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VPADD(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::STRH_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VPADD_FP(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::STRH_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VPADDL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VPMAXMIN(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::SUB_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VPMAXMIN_FP(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SUB_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VPOP(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SUB_RSR(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VPUSH(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SUB_SPI(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VQABS(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SUB_SPR(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VQADD(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VQDML_L(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::SVC(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VQDMULH(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VQDMULL(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::SXTAB(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VQMOV_N(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SXTAB16(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VQNEG(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SXTAH(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VQRDMULH(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SXTB(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VQRSHL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SXTB16(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VQRSHR_N(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::SXTH(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VQSHL_REG(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VQSHL_IMM(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::TB_(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VQSHR_N(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VQSUB(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::TEQ_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VRADDHN(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::TEQ_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VRECPE(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::TEQ_RSR(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VRECPS(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VREV__(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::TST_IMM(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VRHADD(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::TST_REG(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VRSHL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::TST_RSR(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VRSHR(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } +template +void ARMv7DisAsm::VRSHRN(const u32 op, const u32 cond) +{ + write("%s<%s>", __func__, fmt_encoding()); +} -void ARMv7DisAsm::UADD16(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VRSQRTE(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UADD8(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VRSQRTS(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UASX(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VRSRA(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UBFX(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VRSUBHN(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UDIV(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VSHL_IMM(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UHADD16(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VSHL_REG(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UHADD8(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VSHLL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UHASX(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VSHR(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UHSAX(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VSHRN(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UHSUB16(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VSLI(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UHSUB8(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VSQRT(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UMAAL(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VSRA(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UMLAL(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VSRI(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UMULL(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VST__MS(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UQADD16(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VST1_SL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UQADD8(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VST2_SL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UQASX(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VST3_SL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UQSAX(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VST4_SL(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UQSUB16(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VSTM(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UQSUB8(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VSTR(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::USAD8(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VSUB(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::USADA8(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VSUB_FP(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::USAT(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VSUBHN(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::USAT16(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VSUB_(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::USAX(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VSWP(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::USUB16(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VTB_(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::USUB8(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VTRN(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UXTAB(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VTST(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UXTAB16(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VUZP(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UXTAH(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::VZIP(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UXTB(const u32 data, const ARMv7_encoding type) + +template +void ARMv7DisAsm::WFE(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UXTB16(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::WFI(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -void ARMv7DisAsm::UXTH(const u32 data, const ARMv7_encoding type) +template +void ARMv7DisAsm::YIELD(const u32 op, const u32 cond) { - Write(__FUNCTION__); + write("%s<%s>", __func__, fmt_encoding()); } -#endif + + +template void ARMv7DisAsm::HACK(const u32, const u32); +template void ARMv7DisAsm::HACK(const u32, const u32); +template void ARMv7DisAsm::ADC_IMM(const u32, const u32); +template void ARMv7DisAsm::ADC_IMM(const u32, const u32); +template void ARMv7DisAsm::ADC_REG(const u32, const u32); +template void ARMv7DisAsm::ADC_REG(const u32, const u32); +template void ARMv7DisAsm::ADC_REG(const u32, const u32); +template void ARMv7DisAsm::ADC_RSR(const u32, const u32); +template void ARMv7DisAsm::ADD_IMM(const u32, const u32); +template void ARMv7DisAsm::ADD_IMM(const u32, const u32); +template void ARMv7DisAsm::ADD_IMM(const u32, const u32); +template void ARMv7DisAsm::ADD_IMM(const u32, const u32); +template void ARMv7DisAsm::ADD_IMM(const u32, const u32); +template void ARMv7DisAsm::ADD_REG(const u32, const u32); +template void ARMv7DisAsm::ADD_REG(const u32, const u32); +template void ARMv7DisAsm::ADD_REG(const u32, const u32); +template void ARMv7DisAsm::ADD_REG(const u32, const u32); +template void ARMv7DisAsm::ADD_RSR(const u32, const u32); +template void ARMv7DisAsm::ADD_SPI(const u32, const u32); +template void ARMv7DisAsm::ADD_SPI(const u32, const u32); +template void ARMv7DisAsm::ADD_SPI(const u32, const u32); +template void ARMv7DisAsm::ADD_SPI(const u32, const u32); +template void ARMv7DisAsm::ADD_SPI(const u32, const u32); +template void ARMv7DisAsm::ADD_SPR(const u32, const u32); +template void ARMv7DisAsm::ADD_SPR(const u32, const u32); +template void ARMv7DisAsm::ADD_SPR(const u32, const u32); +template void ARMv7DisAsm::ADD_SPR(const u32, const u32); +template void ARMv7DisAsm::ADR(const u32, const u32); +template void ARMv7DisAsm::ADR(const u32, const u32); +template void ARMv7DisAsm::ADR(const u32, const u32); +template void ARMv7DisAsm::ADR(const u32, const u32); +template void ARMv7DisAsm::ADR(const u32, const u32); +template void ARMv7DisAsm::AND_IMM(const u32, const u32); +template void ARMv7DisAsm::AND_IMM(const u32, const u32); +template void ARMv7DisAsm::AND_REG(const u32, const u32); +template void ARMv7DisAsm::AND_REG(const u32, const u32); +template void ARMv7DisAsm::AND_REG(const u32, const u32); +template void ARMv7DisAsm::AND_RSR(const u32, const u32); +template void ARMv7DisAsm::ASR_IMM(const u32, const u32); +template void ARMv7DisAsm::ASR_IMM(const u32, const u32); +template void ARMv7DisAsm::ASR_IMM(const u32, const u32); +template void ARMv7DisAsm::ASR_REG(const u32, const u32); +template void ARMv7DisAsm::ASR_REG(const u32, const u32); +template void ARMv7DisAsm::ASR_REG(const u32, const u32); +template void ARMv7DisAsm::B(const u32, const u32); +template void ARMv7DisAsm::B(const u32, const u32); +template void ARMv7DisAsm::B(const u32, const u32); +template void ARMv7DisAsm::B(const u32, const u32); +template void ARMv7DisAsm::B(const u32, const u32); +template void ARMv7DisAsm::BFC(const u32, const u32); +template void ARMv7DisAsm::BFC(const u32, const u32); +template void ARMv7DisAsm::BFI(const u32, const u32); +template void ARMv7DisAsm::BFI(const u32, const u32); +template void ARMv7DisAsm::BIC_IMM(const u32, const u32); +template void ARMv7DisAsm::BIC_IMM(const u32, const u32); +template void ARMv7DisAsm::BIC_REG(const u32, const u32); +template void ARMv7DisAsm::BIC_REG(const u32, const u32); +template void ARMv7DisAsm::BIC_REG(const u32, const u32); +template void ARMv7DisAsm::BIC_RSR(const u32, const u32); +template void ARMv7DisAsm::BKPT(const u32, const u32); +template void ARMv7DisAsm::BKPT(const u32, const u32); +template void ARMv7DisAsm::BL(const u32, const u32); +template void ARMv7DisAsm::BL(const u32, const u32); +template void ARMv7DisAsm::BL(const u32, const u32); +template void ARMv7DisAsm::BL(const u32, const u32); +template void ARMv7DisAsm::BLX(const u32, const u32); +template void ARMv7DisAsm::BLX(const u32, const u32); +template void ARMv7DisAsm::BX(const u32, const u32); +template void ARMv7DisAsm::BX(const u32, const u32); +template void ARMv7DisAsm::CB_Z(const u32, const u32); +template void ARMv7DisAsm::CLZ(const u32, const u32); +template void ARMv7DisAsm::CLZ(const u32, const u32); +template void ARMv7DisAsm::CMN_IMM(const u32, const u32); +template void ARMv7DisAsm::CMN_IMM(const u32, const u32); +template void ARMv7DisAsm::CMN_REG(const u32, const u32); +template void ARMv7DisAsm::CMN_REG(const u32, const u32); +template void ARMv7DisAsm::CMN_REG(const u32, const u32); +template void ARMv7DisAsm::CMN_RSR(const u32, const u32); +template void ARMv7DisAsm::CMP_IMM(const u32, const u32); +template void ARMv7DisAsm::CMP_IMM(const u32, const u32); +template void ARMv7DisAsm::CMP_IMM(const u32, const u32); +template void ARMv7DisAsm::CMP_REG(const u32, const u32); +template void ARMv7DisAsm::CMP_REG(const u32, const u32); +template void ARMv7DisAsm::CMP_REG(const u32, const u32); +template void ARMv7DisAsm::CMP_REG(const u32, const u32); +template void ARMv7DisAsm::CMP_RSR(const u32, const u32); +template void ARMv7DisAsm::DBG(const u32, const u32); +template void ARMv7DisAsm::DBG(const u32, const u32); +template void ARMv7DisAsm::DMB(const u32, const u32); +template void ARMv7DisAsm::DMB(const u32, const u32); +template void ARMv7DisAsm::DSB(const u32, const u32); +template void ARMv7DisAsm::DSB(const u32, const u32); +template void ARMv7DisAsm::EOR_IMM(const u32, const u32); +template void ARMv7DisAsm::EOR_IMM(const u32, const u32); +template void ARMv7DisAsm::EOR_REG(const u32, const u32); +template void ARMv7DisAsm::EOR_REG(const u32, const u32); +template void ARMv7DisAsm::EOR_REG(const u32, const u32); +template void ARMv7DisAsm::EOR_RSR(const u32, const u32); +template void ARMv7DisAsm::IT(const u32, const u32); +template void ARMv7DisAsm::LDM(const u32, const u32); +template void ARMv7DisAsm::LDM(const u32, const u32); +template void ARMv7DisAsm::LDM(const u32, const u32); +template void ARMv7DisAsm::LDMDA(const u32, const u32); +template void ARMv7DisAsm::LDMDB(const u32, const u32); +template void ARMv7DisAsm::LDMDB(const u32, const u32); +template void ARMv7DisAsm::LDMIB(const u32, const u32); +template void ARMv7DisAsm::LDR_IMM(const u32, const u32); +template void ARMv7DisAsm::LDR_IMM(const u32, const u32); +template void ARMv7DisAsm::LDR_IMM(const u32, const u32); +template void ARMv7DisAsm::LDR_IMM(const u32, const u32); +template void ARMv7DisAsm::LDR_IMM(const u32, const u32); +template void ARMv7DisAsm::LDR_LIT(const u32, const u32); +template void ARMv7DisAsm::LDR_LIT(const u32, const u32); +template void ARMv7DisAsm::LDR_LIT(const u32, const u32); +template void ARMv7DisAsm::LDR_REG(const u32, const u32); +template void ARMv7DisAsm::LDR_REG(const u32, const u32); +template void ARMv7DisAsm::LDR_REG(const u32, const u32); +template void ARMv7DisAsm::LDRB_IMM(const u32, const u32); +template void ARMv7DisAsm::LDRB_IMM(const u32, const u32); +template void ARMv7DisAsm::LDRB_IMM(const u32, const u32); +template void ARMv7DisAsm::LDRB_IMM(const u32, const u32); +template void ARMv7DisAsm::LDRB_LIT(const u32, const u32); +template void ARMv7DisAsm::LDRB_LIT(const u32, const u32); +template void ARMv7DisAsm::LDRB_REG(const u32, const u32); +template void ARMv7DisAsm::LDRB_REG(const u32, const u32); +template void ARMv7DisAsm::LDRB_REG(const u32, const u32); +template void ARMv7DisAsm::LDRD_IMM(const u32, const u32); +template void ARMv7DisAsm::LDRD_IMM(const u32, const u32); +template void ARMv7DisAsm::LDRD_LIT(const u32, const u32); +template void ARMv7DisAsm::LDRD_LIT(const u32, const u32); +template void ARMv7DisAsm::LDRD_REG(const u32, const u32); +template void ARMv7DisAsm::LDREX(const u32, const u32); +template void ARMv7DisAsm::LDREX(const u32, const u32); +template void ARMv7DisAsm::LDREXB(const u32, const u32); +template void ARMv7DisAsm::LDREXB(const u32, const u32); +template void ARMv7DisAsm::LDREXD(const u32, const u32); +template void ARMv7DisAsm::LDREXD(const u32, const u32); +template void ARMv7DisAsm::LDREXH(const u32, const u32); +template void ARMv7DisAsm::LDREXH(const u32, const u32); +template void ARMv7DisAsm::LDRH_IMM(const u32, const u32); +template void ARMv7DisAsm::LDRH_IMM(const u32, const u32); +template void ARMv7DisAsm::LDRH_IMM(const u32, const u32); +template void ARMv7DisAsm::LDRH_IMM(const u32, const u32); +template void ARMv7DisAsm::LDRH_LIT(const u32, const u32); +template void ARMv7DisAsm::LDRH_LIT(const u32, const u32); +template void ARMv7DisAsm::LDRH_REG(const u32, const u32); +template void ARMv7DisAsm::LDRH_REG(const u32, const u32); +template void ARMv7DisAsm::LDRH_REG(const u32, const u32); +template void ARMv7DisAsm::LDRSB_IMM(const u32, const u32); +template void ARMv7DisAsm::LDRSB_IMM(const u32, const u32); +template void ARMv7DisAsm::LDRSB_IMM(const u32, const u32); +template void ARMv7DisAsm::LDRSB_LIT(const u32, const u32); +template void ARMv7DisAsm::LDRSB_LIT(const u32, const u32); +template void ARMv7DisAsm::LDRSB_REG(const u32, const u32); +template void ARMv7DisAsm::LDRSB_REG(const u32, const u32); +template void ARMv7DisAsm::LDRSB_REG(const u32, const u32); +template void ARMv7DisAsm::LDRSH_IMM(const u32, const u32); +template void ARMv7DisAsm::LDRSH_IMM(const u32, const u32); +template void ARMv7DisAsm::LDRSH_IMM(const u32, const u32); +template void ARMv7DisAsm::LDRSH_LIT(const u32, const u32); +template void ARMv7DisAsm::LDRSH_LIT(const u32, const u32); +template void ARMv7DisAsm::LDRSH_REG(const u32, const u32); +template void ARMv7DisAsm::LDRSH_REG(const u32, const u32); +template void ARMv7DisAsm::LDRSH_REG(const u32, const u32); +template void ARMv7DisAsm::LSL_IMM(const u32, const u32); +template void ARMv7DisAsm::LSL_IMM(const u32, const u32); +template void ARMv7DisAsm::LSL_IMM(const u32, const u32); +template void ARMv7DisAsm::LSL_REG(const u32, const u32); +template void ARMv7DisAsm::LSL_REG(const u32, const u32); +template void ARMv7DisAsm::LSL_REG(const u32, const u32); +template void ARMv7DisAsm::LSR_IMM(const u32, const u32); +template void ARMv7DisAsm::LSR_IMM(const u32, const u32); +template void ARMv7DisAsm::LSR_IMM(const u32, const u32); +template void ARMv7DisAsm::LSR_REG(const u32, const u32); +template void ARMv7DisAsm::LSR_REG(const u32, const u32); +template void ARMv7DisAsm::LSR_REG(const u32, const u32); +template void ARMv7DisAsm::MLA(const u32, const u32); +template void ARMv7DisAsm::MLA(const u32, const u32); +template void ARMv7DisAsm::MLS(const u32, const u32); +template void ARMv7DisAsm::MLS(const u32, const u32); +template void ARMv7DisAsm::MOV_IMM(const u32, const u32); +template void ARMv7DisAsm::MOV_IMM(const u32, const u32); +template void ARMv7DisAsm::MOV_IMM(const u32, const u32); +template void ARMv7DisAsm::MOV_IMM(const u32, const u32); +template void ARMv7DisAsm::MOV_IMM(const u32, const u32); +template void ARMv7DisAsm::MOV_REG(const u32, const u32); +template void ARMv7DisAsm::MOV_REG(const u32, const u32); +template void ARMv7DisAsm::MOV_REG(const u32, const u32); +template void ARMv7DisAsm::MOV_REG(const u32, const u32); +template void ARMv7DisAsm::MOVT(const u32, const u32); +template void ARMv7DisAsm::MOVT(const u32, const u32); +template void ARMv7DisAsm::MRC_(const u32, const u32); +template void ARMv7DisAsm::MRC_(const u32, const u32); +template void ARMv7DisAsm::MRC_(const u32, const u32); +template void ARMv7DisAsm::MRC_(const u32, const u32); +template void ARMv7DisAsm::MRS(const u32, const u32); +template void ARMv7DisAsm::MRS(const u32, const u32); +template void ARMv7DisAsm::MSR_IMM(const u32, const u32); +template void ARMv7DisAsm::MSR_REG(const u32, const u32); +template void ARMv7DisAsm::MSR_REG(const u32, const u32); +template void ARMv7DisAsm::MUL(const u32, const u32); +template void ARMv7DisAsm::MUL(const u32, const u32); +template void ARMv7DisAsm::MUL(const u32, const u32); +template void ARMv7DisAsm::MVN_IMM(const u32, const u32); +template void ARMv7DisAsm::MVN_IMM(const u32, const u32); +template void ARMv7DisAsm::MVN_REG(const u32, const u32); +template void ARMv7DisAsm::MVN_REG(const u32, const u32); +template void ARMv7DisAsm::MVN_REG(const u32, const u32); +template void ARMv7DisAsm::MVN_RSR(const u32, const u32); +template void ARMv7DisAsm::NOP(const u32, const u32); +template void ARMv7DisAsm::NOP(const u32, const u32); +template void ARMv7DisAsm::NOP(const u32, const u32); +template void ARMv7DisAsm::ORN_IMM(const u32, const u32); +template void ARMv7DisAsm::ORN_REG(const u32, const u32); +template void ARMv7DisAsm::ORR_IMM(const u32, const u32); +template void ARMv7DisAsm::ORR_IMM(const u32, const u32); +template void ARMv7DisAsm::ORR_REG(const u32, const u32); +template void ARMv7DisAsm::ORR_REG(const u32, const u32); +template void ARMv7DisAsm::ORR_REG(const u32, const u32); +template void ARMv7DisAsm::ORR_RSR(const u32, const u32); +template void ARMv7DisAsm::PKH(const u32, const u32); +template void ARMv7DisAsm::PKH(const u32, const u32); +template void ARMv7DisAsm::POP(const u32, const u32); +template void ARMv7DisAsm::POP(const u32, const u32); +template void ARMv7DisAsm::POP(const u32, const u32); +template void ARMv7DisAsm::POP(const u32, const u32); +template void ARMv7DisAsm::POP(const u32, const u32); +template void ARMv7DisAsm::PUSH(const u32, const u32); +template void ARMv7DisAsm::PUSH(const u32, const u32); +template void ARMv7DisAsm::PUSH(const u32, const u32); +template void ARMv7DisAsm::PUSH(const u32, const u32); +template void ARMv7DisAsm::PUSH(const u32, const u32); +template void ARMv7DisAsm::QADD(const u32, const u32); +template void ARMv7DisAsm::QADD(const u32, const u32); +template void ARMv7DisAsm::QADD16(const u32, const u32); +template void ARMv7DisAsm::QADD16(const u32, const u32); +template void ARMv7DisAsm::QADD8(const u32, const u32); +template void ARMv7DisAsm::QADD8(const u32, const u32); +template void ARMv7DisAsm::QASX(const u32, const u32); +template void ARMv7DisAsm::QASX(const u32, const u32); +template void ARMv7DisAsm::QDADD(const u32, const u32); +template void ARMv7DisAsm::QDADD(const u32, const u32); +template void ARMv7DisAsm::QDSUB(const u32, const u32); +template void ARMv7DisAsm::QDSUB(const u32, const u32); +template void ARMv7DisAsm::QSAX(const u32, const u32); +template void ARMv7DisAsm::QSAX(const u32, const u32); +template void ARMv7DisAsm::QSUB(const u32, const u32); +template void ARMv7DisAsm::QSUB(const u32, const u32); +template void ARMv7DisAsm::QSUB16(const u32, const u32); +template void ARMv7DisAsm::QSUB16(const u32, const u32); +template void ARMv7DisAsm::QSUB8(const u32, const u32); +template void ARMv7DisAsm::QSUB8(const u32, const u32); +template void ARMv7DisAsm::RBIT(const u32, const u32); +template void ARMv7DisAsm::RBIT(const u32, const u32); +template void ARMv7DisAsm::REV(const u32, const u32); +template void ARMv7DisAsm::REV(const u32, const u32); +template void ARMv7DisAsm::REV(const u32, const u32); +template void ARMv7DisAsm::REV16(const u32, const u32); +template void ARMv7DisAsm::REV16(const u32, const u32); +template void ARMv7DisAsm::REV16(const u32, const u32); +template void ARMv7DisAsm::REVSH(const u32, const u32); +template void ARMv7DisAsm::REVSH(const u32, const u32); +template void ARMv7DisAsm::REVSH(const u32, const u32); +template void ARMv7DisAsm::ROR_IMM(const u32, const u32); +template void ARMv7DisAsm::ROR_IMM(const u32, const u32); +template void ARMv7DisAsm::ROR_REG(const u32, const u32); +template void ARMv7DisAsm::ROR_REG(const u32, const u32); +template void ARMv7DisAsm::ROR_REG(const u32, const u32); +template void ARMv7DisAsm::RRX(const u32, const u32); +template void ARMv7DisAsm::RRX(const u32, const u32); +template void ARMv7DisAsm::RSB_IMM(const u32, const u32); +template void ARMv7DisAsm::RSB_IMM(const u32, const u32); +template void ARMv7DisAsm::RSB_IMM(const u32, const u32); +template void ARMv7DisAsm::RSB_REG(const u32, const u32); +template void ARMv7DisAsm::RSB_REG(const u32, const u32); +template void ARMv7DisAsm::RSB_RSR(const u32, const u32); +template void ARMv7DisAsm::RSC_IMM(const u32, const u32); +template void ARMv7DisAsm::RSC_REG(const u32, const u32); +template void ARMv7DisAsm::RSC_RSR(const u32, const u32); +template void ARMv7DisAsm::SADD16(const u32, const u32); +template void ARMv7DisAsm::SADD16(const u32, const u32); +template void ARMv7DisAsm::SADD8(const u32, const u32); +template void ARMv7DisAsm::SADD8(const u32, const u32); +template void ARMv7DisAsm::SASX(const u32, const u32); +template void ARMv7DisAsm::SASX(const u32, const u32); +template void ARMv7DisAsm::SBC_IMM(const u32, const u32); +template void ARMv7DisAsm::SBC_IMM(const u32, const u32); +template void ARMv7DisAsm::SBC_REG(const u32, const u32); +template void ARMv7DisAsm::SBC_REG(const u32, const u32); +template void ARMv7DisAsm::SBC_REG(const u32, const u32); +template void ARMv7DisAsm::SBC_RSR(const u32, const u32); +template void ARMv7DisAsm::SBFX(const u32, const u32); +template void ARMv7DisAsm::SBFX(const u32, const u32); +template void ARMv7DisAsm::SDIV(const u32, const u32); +template void ARMv7DisAsm::SEL(const u32, const u32); +template void ARMv7DisAsm::SEL(const u32, const u32); +template void ARMv7DisAsm::SHADD16(const u32, const u32); +template void ARMv7DisAsm::SHADD16(const u32, const u32); +template void ARMv7DisAsm::SHADD8(const u32, const u32); +template void ARMv7DisAsm::SHADD8(const u32, const u32); +template void ARMv7DisAsm::SHASX(const u32, const u32); +template void ARMv7DisAsm::SHASX(const u32, const u32); +template void ARMv7DisAsm::SHSAX(const u32, const u32); +template void ARMv7DisAsm::SHSAX(const u32, const u32); +template void ARMv7DisAsm::SHSUB16(const u32, const u32); +template void ARMv7DisAsm::SHSUB16(const u32, const u32); +template void ARMv7DisAsm::SHSUB8(const u32, const u32); +template void ARMv7DisAsm::SHSUB8(const u32, const u32); +template void ARMv7DisAsm::SMLA__(const u32, const u32); +template void ARMv7DisAsm::SMLA__(const u32, const u32); +template void ARMv7DisAsm::SMLAD(const u32, const u32); +template void ARMv7DisAsm::SMLAD(const u32, const u32); +template void ARMv7DisAsm::SMLAL(const u32, const u32); +template void ARMv7DisAsm::SMLAL(const u32, const u32); +template void ARMv7DisAsm::SMLAL__(const u32, const u32); +template void ARMv7DisAsm::SMLAL__(const u32, const u32); +template void ARMv7DisAsm::SMLALD(const u32, const u32); +template void ARMv7DisAsm::SMLALD(const u32, const u32); +template void ARMv7DisAsm::SMLAW_(const u32, const u32); +template void ARMv7DisAsm::SMLAW_(const u32, const u32); +template void ARMv7DisAsm::SMLSD(const u32, const u32); +template void ARMv7DisAsm::SMLSD(const u32, const u32); +template void ARMv7DisAsm::SMLSLD(const u32, const u32); +template void ARMv7DisAsm::SMLSLD(const u32, const u32); +template void ARMv7DisAsm::SMMLA(const u32, const u32); +template void ARMv7DisAsm::SMMLA(const u32, const u32); +template void ARMv7DisAsm::SMMLS(const u32, const u32); +template void ARMv7DisAsm::SMMLS(const u32, const u32); +template void ARMv7DisAsm::SMMUL(const u32, const u32); +template void ARMv7DisAsm::SMMUL(const u32, const u32); +template void ARMv7DisAsm::SMUAD(const u32, const u32); +template void ARMv7DisAsm::SMUAD(const u32, const u32); +template void ARMv7DisAsm::SMUL__(const u32, const u32); +template void ARMv7DisAsm::SMUL__(const u32, const u32); +template void ARMv7DisAsm::SMULL(const u32, const u32); +template void ARMv7DisAsm::SMULL(const u32, const u32); +template void ARMv7DisAsm::SMULW_(const u32, const u32); +template void ARMv7DisAsm::SMULW_(const u32, const u32); +template void ARMv7DisAsm::SMUSD(const u32, const u32); +template void ARMv7DisAsm::SMUSD(const u32, const u32); +template void ARMv7DisAsm::SSAT(const u32, const u32); +template void ARMv7DisAsm::SSAT(const u32, const u32); +template void ARMv7DisAsm::SSAT16(const u32, const u32); +template void ARMv7DisAsm::SSAT16(const u32, const u32); +template void ARMv7DisAsm::SSAX(const u32, const u32); +template void ARMv7DisAsm::SSAX(const u32, const u32); +template void ARMv7DisAsm::SSUB16(const u32, const u32); +template void ARMv7DisAsm::SSUB16(const u32, const u32); +template void ARMv7DisAsm::SSUB8(const u32, const u32); +template void ARMv7DisAsm::SSUB8(const u32, const u32); +template void ARMv7DisAsm::STM(const u32, const u32); +template void ARMv7DisAsm::STM(const u32, const u32); +template void ARMv7DisAsm::STM(const u32, const u32); +template void ARMv7DisAsm::STMDA(const u32, const u32); +template void ARMv7DisAsm::STMDB(const u32, const u32); +template void ARMv7DisAsm::STMDB(const u32, const u32); +template void ARMv7DisAsm::STMIB(const u32, const u32); +template void ARMv7DisAsm::STR_IMM(const u32, const u32); +template void ARMv7DisAsm::STR_IMM(const u32, const u32); +template void ARMv7DisAsm::STR_IMM(const u32, const u32); +template void ARMv7DisAsm::STR_IMM(const u32, const u32); +template void ARMv7DisAsm::STR_IMM(const u32, const u32); +template void ARMv7DisAsm::STR_REG(const u32, const u32); +template void ARMv7DisAsm::STR_REG(const u32, const u32); +template void ARMv7DisAsm::STR_REG(const u32, const u32); +template void ARMv7DisAsm::STRB_IMM(const u32, const u32); +template void ARMv7DisAsm::STRB_IMM(const u32, const u32); +template void ARMv7DisAsm::STRB_IMM(const u32, const u32); +template void ARMv7DisAsm::STRB_IMM(const u32, const u32); +template void ARMv7DisAsm::STRB_REG(const u32, const u32); +template void ARMv7DisAsm::STRB_REG(const u32, const u32); +template void ARMv7DisAsm::STRB_REG(const u32, const u32); +template void ARMv7DisAsm::STRD_IMM(const u32, const u32); +template void ARMv7DisAsm::STRD_IMM(const u32, const u32); +template void ARMv7DisAsm::STRD_REG(const u32, const u32); +template void ARMv7DisAsm::STREX(const u32, const u32); +template void ARMv7DisAsm::STREX(const u32, const u32); +template void ARMv7DisAsm::STREXB(const u32, const u32); +template void ARMv7DisAsm::STREXB(const u32, const u32); +template void ARMv7DisAsm::STREXD(const u32, const u32); +template void ARMv7DisAsm::STREXD(const u32, const u32); +template void ARMv7DisAsm::STREXH(const u32, const u32); +template void ARMv7DisAsm::STREXH(const u32, const u32); +template void ARMv7DisAsm::STRH_IMM(const u32, const u32); +template void ARMv7DisAsm::STRH_IMM(const u32, const u32); +template void ARMv7DisAsm::STRH_IMM(const u32, const u32); +template void ARMv7DisAsm::STRH_IMM(const u32, const u32); +template void ARMv7DisAsm::STRH_REG(const u32, const u32); +template void ARMv7DisAsm::STRH_REG(const u32, const u32); +template void ARMv7DisAsm::STRH_REG(const u32, const u32); +template void ARMv7DisAsm::SUB_IMM(const u32, const u32); +template void ARMv7DisAsm::SUB_IMM(const u32, const u32); +template void ARMv7DisAsm::SUB_IMM(const u32, const u32); +template void ARMv7DisAsm::SUB_IMM(const u32, const u32); +template void ARMv7DisAsm::SUB_IMM(const u32, const u32); +template void ARMv7DisAsm::SUB_REG(const u32, const u32); +template void ARMv7DisAsm::SUB_REG(const u32, const u32); +template void ARMv7DisAsm::SUB_REG(const u32, const u32); +template void ARMv7DisAsm::SUB_RSR(const u32, const u32); +template void ARMv7DisAsm::SUB_SPI(const u32, const u32); +template void ARMv7DisAsm::SUB_SPI(const u32, const u32); +template void ARMv7DisAsm::SUB_SPI(const u32, const u32); +template void ARMv7DisAsm::SUB_SPI(const u32, const u32); +template void ARMv7DisAsm::SUB_SPR(const u32, const u32); +template void ARMv7DisAsm::SUB_SPR(const u32, const u32); +template void ARMv7DisAsm::SVC(const u32, const u32); +template void ARMv7DisAsm::SVC(const u32, const u32); +template void ARMv7DisAsm::SXTAB(const u32, const u32); +template void ARMv7DisAsm::SXTAB(const u32, const u32); +template void ARMv7DisAsm::SXTAB16(const u32, const u32); +template void ARMv7DisAsm::SXTAB16(const u32, const u32); +template void ARMv7DisAsm::SXTAH(const u32, const u32); +template void ARMv7DisAsm::SXTAH(const u32, const u32); +template void ARMv7DisAsm::SXTB(const u32, const u32); +template void ARMv7DisAsm::SXTB(const u32, const u32); +template void ARMv7DisAsm::SXTB(const u32, const u32); +template void ARMv7DisAsm::SXTB16(const u32, const u32); +template void ARMv7DisAsm::SXTB16(const u32, const u32); +template void ARMv7DisAsm::SXTH(const u32, const u32); +template void ARMv7DisAsm::SXTH(const u32, const u32); +template void ARMv7DisAsm::SXTH(const u32, const u32); +template void ARMv7DisAsm::TB_(const u32, const u32); +template void ARMv7DisAsm::TEQ_IMM(const u32, const u32); +template void ARMv7DisAsm::TEQ_IMM(const u32, const u32); +template void ARMv7DisAsm::TEQ_REG(const u32, const u32); +template void ARMv7DisAsm::TEQ_REG(const u32, const u32); +template void ARMv7DisAsm::TEQ_RSR(const u32, const u32); +template void ARMv7DisAsm::TST_IMM(const u32, const u32); +template void ARMv7DisAsm::TST_IMM(const u32, const u32); +template void ARMv7DisAsm::TST_REG(const u32, const u32); +template void ARMv7DisAsm::TST_REG(const u32, const u32); +template void ARMv7DisAsm::TST_REG(const u32, const u32); +template void ARMv7DisAsm::TST_RSR(const u32, const u32); +template void ARMv7DisAsm::UADD16(const u32, const u32); +template void ARMv7DisAsm::UADD16(const u32, const u32); +template void ARMv7DisAsm::UADD8(const u32, const u32); +template void ARMv7DisAsm::UADD8(const u32, const u32); +template void ARMv7DisAsm::UASX(const u32, const u32); +template void ARMv7DisAsm::UASX(const u32, const u32); +template void ARMv7DisAsm::UBFX(const u32, const u32); +template void ARMv7DisAsm::UBFX(const u32, const u32); +template void ARMv7DisAsm::UDIV(const u32, const u32); +template void ARMv7DisAsm::UHADD16(const u32, const u32); +template void ARMv7DisAsm::UHADD16(const u32, const u32); +template void ARMv7DisAsm::UHADD8(const u32, const u32); +template void ARMv7DisAsm::UHADD8(const u32, const u32); +template void ARMv7DisAsm::UHASX(const u32, const u32); +template void ARMv7DisAsm::UHASX(const u32, const u32); +template void ARMv7DisAsm::UHSAX(const u32, const u32); +template void ARMv7DisAsm::UHSAX(const u32, const u32); +template void ARMv7DisAsm::UHSUB16(const u32, const u32); +template void ARMv7DisAsm::UHSUB16(const u32, const u32); +template void ARMv7DisAsm::UHSUB8(const u32, const u32); +template void ARMv7DisAsm::UHSUB8(const u32, const u32); +template void ARMv7DisAsm::UMAAL(const u32, const u32); +template void ARMv7DisAsm::UMAAL(const u32, const u32); +template void ARMv7DisAsm::UMLAL(const u32, const u32); +template void ARMv7DisAsm::UMLAL(const u32, const u32); +template void ARMv7DisAsm::UMULL(const u32, const u32); +template void ARMv7DisAsm::UMULL(const u32, const u32); +template void ARMv7DisAsm::UQADD16(const u32, const u32); +template void ARMv7DisAsm::UQADD16(const u32, const u32); +template void ARMv7DisAsm::UQADD8(const u32, const u32); +template void ARMv7DisAsm::UQADD8(const u32, const u32); +template void ARMv7DisAsm::UQASX(const u32, const u32); +template void ARMv7DisAsm::UQASX(const u32, const u32); +template void ARMv7DisAsm::UQSAX(const u32, const u32); +template void ARMv7DisAsm::UQSAX(const u32, const u32); +template void ARMv7DisAsm::UQSUB16(const u32, const u32); +template void ARMv7DisAsm::UQSUB16(const u32, const u32); +template void ARMv7DisAsm::UQSUB8(const u32, const u32); +template void ARMv7DisAsm::UQSUB8(const u32, const u32); +template void ARMv7DisAsm::USAD8(const u32, const u32); +template void ARMv7DisAsm::USAD8(const u32, const u32); +template void ARMv7DisAsm::USADA8(const u32, const u32); +template void ARMv7DisAsm::USADA8(const u32, const u32); +template void ARMv7DisAsm::USAT(const u32, const u32); +template void ARMv7DisAsm::USAT(const u32, const u32); +template void ARMv7DisAsm::USAT16(const u32, const u32); +template void ARMv7DisAsm::USAT16(const u32, const u32); +template void ARMv7DisAsm::USAX(const u32, const u32); +template void ARMv7DisAsm::USAX(const u32, const u32); +template void ARMv7DisAsm::USUB16(const u32, const u32); +template void ARMv7DisAsm::USUB16(const u32, const u32); +template void ARMv7DisAsm::USUB8(const u32, const u32); +template void ARMv7DisAsm::USUB8(const u32, const u32); +template void ARMv7DisAsm::UXTAB(const u32, const u32); +template void ARMv7DisAsm::UXTAB(const u32, const u32); +template void ARMv7DisAsm::UXTAB16(const u32, const u32); +template void ARMv7DisAsm::UXTAB16(const u32, const u32); +template void ARMv7DisAsm::UXTAH(const u32, const u32); +template void ARMv7DisAsm::UXTAH(const u32, const u32); +template void ARMv7DisAsm::UXTB(const u32, const u32); +template void ARMv7DisAsm::UXTB(const u32, const u32); +template void ARMv7DisAsm::UXTB(const u32, const u32); +template void ARMv7DisAsm::UXTB16(const u32, const u32); +template void ARMv7DisAsm::UXTB16(const u32, const u32); +template void ARMv7DisAsm::UXTH(const u32, const u32); +template void ARMv7DisAsm::UXTH(const u32, const u32); +template void ARMv7DisAsm::UXTH(const u32, const u32); +template void ARMv7DisAsm::VABA_(const u32, const u32); +template void ARMv7DisAsm::VABA_(const u32, const u32); +template void ARMv7DisAsm::VABA_(const u32, const u32); +template void ARMv7DisAsm::VABA_(const u32, const u32); +template void ARMv7DisAsm::VABD_(const u32, const u32); +template void ARMv7DisAsm::VABD_(const u32, const u32); +template void ARMv7DisAsm::VABD_(const u32, const u32); +template void ARMv7DisAsm::VABD_(const u32, const u32); +template void ARMv7DisAsm::VABD_FP(const u32, const u32); +template void ARMv7DisAsm::VABD_FP(const u32, const u32); +template void ARMv7DisAsm::VABS(const u32, const u32); +template void ARMv7DisAsm::VABS(const u32, const u32); +template void ARMv7DisAsm::VABS(const u32, const u32); +template void ARMv7DisAsm::VABS(const u32, const u32); +template void ARMv7DisAsm::VAC__(const u32, const u32); +template void ARMv7DisAsm::VAC__(const u32, const u32); +template void ARMv7DisAsm::VADD(const u32, const u32); +template void ARMv7DisAsm::VADD(const u32, const u32); +template void ARMv7DisAsm::VADD_FP(const u32, const u32); +template void ARMv7DisAsm::VADD_FP(const u32, const u32); +template void ARMv7DisAsm::VADD_FP(const u32, const u32); +template void ARMv7DisAsm::VADD_FP(const u32, const u32); +template void ARMv7DisAsm::VADDHN(const u32, const u32); +template void ARMv7DisAsm::VADDHN(const u32, const u32); +template void ARMv7DisAsm::VADD_(const u32, const u32); +template void ARMv7DisAsm::VADD_(const u32, const u32); +template void ARMv7DisAsm::VAND(const u32, const u32); +template void ARMv7DisAsm::VAND(const u32, const u32); +template void ARMv7DisAsm::VBIC_IMM(const u32, const u32); +template void ARMv7DisAsm::VBIC_IMM(const u32, const u32); +template void ARMv7DisAsm::VBIC_REG(const u32, const u32); +template void ARMv7DisAsm::VBIC_REG(const u32, const u32); +template void ARMv7DisAsm::VB__(const u32, const u32); +template void ARMv7DisAsm::VB__(const u32, const u32); +template void ARMv7DisAsm::VCEQ_REG(const u32, const u32); +template void ARMv7DisAsm::VCEQ_REG(const u32, const u32); +template void ARMv7DisAsm::VCEQ_REG(const u32, const u32); +template void ARMv7DisAsm::VCEQ_REG(const u32, const u32); +template void ARMv7DisAsm::VCEQ_ZERO(const u32, const u32); +template void ARMv7DisAsm::VCEQ_ZERO(const u32, const u32); +template void ARMv7DisAsm::VCGE_REG(const u32, const u32); +template void ARMv7DisAsm::VCGE_REG(const u32, const u32); +template void ARMv7DisAsm::VCGE_REG(const u32, const u32); +template void ARMv7DisAsm::VCGE_REG(const u32, const u32); +template void ARMv7DisAsm::VCGE_ZERO(const u32, const u32); +template void ARMv7DisAsm::VCGE_ZERO(const u32, const u32); +template void ARMv7DisAsm::VCGT_REG(const u32, const u32); +template void ARMv7DisAsm::VCGT_REG(const u32, const u32); +template void ARMv7DisAsm::VCGT_REG(const u32, const u32); +template void ARMv7DisAsm::VCGT_REG(const u32, const u32); +template void ARMv7DisAsm::VCGT_ZERO(const u32, const u32); +template void ARMv7DisAsm::VCGT_ZERO(const u32, const u32); +template void ARMv7DisAsm::VCLE_ZERO(const u32, const u32); +template void ARMv7DisAsm::VCLE_ZERO(const u32, const u32); +template void ARMv7DisAsm::VCLS(const u32, const u32); +template void ARMv7DisAsm::VCLS(const u32, const u32); +template void ARMv7DisAsm::VCLT_ZERO(const u32, const u32); +template void ARMv7DisAsm::VCLT_ZERO(const u32, const u32); +template void ARMv7DisAsm::VCLZ(const u32, const u32); +template void ARMv7DisAsm::VCLZ(const u32, const u32); +template void ARMv7DisAsm::VCMP_(const u32, const u32); +template void ARMv7DisAsm::VCMP_(const u32, const u32); +template void ARMv7DisAsm::VCMP_(const u32, const u32); +template void ARMv7DisAsm::VCMP_(const u32, const u32); +template void ARMv7DisAsm::VCNT(const u32, const u32); +template void ARMv7DisAsm::VCNT(const u32, const u32); +template void ARMv7DisAsm::VCVT_FIA(const u32, const u32); +template void ARMv7DisAsm::VCVT_FIA(const u32, const u32); +template void ARMv7DisAsm::VCVT_FIF(const u32, const u32); +template void ARMv7DisAsm::VCVT_FIF(const u32, const u32); +template void ARMv7DisAsm::VCVT_FFA(const u32, const u32); +template void ARMv7DisAsm::VCVT_FFA(const u32, const u32); +template void ARMv7DisAsm::VCVT_FFF(const u32, const u32); +template void ARMv7DisAsm::VCVT_FFF(const u32, const u32); +template void ARMv7DisAsm::VCVT_DF(const u32, const u32); +template void ARMv7DisAsm::VCVT_DF(const u32, const u32); +template void ARMv7DisAsm::VCVT_HFA(const u32, const u32); +template void ARMv7DisAsm::VCVT_HFA(const u32, const u32); +template void ARMv7DisAsm::VCVT_HFF(const u32, const u32); +template void ARMv7DisAsm::VCVT_HFF(const u32, const u32); +template void ARMv7DisAsm::VDIV(const u32, const u32); +template void ARMv7DisAsm::VDIV(const u32, const u32); +template void ARMv7DisAsm::VDUP_S(const u32, const u32); +template void ARMv7DisAsm::VDUP_S(const u32, const u32); +template void ARMv7DisAsm::VDUP_R(const u32, const u32); +template void ARMv7DisAsm::VDUP_R(const u32, const u32); +template void ARMv7DisAsm::VEOR(const u32, const u32); +template void ARMv7DisAsm::VEOR(const u32, const u32); +template void ARMv7DisAsm::VEXT(const u32, const u32); +template void ARMv7DisAsm::VEXT(const u32, const u32); +template void ARMv7DisAsm::VHADDSUB(const u32, const u32); +template void ARMv7DisAsm::VHADDSUB(const u32, const u32); +template void ARMv7DisAsm::VLD__MS(const u32, const u32); +template void ARMv7DisAsm::VLD__MS(const u32, const u32); +template void ARMv7DisAsm::VLD1_SAL(const u32, const u32); +template void ARMv7DisAsm::VLD1_SAL(const u32, const u32); +template void ARMv7DisAsm::VLD1_SL(const u32, const u32); +template void ARMv7DisAsm::VLD1_SL(const u32, const u32); +template void ARMv7DisAsm::VLD2_SAL(const u32, const u32); +template void ARMv7DisAsm::VLD2_SAL(const u32, const u32); +template void ARMv7DisAsm::VLD2_SL(const u32, const u32); +template void ARMv7DisAsm::VLD2_SL(const u32, const u32); +template void ARMv7DisAsm::VLD3_SAL(const u32, const u32); +template void ARMv7DisAsm::VLD3_SAL(const u32, const u32); +template void ARMv7DisAsm::VLD3_SL(const u32, const u32); +template void ARMv7DisAsm::VLD3_SL(const u32, const u32); +template void ARMv7DisAsm::VLD4_SAL(const u32, const u32); +template void ARMv7DisAsm::VLD4_SAL(const u32, const u32); +template void ARMv7DisAsm::VLD4_SL(const u32, const u32); +template void ARMv7DisAsm::VLD4_SL(const u32, const u32); +template void ARMv7DisAsm::VLDM(const u32, const u32); +template void ARMv7DisAsm::VLDM(const u32, const u32); +template void ARMv7DisAsm::VLDM(const u32, const u32); +template void ARMv7DisAsm::VLDM(const u32, const u32); +template void ARMv7DisAsm::VLDR(const u32, const u32); +template void ARMv7DisAsm::VLDR(const u32, const u32); +template void ARMv7DisAsm::VLDR(const u32, const u32); +template void ARMv7DisAsm::VLDR(const u32, const u32); +template void ARMv7DisAsm::VMAXMIN(const u32, const u32); +template void ARMv7DisAsm::VMAXMIN(const u32, const u32); +template void ARMv7DisAsm::VMAXMIN_FP(const u32, const u32); +template void ARMv7DisAsm::VMAXMIN_FP(const u32, const u32); +template void ARMv7DisAsm::VML__(const u32, const u32); +template void ARMv7DisAsm::VML__(const u32, const u32); +template void ARMv7DisAsm::VML__(const u32, const u32); +template void ARMv7DisAsm::VML__(const u32, const u32); +template void ARMv7DisAsm::VML__FP(const u32, const u32); +template void ARMv7DisAsm::VML__FP(const u32, const u32); +template void ARMv7DisAsm::VML__FP(const u32, const u32); +template void ARMv7DisAsm::VML__FP(const u32, const u32); +template void ARMv7DisAsm::VML__S(const u32, const u32); +template void ARMv7DisAsm::VML__S(const u32, const u32); +template void ARMv7DisAsm::VML__S(const u32, const u32); +template void ARMv7DisAsm::VML__S(const u32, const u32); +template void ARMv7DisAsm::VMOV_IMM(const u32, const u32); +template void ARMv7DisAsm::VMOV_IMM(const u32, const u32); +template void ARMv7DisAsm::VMOV_IMM(const u32, const u32); +template void ARMv7DisAsm::VMOV_IMM(const u32, const u32); +template void ARMv7DisAsm::VMOV_REG(const u32, const u32); +template void ARMv7DisAsm::VMOV_REG(const u32, const u32); +template void ARMv7DisAsm::VMOV_REG(const u32, const u32); +template void ARMv7DisAsm::VMOV_REG(const u32, const u32); +template void ARMv7DisAsm::VMOV_RS(const u32, const u32); +template void ARMv7DisAsm::VMOV_RS(const u32, const u32); +template void ARMv7DisAsm::VMOV_SR(const u32, const u32); +template void ARMv7DisAsm::VMOV_SR(const u32, const u32); +template void ARMv7DisAsm::VMOV_RF(const u32, const u32); +template void ARMv7DisAsm::VMOV_RF(const u32, const u32); +template void ARMv7DisAsm::VMOV_2RF(const u32, const u32); +template void ARMv7DisAsm::VMOV_2RF(const u32, const u32); +template void ARMv7DisAsm::VMOV_2RD(const u32, const u32); +template void ARMv7DisAsm::VMOV_2RD(const u32, const u32); +template void ARMv7DisAsm::VMOVL(const u32, const u32); +template void ARMv7DisAsm::VMOVL(const u32, const u32); +template void ARMv7DisAsm::VMOVN(const u32, const u32); +template void ARMv7DisAsm::VMOVN(const u32, const u32); +template void ARMv7DisAsm::VMRS(const u32, const u32); +template void ARMv7DisAsm::VMRS(const u32, const u32); +template void ARMv7DisAsm::VMSR(const u32, const u32); +template void ARMv7DisAsm::VMSR(const u32, const u32); +template void ARMv7DisAsm::VMUL_(const u32, const u32); +template void ARMv7DisAsm::VMUL_(const u32, const u32); +template void ARMv7DisAsm::VMUL_(const u32, const u32); +template void ARMv7DisAsm::VMUL_(const u32, const u32); +template void ARMv7DisAsm::VMUL_FP(const u32, const u32); +template void ARMv7DisAsm::VMUL_FP(const u32, const u32); +template void ARMv7DisAsm::VMUL_FP(const u32, const u32); +template void ARMv7DisAsm::VMUL_FP(const u32, const u32); +template void ARMv7DisAsm::VMUL_S(const u32, const u32); +template void ARMv7DisAsm::VMUL_S(const u32, const u32); +template void ARMv7DisAsm::VMUL_S(const u32, const u32); +template void ARMv7DisAsm::VMUL_S(const u32, const u32); +template void ARMv7DisAsm::VMVN_IMM(const u32, const u32); +template void ARMv7DisAsm::VMVN_IMM(const u32, const u32); +template void ARMv7DisAsm::VMVN_REG(const u32, const u32); +template void ARMv7DisAsm::VMVN_REG(const u32, const u32); +template void ARMv7DisAsm::VNEG(const u32, const u32); +template void ARMv7DisAsm::VNEG(const u32, const u32); +template void ARMv7DisAsm::VNEG(const u32, const u32); +template void ARMv7DisAsm::VNEG(const u32, const u32); +template void ARMv7DisAsm::VNM__(const u32, const u32); +template void ARMv7DisAsm::VNM__(const u32, const u32); +template void ARMv7DisAsm::VNM__(const u32, const u32); +template void ARMv7DisAsm::VNM__(const u32, const u32); +template void ARMv7DisAsm::VORN_REG(const u32, const u32); +template void ARMv7DisAsm::VORN_REG(const u32, const u32); +template void ARMv7DisAsm::VORR_IMM(const u32, const u32); +template void ARMv7DisAsm::VORR_IMM(const u32, const u32); +template void ARMv7DisAsm::VORR_REG(const u32, const u32); +template void ARMv7DisAsm::VORR_REG(const u32, const u32); +template void ARMv7DisAsm::VPADAL(const u32, const u32); +template void ARMv7DisAsm::VPADAL(const u32, const u32); +template void ARMv7DisAsm::VPADD(const u32, const u32); +template void ARMv7DisAsm::VPADD(const u32, const u32); +template void ARMv7DisAsm::VPADD_FP(const u32, const u32); +template void ARMv7DisAsm::VPADD_FP(const u32, const u32); +template void ARMv7DisAsm::VPADDL(const u32, const u32); +template void ARMv7DisAsm::VPADDL(const u32, const u32); +template void ARMv7DisAsm::VPMAXMIN(const u32, const u32); +template void ARMv7DisAsm::VPMAXMIN(const u32, const u32); +template void ARMv7DisAsm::VPMAXMIN_FP(const u32, const u32); +template void ARMv7DisAsm::VPMAXMIN_FP(const u32, const u32); +template void ARMv7DisAsm::VPOP(const u32, const u32); +template void ARMv7DisAsm::VPOP(const u32, const u32); +template void ARMv7DisAsm::VPOP(const u32, const u32); +template void ARMv7DisAsm::VPOP(const u32, const u32); +template void ARMv7DisAsm::VPUSH(const u32, const u32); +template void ARMv7DisAsm::VPUSH(const u32, const u32); +template void ARMv7DisAsm::VPUSH(const u32, const u32); +template void ARMv7DisAsm::VPUSH(const u32, const u32); +template void ARMv7DisAsm::VQABS(const u32, const u32); +template void ARMv7DisAsm::VQABS(const u32, const u32); +template void ARMv7DisAsm::VQADD(const u32, const u32); +template void ARMv7DisAsm::VQADD(const u32, const u32); +template void ARMv7DisAsm::VQDML_L(const u32, const u32); +template void ARMv7DisAsm::VQDML_L(const u32, const u32); +template void ARMv7DisAsm::VQDML_L(const u32, const u32); +template void ARMv7DisAsm::VQDML_L(const u32, const u32); +template void ARMv7DisAsm::VQDMULH(const u32, const u32); +template void ARMv7DisAsm::VQDMULH(const u32, const u32); +template void ARMv7DisAsm::VQDMULH(const u32, const u32); +template void ARMv7DisAsm::VQDMULH(const u32, const u32); +template void ARMv7DisAsm::VQDMULL(const u32, const u32); +template void ARMv7DisAsm::VQDMULL(const u32, const u32); +template void ARMv7DisAsm::VQDMULL(const u32, const u32); +template void ARMv7DisAsm::VQDMULL(const u32, const u32); +template void ARMv7DisAsm::VQMOV_N(const u32, const u32); +template void ARMv7DisAsm::VQMOV_N(const u32, const u32); +template void ARMv7DisAsm::VQNEG(const u32, const u32); +template void ARMv7DisAsm::VQNEG(const u32, const u32); +template void ARMv7DisAsm::VQRDMULH(const u32, const u32); +template void ARMv7DisAsm::VQRDMULH(const u32, const u32); +template void ARMv7DisAsm::VQRDMULH(const u32, const u32); +template void ARMv7DisAsm::VQRDMULH(const u32, const u32); +template void ARMv7DisAsm::VQRSHL(const u32, const u32); +template void ARMv7DisAsm::VQRSHL(const u32, const u32); +template void ARMv7DisAsm::VQRSHR_N(const u32, const u32); +template void ARMv7DisAsm::VQRSHR_N(const u32, const u32); +template void ARMv7DisAsm::VQSHL_REG(const u32, const u32); +template void ARMv7DisAsm::VQSHL_REG(const u32, const u32); +template void ARMv7DisAsm::VQSHL_IMM(const u32, const u32); +template void ARMv7DisAsm::VQSHL_IMM(const u32, const u32); +template void ARMv7DisAsm::VQSHR_N(const u32, const u32); +template void ARMv7DisAsm::VQSHR_N(const u32, const u32); +template void ARMv7DisAsm::VQSUB(const u32, const u32); +template void ARMv7DisAsm::VQSUB(const u32, const u32); +template void ARMv7DisAsm::VRADDHN(const u32, const u32); +template void ARMv7DisAsm::VRADDHN(const u32, const u32); +template void ARMv7DisAsm::VRECPE(const u32, const u32); +template void ARMv7DisAsm::VRECPE(const u32, const u32); +template void ARMv7DisAsm::VRECPS(const u32, const u32); +template void ARMv7DisAsm::VRECPS(const u32, const u32); +template void ARMv7DisAsm::VREV__(const u32, const u32); +template void ARMv7DisAsm::VREV__(const u32, const u32); +template void ARMv7DisAsm::VRHADD(const u32, const u32); +template void ARMv7DisAsm::VRHADD(const u32, const u32); +template void ARMv7DisAsm::VRSHL(const u32, const u32); +template void ARMv7DisAsm::VRSHL(const u32, const u32); +template void ARMv7DisAsm::VRSHR(const u32, const u32); +template void ARMv7DisAsm::VRSHR(const u32, const u32); +template void ARMv7DisAsm::VRSHRN(const u32, const u32); +template void ARMv7DisAsm::VRSHRN(const u32, const u32); +template void ARMv7DisAsm::VRSQRTE(const u32, const u32); +template void ARMv7DisAsm::VRSQRTE(const u32, const u32); +template void ARMv7DisAsm::VRSQRTS(const u32, const u32); +template void ARMv7DisAsm::VRSQRTS(const u32, const u32); +template void ARMv7DisAsm::VRSRA(const u32, const u32); +template void ARMv7DisAsm::VRSRA(const u32, const u32); +template void ARMv7DisAsm::VRSUBHN(const u32, const u32); +template void ARMv7DisAsm::VRSUBHN(const u32, const u32); +template void ARMv7DisAsm::VSHL_IMM(const u32, const u32); +template void ARMv7DisAsm::VSHL_IMM(const u32, const u32); +template void ARMv7DisAsm::VSHL_REG(const u32, const u32); +template void ARMv7DisAsm::VSHL_REG(const u32, const u32); +template void ARMv7DisAsm::VSHLL(const u32, const u32); +template void ARMv7DisAsm::VSHLL(const u32, const u32); +template void ARMv7DisAsm::VSHLL(const u32, const u32); +template void ARMv7DisAsm::VSHLL(const u32, const u32); +template void ARMv7DisAsm::VSHR(const u32, const u32); +template void ARMv7DisAsm::VSHR(const u32, const u32); +template void ARMv7DisAsm::VSHRN(const u32, const u32); +template void ARMv7DisAsm::VSHRN(const u32, const u32); +template void ARMv7DisAsm::VSLI(const u32, const u32); +template void ARMv7DisAsm::VSLI(const u32, const u32); +template void ARMv7DisAsm::VSQRT(const u32, const u32); +template void ARMv7DisAsm::VSQRT(const u32, const u32); +template void ARMv7DisAsm::VSRA(const u32, const u32); +template void ARMv7DisAsm::VSRA(const u32, const u32); +template void ARMv7DisAsm::VSRI(const u32, const u32); +template void ARMv7DisAsm::VSRI(const u32, const u32); +template void ARMv7DisAsm::VST__MS(const u32, const u32); +template void ARMv7DisAsm::VST__MS(const u32, const u32); +template void ARMv7DisAsm::VST1_SL(const u32, const u32); +template void ARMv7DisAsm::VST1_SL(const u32, const u32); +template void ARMv7DisAsm::VST2_SL(const u32, const u32); +template void ARMv7DisAsm::VST2_SL(const u32, const u32); +template void ARMv7DisAsm::VST3_SL(const u32, const u32); +template void ARMv7DisAsm::VST3_SL(const u32, const u32); +template void ARMv7DisAsm::VST4_SL(const u32, const u32); +template void ARMv7DisAsm::VST4_SL(const u32, const u32); +template void ARMv7DisAsm::VSTM(const u32, const u32); +template void ARMv7DisAsm::VSTM(const u32, const u32); +template void ARMv7DisAsm::VSTM(const u32, const u32); +template void ARMv7DisAsm::VSTM(const u32, const u32); +template void ARMv7DisAsm::VSTR(const u32, const u32); +template void ARMv7DisAsm::VSTR(const u32, const u32); +template void ARMv7DisAsm::VSTR(const u32, const u32); +template void ARMv7DisAsm::VSTR(const u32, const u32); +template void ARMv7DisAsm::VSUB(const u32, const u32); +template void ARMv7DisAsm::VSUB(const u32, const u32); +template void ARMv7DisAsm::VSUB_FP(const u32, const u32); +template void ARMv7DisAsm::VSUB_FP(const u32, const u32); +template void ARMv7DisAsm::VSUB_FP(const u32, const u32); +template void ARMv7DisAsm::VSUB_FP(const u32, const u32); +template void ARMv7DisAsm::VSUBHN(const u32, const u32); +template void ARMv7DisAsm::VSUBHN(const u32, const u32); +template void ARMv7DisAsm::VSUB_(const u32, const u32); +template void ARMv7DisAsm::VSUB_(const u32, const u32); +template void ARMv7DisAsm::VSWP(const u32, const u32); +template void ARMv7DisAsm::VSWP(const u32, const u32); +template void ARMv7DisAsm::VTB_(const u32, const u32); +template void ARMv7DisAsm::VTB_(const u32, const u32); +template void ARMv7DisAsm::VTRN(const u32, const u32); +template void ARMv7DisAsm::VTRN(const u32, const u32); +template void ARMv7DisAsm::VTST(const u32, const u32); +template void ARMv7DisAsm::VTST(const u32, const u32); +template void ARMv7DisAsm::VUZP(const u32, const u32); +template void ARMv7DisAsm::VUZP(const u32, const u32); +template void ARMv7DisAsm::VZIP(const u32, const u32); +template void ARMv7DisAsm::VZIP(const u32, const u32); +template void ARMv7DisAsm::WFE(const u32, const u32); +template void ARMv7DisAsm::WFE(const u32, const u32); +template void ARMv7DisAsm::WFE(const u32, const u32); +template void ARMv7DisAsm::WFI(const u32, const u32); +template void ARMv7DisAsm::WFI(const u32, const u32); +template void ARMv7DisAsm::WFI(const u32, const u32); +template void ARMv7DisAsm::YIELD(const u32, const u32); +template void ARMv7DisAsm::YIELD(const u32, const u32); +template void ARMv7DisAsm::YIELD(const u32, const u32); diff --git a/rpcs3/Emu/ARMv7/ARMv7DisAsm.h b/rpcs3/Emu/ARMv7/ARMv7DisAsm.h index 848baaf7cb..68b60dc20f 100644 --- a/rpcs3/Emu/ARMv7/ARMv7DisAsm.h +++ b/rpcs3/Emu/ARMv7/ARMv7DisAsm.h @@ -1,328 +1,459 @@ #pragma once + #include "Emu/CPU/CPUDisAsm.h" -static const char* g_arm_cond_name[16] = -{ - "eq", "ne", "cs", "cc", - "mi", "pl", "vs", "vc", - "hi", "ls", "ge", "lt", - "gt", "le", "al", "al", -}; +enum class arm_encoding; -static const char* g_arm_reg_name[16] = -{ - "r0", "r1", "r2", "r3", - "r4", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", - "r12", "sp", "lr", "pc", -}; - -class ARMv7DisAsm - : public CPUDisAsm +class ARMv7DisAsm final : public CPUDisAsm { public: - ARMv7DisAsm() : CPUDisAsm(CPUDisAsm_InterpreterMode) + ARMv7DisAsm(CPUDisAsmMode mode) : CPUDisAsm(mode) { } protected: - virtual u32 DisAsmBranchTarget(const s32 imm) + virtual u32 DisAsmBranchTarget(const s32 imm) override { - return (u32)dump_pc + imm; + // TODO: ARM + return dump_pc + (true ? 4 : 8) + imm; } -#if 0 - std::string GetRegsListString(u16 regs_list) + virtual void Write(const std::string& value) override; + +private: + template + void write(const char* fmt, const Args&... args) { - std::string regs_str; - - for(u16 mask=0x1, i=0; mask; mask <<= 1, i++) - { - if(regs_list & mask) - { - if(!regs_str.empty()) - { - regs_str += ", "; - } - - regs_str += g_arm_reg_name[i]; - } - } - - return regs_str; + Write(fmt::format(fmt, args...)); } - virtual void UNK(const u32 data); +public: + void UNK(const u32 op, const u32 cond); - virtual void NULL_OP(const u32 data, const ARMv7_encoding type); + template void HACK(const u32, const u32); + template void MRC_(const u32, const u32); - virtual void HACK(const u32 data, const ARMv7_encoding type); + template void ADC_IMM(const u32, const u32); + template void ADC_REG(const u32, const u32); + template void ADC_RSR(const u32, const u32); - virtual void ADC_IMM(const u32 data, const ARMv7_encoding type); - virtual void ADC_REG(const u32 data, const ARMv7_encoding type); - virtual void ADC_RSR(const u32 data, const ARMv7_encoding type); + template void ADD_IMM(const u32, const u32); + template void ADD_REG(const u32, const u32); + template void ADD_RSR(const u32, const u32); + template void ADD_SPI(const u32, const u32); + template void ADD_SPR(const u32, const u32); - virtual void ADD_IMM(const u32 data, const ARMv7_encoding type); - virtual void ADD_REG(const u32 data, const ARMv7_encoding type); - virtual void ADD_RSR(const u32 data, const ARMv7_encoding type); - virtual void ADD_SPI(const u32 data, const ARMv7_encoding type); - virtual void ADD_SPR(const u32 data, const ARMv7_encoding type); + template void ADR(const u32, const u32); - virtual void ADR(const u32 data, const ARMv7_encoding type); + template void AND_IMM(const u32, const u32); + template void AND_REG(const u32, const u32); + template void AND_RSR(const u32, const u32); - virtual void AND_IMM(const u32 data, const ARMv7_encoding type); - virtual void AND_REG(const u32 data, const ARMv7_encoding type); - virtual void AND_RSR(const u32 data, const ARMv7_encoding type); + template void ASR_IMM(const u32, const u32); + template void ASR_REG(const u32, const u32); - virtual void ASR_IMM(const u32 data, const ARMv7_encoding type); - virtual void ASR_REG(const u32 data, const ARMv7_encoding type); + template void B(const u32, const u32); - virtual void B(const u32 data, const ARMv7_encoding type); + template void BFC(const u32, const u32); + template void BFI(const u32, const u32); - virtual void BFC(const u32 data, const ARMv7_encoding type); - virtual void BFI(const u32 data, const ARMv7_encoding type); + template void BIC_IMM(const u32, const u32); + template void BIC_REG(const u32, const u32); + template void BIC_RSR(const u32, const u32); - virtual void BIC_IMM(const u32 data, const ARMv7_encoding type); - virtual void BIC_REG(const u32 data, const ARMv7_encoding type); - virtual void BIC_RSR(const u32 data, const ARMv7_encoding type); + template void BKPT(const u32, const u32); - virtual void BKPT(const u32 data, const ARMv7_encoding type); + template void BL(const u32, const u32); + template void BLX(const u32, const u32); + template void BX(const u32, const u32); - virtual void BL(const u32 data, const ARMv7_encoding type); - virtual void BLX(const u32 data, const ARMv7_encoding type); - virtual void BX(const u32 data, const ARMv7_encoding type); + template void CB_Z(const u32, const u32); - virtual void CB_Z(const u32 data, const ARMv7_encoding type); + template void CLZ(const u32, const u32); - virtual void CLZ(const u32 data, const ARMv7_encoding type); + template void CMN_IMM(const u32, const u32); + template void CMN_REG(const u32, const u32); + template void CMN_RSR(const u32, const u32); - virtual void CMN_IMM(const u32 data, const ARMv7_encoding type); - virtual void CMN_REG(const u32 data, const ARMv7_encoding type); - virtual void CMN_RSR(const u32 data, const ARMv7_encoding type); + template void CMP_IMM(const u32, const u32); + template void CMP_REG(const u32, const u32); + template void CMP_RSR(const u32, const u32); - virtual void CMP_IMM(const u32 data, const ARMv7_encoding type); - virtual void CMP_REG(const u32 data, const ARMv7_encoding type); - virtual void CMP_RSR(const u32 data, const ARMv7_encoding type); + template void DBG(const u32, const u32); + template void DMB(const u32, const u32); + template void DSB(const u32, const u32); - virtual void EOR_IMM(const u32 data, const ARMv7_encoding type); - virtual void EOR_REG(const u32 data, const ARMv7_encoding type); - virtual void EOR_RSR(const u32 data, const ARMv7_encoding type); + template void EOR_IMM(const u32, const u32); + template void EOR_REG(const u32, const u32); + template void EOR_RSR(const u32, const u32); - virtual void IT(const u32 data, const ARMv7_encoding type); + template void IT(const u32, const u32); - virtual void LDM(const u32 data, const ARMv7_encoding type); - virtual void LDMDA(const u32 data, const ARMv7_encoding type); - virtual void LDMDB(const u32 data, const ARMv7_encoding type); - virtual void LDMIB(const u32 data, const ARMv7_encoding type); + template void LDM(const u32, const u32); + template void LDMDA(const u32, const u32); + template void LDMDB(const u32, const u32); + template void LDMIB(const u32, const u32); - virtual void LDR_IMM(const u32 data, const ARMv7_encoding type); - virtual void LDR_LIT(const u32 data, const ARMv7_encoding type); - virtual void LDR_REG(const u32 data, const ARMv7_encoding type); + template void LDR_IMM(const u32, const u32); + template void LDR_LIT(const u32, const u32); + template void LDR_REG(const u32, const u32); - virtual void LDRB_IMM(const u32 data, const ARMv7_encoding type); - virtual void LDRB_LIT(const u32 data, const ARMv7_encoding type); - virtual void LDRB_REG(const u32 data, const ARMv7_encoding type); + template void LDRB_IMM(const u32, const u32); + template void LDRB_LIT(const u32, const u32); + template void LDRB_REG(const u32, const u32); - virtual void LDRD_IMM(const u32 data, const ARMv7_encoding type); - virtual void LDRD_LIT(const u32 data, const ARMv7_encoding type); - virtual void LDRD_REG(const u32 data, const ARMv7_encoding type); + template void LDRD_IMM(const u32, const u32); + template void LDRD_LIT(const u32, const u32); + template void LDRD_REG(const u32, const u32); - virtual void LDRH_IMM(const u32 data, const ARMv7_encoding type); - virtual void LDRH_LIT(const u32 data, const ARMv7_encoding type); - virtual void LDRH_REG(const u32 data, const ARMv7_encoding type); + template void LDRH_IMM(const u32, const u32); + template void LDRH_LIT(const u32, const u32); + template void LDRH_REG(const u32, const u32); - virtual void LDRSB_IMM(const u32 data, const ARMv7_encoding type); - virtual void LDRSB_LIT(const u32 data, const ARMv7_encoding type); - virtual void LDRSB_REG(const u32 data, const ARMv7_encoding type); + template void LDRSB_IMM(const u32, const u32); + template void LDRSB_LIT(const u32, const u32); + template void LDRSB_REG(const u32, const u32); - virtual void LDRSH_IMM(const u32 data, const ARMv7_encoding type); - virtual void LDRSH_LIT(const u32 data, const ARMv7_encoding type); - virtual void LDRSH_REG(const u32 data, const ARMv7_encoding type); + template void LDRSH_IMM(const u32, const u32); + template void LDRSH_LIT(const u32, const u32); + template void LDRSH_REG(const u32, const u32); - virtual void LSL_IMM(const u32 data, const ARMv7_encoding type); - virtual void LSL_REG(const u32 data, const ARMv7_encoding type); + template void LDREX(const u32, const u32); + template void LDREXB(const u32, const u32); + template void LDREXD(const u32, const u32); + template void LDREXH(const u32, const u32); - virtual void LSR_IMM(const u32 data, const ARMv7_encoding type); - virtual void LSR_REG(const u32 data, const ARMv7_encoding type); + template void LSL_IMM(const u32, const u32); + template void LSL_REG(const u32, const u32); - virtual void MLA(const u32 data, const ARMv7_encoding type); - virtual void MLS(const u32 data, const ARMv7_encoding type); + template void LSR_IMM(const u32, const u32); + template void LSR_REG(const u32, const u32); - virtual void MOV_IMM(const u32 data, const ARMv7_encoding type); - virtual void MOV_REG(const u32 data, const ARMv7_encoding type); - virtual void MOVT(const u32 data, const ARMv7_encoding type); + template void MLA(const u32, const u32); + template void MLS(const u32, const u32); - virtual void MRS(const u32 data, const ARMv7_encoding type); - virtual void MSR_IMM(const u32 data, const ARMv7_encoding type); - virtual void MSR_REG(const u32 data, const ARMv7_encoding type); + template void MOV_IMM(const u32, const u32); + template void MOV_REG(const u32, const u32); + template void MOVT(const u32, const u32); - virtual void MUL(const u32 data, const ARMv7_encoding type); + template void MRS(const u32, const u32); + template void MSR_IMM(const u32, const u32); + template void MSR_REG(const u32, const u32); - virtual void MVN_IMM(const u32 data, const ARMv7_encoding type); - virtual void MVN_REG(const u32 data, const ARMv7_encoding type); - virtual void MVN_RSR(const u32 data, const ARMv7_encoding type); + template void MUL(const u32, const u32); - virtual void NOP(const u32 data, const ARMv7_encoding type); + template void MVN_IMM(const u32, const u32); + template void MVN_REG(const u32, const u32); + template void MVN_RSR(const u32, const u32); - virtual void ORN_IMM(const u32 data, const ARMv7_encoding type); - virtual void ORN_REG(const u32 data, const ARMv7_encoding type); + template void NOP(const u32, const u32); - virtual void ORR_IMM(const u32 data, const ARMv7_encoding type); - virtual void ORR_REG(const u32 data, const ARMv7_encoding type); - virtual void ORR_RSR(const u32 data, const ARMv7_encoding type); + template void ORN_IMM(const u32, const u32); + template void ORN_REG(const u32, const u32); - virtual void PKH(const u32 data, const ARMv7_encoding type); + template void ORR_IMM(const u32, const u32); + template void ORR_REG(const u32, const u32); + template void ORR_RSR(const u32, const u32); - virtual void POP(const u32 data, const ARMv7_encoding type); - virtual void PUSH(const u32 data, const ARMv7_encoding type); + template void PKH(const u32, const u32); - virtual void QADD(const u32 data, const ARMv7_encoding type); - virtual void QADD16(const u32 data, const ARMv7_encoding type); - virtual void QADD8(const u32 data, const ARMv7_encoding type); - virtual void QASX(const u32 data, const ARMv7_encoding type); - virtual void QDADD(const u32 data, const ARMv7_encoding type); - virtual void QDSUB(const u32 data, const ARMv7_encoding type); - virtual void QSAX(const u32 data, const ARMv7_encoding type); - virtual void QSUB(const u32 data, const ARMv7_encoding type); - virtual void QSUB16(const u32 data, const ARMv7_encoding type); - virtual void QSUB8(const u32 data, const ARMv7_encoding type); + template void POP(const u32, const u32); + template void PUSH(const u32, const u32); - virtual void RBIT(const u32 data, const ARMv7_encoding type); - virtual void REV(const u32 data, const ARMv7_encoding type); - virtual void REV16(const u32 data, const ARMv7_encoding type); - virtual void REVSH(const u32 data, const ARMv7_encoding type); + template void QADD(const u32, const u32); + template void QADD16(const u32, const u32); + template void QADD8(const u32, const u32); + template void QASX(const u32, const u32); + template void QDADD(const u32, const u32); + template void QDSUB(const u32, const u32); + template void QSAX(const u32, const u32); + template void QSUB(const u32, const u32); + template void QSUB16(const u32, const u32); + template void QSUB8(const u32, const u32); - virtual void ROR_IMM(const u32 data, const ARMv7_encoding type); - virtual void ROR_REG(const u32 data, const ARMv7_encoding type); + template void RBIT(const u32, const u32); + template void REV(const u32, const u32); + template void REV16(const u32, const u32); + template void REVSH(const u32, const u32); - virtual void RRX(const u32 data, const ARMv7_encoding type); + template void ROR_IMM(const u32, const u32); + template void ROR_REG(const u32, const u32); - virtual void RSB_IMM(const u32 data, const ARMv7_encoding type); - virtual void RSB_REG(const u32 data, const ARMv7_encoding type); - virtual void RSB_RSR(const u32 data, const ARMv7_encoding type); + template void RRX(const u32, const u32); - virtual void RSC_IMM(const u32 data, const ARMv7_encoding type); - virtual void RSC_REG(const u32 data, const ARMv7_encoding type); - virtual void RSC_RSR(const u32 data, const ARMv7_encoding type); + template void RSB_IMM(const u32, const u32); + template void RSB_REG(const u32, const u32); + template void RSB_RSR(const u32, const u32); - virtual void SADD16(const u32 data, const ARMv7_encoding type); - virtual void SADD8(const u32 data, const ARMv7_encoding type); - virtual void SASX(const u32 data, const ARMv7_encoding type); + template void RSC_IMM(const u32, const u32); + template void RSC_REG(const u32, const u32); + template void RSC_RSR(const u32, const u32); - virtual void SBC_IMM(const u32 data, const ARMv7_encoding type); - virtual void SBC_REG(const u32 data, const ARMv7_encoding type); - virtual void SBC_RSR(const u32 data, const ARMv7_encoding type); + template void SADD16(const u32, const u32); + template void SADD8(const u32, const u32); + template void SASX(const u32, const u32); - virtual void SBFX(const u32 data, const ARMv7_encoding type); + template void SBC_IMM(const u32, const u32); + template void SBC_REG(const u32, const u32); + template void SBC_RSR(const u32, const u32); - virtual void SDIV(const u32 data, const ARMv7_encoding type); + template void SBFX(const u32, const u32); - virtual void SEL(const u32 data, const ARMv7_encoding type); + template void SDIV(const u32, const u32); - virtual void SHADD16(const u32 data, const ARMv7_encoding type); - virtual void SHADD8(const u32 data, const ARMv7_encoding type); - virtual void SHASX(const u32 data, const ARMv7_encoding type); - virtual void SHSAX(const u32 data, const ARMv7_encoding type); - virtual void SHSUB16(const u32 data, const ARMv7_encoding type); - virtual void SHSUB8(const u32 data, const ARMv7_encoding type); + template void SEL(const u32, const u32); - virtual void SMLA__(const u32 data, const ARMv7_encoding type); - virtual void SMLAD(const u32 data, const ARMv7_encoding type); - virtual void SMLAL(const u32 data, const ARMv7_encoding type); - virtual void SMLAL__(const u32 data, const ARMv7_encoding type); - virtual void SMLALD(const u32 data, const ARMv7_encoding type); - virtual void SMLAW_(const u32 data, const ARMv7_encoding type); - virtual void SMLSD(const u32 data, const ARMv7_encoding type); - virtual void SMLSLD(const u32 data, const ARMv7_encoding type); - virtual void SMMLA(const u32 data, const ARMv7_encoding type); - virtual void SMMLS(const u32 data, const ARMv7_encoding type); - virtual void SMMUL(const u32 data, const ARMv7_encoding type); - virtual void SMUAD(const u32 data, const ARMv7_encoding type); - virtual void SMUL__(const u32 data, const ARMv7_encoding type); - virtual void SMULL(const u32 data, const ARMv7_encoding type); - virtual void SMULW_(const u32 data, const ARMv7_encoding type); - virtual void SMUSD(const u32 data, const ARMv7_encoding type); + template void SHADD16(const u32, const u32); + template void SHADD8(const u32, const u32); + template void SHASX(const u32, const u32); + template void SHSAX(const u32, const u32); + template void SHSUB16(const u32, const u32); + template void SHSUB8(const u32, const u32); - virtual void SSAT(const u32 data, const ARMv7_encoding type); - virtual void SSAT16(const u32 data, const ARMv7_encoding type); - virtual void SSAX(const u32 data, const ARMv7_encoding type); - virtual void SSUB16(const u32 data, const ARMv7_encoding type); - virtual void SSUB8(const u32 data, const ARMv7_encoding type); + template void SMLA__(const u32, const u32); + template void SMLAD(const u32, const u32); + template void SMLAL(const u32, const u32); + template void SMLAL__(const u32, const u32); + template void SMLALD(const u32, const u32); + template void SMLAW_(const u32, const u32); + template void SMLSD(const u32, const u32); + template void SMLSLD(const u32, const u32); + template void SMMLA(const u32, const u32); + template void SMMLS(const u32, const u32); + template void SMMUL(const u32, const u32); + template void SMUAD(const u32, const u32); + template void SMUL__(const u32, const u32); + template void SMULL(const u32, const u32); + template void SMULW_(const u32, const u32); + template void SMUSD(const u32, const u32); - virtual void STM(const u32 data, const ARMv7_encoding type); - virtual void STMDA(const u32 data, const ARMv7_encoding type); - virtual void STMDB(const u32 data, const ARMv7_encoding type); - virtual void STMIB(const u32 data, const ARMv7_encoding type); + template void SSAT(const u32, const u32); + template void SSAT16(const u32, const u32); + template void SSAX(const u32, const u32); + template void SSUB16(const u32, const u32); + template void SSUB8(const u32, const u32); - virtual void STR_IMM(const u32 data, const ARMv7_encoding type); - virtual void STR_REG(const u32 data, const ARMv7_encoding type); + template void STM(const u32, const u32); + template void STMDA(const u32, const u32); + template void STMDB(const u32, const u32); + template void STMIB(const u32, const u32); - virtual void STRB_IMM(const u32 data, const ARMv7_encoding type); - virtual void STRB_REG(const u32 data, const ARMv7_encoding type); + template void STR_IMM(const u32, const u32); + template void STR_REG(const u32, const u32); - virtual void STRD_IMM(const u32 data, const ARMv7_encoding type); - virtual void STRD_REG(const u32 data, const ARMv7_encoding type); + template void STRB_IMM(const u32, const u32); + template void STRB_REG(const u32, const u32); - virtual void STRH_IMM(const u32 data, const ARMv7_encoding type); - virtual void STRH_REG(const u32 data, const ARMv7_encoding type); + template void STRD_IMM(const u32, const u32); + template void STRD_REG(const u32, const u32); - virtual void SUB_IMM(const u32 data, const ARMv7_encoding type); - virtual void SUB_REG(const u32 data, const ARMv7_encoding type); - virtual void SUB_RSR(const u32 data, const ARMv7_encoding type); - virtual void SUB_SPI(const u32 data, const ARMv7_encoding type); - virtual void SUB_SPR(const u32 data, const ARMv7_encoding type); + template void STRH_IMM(const u32, const u32); + template void STRH_REG(const u32, const u32); - virtual void SVC(const u32 data, const ARMv7_encoding type); + template void STREX(const u32, const u32); + template void STREXB(const u32, const u32); + template void STREXD(const u32, const u32); + template void STREXH(const u32, const u32); - virtual void SXTAB(const u32 data, const ARMv7_encoding type); - virtual void SXTAB16(const u32 data, const ARMv7_encoding type); - virtual void SXTAH(const u32 data, const ARMv7_encoding type); - virtual void SXTB(const u32 data, const ARMv7_encoding type); - virtual void SXTB16(const u32 data, const ARMv7_encoding type); - virtual void SXTH(const u32 data, const ARMv7_encoding type); + template void SUB_IMM(const u32, const u32); + template void SUB_REG(const u32, const u32); + template void SUB_RSR(const u32, const u32); + template void SUB_SPI(const u32, const u32); + template void SUB_SPR(const u32, const u32); - virtual void TB_(const u32 data, const ARMv7_encoding type); + template void SVC(const u32, const u32); - virtual void TEQ_IMM(const u32 data, const ARMv7_encoding type); - virtual void TEQ_REG(const u32 data, const ARMv7_encoding type); - virtual void TEQ_RSR(const u32 data, const ARMv7_encoding type); + template void SXTAB(const u32, const u32); + template void SXTAB16(const u32, const u32); + template void SXTAH(const u32, const u32); + template void SXTB(const u32, const u32); + template void SXTB16(const u32, const u32); + template void SXTH(const u32, const u32); - virtual void TST_IMM(const u32 data, const ARMv7_encoding type); - virtual void TST_REG(const u32 data, const ARMv7_encoding type); - virtual void TST_RSR(const u32 data, const ARMv7_encoding type); + template void TB_(const u32, const u32); - virtual void UADD16(const u32 data, const ARMv7_encoding type); - virtual void UADD8(const u32 data, const ARMv7_encoding type); - virtual void UASX(const u32 data, const ARMv7_encoding type); - virtual void UBFX(const u32 data, const ARMv7_encoding type); - virtual void UDIV(const u32 data, const ARMv7_encoding type); - virtual void UHADD16(const u32 data, const ARMv7_encoding type); - virtual void UHADD8(const u32 data, const ARMv7_encoding type); - virtual void UHASX(const u32 data, const ARMv7_encoding type); - virtual void UHSAX(const u32 data, const ARMv7_encoding type); - virtual void UHSUB16(const u32 data, const ARMv7_encoding type); - virtual void UHSUB8(const u32 data, const ARMv7_encoding type); - virtual void UMAAL(const u32 data, const ARMv7_encoding type); - virtual void UMLAL(const u32 data, const ARMv7_encoding type); - virtual void UMULL(const u32 data, const ARMv7_encoding type); - virtual void UQADD16(const u32 data, const ARMv7_encoding type); - virtual void UQADD8(const u32 data, const ARMv7_encoding type); - virtual void UQASX(const u32 data, const ARMv7_encoding type); - virtual void UQSAX(const u32 data, const ARMv7_encoding type); - virtual void UQSUB16(const u32 data, const ARMv7_encoding type); - virtual void UQSUB8(const u32 data, const ARMv7_encoding type); - virtual void USAD8(const u32 data, const ARMv7_encoding type); - virtual void USADA8(const u32 data, const ARMv7_encoding type); - virtual void USAT(const u32 data, const ARMv7_encoding type); - virtual void USAT16(const u32 data, const ARMv7_encoding type); - virtual void USAX(const u32 data, const ARMv7_encoding type); - virtual void USUB16(const u32 data, const ARMv7_encoding type); - virtual void USUB8(const u32 data, const ARMv7_encoding type); - virtual void UXTAB(const u32 data, const ARMv7_encoding type); - virtual void UXTAB16(const u32 data, const ARMv7_encoding type); - virtual void UXTAH(const u32 data, const ARMv7_encoding type); - virtual void UXTB(const u32 data, const ARMv7_encoding type); - virtual void UXTB16(const u32 data, const ARMv7_encoding type); - virtual void UXTH(const u32 data, const ARMv7_encoding type); -#endif + template void TEQ_IMM(const u32, const u32); + template void TEQ_REG(const u32, const u32); + template void TEQ_RSR(const u32, const u32); + + template void TST_IMM(const u32, const u32); + template void TST_REG(const u32, const u32); + template void TST_RSR(const u32, const u32); + + template void UADD16(const u32, const u32); + template void UADD8(const u32, const u32); + template void UASX(const u32, const u32); + template void UBFX(const u32, const u32); + template void UDIV(const u32, const u32); + template void UHADD16(const u32, const u32); + template void UHADD8(const u32, const u32); + template void UHASX(const u32, const u32); + template void UHSAX(const u32, const u32); + template void UHSUB16(const u32, const u32); + template void UHSUB8(const u32, const u32); + template void UMAAL(const u32, const u32); + template void UMLAL(const u32, const u32); + template void UMULL(const u32, const u32); + template void UQADD16(const u32, const u32); + template void UQADD8(const u32, const u32); + template void UQASX(const u32, const u32); + template void UQSAX(const u32, const u32); + template void UQSUB16(const u32, const u32); + template void UQSUB8(const u32, const u32); + template void USAD8(const u32, const u32); + template void USADA8(const u32, const u32); + template void USAT(const u32, const u32); + template void USAT16(const u32, const u32); + template void USAX(const u32, const u32); + template void USUB16(const u32, const u32); + template void USUB8(const u32, const u32); + template void UXTAB(const u32, const u32); + template void UXTAB16(const u32, const u32); + template void UXTAH(const u32, const u32); + template void UXTB(const u32, const u32); + template void UXTB16(const u32, const u32); + template void UXTH(const u32, const u32); + + template void VABA_(const u32, const u32); + template void VABD_(const u32, const u32); + template void VABD_FP(const u32, const u32); + template void VABS(const u32, const u32); + template void VAC__(const u32, const u32); + template void VADD(const u32, const u32); + template void VADD_FP(const u32, const u32); + template void VADDHN(const u32, const u32); + template void VADD_(const u32, const u32); + template void VAND(const u32, const u32); + template void VBIC_IMM(const u32, const u32); + template void VBIC_REG(const u32, const u32); + template void VB__(const u32, const u32); + template void VCEQ_REG(const u32, const u32); + template void VCEQ_ZERO(const u32, const u32); + template void VCGE_REG(const u32, const u32); + template void VCGE_ZERO(const u32, const u32); + template void VCGT_REG(const u32, const u32); + template void VCGT_ZERO(const u32, const u32); + template void VCLE_ZERO(const u32, const u32); + template void VCLS(const u32, const u32); + template void VCLT_ZERO(const u32, const u32); + template void VCLZ(const u32, const u32); + template void VCMP_(const u32, const u32); + template void VCNT(const u32, const u32); + template void VCVT_FIA(const u32, const u32); + template void VCVT_FIF(const u32, const u32); + template void VCVT_FFA(const u32, const u32); + template void VCVT_FFF(const u32, const u32); + template void VCVT_DF(const u32, const u32); + template void VCVT_HFA(const u32, const u32); + template void VCVT_HFF(const u32, const u32); + template void VDIV(const u32, const u32); + template void VDUP_S(const u32, const u32); + template void VDUP_R(const u32, const u32); + template void VEOR(const u32, const u32); + template void VEXT(const u32, const u32); + template void VHADDSUB(const u32, const u32); + template void VLD__MS(const u32, const u32); + template void VLD1_SL(const u32, const u32); + template void VLD1_SAL(const u32, const u32); + template void VLD2_SL(const u32, const u32); + template void VLD2_SAL(const u32, const u32); + template void VLD3_SL(const u32, const u32); + template void VLD3_SAL(const u32, const u32); + template void VLD4_SL(const u32, const u32); + template void VLD4_SAL(const u32, const u32); + template void VLDM(const u32, const u32); + template void VLDR(const u32, const u32); + template void VMAXMIN(const u32, const u32); + template void VMAXMIN_FP(const u32, const u32); + template void VML__(const u32, const u32); + template void VML__FP(const u32, const u32); + template void VML__S(const u32, const u32); + template void VMOV_IMM(const u32, const u32); + template void VMOV_REG(const u32, const u32); + template void VMOV_RS(const u32, const u32); + template void VMOV_SR(const u32, const u32); + template void VMOV_RF(const u32, const u32); + template void VMOV_2RF(const u32, const u32); + template void VMOV_2RD(const u32, const u32); + template void VMOVL(const u32, const u32); + template void VMOVN(const u32, const u32); + template void VMRS(const u32, const u32); + template void VMSR(const u32, const u32); + template void VMUL_(const u32, const u32); + template void VMUL_FP(const u32, const u32); + template void VMUL_S(const u32, const u32); + template void VMVN_IMM(const u32, const u32); + template void VMVN_REG(const u32, const u32); + template void VNEG(const u32, const u32); + template void VNM__(const u32, const u32); + template void VORN_REG(const u32, const u32); + template void VORR_IMM(const u32, const u32); + template void VORR_REG(const u32, const u32); + template void VPADAL(const u32, const u32); + template void VPADD(const u32, const u32); + template void VPADD_FP(const u32, const u32); + template void VPADDL(const u32, const u32); + template void VPMAXMIN(const u32, const u32); + template void VPMAXMIN_FP(const u32, const u32); + template void VPOP(const u32, const u32); + template void VPUSH(const u32, const u32); + template void VQABS(const u32, const u32); + template void VQADD(const u32, const u32); + template void VQDML_L(const u32, const u32); + template void VQDMULH(const u32, const u32); + template void VQDMULL(const u32, const u32); + template void VQMOV_N(const u32, const u32); + template void VQNEG(const u32, const u32); + template void VQRDMULH(const u32, const u32); + template void VQRSHL(const u32, const u32); + template void VQRSHR_N(const u32, const u32); + template void VQSHL_REG(const u32, const u32); + template void VQSHL_IMM(const u32, const u32); + template void VQSHR_N(const u32, const u32); + template void VQSUB(const u32, const u32); + template void VRADDHN(const u32, const u32); + template void VRECPE(const u32, const u32); + template void VRECPS(const u32, const u32); + template void VREV__(const u32, const u32); + template void VRHADD(const u32, const u32); + template void VRSHL(const u32, const u32); + template void VRSHR(const u32, const u32); + template void VRSHRN(const u32, const u32); + template void VRSQRTE(const u32, const u32); + template void VRSQRTS(const u32, const u32); + template void VRSRA(const u32, const u32); + template void VRSUBHN(const u32, const u32); + template void VSHL_IMM(const u32, const u32); + template void VSHL_REG(const u32, const u32); + template void VSHLL(const u32, const u32); + template void VSHR(const u32, const u32); + template void VSHRN(const u32, const u32); + template void VSLI(const u32, const u32); + template void VSQRT(const u32, const u32); + template void VSRA(const u32, const u32); + template void VSRI(const u32, const u32); + template void VST__MS(const u32, const u32); + template void VST1_SL(const u32, const u32); + template void VST2_SL(const u32, const u32); + template void VST3_SL(const u32, const u32); + template void VST4_SL(const u32, const u32); + template void VSTM(const u32, const u32); + template void VSTR(const u32, const u32); + template void VSUB(const u32, const u32); + template void VSUB_FP(const u32, const u32); + template void VSUBHN(const u32, const u32); + template void VSUB_(const u32, const u32); + template void VSWP(const u32, const u32); + template void VTB_(const u32, const u32); + template void VTRN(const u32, const u32); + template void VTST(const u32, const u32); + template void VUZP(const u32, const u32); + template void VZIP(const u32, const u32); + + template void WFE(const u32, const u32); + template void WFI(const u32, const u32); + template void YIELD(const u32, const u32); + +public: + u32 disasm(u32 pc) override; }; diff --git a/rpcs3/Emu/ARMv7/ARMv7Function.cpp b/rpcs3/Emu/ARMv7/ARMv7Function.cpp new file mode 100644 index 0000000000..f61bc3486f --- /dev/null +++ b/rpcs3/Emu/ARMv7/ARMv7Function.cpp @@ -0,0 +1,59 @@ +#include "stdafx.h" +#include "ARMv7Module.h" + +// Get function name by FNID +extern std::string arm_get_function_name(const std::string& module, u32 fnid) +{ + // Check registered functions + if (const auto sm = arm_module_manager::get_module(module)) + { + const auto found = sm->functions.find(fnid); + + if (found != sm->functions.end()) + { + return found->second.name; + } + } + + return fmt::format("0x%08X", fnid); +} + +// Get variable name by VNID +extern std::string arm_get_variable_name(const std::string& module, u32 vnid) +{ + // Check registered variables + if (const auto sm = arm_module_manager::get_module(module)) + { + const auto found = sm->variables.find(vnid); + + if (found != sm->variables.end()) + { + return found->second.name; + } + } + + return fmt::format("0x%08X", vnid); +} + +s32 arm_error_code::report(s32 error, const char* text) +{ + if (auto thread = get_current_cpu_thread()) + { + if (thread->type == cpu_type::arm) + { + if (auto func = static_cast(thread)->last_function) + { + LOG_ERROR(ARMv7, "Function '%s' failed with 0x%08x : %s", func, error, text); + } + else + { + LOG_ERROR(ARMv7, "Unknown function failed with 0x%08x : %s", error, text); + } + + return error; + } + } + + LOG_ERROR(ARMv7, "Illegal call to ppu_report_error(0x%x, '%s')!"); + return error; +} diff --git a/rpcs3/Emu/ARMv7/ARMv7Function.h b/rpcs3/Emu/ARMv7/ARMv7Function.h new file mode 100644 index 0000000000..ebbf02a119 --- /dev/null +++ b/rpcs3/Emu/ARMv7/ARMv7Function.h @@ -0,0 +1,487 @@ +#pragma once + +#include "ARMv7Thread.h" + +using arm_function_t = void(*)(ARMv7Thread&); + +#define BIND_FUNC(func) [](ARMv7Thread& cpu){ cpu.last_function = #func; arm_func_detail::do_call(cpu, func); } + +struct arm_va_args_t +{ + u32 count; // Number of 32-bit args passed +}; + +namespace arm_func_detail +{ + enum arg_class : u32 + { + ARG_GENERAL, + ARG_FLOAT, + ARG_VECTOR, + ARG_STACK, + ARG_CONTEXT, + ARG_VARIADIC, + ARG_UNKNOWN, + }; + + static const auto FIXED_STACK_FRAME_SIZE = 0x80; + + template + struct bind_arg + { + static_assert(type == ARG_GENERAL, "Unknown function argument type"); + static_assert(!std::is_pointer::value, "Invalid function argument type (pointer)"); + static_assert(!std::is_reference::value, "Invalid function argument type (reference)"); + static_assert(sizeof(T) <= 4, "Invalid function argument type for ARG_GENERAL"); + + force_inline static T get_arg(ARMv7Thread& cpu) + { + return arm_gpr_cast(cpu.GPR[g_count - 1]); + } + + force_inline static void put_arg(ARMv7Thread& cpu, const T& arg) + { + cpu.GPR[g_count - 1] = arm_gpr_cast(arg); + } + }; + + template + struct bind_arg + { + // first u64 argument is passed in r0-r1, second one is passed in r2-r3 (if g_count = 3) + static_assert(g_count == 2 || g_count == 4, "Wrong u64 argument position"); + + force_inline static u64 get_arg(ARMv7Thread& cpu) + { + return cpu.GPR_D[(g_count - 1) >> 1]; + } + + force_inline static void put_arg(ARMv7Thread& cpu, u64 arg) + { + cpu.GPR_D[(g_count - 1) >> 1] = arg; + } + }; + + template + struct bind_arg + { + static_assert(g_count == 2 || g_count == 4, "Wrong s64 argument position"); + + force_inline static s64 get_arg(ARMv7Thread& cpu) + { + return cpu.GPR_D[(g_count - 1) >> 1]; + } + + force_inline static void put_arg(ARMv7Thread& cpu, s64 arg) + { + cpu.GPR_D[(g_count - 1) >> 1] = arg; + } + }; + + template + struct bind_arg + { + static_assert(f_count <= 0, "TODO: Unsupported argument type (float)"); + static_assert(sizeof(T) <= 8, "Invalid function argument type for ARG_FLOAT"); + + force_inline static T get_arg(ARMv7Thread& cpu) + { + } + + force_inline static void put_arg(ARMv7Thread& cpu, const T& arg) + { + } + }; + + template + struct bind_arg + { + static_assert(v_count <= 0, "TODO: Unsupported argument type (vector)"); + static_assert(std::is_same::value, "Invalid function argument type for ARG_VECTOR"); + + force_inline static T get_arg(ARMv7Thread& cpu) + { + } + + force_inline static void put_arg(ARMv7Thread& cpu, const T& arg) + { + } + }; + + template + struct bind_arg + { + static_assert(f_count <= 0, "TODO: Unsupported stack argument type (float)"); + static_assert(v_count <= 0, "TODO: Unsupported stack argument type (vector)"); + static_assert(sizeof(T) <= 4, "Invalid function argument type for ARG_STACK"); + + force_inline static T get_arg(ARMv7Thread& cpu) + { + // TODO: check + return arm_gpr_cast(vm::psv::read32(cpu.SP + sizeof(u32) * (g_count - 5))); + } + + force_inline static void put_arg(ARMv7Thread& cpu, const T& arg) + { + // TODO: check + const int stack_pos = (g_count - 5) * 4 - FIXED_STACK_FRAME_SIZE; + static_assert(stack_pos < 0, "TODO: Increase fixed stack frame size (arg count limit broken)"); + + vm::psv::write32(cpu.SP + stack_pos, arm_gpr_cast(arg)); + } + }; + + template + struct bind_arg + { + force_inline static u64 get_arg(ARMv7Thread& cpu) + { + // TODO: check + return vm::psv::read64(cpu.SP + sizeof(u32) * (g_count - 6)); + } + + force_inline static void put_arg(ARMv7Thread& cpu, u64 arg) + { + // TODO: check + const int stack_pos = (g_count - 6) * 4 - FIXED_STACK_FRAME_SIZE; + static_assert(stack_pos < -4, "TODO: Increase fixed stack frame size (arg count limit broken)"); + + vm::psv::write64(cpu.SP + stack_pos, arg); + } + }; + + template + struct bind_arg + { + force_inline static s64 get_arg(ARMv7Thread& cpu) + { + // TODO: check + return vm::psv::read64(cpu.SP + sizeof(u32) * (g_count - 6)); + } + + force_inline static void put_arg(ARMv7Thread& cpu, s64 arg) + { + // TODO: check + const int stack_pos = (g_count - 6) * 4 - FIXED_STACK_FRAME_SIZE; + static_assert(stack_pos < -4, "TODO: Increase fixed stack frame size (arg count limit broken)"); + + vm::psv::write64(cpu.SP + stack_pos, arg); + } + }; + + template + struct bind_arg + { + static_assert(std::is_same::value, "Invalid function argument type for ARG_CONTEXT"); + + force_inline static ARMv7Thread& get_arg(ARMv7Thread& cpu) + { + return cpu; + } + + force_inline static void put_arg(ARMv7Thread& cpu, ARMv7Thread& arg) + { + } + }; + + template + struct bind_arg + { + static_assert(std::is_same::value, "Invalid function argument type for ARG_VARIADIC"); + + force_inline static arm_va_args_t get_arg(ARMv7Thread& cpu) + { + return{ g_count }; + } + }; + + template + struct bind_result + { + static_assert(type != ARG_FLOAT, "TODO: Unsupported funcion result type (float)"); + static_assert(type != ARG_VECTOR, "TODO: Unsupported funcion result type (vector)"); + static_assert(type == ARG_GENERAL, "Wrong use of bind_result template"); + static_assert(sizeof(T) <= 4, "Invalid function result type for ARG_GENERAL"); + + force_inline static T get_result(ARMv7Thread& cpu) + { + return arm_gpr_cast(cpu.GPR[0]); + } + + force_inline static void put_result(ARMv7Thread& cpu, const T& result) + { + cpu.GPR[0] = arm_gpr_cast(result); + } + }; + + template<> + struct bind_result + { + force_inline static u64 get_result(ARMv7Thread& cpu) + { + return cpu.GPR_D[0]; + } + + force_inline static void put_result(ARMv7Thread& cpu, u64 result) + { + cpu.GPR_D[0] = result; + } + }; + + template<> + struct bind_result + { + force_inline static s64 get_result(ARMv7Thread& cpu) + { + return cpu.GPR_D[0]; + } + + force_inline static void put_result(ARMv7Thread& cpu, s64 result) + { + cpu.GPR_D[0] = result; + } + }; + + //template + //struct bind_result + //{ + // static_assert(sizeof(T) <= 8, "Invalid function result type for ARG_FLOAT"); + + // static force_inline void put_result(ARMv7Thread& cpu, const T& result) + // { + // } + //}; + + //template + //struct bind_result + //{ + // static_assert(std::is_same, v128>::value, "Invalid function result type for ARG_VECTOR"); + + // static force_inline void put_result(ARMv7Thread& cpu, const T& result) + // { + // } + //}; + + template + struct result_type + { + static_assert(!std::is_pointer::value, "Invalid function result type (pointer)"); + static_assert(!std::is_reference::value, "Invalid function result type (reference)"); + static const bool is_float = std::is_floating_point::value; + static const bool is_vector = std::is_same::value; + static const arg_class value = is_float ? ARG_FLOAT : (is_vector ? ARG_VECTOR : ARG_GENERAL); + }; + + template + struct arg_type + { + // TODO: check calculations + static const bool is_float = std::is_floating_point::value; + static const bool is_vector = std::is_same::value; + static const bool is_context = std::is_same::value; + static const bool is_variadic = std::is_same::value; + static const bool is_general = !is_float && !is_vector && !is_context && !is_variadic; + + static const u32 g_align = ALIGN_32(T) > 4 ? ALIGN_32(T) >> 2 : 1; + static const u32 g_value = is_general ? ((g_count + (g_align - 1)) & ~(g_align - 1)) + (g_align) : g_count; + static const u32 f_value = f_count + is_float; + static const u32 v_value = v_count + is_vector; + + static const arg_class value = + is_general ? (g_value > 4 ? ARG_STACK : ARG_GENERAL) : + is_float ? (f_value > 9000 ? ARG_STACK : ARG_FLOAT) : + is_vector ? (v_value > 9000 ? ARG_STACK : ARG_VECTOR) : + is_context ? ARG_CONTEXT : + is_variadic ? ARG_VARIADIC : + ARG_UNKNOWN; + }; + + // wrapper for variadic argument info list, each value contains packed argument type and counts of GENERAL, FLOAT and VECTOR arguments + template struct arg_info_pack_t; + + template struct arg_info_pack_t + { + static const u32 last_value = arg_info_pack_t::last_value; + }; + + template struct arg_info_pack_t + { + static const u32 last_value = First; + }; + + template<> struct arg_info_pack_t<> + { + static const u32 last_value = 0; + }; + + // argument type + g/f/v_count unpacker + template struct bind_arg_packed + { + force_inline static T get_arg(ARMv7Thread& cpu) + { + return bind_arg(type_pack & 0xff), (type_pack >> 8) & 0xff, (type_pack >> 16) & 0xff, (type_pack >> 24)>::get_arg(cpu); + } + }; + + template + force_inline RT call(ARMv7Thread& cpu, RT(*func)(Args...), arg_info_pack_t info) + { + // do the actual function call when all arguments are prepared (simultaneous unpacking of Args... and Info...) + return func(bind_arg_packed::get_arg(cpu)...); + } + + template + force_inline RT call(ARMv7Thread& cpu, RT(*func)(Args...), arg_info_pack_t info) + { + // unpack previous type counts (0/0/0 for the first time) + const u32 g_count = (info.last_value >> 8) & 0xff; + const u32 f_count = (info.last_value >> 16) & 0xff; + const u32 v_count = (info.last_value >> 24); + + using type = arg_type; + const arg_class t = type::value; + const u32 g = type::g_value; + const u32 f = type::f_value; + const u32 v = type::v_value; + + return call(cpu, func, arg_info_pack_t{}); + } + + template + force_inline static bool put_func_args(ARMv7Thread& cpu) + { + // terminator + return false; + } + + template + force_inline static bool put_func_args(ARMv7Thread& cpu, T1 arg, T... args) + { + using type = arg_type; + const arg_class t = type::value; + const u32 g = type::g_value; + const u32 f = type::f_value; + const u32 v = type::v_value; + + bind_arg::put_arg(cpu, arg); + + // return true if stack was used + return put_func_args(cpu, args...) || (t == ARG_STACK); + } + + template + struct func_binder; + + template + struct func_binder + { + using func_t = void(*)(T...); + + static void do_call(ARMv7Thread& cpu, func_t func) + { + call(cpu, func, arg_info_pack_t<>{}); + } + }; + + template + struct func_binder + { + using func_t = RT(*)(T...); + + static void do_call(ARMv7Thread& cpu, func_t func) + { + bind_result::value>::put_result(cpu, call(cpu, func, arg_info_pack_t<>{})); + } + }; + + template + struct func_caller + { + force_inline static RT call(ARMv7Thread& cpu, u32 addr, T... args) + { + func_caller::call(cpu, addr, args...); + + return bind_result::value>::get_result(cpu); + } + }; + + template + struct func_caller + { + force_inline static void call(ARMv7Thread& cpu, u32 addr, T... args) + { + if (put_func_args<0, 0, 0, T...>(cpu, args...)) + { + cpu.SP -= FIXED_STACK_FRAME_SIZE; + cpu.fast_call(addr); + cpu.SP += FIXED_STACK_FRAME_SIZE; + } + else + { + cpu.fast_call(addr); + } + } + }; + + template force_inline void do_call(ARMv7Thread& cpu, RT(*func)(T...)) + { + func_binder::do_call(cpu, func); + } +} + +class arm_function_manager +{ + // Global variable for each registered function + template + struct registered + { + static u32 index; + }; + + // Access global function list + static never_inline auto& access() + { + static std::vector list + { + nullptr, + [](ARMv7Thread& cpu) { cpu.state += cpu_state::ret; }, + }; + + return list; + } + + static never_inline u32 add_function(arm_function_t function) + { + auto& list = access(); + + list.push_back(function); + + return ::size32(list) - 1; + } + +public: + // Register function (shall only be called during global initialization) + template + static inline u32 register_function(arm_function_t func) + { + return registered::index = add_function(func); + } + + // Get function index + template + static inline u32 get_index() + { + return registered::index; + } + + // Read all registered functions + static inline const auto& get() + { + return access(); + } +}; + +template +u32 arm_function_manager::registered::index = 0; + +#define FIND_FUNC(func) arm_function_manager::get_index() diff --git a/rpcs3/Emu/ARMv7/ARMv7Interpreter.cpp b/rpcs3/Emu/ARMv7/ARMv7Interpreter.cpp index 91a96411c3..30330a477a 100644 --- a/rpcs3/Emu/ARMv7/ARMv7Interpreter.cpp +++ b/rpcs3/Emu/ARMv7/ARMv7Interpreter.cpp @@ -1,585 +1,62 @@ #include "stdafx.h" -#include "Emu/System.h" #include "Emu/Memory/Memory.h" -#include "Emu/CPU/CPUDecoder.h" +#include "Emu/System.h" #include "ARMv7Thread.h" -#include "PSVFuncList.h" #include "ARMv7Interpreter.h" -#define reject(cond, info) { if (cond) throw EXCEPTION("%s ('%s', type=%s)", info, #cond, fmt_encoding(type)); } +using namespace arm_code::arm_encoding_alias; -std::map g_armv7_dump; +#define ARG(arg, ...) const u32 arg = args::arg::extract(__VA_ARGS__); -namespace ARMv7_instrs +extern void arm_execute_function(ARMv7Thread& cpu, u32 index); + +namespace vm { using namespace psv; } + +void arm_interpreter::UNK(ARMv7Thread& cpu, const u32 op, const u32 cond) { - template - u32 BitCount(T x, size_t len = sizeof(T) * 8) + if (cpu.ISET == Thumb) { - u32 result = 0; - - for (T mask = static_cast(1) << (len - 1); mask; mask >>= 1) + if (op > 0xffff) { - if (x & mask) result++; - } - - return result; - } - - //template - //s8 LowestSetBit(T x, u8 len) - //{ - // if (!x) return len; - - // u8 result = 0; - - // for (T mask = 1, i = 0; i - //s8 HighestSetBit(T x, u8 len) - //{ - // if (!x) return -1; - - // u8 result = len; - - // for (T mask = T(1) << (len - 1); (x & mask) == 0; mask >>= 1) - // { - // result--; - // } - - // return result; - //} - - //template - //s8 CountLeadingZeroBits(T x, u8 len) - //{ - // return len - 1 - HighestSetBit(x, len); - //} - - SRType DecodeImmShift(u32 type, u32 imm5, u32* shift_n) - { - SRType shift_t; - - switch (type) - { - case 0: shift_t = SRType_LSL; if (shift_n) *shift_n = imm5; break; - case 1: shift_t = SRType_LSR; if (shift_n) *shift_n = imm5 == 0 ? 32 : imm5; break; - case 2: shift_t = SRType_ASR; if (shift_n) *shift_n = imm5 == 0 ? 32 : imm5; break; - case 3: - if (imm5 == 0) - { - shift_t = SRType_RRX; if (shift_n) *shift_n = 1; - } - else - { - shift_t = SRType_ROR; if (shift_n) *shift_n = imm5; - } - break; - - default: throw EXCEPTION(""); - } - - return shift_t; - } - - //SRType DecodeRegShift(u8 type) - //{ - // SRType shift_t; - - // switch (type) - // { - // case 0: shift_t = SRType_LSL; break; - // case 1: shift_t = SRType_LSR; break; - // case 2: shift_t = SRType_ASR; break; - // case 3: shift_t = SRType_ROR; break; - // default: throw EXCEPTION(""); - // } - - // return shift_t; - //} - - u32 LSL_C(u32 x, s32 shift, bool& carry_out) - { - assert(shift > 0); - carry_out = shift <= 32 ? (x & (1 << (32 - shift))) != 0 : false; - return shift < 32 ? x << shift : 0; - } - - u32 LSL_(u32 x, s32 shift) - { - assert(shift >= 0); - return shift < 32 ? x << shift : 0; - } - - u32 LSR_C(u32 x, s32 shift, bool& carry_out) - { - assert(shift > 0); - carry_out = shift <= 32 ? (x & (1 << (shift - 1))) != 0 : false; - return shift < 32 ? x >> shift : 0; - } - - u32 LSR_(u32 x, s32 shift) - { - assert(shift >= 0); - return shift < 32 ? x >> shift : 0; - } - - s32 ASR_C(s32 x, s32 shift, bool& carry_out) - { - assert(shift > 0); - carry_out = shift <= 32 ? (x & (1 << (shift - 1))) != 0 : x < 0; - return shift < 32 ? x >> shift : x >> 31; - } - - s32 ASR_(s32 x, s32 shift) - { - assert(shift >= 0); - return shift < 32 ? x >> shift : x >> 31; - } - - u32 ROR_C(u32 x, s32 shift, bool& carry_out) - { - assert(shift); - const u32 result = x >> shift | x << (32 - shift); - carry_out = (result >> 31) != 0; - return result; - } - - u32 ROR_(u32 x, s32 shift) - { - return x >> shift | x << (32 - shift); - } - - u32 RRX_C(u32 x, bool carry_in, bool& carry_out) - { - carry_out = x & 0x1; - return ((u32)carry_in << 31) | (x >> 1); - } - - u32 RRX_(u32 x, bool carry_in) - { - return ((u32)carry_in << 31) | (x >> 1); - } - - u32 Shift_C(u32 value, u32 type, s32 amount, bool carry_in, bool& carry_out) - { - assert(type != SRType_RRX || amount == 1); - - if (amount) - { - switch (type) - { - case SRType_LSL: return LSL_C(value, amount, carry_out); - case SRType_LSR: return LSR_C(value, amount, carry_out); - case SRType_ASR: return ASR_C(value, amount, carry_out); - case SRType_ROR: return ROR_C(value, amount, carry_out); - case SRType_RRX: return RRX_C(value, carry_in, carry_out); - default: throw EXCEPTION(""); - } - } - - carry_out = carry_in; - return value; - } - - u32 Shift(u32 value, u32 type, s32 amount, bool carry_in) - { - bool carry_out; - return Shift_C(value, type, amount, carry_in, carry_out); - } - - template T AddWithCarry(T x, T y, bool carry_in, bool& carry_out, bool& overflow) - { - const T sign_mask = (T)1 << (sizeof(T) * 8 - 1); - - T result = x + y; - carry_out = (((x & y) | ((x ^ y) & ~result)) & sign_mask) != 0; - overflow = ((x ^ result) & (y ^ result) & sign_mask) != 0; - if (carry_in) - { - result += 1; - carry_out ^= (result == 0); - overflow ^= (result == sign_mask); - } - return result; - } - - u32 ThumbExpandImm_C(u32 imm12, bool carry_in, bool& carry_out) - { - if ((imm12 & 0xc00) >> 10) - { - u32 unrotated_value = (imm12 & 0x7f) | 0x80; - - return ROR_C(unrotated_value, (imm12 & 0xf80) >> 7, carry_out); + throw fmt::exception("Unknown/Illegal opcode: 0x%04X 0x%04X (cond=0x%x)", op >> 16, op & 0xffff, cond); } else { - carry_out = carry_in; - - u32 imm8 = imm12 & 0xff; - switch ((imm12 & 0x300) >> 8) - { - case 0: return imm8; - case 1: return imm8 << 16 | imm8; - case 2: return imm8 << 24 | imm8 << 8; - default: return imm8 << 24 | imm8 << 16 | imm8 << 8 | imm8; - } + throw fmt::exception("Unknown/Illegal opcode: 0x%04X (cond=0x%x)", op, cond); } } - - u32 ThumbExpandImm(u32 imm12) - { - bool carry = false; - return ThumbExpandImm_C(imm12, carry, carry); - } - - bool ConditionPassed(ARMv7Context& context, u32 cond) - { - bool result = false; - - switch (cond >> 1) - { - case 0: result = (context.APSR.Z == 1); break; - case 1: result = (context.APSR.C == 1); break; - case 2: result = (context.APSR.N == 1); break; - case 3: result = (context.APSR.V == 1); break; - case 4: result = (context.APSR.C == 1) && (context.APSR.Z == 0); break; - case 5: result = (context.APSR.N == context.APSR.V); break; - case 6: result = (context.APSR.N == context.APSR.V) && (context.APSR.Z == 0); break; - case 7: return true; - } - - if (cond & 0x1) - { - return !result; - } - - return result; - } - - bool process_debug(ARMv7Context& context) - { - if (context.debug & DF_PRINT) - { - auto pos = context.debug_str.find(' '); - if (pos != std::string::npos && pos < 8) - { - context.debug_str.insert(pos, 8 - pos, ' '); - } - - context.fmt_debug_str("0x%08x: %s", context.PC, context.debug_str); - - LV2_LOCK; - - auto found = g_armv7_dump.find(context.PC); - if (found != g_armv7_dump.end()) - { - if (found->second != context.debug_str) - { - throw EXCEPTION("Disasm inconsistency: '%s' != '%s'", found->second.c_str(), context.debug_str.c_str()); - } - } - else - { - g_armv7_dump[context.PC] = context.debug_str; - } - } - - if (context.debug & DF_NO_EXE) - { - return true; - } - - return false; - } - - const char* fmt_encoding(const ARMv7_encoding type) - { - switch (type) - { - case T1: return "T1"; - case T2: return "T2"; - case T3: return "T3"; - case T4: return "T4"; - case A1: return "A1"; - case A2: return "A2"; - default: return "???"; - } - }; - - const char* fmt_cond(u32 cond) - { - switch (cond) - { - case 0: return "eq"; - case 1: return "ne"; - case 2: return "cs"; - case 3: return "cc"; - case 4: return "mi"; - case 5: return "pl"; - case 6: return "vs"; - case 7: return "vc"; - case 8: return "hi"; - case 9: return "ls"; - case 10: return "ge"; - case 11: return "lt"; - case 12: return "gt"; - case 13: return "le"; - case 14: return ""; - default: return "???"; - } - } - - const char* fmt_it(u32 state) - { - switch (state & ~0x10) - { - case 0x8: return ""; - - case 0x4: return state & 0x10 ? "e" : "t"; - case 0xc: return state & 0x10 ? "t" : "e"; - - case 0x2: return state & 0x10 ? "ee" : "tt"; - case 0x6: return state & 0x10 ? "et" : "te"; - case 0xa: return state & 0x10 ? "te" : "et"; - case 0xe: return state & 0x10 ? "tt" : "ee"; - - case 0x1: return state & 0x10 ? "eee" : "ttt"; - case 0x3: return state & 0x10 ? "eet" : "tte"; - case 0x5: return state & 0x10 ? "ete" : "tet"; - case 0x7: return state & 0x10 ? "ett" : "tee"; - case 0x9: return state & 0x10 ? "tee" : "ett"; - case 0xb: return state & 0x10 ? "tet" : "ete"; - case 0xd: return state & 0x10 ? "tte" : "eet"; - case 0xf: return state & 0x10 ? "ttt" : "eee"; - - default: return "???"; - } - } - - const char* fmt_reg(u32 reg) - { - switch (reg) - { - case 0: return "r0"; - case 1: return "r1"; - case 2: return "r2"; - case 3: return "r3"; - case 4: return "r4"; - case 5: return "r5"; - case 6: return "r6"; - case 7: return "r7"; - case 8: return "r8"; - case 9: return "r9"; - case 10: return "r10"; - case 11: return "r11"; - case 12: return "r12"; - case 13: return "sp"; - case 14: return "lr"; - case 15: return "pc"; - default: return "r???"; - } - } - - std::string fmt_shift(u32 type, u32 amount) - { - assert(type != SRType_RRX || amount == 1); - assert(amount <= 32); - - if (amount) - { - switch (type) - { - case SRType_LSL: return ",lsl #" + fmt::to_udec(amount); - case SRType_LSR: return ",lsr #" + fmt::to_udec(amount); - case SRType_ASR: return ",asr #" + fmt::to_udec(amount); - case SRType_ROR: return ",ror #" + fmt::to_udec(amount); - case SRType_RRX: return ",rrx"; - default: return ",?????"; - } - } - - return{}; - } - - std::string fmt_reg_list(u32 reg_list) - { - std::vector> lines; - - for (u32 i = 0; i < 13; i++) - { - if (reg_list & (1 << i)) - { - if (lines.size() && lines.rbegin()->second == i - 1) - { - lines.rbegin()->second = i; - } - else - { - lines.push_back({ i, i }); - } - } - } - - if (reg_list & 0x2000) lines.push_back({ 13, 13 }); // sp - if (reg_list & 0x4000) lines.push_back({ 14, 14 }); // lr - if (reg_list & 0x8000) lines.push_back({ 15, 15 }); // pc - - std::string result; - - if (reg_list >> 16) result = "???"; // invalid bits - - for (auto& line : lines) - { - if (!result.empty()) - { - result += ","; - } - - if (line.first == line.second) - { - result += fmt_reg(line.first); - } - else - { - result += fmt_reg(line.first); - result += '-'; - result += fmt_reg(line.second); - } - } - - return result; - } - - std::string fmt_mem_imm(u32 reg, u32 imm, bool index, bool add, bool wback) - { - if (index) - { - return fmt::format("[%s,#%s0x%X]%s", fmt_reg(reg), add ? "" : "-", imm, wback ? "!" : ""); - } - else - { - return fmt::format("[%s],#%s0x%X%s", fmt_reg(reg), add ? "" : "-", imm, wback ? "" : "???"); - } - } - - std::string fmt_mem_reg(u32 n, u32 m, bool index, bool add, bool wback, u32 shift_t = SRType_LSL, u32 shift_n = 0) - { - if (index) - { - return fmt::format("[%s,%s%s%s]%s", fmt_reg(n), add ? "" : "-", fmt_reg(m), fmt_shift(shift_t, shift_n), wback ? "!" : ""); - } - else - { - return fmt::format("[%s],%s%s%s%s", fmt_reg(n), add ? "" : "-", fmt_reg(m), fmt_shift(shift_t, shift_n), wback ? "" : "???"); - } - } -} - -void ARMv7_instrs::UNK(ARMv7Context& context, const ARMv7Code code) -{ - if (context.ISET == Thumb) - { - throw EXCEPTION("Unknown/illegal opcode: 0x%04X 0x%04X", code.code1, code.code0); - } else { - throw EXCEPTION("Unknown/illegal opcode: 0x%08X", code.data); + throw fmt::exception("Unknown/Illegal opcode: 0x%08X", op); } } -void ARMv7_instrs::HACK(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::HACK(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, index; + using args = arm_code::hack; + ARG(index, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - index = code.data & 0xffff; - break; - } - case A1: - { - cond = code.data >> 28; - index = (code.data & 0xfff00) >> 4 | (code.data & 0xf); - break; - } - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) - { - if (auto func = get_psv_func_by_index(index)) - { - if (func->func) - { - context.fmt_debug_str("hack%s %s", fmt_cond(cond), func->name); - } - else - { - context.fmt_debug_str("hack%s UNIMPLEMENTED:0x%08X (%s)", fmt_cond(cond), func->nid, func->name); - } - } - else - { - context.fmt_debug_str("hack%s %d", fmt_cond(cond), index); - } - } - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - execute_psv_func_by_index(static_cast(context), index); + arm_execute_function(cpu, index); } } -void ARMv7_instrs::MRC_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) + +template +void arm_interpreter::MRC_(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, t, cp, opc1, opc2, cn, cm; + using args = arm_code::mrc; + ARG(t, op); + ARG(cp, op); + ARG(opc1, op); + ARG(opc2, op); + ARG(cn, op); + ARG(cm, op); - switch (type) - { - case T1: case A1: - case T2: case A2: - { - cond = type == A1 ? code.data >> 28 : context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - cp = (code.data & 0xf00) >> 8; - opc1 = (code.data & 0xe00000) >> 21; - opc2 = (code.data & 0xe0) >> 5; - cn = (code.data & 0xf0000) >> 16; - cm = (code.data & 0xf); - - reject(cp - 10 < 2 && (type == T1 || type == A1), "Advanced SIMD and VFP"); - reject(t == 13 && (type == T1 || type == T2), "UNPREDICTABLE"); - break; - } - default: throw EXCEPTION(""); - } - - auto disasm = [&]() - { - context.fmt_debug_str("mrc%s p%d,%d,r%d,c%d,c%d,%d", fmt_cond(cond), cp, opc1, t, cn, cm, opc2); - }; - - if (context.debug) - { - if (context.debug & DF_DISASM) disasm(); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { // APSR flags are written if t = 15 @@ -587,6252 +64,4122 @@ void ARMv7_instrs::MRC_(ARMv7Context& context, const ARMv7Code code, const ARMv7 { // Read CP15 User Read-only Thread ID Register (seems used as TLS address) - if (!context.TLS) + if (!cpu.TLS) { - throw EXCEPTION("TLS not initialized"); + throw fmt::exception("TLS not initialized" HERE); } - context.GPR[t] = context.TLS; + cpu.GPR[t] = cpu.TLS; return; } - throw EXCEPTION("Bad instruction: '%s' (code=0x%x, type=%d)", (disasm(), context.debug_str.c_str()), code.data, type); + throw fmt::exception("mrc?? p%d,%d,r%d,c%d,c%d,%d" HERE, cp, opc1, t, cn, cm, opc2); } } -void ARMv7_instrs::ADC_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::ADC_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, d, n, imm32; - bool set_flags; + using args = arm_code::adc_imm; + ARG(d, op); + ARG(n, op); + ARG(imm32, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - set_flags = (code.data & 0x100000) != 0; - imm32 = ThumbExpandImm((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff)); - - reject(d == 13 || d == 15 || n == 13 || n == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("adc%s%s %s,%s,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), imm32); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry, overflow; - const u32 result = AddWithCarry(context.read_gpr(n), imm32, context.APSR.C, carry, overflow); - context.write_gpr(d, result, 4); + const u32 result = AddWithCarry(cpu.read_gpr(n), imm32, cpu.APSR.C, carry, overflow); + cpu.write_gpr(d, result, 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; - context.APSR.V = overflow; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; + cpu.APSR.V = overflow; } } } -void ARMv7_instrs::ADC_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::ADC_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - bool set_flags = !context.ITSTATE; - u32 cond, d, n, m, shift_t, shift_n; + using args = arm_code::adc_reg; + ARG(d, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = n = (code.data & 0x7); - m = (code.data & 0x38) >> 3; - shift_t = SRType_LSL; - shift_n = 0; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - m = (code.data & 0xf); - set_flags = (code.data & 0x100000) != 0; - shift_t = DecodeImmShift((code.data & 0x30) >> 4, (code.data & 0x7000) >> 10 | (code.data & 0xc0) >> 6, &shift_n); - - reject(d == 13 || d == 15 || n == 13 || n == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("adc%s%s %s,%s,%s%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), fmt_reg(m), fmt_shift(shift_t, shift_n)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry, overflow; - const u32 shifted = Shift(context.read_gpr(m), shift_t, shift_n, context.APSR.C); - const u32 result = AddWithCarry(context.read_gpr(n), shifted, context.APSR.C, carry, overflow); - context.write_gpr(d, result, type == T1 ? 2 : 4); + const u32 shifted = Shift(cpu.read_gpr(m), shift_t, shift_n, cpu.APSR.C); + const u32 result = AddWithCarry(cpu.read_gpr(n), shifted, cpu.APSR.C, carry, overflow); + cpu.write_gpr(d, result, type == T1 ? 2 : 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; - context.APSR.V = overflow; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; + cpu.APSR.V = overflow; } } } -void ARMv7_instrs::ADC_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::ADC_RSR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::ADD_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::ADD_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - bool set_flags = !context.ITSTATE; - u32 cond, d, n, imm32; + using args = arm_code::add_imm; + ARG(d, op); + ARG(n, op); + ARG(imm32, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0x7); - n = (code.data & 0x38) >> 3; - imm32 = (code.data & 0x1c0) >> 6; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - d = n = (code.data & 0x700) >> 8; - imm32 = (code.data & 0xff); - break; - } - case T3: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - set_flags = (code.data & 0x100000) != 0; - imm32 = ThumbExpandImm((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff)); - - reject(d == 15 && set_flags, "CMN (immediate)"); - reject(n == 13, "ADD (SP plus immediate)"); - reject(d == 13 || n == 15, "UNPREDICTABLE"); - break; - } - case T4: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - set_flags = false; - imm32 = (code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff); - - reject(n == 15, "ADR"); - reject(n == 13, "ADD (SP plus immediate)"); - reject(d == 13 || d == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("add%s%s %s,%s,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), imm32); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry, overflow; - const u32 result = AddWithCarry(context.read_gpr(n), imm32, false, carry, overflow); - context.write_gpr(d, result, type < T3 ? 2 : 4); + const u32 result = AddWithCarry(cpu.read_gpr(n), imm32, false, carry, overflow); + cpu.write_gpr(d, result, type < T3 ? 2 : 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; - context.APSR.V = overflow; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; + cpu.APSR.V = overflow; } } } -void ARMv7_instrs::ADD_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::ADD_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - bool set_flags = !context.ITSTATE; - u32 cond, d, n, m, shift_t, shift_n; + using args = arm_code::add_reg; + ARG(d, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0x7); - n = (code.data & 0x38) >> 3; - m = (code.data & 0x1c0) >> 6; - shift_t = SRType_LSL; - shift_n = 0; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - n = d = (code.data & 0x80) >> 4 | (code.data & 0x7); - m = (code.data & 0x78) >> 3; - set_flags = false; - shift_t = SRType_LSL; - shift_n = 0; - - reject(n == 13 || m == 13, "ADD (SP plus register)"); - reject(n == 15 && m == 15, "UNPREDICTABLE"); - reject(d == 15 && context.ITSTATE, "UNPREDICTABLE"); - break; - } - case T3: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - m = (code.data & 0xf); - set_flags = (code.data & 0x100000) != 0; - shift_t = DecodeImmShift((code.data & 0x30) >> 4, (code.data & 0x7000) >> 10 | (code.data & 0xc0) >> 6, &shift_n); - - reject(d == 15 && set_flags, "CMN (register)"); - reject(n == 13, "ADD (SP plus register)"); - reject(d == 13 || n == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("add%s%s %s,%s,%s%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), fmt_reg(m), fmt_shift(shift_t, shift_n)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry, overflow; - const u32 shifted = Shift(context.read_gpr(m), shift_t, shift_n, true); - const u32 result = AddWithCarry(context.read_gpr(n), shifted, false, carry, overflow); - context.write_gpr(d, result, type < T3 ? 2 : 4); + const u32 shifted = Shift(cpu.read_gpr(m), shift_t, shift_n, true); + const u32 result = AddWithCarry(cpu.read_gpr(n), shifted, false, carry, overflow); + cpu.write_gpr(d, result, type < T3 ? 2 : 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; - context.APSR.V = overflow; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; + cpu.APSR.V = overflow; } } } -void ARMv7_instrs::ADD_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::ADD_RSR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::ADD_SPI(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::ADD_SPI(ARMv7Thread& cpu, const u32 op, const u32 cond) { - bool set_flags; - u32 cond, d, imm32; + using args = arm_code::add_spi; + ARG(d, op); + ARG(imm32, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0x700) >> 8; - set_flags = false; - imm32 = (code.data & 0xff) << 2; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - d = 13; - set_flags = false; - imm32 = (code.data & 0x7f) << 2; - break; - } - case T3: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - set_flags = (code.data & 0x100000) != 0; - imm32 = ThumbExpandImm((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff)); - - reject(d == 15 && set_flags, "CMN (immediate)"); - reject(d == 15, "UNPREDICTABLE"); - break; - } - case T4: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - set_flags = false; - imm32 = (code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff); - - reject(d == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("add%s%s %s,sp,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), imm32); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry, overflow; - const u32 result = AddWithCarry(context.SP, imm32, false, carry, overflow); - context.write_gpr(d, result, type < T3 ? 2 : 4); + const u32 result = AddWithCarry(cpu.SP, imm32, false, carry, overflow); + cpu.write_gpr(d, result, type < T3 ? 2 : 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; - context.APSR.V = overflow; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; + cpu.APSR.V = overflow; } } } -void ARMv7_instrs::ADD_SPR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::ADD_SPR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - bool set_flags; - u32 cond, d, m, shift_t, shift_n; + using args = arm_code::add_spr; + ARG(d, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = m = (code.data & 0x80) >> 4 | (code.data & 0x7); - set_flags = false; - shift_t = SRType_LSL; - shift_n = 0; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - d = 13; - m = (code.data & 0x78) >> 3; - set_flags = false; - shift_t = SRType_LSL; - shift_n = 0; - - reject(m == 13, "encoding T1"); - break; - } - case T3: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - m = (code.data & 0xf); - set_flags = (code.data & 0x100000) != 0; - shift_t = DecodeImmShift((code.data & 0x30) >> 4, (code.data & 0x7000) >> 10 | (code.data & 0xc0) >> 6, &shift_n); - - reject(d == 13 && (shift_t != SRType_LSL || shift_n > 3), "UNPREDICTABLE"); - reject(d == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("add%s%s %s,sp,%s%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(m), fmt_shift(shift_t, shift_n)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry, overflow; - const u32 shifted = Shift(context.read_gpr(m), shift_t, shift_n, context.APSR.C); - const u32 result = AddWithCarry(context.SP, shifted, false, carry, overflow); - context.write_gpr(d, result, type < T3 ? 2 : 4); + const u32 shifted = Shift(cpu.read_gpr(m), shift_t, shift_n, cpu.APSR.C); + const u32 result = AddWithCarry(cpu.SP, shifted, false, carry, overflow); + cpu.write_gpr(d, result, type < T3 ? 2 : 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; - context.APSR.V = overflow; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; + cpu.APSR.V = overflow; } } } -void ARMv7_instrs::ADR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::ADR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, d, imm32; - bool add; + using args = arm_code::adr; + ARG(d, op); + ARG(i, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0x700) >> 8; - imm32 = (code.data & 0xff) << 2; - add = true; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - imm32 = (code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff); - add = false; - - reject(d == 13 || d == 15, "UNPREDICTABLE"); - break; - } - case T3: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - imm32 = (code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff); - add = true; - - reject(d == 13 || d == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - const u32 base = context.read_pc() & ~3; - const u32 result = add ? base + imm32 : base - imm32; - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("adr%s r%d, 0x%08X", fmt_cond(cond), d, result); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - context.write_gpr(d, result, type == T1 ? 2 : 4); + cpu.write_gpr(d, (cpu.read_pc() & ~3) + i, type == T1 ? 2 : 4); } } -void ARMv7_instrs::AND_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::AND_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, d, n, imm32; - bool set_flags, carry = context.APSR.C; + using args = arm_code::and_imm; + ARG(d, op); + ARG(n, op); + ARG(imm32, op); + ARG(set_flags, op, cond); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - set_flags = (code.data & 0x100000) != 0; - imm32 = ThumbExpandImm_C((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff), carry, carry); - - reject(d == 15 && set_flags, "TST (immediate)"); - reject(d == 13 || d == 15 || n == 13 || n == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("and%s%s %s,%s,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), imm32); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 result = context.read_gpr(n) & imm32; - context.write_gpr(d, result, 4); + const u32 result = cpu.read_gpr(n) & imm32; + cpu.write_gpr(d, result, 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = args::carry::extract(op, cpu.APSR.C); } } } -void ARMv7_instrs::AND_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::AND_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - bool set_flags = !context.ITSTATE; - u32 cond, d, n, m, shift_t, shift_n; + using args = arm_code::and_reg; + ARG(d, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = n = (code.data & 0x7); - m = (code.data & 0x38) >> 3; - shift_t = SRType_LSL; - shift_n = 0; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - m = (code.data & 0xf); - set_flags = (code.data & 0x100000) != 0; - shift_t = DecodeImmShift((code.data & 0x30) >> 4, (code.data & 0x7000) >> 10 | (code.data & 0xc0) >> 6, &shift_n); - - reject(d == 15 && set_flags, "TST (register)"); - reject(d == 13 || d == 15 || n == 13 || n == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("and%s%s %s,%s,%s%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), fmt_reg(m), fmt_shift(shift_t, shift_n)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry; - const u32 shifted = Shift_C(context.read_gpr(m), shift_t, shift_n, context.APSR.C, carry); - const u32 result = context.read_gpr(n) & shifted; - context.write_gpr(d, result, type == T1 ? 2 : 4); + const u32 shifted = Shift_C(cpu.read_gpr(m), shift_t, shift_n, cpu.APSR.C, carry); + const u32 result = cpu.read_gpr(n) & shifted; + cpu.write_gpr(d, result, type == T1 ? 2 : 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; } } } -void ARMv7_instrs::AND_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::AND_RSR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) + throw EXCEPTION("TODO"); +} + + +template +void arm_interpreter::ASR_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) +{ + throw EXCEPTION("TODO"); +} + +template +void arm_interpreter::ASR_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) +{ + throw EXCEPTION("TODO"); +} + + +template +void arm_interpreter::B(ARMv7Thread& cpu, const u32 op, const u32 _cond) +{ + using args = arm_code::b; + ARG(imm32, op); + + if (ConditionPassed(cpu, args::cond::extract(op, _cond))) { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); + cpu.PC = cpu.read_pc() + imm32 - (type < T3 ? 2 : 4); } } -void ARMv7_instrs::ASR_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::BFC(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::ASR_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::BFI(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::B(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::BIC_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, imm32; + using args = arm_code::bic_imm; + ARG(d, op); + ARG(n, op); + ARG(imm32, op); + ARG(set_flags, op, cond); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = (code.data >> 8) & 0xf; - imm32 = sign<9, u32>((code.data & 0xff) << 1); - - reject(cond == 14, "UNDEFINED"); - reject(cond == 15, "SVC"); - reject(context.ITSTATE, "UNPREDICTABLE"); - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - imm32 = sign<12, u32>((code.data & 0x7ff) << 1); - - reject(context.ITSTATE, "UNPREDICTABLE"); - break; - } - case T3: - { - cond = (code.data >> 22) & 0xf; - { - const u32 s = (code.data >> 26) & 0x1; - const u32 j1 = (code.data >> 13) & 0x1; - const u32 j2 = (code.data >> 11) & 0x1; - imm32 = sign<21, u32>(s << 20 | j2 << 19 | j1 << 18 | (code.data & 0x3f0000) >> 4 | (code.data & 0x7ff) << 1); - } - - reject(cond >= 14, "Related encodings"); - reject(context.ITSTATE, "UNPREDICTABLE"); - break; - } - case T4: - { - cond = context.ITSTATE.advance(); - { - const u32 s = (code.data >> 26) & 0x1; - const u32 i1 = (code.data >> 13) & 0x1 ^ s ^ 1; - const u32 i2 = (code.data >> 11) & 0x1 ^ s ^ 1; - imm32 = sign<25, u32>(s << 24 | i2 << 23 | i1 << 22 | (code.data & 0x3ff0000) >> 4 | (code.data & 0x7ff) << 1); - } - - reject(context.ITSTATE, "UNPREDICTABLE"); - break; - } - case A1: - { - cond = code.data >> 28; - imm32 = sign<26, u32>((code.data & 0xffffff) << 2); - break; - } - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("b%s 0x%08X", fmt_cond(cond), context.read_pc() + imm32); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - context.PC = context.read_pc() + imm32 - (type < T3 ? 2 : 4); - } -} - - -void ARMv7_instrs::BFC(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } -} - -void ARMv7_instrs::BFI(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } -} - - -void ARMv7_instrs::BIC_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - bool set_flags, carry = context.APSR.C; - u32 cond, d, n, imm32; - - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - set_flags = (code.data & 0x100000) != 0; - imm32 = ThumbExpandImm_C((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff), carry, carry); - - reject(d == 13 || d == 15 || n == 13 || n == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("bic%s%s %s,%s,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), imm32); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 result = context.read_gpr(n) & ~imm32; - context.write_gpr(d, result, 4); + const u32 result = cpu.read_gpr(n) & ~imm32; + cpu.write_gpr(d, result, 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = args::carry::extract(op, cpu.APSR.C); } } } -void ARMv7_instrs::BIC_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::BIC_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - bool set_flags = !context.ITSTATE; - u32 cond, d, n, m, shift_t, shift_n; + using args = arm_code::bic_reg; + ARG(d, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = n = (code.data & 0x7); - m = (code.data & 0x38) >> 3; - shift_t = SRType_LSL; - shift_n = 0; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - m = (code.data & 0xf); - set_flags = (code.data & 0x100000) != 0; - shift_t = DecodeImmShift((code.data & 0x30) >> 4, (code.data & 0x7000) >> 10 | (code.data & 0xc0) >> 6, &shift_n); - - reject(d == 13 || d == 15 || n == 13 || n == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("bic%s%s %s,%s,%s%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), fmt_reg(m), fmt_shift(shift_t, shift_n)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry; - const u32 shifted = Shift_C(context.read_gpr(m), shift_t, shift_n, context.APSR.C, carry); - const u32 result = context.read_gpr(n) & ~shifted; - context.write_gpr(d, result, type == T1 ? 2 : 4); + const u32 shifted = Shift_C(cpu.read_gpr(m), shift_t, shift_n, cpu.APSR.C, carry); + const u32 result = cpu.read_gpr(n) & ~shifted; + cpu.write_gpr(d, result, type == T1 ? 2 : 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; } } } -void ARMv7_instrs::BIC_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::BIC_RSR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::BKPT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::BKPT(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::BL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::BL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, imm32; + using args = arm_code::bl; + ARG(imm32, op); + ARG(to_arm); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); + cpu.LR = (cpu.PC + 4) | (cpu.ISET != ARM); + + // TODO: this is quite a mess + if ((cpu.ISET == ARM) == to_arm) { - const u32 s = (code.data >> 26) & 0x1; - const u32 i1 = (code.data >> 13) & 0x1 ^ s ^ 1; - const u32 i2 = (code.data >> 11) & 0x1 ^ s ^ 1; - imm32 = sign<25, u32>(s << 24 | i2 << 23 | i1 << 22 | (code.data & 0x3ff0000) >> 4 | (code.data & 0x7ff) << 1); + const u32 pc = cpu.ISET == ARM ? (cpu.read_pc() & ~3) + imm32 : cpu.read_pc() + imm32; + + cpu.PC = pc - 4; } - - reject(context.ITSTATE, "UNPREDICTABLE"); - break; - } - case A1: - { - cond = code.data >> 28; - imm32 = sign<26, u32>((code.data & 0xffffff) << 2); - break; - } - default: throw EXCEPTION(""); - } - - const u32 lr = context.ISET == ARM ? context.read_pc() - 4 : context.read_pc() | 1; - const u32 pc = context.ISET == ARM ? (context.read_pc() & ~3) + imm32 : context.read_pc() + imm32; - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("bl%s 0x%08X", fmt_cond(cond), pc); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - context.LR = lr; - context.PC = pc - 4; - } -} - -void ARMv7_instrs::BLX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 cond, target, newLR; - - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - newLR = (context.PC + 2) | 1; + else { - const u32 m = (code.data >> 3) & 0xf; - reject(m == 15, "UNPREDICTABLE"); - target = context.read_gpr(m); + const u32 pc = type == T2 ? ~3 & cpu.PC + 4 + imm32 : 1 | cpu.PC + 8 + imm32; + + cpu.write_pc(pc, type == T1 ? 2 : 4); } - - reject(context.ITSTATE, "UNPREDICTABLE"); - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - newLR = (context.PC + 4) | 1; - { - const u32 s = (code.data >> 26) & 0x1; - const u32 i1 = (code.data >> 13) & 0x1 ^ s ^ 1; - const u32 i2 = (code.data >> 11) & 0x1 ^ s ^ 1; - target = ~3 & context.PC + 4 + sign<25, u32>(s << 24 | i2 << 23 | i1 << 22 | (code.data & 0x3ff0000) >> 4 | (code.data & 0x7ff) << 1); - } - - reject(context.ITSTATE, "UNPREDICTABLE"); - break; - } - case A1: - { - cond = code.data >> 28; - newLR = context.PC + 4; - target = context.read_gpr(code.data & 0xf); - break; - } - case A2: - { - cond = 0xe; // always true - newLR = context.PC + 4; - target = 1 | context.PC + 8 + sign<25, u32>((code.data & 0xffffff) << 2 | (code.data & 0x1000000) >> 23); - break; - } - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) - { - switch (type) - { - case T1: context.fmt_debug_str("blx%s %s", fmt_cond(cond), fmt_reg((code.data >> 3) & 0xf)); break; - case T2: context.fmt_debug_str("blx%s 0x%08X", fmt_cond(cond), target); break; - case A1: context.fmt_debug_str("blx%s %s", fmt_cond(cond), fmt_reg(code.data & 0xf)); break; - default: context.fmt_debug_str("blx%s ???", fmt_cond(cond)); - } - } - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - context.LR = newLR; - context.write_pc(target, type == T1 ? 2 : 4); } } -void ARMv7_instrs::BX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::BLX(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, m; + using args = arm_code::blx; + ARG(m, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - m = (code.data >> 3) & 0xf; + cpu.LR = type == T1 ? (cpu.PC + 2) | 1 : cpu.PC + 4; + cpu.write_pc(cpu.read_gpr(m), type == T1 ? 2 : 4); + } +} - reject(context.ITSTATE, "UNPREDICTABLE"); - break; - } - case A1: - { - cond = code.data >> 28; - m = (code.data & 0xf); - break; - } - default: throw EXCEPTION(""); - } +template +void arm_interpreter::BX(ARMv7Thread& cpu, const u32 op, const u32 cond) +{ + using args = arm_code::bx; + ARG(m, op); - if (context.debug) + if (ConditionPassed(cpu, cond)) { - if (context.debug & DF_DISASM) context.fmt_debug_str("bx%s %s", fmt_cond(cond), fmt_reg(m)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - context.write_pc(context.read_gpr(m), type == T1 ? 2 : 4); + cpu.write_pc(cpu.read_gpr(m), type == T1 ? 2 : 4); } } -void ARMv7_instrs::CB_Z(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::CB_Z(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 n, imm32; - bool nonzero; + using args = arm_code::cb_z; + ARG(n, op); + ARG(imm32, op); + ARG(nonzero, op); - switch (type) + if ((cpu.read_gpr(n) == 0) ^ nonzero) { - case T1: - { - n = code.data & 0x7; - imm32 = (code.data & 0xf8) >> 2 | (code.data & 0x200) >> 3; - nonzero = (code.data & 0x800) != 0; - - reject(context.ITSTATE, "UNPREDICTABLE"); - break; - } - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("cb%sz 0x%08X", nonzero ? "n" : "", context.read_pc() + imm32); - if (process_debug(context)) return; - } - - if ((context.read_gpr(n) == 0) ^ nonzero) - { - context.PC = context.read_pc() + imm32 - 2; + cpu.PC = cpu.read_pc() + imm32 - 2; } } -void ARMv7_instrs::CLZ(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::CLZ(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, d, m; + using args = arm_code::clz; + ARG(d, op); + ARG(m, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - m = (code.data & 0xf); - - reject(m != (code.data & 0xf0000) >> 16, "UNPREDICTABLE"); - reject(d == 13 || d == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("clz%s %s,%s", fmt_cond(cond), fmt_reg(d), fmt_reg(m)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - context.write_gpr(d, cntlz32(context.read_gpr(m)), 4); + cpu.write_gpr(d, cntlz32(cpu.read_gpr(m)), 4); } } -void ARMv7_instrs::CMN_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::CMN_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::CMN_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::CMN_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::CMN_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::CMN_RSR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::CMP_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::CMP_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, n, imm32; + using args = arm_code::cmp_imm; + ARG(n, op); + ARG(imm32, op); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - n = (code.data & 0x700) >> 8; - imm32 = (code.data & 0xff); - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - n = (code.data & 0xf0000) >> 16; - imm32 = ThumbExpandImm((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff)); - - reject(n == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("cmp%s %s,#0x%X", fmt_cond(cond), fmt_reg(n), imm32); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry, overflow; - const u32 n_value = context.read_gpr(n); + const u32 n_value = cpu.read_gpr(n); const u32 result = AddWithCarry(n_value, ~imm32, true, carry, overflow); - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; - context.APSR.V = overflow; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; + cpu.APSR.V = overflow; //LOG_NOTICE(ARMv7, "CMP: r%d=0x%08x <> 0x%08x, res=0x%08x", n, n_value, imm32, res); } } -void ARMv7_instrs::CMP_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::CMP_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, n, m, shift_t, shift_n; + using args = arm_code::cmp_reg; + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - n = (code.data & 0x7); - m = (code.data & 0x38) >> 3; - shift_t = SRType_LSL; - shift_n = 0; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - n = (code.data & 0x80) >> 4 | (code.data & 0x7); - m = (code.data & 0x78) >> 3; - shift_t = SRType_LSL; - shift_n = 0; - - reject(n < 8 && m < 8, "UNPREDICTABLE"); - reject(n == 15 || m == 15, "UNPREDICTABLE"); - break; - } - case T3: - { - cond = context.ITSTATE.advance(); - n = (code.data & 0xf0000) >> 16; - m = (code.data & 0xf); - shift_t = DecodeImmShift((code.data & 0x30) >> 4, (code.data & 0x7000) >> 10 | (code.data & 0xc0) >> 6, &shift_n); - - reject(n == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("cmp%s %s,%s%s", fmt_cond(cond), fmt_reg(n), fmt_reg(m), fmt_shift(shift_t, shift_n)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry, overflow; - const u32 m_value = context.read_gpr(m); - const u32 n_value = context.read_gpr(n); + const u32 m_value = cpu.read_gpr(m); + const u32 n_value = cpu.read_gpr(n); const u32 shifted = Shift(m_value, shift_t, shift_n, true); const u32 result = AddWithCarry(n_value, ~shifted, true, carry, overflow); - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; - context.APSR.V = overflow; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; + cpu.APSR.V = overflow; //LOG_NOTICE(ARMv7, "CMP: r%d=0x%08x <> r%d=0x%08x, shifted=0x%08x, res=0x%08x", n, n_value, m, m_value, shifted, res); } } -void ARMv7_instrs::CMP_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::CMP_RSR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::DBG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::DBG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::DMB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::DMB(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::DSB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::DSB(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::EOR_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::EOR_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - bool set_flags, carry = context.APSR.C; - u32 cond, d, n, imm32; + using args = arm_code::eor_imm; + ARG(d, op); + ARG(n, op); + ARG(imm32, op); + ARG(set_flags, op, cond); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - set_flags = (code.data & 0x100000) != 0; - imm32 = ThumbExpandImm_C((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff), carry, carry); - - reject(d == 15 && set_flags, "TEQ (immediate)"); - reject(d == 13 || d == 15 || n == 13 || n == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("eor%s%s %s,%s,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), imm32); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 result = context.read_gpr(n) ^ imm32; - context.write_gpr(d, result, 4); + const u32 result = cpu.read_gpr(n) ^ imm32; + cpu.write_gpr(d, result, 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = args::carry::extract(op, cpu.APSR.C); } } } -void ARMv7_instrs::EOR_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::EOR_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - bool set_flags = !context.ITSTATE; - u32 cond, d, n, m, shift_t, shift_n; + using args = arm_code::eor_reg; + ARG(d, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = n = (code.data & 0x7); - m = (code.data & 0x38) >> 3; - shift_t = SRType_LSL; - shift_n = 0; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - m = (code.data & 0xf); - set_flags = (code.data & 0x100000) != 0; - shift_t = DecodeImmShift((code.data & 0x30) >> 4, (code.data & 0x7000) >> 10 | (code.data & 0xc0) >> 6, &shift_n); - - reject(d == 15 && set_flags, "TEQ (register)"); - reject(d == 13 || d == 15 || n == 13 || n == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("eor%s%s %s,%s,%s%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), fmt_reg(m), fmt_shift(shift_t, shift_n)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry; - const u32 shifted = Shift_C(context.read_gpr(m), shift_t, shift_n, context.APSR.C, carry); - const u32 result = context.read_gpr(n) ^ shifted; - context.write_gpr(d, result, type == T1 ? 2 : 4); + const u32 shifted = Shift_C(cpu.read_gpr(m), shift_t, shift_n, cpu.APSR.C, carry); + const u32 result = cpu.read_gpr(n) ^ shifted; + cpu.write_gpr(d, result, type == T1 ? 2 : 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; } } } -void ARMv7_instrs::EOR_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::EOR_RSR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::IT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::IT(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case T1: - { - const u32 mask = (code.data & 0xf); - const u32 first = (code.data & 0xf0) >> 4; - - reject(mask == 0, "Related encodings"); - reject(first == 15, "UNPREDICTABLE"); - reject(first == 14 && BitCount(mask, 4) != 1, "UNPREDICTABLE"); - reject(context.ITSTATE, "UNPREDICTABLE"); - - context.ITSTATE.IT = code.data & 0xff; - break; - } - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("IT%s %s", fmt_it(context.ITSTATE.shift_state), fmt_cond(context.ITSTATE.condition)); - if (process_debug(context)) return; - } + cpu.ITSTATE.IT = op & 0xff; } -void ARMv7_instrs::LDM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, n, reg_list; - bool wback; + using args = arm_code::ldm; + ARG(n, op); + ARG(registers, op); + ARG(wback, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - n = (code.data & 0x700) >> 8; - reg_list = (code.data & 0xff); - wback = !(reg_list & (1 << n)); - - reject(reg_list == 0, "UNPREDICTABLE"); - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - n = (code.data & 0xf0000) >> 16; - reg_list = (code.data & 0xdfff); - wback = (code.data & 0x200000) != 0; - - reject(wback && n == 13, "POP"); - reject(n == 15 || BitCount(reg_list, 16) < 2 || reg_list >= 0xc000, "UNPREDICTABLE"); - reject(reg_list & 0x8000 && context.ITSTATE, "UNPREDICTABLE"); - reject(wback && reg_list & (1 << n), "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("ldm%s %s%s,{%s}", fmt_cond(cond), fmt_reg(n), wback ? "!" : "", fmt_reg_list(reg_list)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - vm::ptr memory{ context.read_gpr(n), vm::addr }; + vm::ptr memory(cpu.read_gpr(n), vm::addr); for (u32 i = 0; i < 16; i++) { - if (reg_list & (1 << i)) + if (registers & (1 << i)) { - context.write_gpr(i, *memory++, type == T1 ? 2 : 4); + cpu.write_gpr(i, *memory++, type == T1 ? 2 : 4); } } - - if (wback) + + // Warning: wback set true for T1 + if (wback && ~registers & (1 << n)) { - context.write_gpr(n, memory.addr(), type == T1 ? 2 : 4); + cpu.write_gpr(n, memory.addr(), type == T1 ? 2 : 4); } } } -void ARMv7_instrs::LDMDA(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDMDA(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::LDMDB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDMDB(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::LDMIB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDMIB(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::LDR_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDR_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, t, n, imm32; - bool index, add, wback; + using args = arm_code::ldr_imm; + ARG(t, op); + ARG(n, op); + ARG(imm32, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0x7); - n = (code.data & 0x38) >> 3; - imm32 = (code.data & 0x7c0) >> 4; - index = true; - add = true; - wback = false; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0x700) >> 8; - n = 13; - imm32 = (code.data & 0xff) << 2; - index = true; - add = true; - wback = false; - break; - } - case T3: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - n = (code.data & 0xf0000) >> 16; - imm32 = (code.data & 0xfff); - index = true; - add = true; - wback = false; - - reject(n == 15, "LDR (literal)"); - reject(t == 15 && context.ITSTATE, "UNPREDICTABLE"); - break; - } - case T4: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - n = (code.data & 0xf0000) >> 16; - imm32 = (code.data & 0xff); - index = (code.data & 0x400) != 0; - add = (code.data & 0x200) != 0; - wback = (code.data & 0x100) != 0; - - reject(n == 15, "LDR (literal)"); - reject(index && add && !wback, "LDRT"); - reject(n == 13 && !index && add && wback && imm32 == 4, "POP"); - reject(!index && !wback, "UNDEFINED"); - reject((wback && n == t) || (t == 15 && context.ITSTATE), "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("ldr%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_imm(n, imm32, index, add, wback)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 offset_addr = add ? context.read_gpr(n) + imm32 : context.read_gpr(n) - imm32; - const u32 addr = index ? offset_addr : context.read_gpr(n); - context.write_gpr(t, vm::read32(addr), type < T3 ? 2 : 4); + const u32 offset_addr = add ? cpu.read_gpr(n) + imm32 : cpu.read_gpr(n) - imm32; + const u32 addr = index ? offset_addr : cpu.read_gpr(n); + cpu.write_gpr(t, vm::read32(addr), type < T3 ? 2 : 4); if (wback) { - context.write_gpr(n, offset_addr, type < T3 ? 2 : 4); + cpu.write_gpr(n, offset_addr, type < T3 ? 2 : 4); } } } -void ARMv7_instrs::LDR_LIT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDR_LIT(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, t, imm32; - bool add; + using args = arm_code::ldr_lit; + ARG(t, op); + ARG(imm32, op); + ARG(add, op); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0x700) >> 8; - imm32 = (code.data & 0xff) << 2; - add = true; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - imm32 = (code.data & 0xfff); - add = (code.data & 0x800000) != 0; - - reject(t == 15 && context.ITSTATE, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - const u32 base = context.read_pc() & ~3; + const u32 base = cpu.read_pc() & ~3; const u32 addr = add ? base + imm32 : base - imm32; - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("ldr%s %s,0x%08X", fmt_cond(cond), fmt_reg(t), addr); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { const u32 data = vm::read32(addr); - context.write_gpr(t, data, type == T1 ? 2 : 4); + cpu.write_gpr(t, data, type == T1 ? 2 : 4); } } -void ARMv7_instrs::LDR_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDR_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, t, n, m, shift_t, shift_n; - bool index, add, wback; + using args = arm_code::ldr_reg; + ARG(t, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0x7); - n = (code.data & 0x38) >> 3; - m = (code.data & 0x1c0) >> 6; - index = true; - add = true; - wback = false; - shift_t = SRType_LSL; - shift_n = 0; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - n = (code.data & 0xf0000) >> 16; - m = (code.data & 0xf); - index = true; - add = true; - wback = false; - shift_t = SRType_LSL; - shift_n = (code.data & 0x30) >> 4; - - reject(n == 15, "LDR (literal)"); - reject(m == 13 || m == 15, "UNPREDICTABLE"); - reject(t == 15 && context.ITSTATE, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("ldr%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_reg(n, m, index, add, wback, shift_t, shift_n)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 offset = Shift(context.read_gpr(m), shift_t, shift_n, context.APSR.C); - const u32 offset_addr = add ? context.read_gpr(n) + offset : context.read_gpr(n) - offset; - const u32 addr = index ? offset_addr : context.read_gpr(n); - context.write_gpr(t, vm::read32(addr), type == T1 ? 2 : 4); + const u32 offset = Shift(cpu.read_gpr(m), shift_t, shift_n, cpu.APSR.C); + const u32 offset_addr = add ? cpu.read_gpr(n) + offset : cpu.read_gpr(n) - offset; + const u32 addr = index ? offset_addr : cpu.read_gpr(n); + cpu.write_gpr(t, vm::read32(addr), type == T1 ? 2 : 4); if (wback) { - context.write_gpr(n, offset_addr, type == T1 ? 2 : 4); + cpu.write_gpr(n, offset_addr, type == T1 ? 2 : 4); } } } -void ARMv7_instrs::LDRB_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDRB_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, t, n, imm32; - bool index, add, wback; + using args = arm_code::ldrb_imm; + ARG(t, op); + ARG(n, op); + ARG(imm32, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0x7); - n = (code.data & 0x38) >> 3; - imm32 = (code.data & 0x7c0) >> 6; - index = true; - add = true; - wback = false; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - n = (code.data & 0xf0000) >> 16; - imm32 = (code.data & 0xfff); - index = true; - add = true; - wback = false; - - reject(t == 15, "PLD"); - reject(n == 15, "LDRB (literal)"); - reject(t == 13, "UNPREDICTABLE"); - break; - } - case T3: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - n = (code.data & 0xf0000) >> 16; - imm32 = (code.data & 0xff); - index = (code.data & 0x400) != 0; - add = (code.data & 0x200) != 0; - wback = (code.data & 0x100) != 0; - - reject(t == 15 && index && !add && !wback, "PLD"); - reject(n == 15, "LDRB (literal)"); - reject(index && add && !wback, "LDRBT"); - reject(!index && !wback, "UNDEFINED"); - reject(t == 13 || t == 15 || (wback && n == t), "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("ldrb%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_imm(n, imm32, index, add, wback)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 offset_addr = add ? context.read_gpr(n) + imm32 : context.read_gpr(n) - imm32; - const u32 addr = index ? offset_addr : context.read_gpr(n); - context.write_gpr(t, vm::read8(addr), type == T1 ? 2 : 4); + const u32 offset_addr = add ? cpu.read_gpr(n) + imm32 : cpu.read_gpr(n) - imm32; + const u32 addr = index ? offset_addr : cpu.read_gpr(n); + cpu.write_gpr(t, vm::read8(addr), type == T1 ? 2 : 4); if (wback) { - context.write_gpr(n, offset_addr, type == T1 ? 2 : 4); + cpu.write_gpr(n, offset_addr, type == T1 ? 2 : 4); } } } -void ARMv7_instrs::LDRB_LIT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDRB_LIT(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::LDRB_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDRB_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, t, n, m, shift_t, shift_n; - bool index, add, wback; + using args = arm_code::ldrb_reg; + ARG(t, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0x7); - n = (code.data & 0x38) >> 3; - m = (code.data & 0x1c0) >> 6; - index = true; - add = true; - wback = false; - shift_t = SRType_LSL; - shift_n = 0; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - n = (code.data & 0xf0000) >> 16; - m = (code.data & 0xf); - index = true; - add = true; - wback = false; - shift_t = SRType_LSL; - shift_n = (code.data & 0x30) >> 4; - - reject(t == 15, "PLD"); - reject(n == 15, "LDRB (literal)"); - reject(t == 13 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("ldrb%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_reg(n, m, index, add, wback, shift_t, shift_n)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 offset = Shift(context.read_gpr(m), shift_t, shift_n, context.APSR.C); - const u32 offset_addr = add ? context.read_gpr(n) + offset : context.read_gpr(n) - offset; - const u32 addr = index ? offset_addr : context.read_gpr(n); - context.write_gpr(t, vm::read8(addr), type == T1 ? 2 : 4); + const u32 offset = Shift(cpu.read_gpr(m), shift_t, shift_n, cpu.APSR.C); + const u32 offset_addr = add ? cpu.read_gpr(n) + offset : cpu.read_gpr(n) - offset; + const u32 addr = index ? offset_addr : cpu.read_gpr(n); + cpu.write_gpr(t, vm::read8(addr), type == T1 ? 2 : 4); if (wback) { - context.write_gpr(n, offset_addr, type == T1 ? 2 : 4); + cpu.write_gpr(n, offset_addr, type == T1 ? 2 : 4); } } } -void ARMv7_instrs::LDRD_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDRD_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, t, t2, n, imm32; - bool index, add, wback; + using args = arm_code::ldrd_imm; + ARG(t, op); + ARG(t2, op); + ARG(n, op); + ARG(imm32, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - t2 = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - imm32 = (code.data & 0xff) << 2; - index = (code.data & 0x1000000) != 0; - add = (code.data & 0x800000) != 0; - wback = (code.data & 0x200000) != 0; - - reject(!index && !wback, "Related encodings"); - reject(n == 15, "LDRD (literal)"); - reject(wback && (n == t || n == t2), "UNPREDICTABLE"); - reject(t == 13 || t == 15 || t2 == 13 || t2 == 15 || t == t2, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("ldrd%s %s,%s,%s", fmt_cond(cond), fmt_reg(t), fmt_reg(t2), fmt_mem_imm(n, imm32, index, add, wback)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 offset_addr = add ? context.read_gpr(n) + imm32 : context.read_gpr(n) - imm32; - const u32 addr = index ? offset_addr : context.read_gpr(n); + const u32 offset_addr = add ? cpu.read_gpr(n) + imm32 : cpu.read_gpr(n) - imm32; + const u32 addr = index ? offset_addr : cpu.read_gpr(n); const u64 value = vm::read64(addr); - context.write_gpr(t, (u32)(value), 4); - context.write_gpr(t2, (u32)(value >> 32), 4); + cpu.write_gpr(t, (u32)(value), 4); + cpu.write_gpr(t2, (u32)(value >> 32), 4); if (wback) { - context.write_gpr(n, offset_addr, 4); + cpu.write_gpr(n, offset_addr, 4); } } } -void ARMv7_instrs::LDRD_LIT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDRD_LIT(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, t, t2, imm32; - bool add; + using args = arm_code::ldrd_lit; + ARG(t, op); + ARG(t2, op); + ARG(imm32, op); + ARG(add, op); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - t2 = (code.data & 0xf00) >> 8; - imm32 = (code.data & 0xff) << 2; - add = (code.data & 0x800000) != 0; - - reject(!(code.data & 0x1000000), "Related encodings"); // ??? - reject(t == 13 || t == 15 || t2 == 13 || t2 == 15 || t == t2, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - const u32 base = context.read_pc() & ~3; + const u32 base = cpu.read_pc() & ~3; const u32 addr = add ? base + imm32 : base - imm32; - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("ldrd%s %s,%s,0x%08X", fmt_cond(cond), fmt_reg(t), fmt_reg(t2), addr); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { const u64 value = vm::read64(addr); - context.write_gpr(t, (u32)(value), 4); - context.write_gpr(t2, (u32)(value >> 32), 4); + cpu.write_gpr(t, (u32)(value), 4); + cpu.write_gpr(t2, (u32)(value >> 32), 4); } } -void ARMv7_instrs::LDRD_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDRD_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::LDRH_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDRH_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, t, n, imm32; - bool index, add, wback; + using args = arm_code::ldrh_imm; + ARG(t, op); + ARG(n, op); + ARG(imm32, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0x7); - n = (code.data & 0x38) >> 3; - imm32 = (code.data & 0x7c0) >> 5; - index = true; - add = true; - wback = false; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - n = (code.data & 0xf0000) >> 16; - imm32 = (code.data & 0xfff); - index = true; - add = true; - wback = false; - - reject(t == 15, "Unallocated memory hints"); - reject(n == 15, "LDRH (literal)"); - reject(t == 13, "UNPREDICTABLE"); - break; - } - case T3: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - n = (code.data & 0xf0000) >> 16; - imm32 = (code.data & 0xff); - index = (code.data & 0x400) != 0; - add = (code.data & 0x200) != 0; - wback = (code.data & 0x100) != 0; - - reject(n == 15, "LDRH (literal)"); - reject(t == 15 && index && !add && !wback, "Unallocated memory hints"); - reject(index && add && !wback, "LDRHT"); - reject(!index && !wback, "UNDEFINED"); - reject(t == 13 || t == 15 || (wback && n == t), "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("ldrh%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_imm(n, imm32, index, add, wback)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 offset_addr = add ? context.read_gpr(n) + imm32 : context.read_gpr(n) - imm32; - const u32 addr = index ? offset_addr : context.read_gpr(n); - context.write_gpr(t, vm::read16(addr), type == T1 ? 2 : 4); + const u32 offset_addr = add ? cpu.read_gpr(n) + imm32 : cpu.read_gpr(n) - imm32; + const u32 addr = index ? offset_addr : cpu.read_gpr(n); + cpu.write_gpr(t, vm::read16(addr), type == T1 ? 2 : 4); if (wback) { - context.write_gpr(n, offset_addr, type == T1 ? 2 : 4); + cpu.write_gpr(n, offset_addr, type == T1 ? 2 : 4); } } } -void ARMv7_instrs::LDRH_LIT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDRH_LIT(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::LDRH_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDRH_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::LDRSB_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDRSB_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, t, n, imm32; - bool index, add, wback; + using args = arm_code::ldrsb_imm; + ARG(t, op); + ARG(n, op); + ARG(imm32, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - n = (code.data & 0xf0000) >> 16; - imm32 = (code.data & 0xfff); - index = true; - add = true; - wback = false; - - reject(t == 15, "PLI"); - reject(n == 15, "LDRSB (literal)"); - reject(t == 13, "UNPREDICTABLE"); - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - n = (code.data & 0xf0000) >> 16; - imm32 = (code.data & 0xff); - index = (code.data & 0x400) != 0; - add = (code.data & 0x200) != 0; - wback = (code.data & 0x100) != 0; - - reject(t == 15 && index && !add && !wback, "PLI"); - reject(n == 15, "LDRSB (literal)"); - reject(index && add && !wback, "LDRSBT"); - reject(!index && !wback, "UNDEFINED"); - reject(t == 13 || t == 15 || (wback && n == t), "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("ldrsb%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_imm(n, imm32, index, add, wback)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 offset_addr = add ? context.read_gpr(n) + imm32 : context.read_gpr(n) - imm32; - const u32 addr = index ? offset_addr : context.read_gpr(n); + const u32 offset_addr = add ? cpu.read_gpr(n) + imm32 : cpu.read_gpr(n) - imm32; + const u32 addr = index ? offset_addr : cpu.read_gpr(n); const s8 value = vm::read8(addr); - context.write_gpr(t, value, 4); // sign-extend + cpu.write_gpr(t, value, 4); // sign-extend if (wback) { - context.write_gpr(n, offset_addr, 4); + cpu.write_gpr(n, offset_addr, 4); } } } -void ARMv7_instrs::LDRSB_LIT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDRSB_LIT(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::LDRSB_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDRSB_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::LDRSH_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDRSH_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::LDRSH_LIT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDRSH_LIT(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::LDRSH_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDRSH_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::LDREX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDREX(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, t, n, imm32; + using args = arm_code::ldrex; + ARG(t, op); + ARG(n, op); + ARG(imm32, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - n = (code.data & 0xf0000) >> 16; - imm32 = (code.data & 0xff) << 2; - - reject(t == 13 || t == 15 || n == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("ldrex%s %s,[%s,#0x%X]", fmt_cond(cond), fmt_reg(t), fmt_reg(n), imm32); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 addr = context.read_gpr(n) + imm32; + const u32 addr = cpu.read_gpr(n) + imm32; u32 value; vm::reservation_acquire(&value, addr, sizeof(value)); - context.write_gpr(t, value, 4); + cpu.write_gpr(t, value, 4); } } -void ARMv7_instrs::LDREXB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDREXB(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::LDREXD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDREXD(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::LDREXH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LDREXH(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::LSL_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LSL_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - bool set_flags = !context.ITSTATE; - u32 cond, d, m, shift_n; + using args = arm_code::lsl_imm; + ARG(d, op); + ARG(m, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0x7); - m = (code.data & 0x38) >> 3; - DecodeImmShift(0, (code.data & 0x7c0) >> 6, &shift_n); - - reject(!shift_n, "MOV (register)"); - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - m = (code.data & 0xf); - set_flags = (code.data & 0x100000) != 0; - DecodeImmShift(0, (code.data & 0x7000) >> 10 | (code.data & 0xc0) >> 6, &shift_n); - - reject(!shift_n, "MOV (register)"); - reject(d == 13 || d == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("lsl%s%s %s,%s,#%d", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(m), shift_n); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry; - const u32 result = Shift_C(context.read_gpr(m), SRType_LSL, shift_n, context.APSR.C, carry); - context.write_gpr(d, result, type == T1 ? 2 : 4); + const u32 result = Shift_C(cpu.read_gpr(m), arm_code::SRType_LSL, shift_n, cpu.APSR.C, carry); + cpu.write_gpr(d, result, type == T1 ? 2 : 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; } } } -void ARMv7_instrs::LSL_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LSL_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - bool set_flags = !context.ITSTATE; - u32 cond, d, n, m; + using args = arm_code::lsl_reg; + ARG(d, op); + ARG(n, op); + ARG(m, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = n = (code.data & 0x7); - m = (code.data & 0x38) >> 3; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - m = (code.data & 0xf); - set_flags = (code.data & 0x100000) != 0; - - reject(d == 13 || d == 15 || n == 13 || n == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("lsl%s%s %s,%s,%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), fmt_reg(m)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry; - const u32 result = Shift_C(context.read_gpr(n), SRType_LSL, (context.read_gpr(m) & 0xff), context.APSR.C, carry); - context.write_gpr(d, result, type == T1 ? 2 : 4); + const u32 result = Shift_C(cpu.read_gpr(n), arm_code::SRType_LSL, (cpu.read_gpr(m) & 0xff), cpu.APSR.C, carry); + cpu.write_gpr(d, result, type == T1 ? 2 : 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; } } } -void ARMv7_instrs::LSR_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LSR_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - bool set_flags = !context.ITSTATE; - u32 cond, d, m, shift_n; + using args = arm_code::lsr_imm; + ARG(d, op); + ARG(m, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0x7); - m = (code.data & 0x38) >> 3; - DecodeImmShift(1, (code.data & 0x7c0) >> 6, &shift_n); - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - m = (code.data & 0xf); - set_flags = (code.data & 0x100000) != 0; - DecodeImmShift(1, (code.data & 0x7000) >> 10 | (code.data & 0xc0) >> 6, &shift_n); - - reject(d == 13 || d == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("lsr%s%s %s,%s,#%d", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(m), shift_n); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry; - const u32 result = Shift_C(context.read_gpr(m), SRType_LSR, shift_n, context.APSR.C, carry); - context.write_gpr(d, result, type == T1 ? 2 : 4); + const u32 result = Shift_C(cpu.read_gpr(m), arm_code::SRType_LSR, shift_n, cpu.APSR.C, carry); + cpu.write_gpr(d, result, type == T1 ? 2 : 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; } } } -void ARMv7_instrs::LSR_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::LSR_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::MLA(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::MLA(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::MLS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::MLS(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::MOV_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::MOV_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - bool set_flags = !context.ITSTATE; - bool carry = context.APSR.C; - u32 cond, d, imm32; + using args = arm_code::mov_imm; + ARG(d, op); + ARG(imm32, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data >> 8) & 0x7; - imm32 = sign<8, u32>(code.data & 0xff); - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - set_flags = (code.data & 0x100000) != 0; - d = (code.data >> 8) & 0xf; - imm32 = ThumbExpandImm_C((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff), carry, carry); - - reject(d == 13 || d == 15, "UNPREDICTABLE"); - break; - } - case T3: - { - cond = context.ITSTATE.advance(); - set_flags = false; - d = (code.data >> 8) & 0xf; - imm32 = (code.data & 0xf0000) >> 4 | (code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff); - - reject(d == 13 || d == 15, "UNPREDICTABLE"); - break; - } - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) - { - switch (type) - { - case T3: case A2: context.fmt_debug_str("movw%s%s %s,#0x%04X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), imm32); break; - default: context.fmt_debug_str("mov%s%s %s,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), imm32); - } - } - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { const u32 result = imm32; - context.write_gpr(d, result, type == T1 ? 2 : 4); + cpu.write_gpr(d, result, type == T1 ? 2 : 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = args::carry::extract(op, cpu.APSR.C); } } } -void ARMv7_instrs::MOV_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::MOV_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, d, m; - bool set_flags; + using args = arm_code::mov_reg; + ARG(d, op); + ARG(m, op); + ARG(set_flags, op, cond); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0x80) >> 4 | (code.data & 0x7); - m = (code.data & 0x78) >> 3; - set_flags = false; + const u32 result = cpu.read_gpr(m); + cpu.write_gpr(d, result, type < T3 ? 2 : 4); - reject(d == 15 && context.ITSTATE, "UNPREDICTABLE"); - break; - } - case T2: - { - cond = 0xe; // always true - d = (code.data & 0x7); - m = (code.data & 0x38) >> 3; - set_flags = true; - - reject(context.ITSTATE, "UNPREDICTABLE"); - break; - } - case T3: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - m = (code.data & 0xf); - set_flags = (code.data & 0x100000) != 0; - - reject((d == 13 || m == 13 || m == 15) && set_flags, "UNPREDICTABLE"); - reject((d == 13 && (m == 13 || m == 15)) || d == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("mov%s%s %s,%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(m)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 result = context.read_gpr(m); - context.write_gpr(d, result, type < T3 ? 2 : 4); - - if (set_flags) + if (set_flags) // cond is not used { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - //context.APSR.C = carry; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + //cpu.APSR.C = carry; } } } -void ARMv7_instrs::MOVT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::MOVT(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, d, imm16; + using args = arm_code::movt; + ARG(d, op); + ARG(imm16, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - imm16 = (code.data & 0xf0000) >> 4 | (code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff); - - reject(d == 13 || d == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("movt%s %s,#0x%04X", fmt_cond(cond), fmt_reg(d), imm16); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - context.write_gpr(d, (context.read_gpr(d) & 0xffff) | (imm16 << 16), 4); + cpu.write_gpr(d, (cpu.read_gpr(d) & 0xffff) | (imm16 << 16), 4); } } -void ARMv7_instrs::MRS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::MRS(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::MSR_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::MSR_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::MSR_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::MSR_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::MUL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::MUL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - bool set_flags = !context.ITSTATE; - u32 cond, d, n, m; + using args = arm_code::mul; + ARG(d, op); + ARG(n, op); + ARG(m, op); + ARG(set_flags, op, cond); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - d = m = code.data & 0x7; - n = (code.data & 0x38) >> 3; - - //reject(ArchVersion() < 6 && d == n, "UNPREDICTABLE"); - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - m = (code.data & 0xf); - set_flags = false; - - reject(d == 13 || d == 15 || n == 13 || n == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("mul%s%s %s,%s,%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), fmt_reg(m)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 op1 = context.read_gpr(n); - const u32 op2 = context.read_gpr(m); + const u32 op1 = cpu.read_gpr(n); + const u32 op2 = cpu.read_gpr(m); const u32 result = op1 * op2; - context.write_gpr(d, result, type == T1 ? 2 : 4); + cpu.write_gpr(d, result, type == T1 ? 2 : 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; } } } -void ARMv7_instrs::MVN_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::MVN_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, d, imm32; - bool set_flags, carry; + using args = arm_code::mvn_imm; + ARG(d, op); + ARG(imm32, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - set_flags = (code.data & 0x100000) != 0; - imm32 = ThumbExpandImm_C((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff), context.APSR.C, carry); - - reject(d == 13 || d == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("mvn%s%s %s,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), imm32); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { const u32 result = ~imm32; - context.write_gpr(d, result, 4); + cpu.write_gpr(d, result, 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = args::carry::extract(op, cpu.APSR.C); } } } -void ARMv7_instrs::MVN_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::MVN_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - bool set_flags = !context.ITSTATE; - u32 cond, d, m, shift_t, shift_n; + using args = arm_code::mvn_reg; + ARG(d, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0x7); - m = (code.data & 0x38) >> 3; - shift_t = SRType_LSL; - shift_n = 0; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - m = (code.data & 0xf); - set_flags = (code.data & 0x100000) != 0; - shift_t = DecodeImmShift((code.data & 0x30) >> 4, (code.data & 0x7000) >> 10 | (code.data & 0xc0) >> 6, &shift_n); - - reject(d == 13 || d == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("mvn%s%s %s,%s%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(m), fmt_shift(shift_t, shift_n)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry; - const u32 shifted = Shift_C(context.read_gpr(m), shift_t, shift_n, context.APSR.C, carry); + const u32 shifted = Shift_C(cpu.read_gpr(m), shift_t, shift_n, cpu.APSR.C, carry); const u32 result = ~shifted; - context.write_gpr(d, result, type == T1 ? 2 : 4); + cpu.write_gpr(d, result, type == T1 ? 2 : 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; } } } -void ARMv7_instrs::MVN_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::MVN_RSR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::NOP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::NOP(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond; - - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - break; - } - case A1: - { - cond = code.data >> 28; - break; - } - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("nop%s", fmt_cond(cond)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { } } -void ARMv7_instrs::ORN_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::ORN_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::ORN_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::ORN_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::ORR_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::ORR_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, d, n, imm32; - bool set_flags, carry = context.APSR.C; + using args = arm_code::orr_imm; + ARG(d, op); + ARG(n, op); + ARG(imm32, op); + ARG(set_flags, op, cond); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - set_flags = (code.data & 0x100000) != 0; - imm32 = ThumbExpandImm_C((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff), carry, carry); - - reject(n == 15, "MOV (immediate)"); - reject(d == 13 || d == 15 || n == 13, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("orr%s%s %s,%s,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), imm32); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 result = context.read_gpr(n) | imm32; - context.write_gpr(d, result, 4); + const u32 result = cpu.read_gpr(n) | imm32; + cpu.write_gpr(d, result, 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = args::carry::extract(op, cpu.APSR.C); } } } -void ARMv7_instrs::ORR_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::ORR_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - bool set_flags = !context.ITSTATE; - u32 cond, d, n, m, shift_t, shift_n; + using args = arm_code::orr_reg; + ARG(d, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = n = (code.data & 0x7); - m = (code.data & 0x38) >> 3; - shift_t = SRType_LSL; - shift_n = 0; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - m = (code.data & 0xf); - set_flags = (code.data & 0x100000) != 0; - shift_t = DecodeImmShift((code.data & 0x30) >> 4, (code.data & 0x7000) >> 10 | (code.data & 0xc0) >> 6, &shift_n); - - reject(n == 15, "ROR (immediate)"); - reject(d == 13 || d == 15 || n == 13 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("orr%s%s %s,%s,%s%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), fmt_reg(m), fmt_shift(shift_t, shift_n)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry; - const u32 shifted = Shift_C(context.read_gpr(m), shift_t, shift_n, context.APSR.C, carry); - const u32 result = context.read_gpr(n) | shifted; - context.write_gpr(d, result, type == T1 ? 2 : 4); + const u32 shifted = Shift_C(cpu.read_gpr(m), shift_t, shift_n, cpu.APSR.C, carry); + const u32 result = cpu.read_gpr(n) | shifted; + cpu.write_gpr(d, result, type == T1 ? 2 : 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; } } } -void ARMv7_instrs::ORR_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::ORR_RSR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::PKH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::PKH(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::POP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::POP(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, reg_list; + const u32 registers = arm_code::pop::registers::extract(op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - reg_list = ((code.data & 0x100) << 7) | (code.data & 0xff); - - reject(!reg_list, "UNPREDICTABLE"); - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - reg_list = code.data & 0xdfff; - - reject(BitCount(reg_list, 16) < 2 || ((reg_list & 0x8000) && (reg_list & 0x4000)), "UNPREDICTABLE"); - reject((reg_list & 0x8000) && context.ITSTATE, "UNPREDICTABLE"); - break; - } - case T3: - { - cond = context.ITSTATE.advance(); - reg_list = 1 << ((code.data & 0xf000) >> 12); - - reject((reg_list & 0x2000) || ((reg_list & 0x8000) && context.ITSTATE), "UNPREDICTABLE"); - break; - } - case A1: - { - cond = code.data >> 28; - reg_list = code.data & 0xffff; - - reject(BitCount(reg_list, 16) < 2, "LDM / LDMIA / LDMFD"); - reject((reg_list & 0x2000) /* && ArchVersion() >= 7*/, "UNPREDICTABLE"); - break; - } - case A2: - { - cond = code.data >> 28; - reg_list = 1 << ((code.data & 0xf000) >> 12); - - reject(reg_list & 0x2000, "UNPREDICTABLE"); - break; - } - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("pop%s {%s}", fmt_cond(cond), fmt_reg_list(reg_list)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - auto stack = vm::ptr::make(context.SP); + auto stack = vm::ptr::make(cpu.SP); for (u32 i = 0; i < 16; i++) { - if (reg_list & (1 << i)) + if (registers & (1 << i)) { - context.write_gpr(i, *stack++, type == T1 ? 2 : 4); + cpu.write_gpr(i, *stack++, type == T1 ? 2 : 4); } } - context.SP = stack.addr(); + cpu.SP = stack.addr(); } } -void ARMv7_instrs::PUSH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::PUSH(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, reg_list; + const u32 registers = arm_code::push::registers::extract(op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - reg_list = ((code.data & 0x100) << 6) | (code.data & 0xff); - - reject(!reg_list, "UNPREDICTABLE"); - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - reg_list = code.data & 0x5fff; - - reject(BitCount(reg_list, 16) < 2, "UNPREDICTABLE"); - break; - } - case T3: - { - cond = context.ITSTATE.advance(); - reg_list = 1 << ((code.data & 0xf000) >> 12); - - reject((reg_list & 0x8000) || (reg_list & 0x2000), "UNPREDICTABLE"); - break; - } - case A1: - { - cond = code.data >> 28; - reg_list = code.data & 0xffff; - - reject(BitCount(reg_list) < 2, "STMDB / STMFD"); - break; - } - case A2: - { - cond = code.data >> 28; - reg_list = 1 << ((code.data & 0xf000) >> 12); - - reject(reg_list & 0x2000, "UNPREDICTABLE"); - break; - } - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("push%s {%s}", fmt_cond(cond), fmt_reg_list(reg_list)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - vm::ptr memory{ context.SP, vm::addr }; + vm::ptr memory(cpu.SP, vm::addr); for (u32 i = 15; ~i; i--) { - if (reg_list & (1 << i)) + if (registers & (1 << i)) { - *--memory = context.read_gpr(i); + *--memory = cpu.read_gpr(i); } } - context.SP = memory.addr(); + cpu.SP = memory.addr(); } } -void ARMv7_instrs::QADD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::QADD(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::QADD16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::QADD16(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::QADD8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::QADD8(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::QASX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::QASX(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::QDADD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::QDADD(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::QDSUB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::QDSUB(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::QSAX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::QSAX(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::QSUB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::QSUB(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::QSUB16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::QSUB16(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::QSUB8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::QSUB8(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::RBIT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::RBIT(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) + throw EXCEPTION("TODO"); +} + +template +void arm_interpreter::REV(ARMv7Thread& cpu, const u32 op, const u32 cond) +{ + using args = arm_code::rev; + ARG(d, op); + ARG(m, op); + + if (ConditionPassed(cpu, cond)) { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); + cpu.write_gpr(d, se_storage::swap(cpu.read_gpr(m)), type == T1 ? 2 : 4); } } -void ARMv7_instrs::REV(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::REV16(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, d, m; - - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0x7); - m = (code.data & 0x38) >> 3; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - m = (code.data & 0xf); - - reject(m != (code.data & 0xf0000) >> 16, "UNPREDICTABLE"); - reject(d == 13 || d == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("rev%s %s,%s", fmt_cond(cond), fmt_reg(d), fmt_reg(m)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - context.write_gpr(d, se_storage::swap(context.read_gpr(m)), type == T1 ? 2 : 4); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::REV16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::REVSH(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } -} - -void ARMv7_instrs::REVSH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::ROR_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::ROR_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, d, m, shift_n; - bool set_flags; + using args = arm_code::ror_imm; + ARG(d, op); + ARG(m, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - m = (code.data & 0xf); - set_flags = (code.data & 0x100000) != 0; - const u32 shift_t = DecodeImmShift(3, (code.data & 0x7000) >> 10 | (code.data & 0xc0) >> 6, &shift_n); - - reject(shift_t == SRType_RRX, "RRX"); - reject(d == 13 || d == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("ror%s%s %s,%s,#%d", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(m), shift_n); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry; - const u32 result = Shift_C(context.read_gpr(m), SRType_ROR, shift_n, context.APSR.C, carry); - context.write_gpr(d, result, 4); + const u32 result = Shift_C(cpu.read_gpr(m), arm_code::SRType_ROR, shift_n, cpu.APSR.C, carry); + cpu.write_gpr(d, result, 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; } } } -void ARMv7_instrs::ROR_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::ROR_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - bool set_flags = !context.ITSTATE; - u32 cond, d, n, m; + using args = arm_code::ror_reg; + ARG(d, op); + ARG(n, op); + ARG(m, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = n = (code.data & 0x7); - m = (code.data & 0x38) >> 3; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - m = (code.data & 0xf); - set_flags = (code.data & 0x100000) != 0; - - reject(d == 13 || d == 15 || n == 13 || n == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("ror%s%s %s,%s,%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), fmt_reg(m)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry; - const u32 shift_n = context.read_gpr(m) & 0xff; - const u32 result = Shift_C(context.read_gpr(n), SRType_ROR, shift_n, context.APSR.C, carry); - context.write_gpr(d, result, type == T1 ? 2 : 4); + const u32 shift_n = cpu.read_gpr(m) & 0xff; + const u32 result = Shift_C(cpu.read_gpr(n), arm_code::SRType_ROR, shift_n, cpu.APSR.C, carry); + cpu.write_gpr(d, result, type == T1 ? 2 : 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; } } } -void ARMv7_instrs::RRX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::RRX(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::RSB_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::RSB_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - bool set_flags = !context.ITSTATE; - u32 cond, d, n, imm32; + using args = arm_code::rsb_imm; + ARG(d, op); + ARG(n, op); + ARG(imm32, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0x7); - n = (code.data & 0x38) >> 3; - imm32 = 0; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - set_flags = (code.data & 0x100000) != 0; - imm32 = ThumbExpandImm((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff)); - - reject(d == 13 || d == 15 || n == 13 || n == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("rsb%s%s %s,%s,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), imm32); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry, overflow; - const u32 result = AddWithCarry(~context.read_gpr(n), imm32, true, carry, overflow); - context.write_gpr(d, result, type == T1 ? 2 : 4); + const u32 result = AddWithCarry(~cpu.read_gpr(n), imm32, true, carry, overflow); + cpu.write_gpr(d, result, type == T1 ? 2 : 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; - context.APSR.V = overflow; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; + cpu.APSR.V = overflow; } } } -void ARMv7_instrs::RSB_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::RSB_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::RSB_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::RSB_RSR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::RSC_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::RSC_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::RSC_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::RSC_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::RSC_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::RSC_RSR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SADD16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SADD16(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SADD8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SADD8(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SASX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SASX(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SBC_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SBC_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SBC_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SBC_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SBC_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SBC_RSR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SBFX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SBFX(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SDIV(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SDIV(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SEL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SEL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SHADD16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SHADD16(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SHADD8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SHADD8(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SHASX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SHASX(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SHSAX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SHSAX(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SHSUB16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SHSUB16(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SHSUB8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SHSUB8(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SMLA__(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SMLA__(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SMLAD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SMLAD(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SMLAL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SMLAL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SMLAL__(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SMLAL__(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SMLALD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SMLALD(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SMLAW_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SMLAW_(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SMLSD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SMLSD(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SMLSLD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SMLSLD(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SMMLA(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SMMLA(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SMMLS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SMMLS(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SMMUL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SMMUL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SMUAD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SMUAD(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SMUL__(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SMUL__(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SMULL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SMULL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SMULW_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SMULW_(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SMUSD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SMUSD(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SSAT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SSAT(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SSAT16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SSAT16(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SSAX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SSAX(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SSUB16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SSUB16(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SSUB8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SSUB8(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::STM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::STM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, n, reg_list; - bool wback; + using args = arm_code::stm; + ARG(n, op); + ARG(registers, op); + ARG(wback, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - n = (code.data & 0x700) >> 8; - reg_list = (code.data & 0xff); - wback = true; - - reject(reg_list == 0, "UNPREDICTABLE"); - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - n = (code.data & 0xf0000) >> 16; - reg_list = (code.data & 0x5fff); - wback = (code.data & 0x200000) != 0; - - reject(n == 15 || BitCount(reg_list, 16) < 2, "UNPREDICTABLE"); - reject(wback && reg_list & (1 << n), "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("stm%s %s%s,{%s}", fmt_cond(cond), fmt_reg(n), wback ? "!" : "", fmt_reg_list(reg_list)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - auto memory = vm::ptr::make(context.read_gpr(n)); + auto memory = vm::ptr::make(cpu.read_gpr(n)); for (u32 i = 0; i < 16; i++) { - if (reg_list & (1 << i)) + if (registers & (1 << i)) { - *memory++ = context.read_gpr(i); + *memory++ = cpu.read_gpr(i); } } if (wback) { - context.write_gpr(n, memory.addr(), type == T1 ? 2 : 4); + cpu.write_gpr(n, memory.addr(), type == T1 ? 2 : 4); } } } -void ARMv7_instrs::STMDA(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::STMDA(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::STMDB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::STMDB(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::STMIB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::STMIB(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::STR_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::STR_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, t, n, imm32; - bool index, add, wback; + using args = arm_code::str_imm; + ARG(t, op); + ARG(n, op); + ARG(imm32, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0x7); - n = (code.data & 0x38) >> 3; - imm32 = (code.data & 0x7c0) >> 4; - index = true; - add = true; - wback = false; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0x700) >> 8; - n = 13; - imm32 = (code.data & 0xff) << 2; - index = true; - add = true; - wback = false; - break; - } - case T3: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - n = (code.data & 0xf0000) >> 16; - imm32 = (code.data & 0xfff); - index = true; - add = true; - wback = false; - - reject(n == 15, "UNDEFINED"); - reject(t == 15, "UNPREDICTABLE"); - break; - } - case T4: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - n = (code.data & 0xf0000) >> 16; - imm32 = (code.data & 0xff); - index = (code.data & 0x400) != 0; - add = (code.data & 0x200) != 0; - wback = (code.data & 0x100) != 0; - - reject(index && add && !wback, "STRT"); - reject(n == 13 && index && !add && wback && imm32 == 4, "PUSH"); - reject(n == 15 || (!index && !wback), "UNDEFINED"); - reject(t == 15 || (wback && n == t), "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("str%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_imm(n, imm32, index, add, wback)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 offset_addr = add ? context.read_gpr(n) + imm32 : context.read_gpr(n) - imm32; - const u32 addr = index ? offset_addr : context.read_gpr(n); - vm::write32(addr, context.read_gpr(t)); + const u32 offset_addr = add ? cpu.read_gpr(n) + imm32 : cpu.read_gpr(n) - imm32; + const u32 addr = index ? offset_addr : cpu.read_gpr(n); + vm::write32(addr, cpu.read_gpr(t)); if (wback) { - context.write_gpr(n, offset_addr, type < T3 ? 2 : 4); + cpu.write_gpr(n, offset_addr, type < T3 ? 2 : 4); } } } -void ARMv7_instrs::STR_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::STR_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, t, n, m, shift_t, shift_n; - bool index, add, wback; + using args = arm_code::str_reg; + ARG(t, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0x7); - n = (code.data & 0x38) >> 3; - m = (code.data & 0x1c0) >> 6; - index = true; - add = true; - wback = false; - shift_t = SRType_LSL; - shift_n = 0; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - n = (code.data & 0xf0000) >> 16; - m = (code.data & 0xf); - index = true; - add = true; - wback = false; - shift_t = SRType_LSL; - shift_n = (code.data & 0x30) >> 4; - - reject(n == 15, "UNDEFINED"); - reject(t == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("str%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_reg(n, m, index, add, wback, shift_t, shift_n)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 offset = Shift(context.read_gpr(m), shift_t, shift_n, context.APSR.C); - const u32 offset_addr = add ? context.read_gpr(n) + offset : context.read_gpr(n) - offset; - const u32 addr = index ? offset_addr : context.read_gpr(n); - vm::write32(addr, context.read_gpr(t)); + const u32 offset = Shift(cpu.read_gpr(m), shift_t, shift_n, cpu.APSR.C); + const u32 offset_addr = add ? cpu.read_gpr(n) + offset : cpu.read_gpr(n) - offset; + const u32 addr = index ? offset_addr : cpu.read_gpr(n); + vm::write32(addr, cpu.read_gpr(t)); if (wback) { - context.write_gpr(n, offset_addr, type == T1 ? 2 : 4); + cpu.write_gpr(n, offset_addr, type == T1 ? 2 : 4); } } } -void ARMv7_instrs::STRB_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::STRB_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, t, n, imm32; - bool index, add, wback; + using args = arm_code::strb_imm; + ARG(t, op); + ARG(n, op); + ARG(imm32, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0x7); - n = (code.data & 0x38) >> 3; - imm32 = (code.data & 0x7c0) >> 6; - index = true; - add = true; - wback = false; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - n = (code.data & 0xf0000) >> 16; - imm32 = (code.data & 0xfff); - index = true; - add = true; - wback = false; - - reject(n == 15, "UNDEFINED"); - reject(t == 13 || t == 15, "UNPREDICTABLE"); - break; - } - case T3: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - n = (code.data & 0xf0000) >> 16; - imm32 = (code.data & 0xff); - index = (code.data & 0x400) != 0; - add = (code.data & 0x200) != 0; - wback = (code.data & 0x100) != 0; - - reject(index && add && !wback, "STRBT"); - reject(n == 15 || (!index && !wback), "UNDEFINED"); - reject(t == 13 || t == 15 || (wback && n == t), "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("strb%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_imm(n, imm32, index, add, wback)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 offset_addr = add ? context.read_gpr(n) + imm32 : context.read_gpr(n) - imm32; - const u32 addr = index ? offset_addr : context.read_gpr(n); - vm::write8(addr, (u8)context.read_gpr(t)); + const u32 offset_addr = add ? cpu.read_gpr(n) + imm32 : cpu.read_gpr(n) - imm32; + const u32 addr = index ? offset_addr : cpu.read_gpr(n); + vm::write8(addr, (u8)cpu.read_gpr(t)); if (wback) { - context.write_gpr(n, offset_addr, type == T1 ? 2 : 4); + cpu.write_gpr(n, offset_addr, type == T1 ? 2 : 4); } } } -void ARMv7_instrs::STRB_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::STRB_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, t, n, m, shift_t, shift_n; - bool index, add, wback; + using args = arm_code::strb_reg; + ARG(t, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0x7); - n = (code.data & 0x38) >> 3; - m = (code.data & 0x1c0) >> 6; - index = true; - add = true; - wback = false; - shift_t = SRType_LSL; - shift_n = 0; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - n = (code.data & 0xf0000) >> 16; - m = (code.data & 0xf); - index = true; - add = true; - wback = false; - shift_t = SRType_LSL; - shift_n = (code.data & 0x30) >> 4; - - reject(n == 15, "UNDEFINED"); - reject(t == 13 || t == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("strb%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_reg(n, m, index, add, wback, shift_t, shift_n)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 offset = Shift(context.read_gpr(m), shift_t, shift_n, context.APSR.C); - const u32 offset_addr = add ? context.read_gpr(n) + offset : context.read_gpr(n) - offset; - const u32 addr = index ? offset_addr : context.read_gpr(n); - vm::write8(addr, (u8)context.read_gpr(t)); + const u32 offset = Shift(cpu.read_gpr(m), shift_t, shift_n, cpu.APSR.C); + const u32 offset_addr = add ? cpu.read_gpr(n) + offset : cpu.read_gpr(n) - offset; + const u32 addr = index ? offset_addr : cpu.read_gpr(n); + vm::write8(addr, (u8)cpu.read_gpr(t)); if (wback) { - context.write_gpr(n, offset_addr, type == T1 ? 2 : 4); + cpu.write_gpr(n, offset_addr, type == T1 ? 2 : 4); } } } -void ARMv7_instrs::STRD_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::STRD_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, t, t2, n, imm32; - bool index, add, wback; + using args = arm_code::strd_imm; + ARG(t, op); + ARG(t2, op); + ARG(n, op); + ARG(imm32, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - t2 = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - imm32 = (code.data & 0xff) << 2; - index = (code.data & 0x1000000) != 0; - add = (code.data & 0x800000) != 0; - wback = (code.data & 0x200000) != 0; - - reject(!index && !wback, "Related encodings"); - reject(wback && (n == t || n == t2), "UNPREDICTABLE"); - reject(n == 15 || t == 13 || t == 15 || t2 == 13 || t2 == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("strd%s %s,%s,%s", fmt_cond(cond), fmt_reg(t), fmt_reg(t2), fmt_mem_imm(n, imm32, index, add, wback)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 n_value = context.read_gpr(n); + const u32 n_value = cpu.read_gpr(n); const u32 offset = add ? n_value + imm32 : n_value - imm32; const u32 addr = index ? offset : n_value; - vm::write64(addr, (u64)context.read_gpr(t2) << 32 | (u64)context.read_gpr(t)); + vm::write64(addr, (u64)cpu.read_gpr(t2) << 32 | (u64)cpu.read_gpr(t)); if (wback) { - context.write_gpr(n, offset, 4); + cpu.write_gpr(n, offset, 4); } } } -void ARMv7_instrs::STRD_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::STRD_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::STRH_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::STRH_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, t, n, imm32; - bool index, add, wback; + using args = arm_code::strh_imm; + ARG(t, op); + ARG(n, op); + ARG(imm32, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0x7); - n = (code.data & 0x38) >> 3; - imm32 = (code.data & 0x7c0) >> 5; - index = true; - add = true; - wback = false; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - n = (code.data & 0xf0000) >> 16; - imm32 = (code.data & 0xfff); - index = true; - add = true; - wback = false; - - reject(n == 15, "UNDEFINED"); - reject(t == 13 || t == 15, "UNPREDICTABLE"); - break; - } - case T3: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - n = (code.data & 0xf0000) >> 16; - imm32 = (code.data & 0xff); - index = (code.data & 0x400) != 0; - add = (code.data & 0x200) != 0; - wback = (code.data & 0x100) != 0; - - reject(index && add && !wback, "STRHT"); - reject(n == 15 || (!index && !wback), "UNDEFINED"); - reject(t == 13 || t == 15 || (wback && n == t), "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("strh%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_imm(n, imm32, index, add, wback)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 offset_addr = add ? context.read_gpr(n) + imm32 : context.read_gpr(n) - imm32; - const u32 addr = index ? offset_addr : context.read_gpr(n); - vm::write16(addr, (u16)context.read_gpr(t)); + const u32 offset_addr = add ? cpu.read_gpr(n) + imm32 : cpu.read_gpr(n) - imm32; + const u32 addr = index ? offset_addr : cpu.read_gpr(n); + vm::write16(addr, (u16)cpu.read_gpr(t)); if (wback) { - context.write_gpr(n, offset_addr, type == T1 ? 2 : 4); + cpu.write_gpr(n, offset_addr, type == T1 ? 2 : 4); } } } -void ARMv7_instrs::STRH_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::STRH_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, t, n, m, shift_t, shift_n; - bool index, add, wback; + using args = arm_code::strh_reg; + ARG(t, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(index, op); + ARG(add, op); + ARG(wback, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0x7); - n = (code.data & 0x38) >> 3; - m = (code.data & 0x1c0) >> 6; - index = true; - add = true; - wback = false; - shift_t = SRType_LSL; - shift_n = 0; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - t = (code.data & 0xf000) >> 12; - n = (code.data & 0xf0000) >> 16; - m = (code.data & 0xf); - index = true; - add = true; - wback = false; - shift_t = SRType_LSL; - shift_n = (code.data & 0x30) >> 4; - - reject(n == 15, "UNDEFINED"); - reject(t == 13 || t == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("strh%s %s,%s", fmt_cond(cond), fmt_reg(t), fmt_mem_reg(n, m, index, add, wback, shift_t, shift_n)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 offset = Shift(context.read_gpr(m), shift_t, shift_n, context.APSR.C); - const u32 offset_addr = add ? context.read_gpr(n) + offset : context.read_gpr(n) - offset; - const u32 addr = index ? offset_addr : context.read_gpr(n); - vm::write16(addr, (u16)context.read_gpr(t)); + const u32 offset = Shift(cpu.read_gpr(m), shift_t, shift_n, cpu.APSR.C); + const u32 offset_addr = add ? cpu.read_gpr(n) + offset : cpu.read_gpr(n) - offset; + const u32 addr = index ? offset_addr : cpu.read_gpr(n); + vm::write16(addr, (u16)cpu.read_gpr(t)); if (wback) { - context.write_gpr(n, offset_addr, type == T1 ? 2 : 4); + cpu.write_gpr(n, offset_addr, type == T1 ? 2 : 4); } } } -void ARMv7_instrs::STREX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::STREX(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, d, t, n, imm32; + using args = arm_code::strex; + ARG(d, op); + ARG(t, op); + ARG(n, op); + ARG(imm32, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - t = (code.data & 0xf000) >> 12; - n = (code.data & 0xf0000) >> 16; - imm32 = (code.data & 0xff) << 2; - - reject(d == 13 || d == 15 || t == 13 || t == 15 || n == 15, "UNPREDICTABLE"); - reject(d == n || d == t, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("strex%s %s,%s,[%s,#0x%x]", fmt_cond(cond), fmt_reg(d), fmt_reg(t), fmt_reg(n), imm32); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 addr = context.read_gpr(n) + imm32; - const u32 value = context.read_gpr(t); - context.write_gpr(d, !vm::reservation_update(addr, &value, sizeof(value)), 4); + const u32 addr = cpu.read_gpr(n) + imm32; + const u32 value = cpu.read_gpr(t); + cpu.write_gpr(d, !vm::reservation_update(addr, &value, sizeof(value)), 4); } } -void ARMv7_instrs::STREXB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::STREXB(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::STREXD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::STREXD(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::STREXH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::STREXH(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SUB_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SUB_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - bool set_flags = !context.ITSTATE; - u32 cond, d, n, imm32; + using args = arm_code::sub_imm; + ARG(d, op); + ARG(n, op); + ARG(imm32, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0x7); - n = (code.data & 0x38) >> 3; - imm32 = (code.data & 0x1c) >> 6; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - d = n = (code.data & 0x700) >> 8; - imm32 = (code.data & 0xff); - break; - } - case T3: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - set_flags = (code.data & 0x100000) != 0; - imm32 = ThumbExpandImm((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff)); - - reject(d == 15 && set_flags, "CMP (immediate)"); - reject(n == 13, "SUB (SP minus immediate)"); - reject(d == 13 || d == 15 || n == 15, "UNPREDICTABLE"); - break; - } - case T4: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - set_flags = false; - imm32 = (code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff); - - reject(d == 15, "ADR"); - reject(n == 13, "SUB (SP minus immediate)"); - reject(d == 13 || d == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("sub%s%s %s,%s,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), imm32); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry, overflow; - const u32 result = AddWithCarry(context.read_gpr(n), ~imm32, true, carry, overflow); - context.write_gpr(d, result, type < T3 ? 2 : 4); + const u32 result = AddWithCarry(cpu.read_gpr(n), ~imm32, true, carry, overflow); + cpu.write_gpr(d, result, type < T3 ? 2 : 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; - context.APSR.V = overflow; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; + cpu.APSR.V = overflow; } } } -void ARMv7_instrs::SUB_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SUB_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - bool set_flags = !context.ITSTATE; - u32 cond, d, n, m, shift_t, shift_n; + using args = arm_code::sub_reg; + ARG(d, op); + ARG(n, op); + ARG(m, op); + ARG(shift_t, op); + ARG(shift_n, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0x7); - n = (code.data & 0x38) >> 3; - m = (code.data & 0x1c0) >> 6; - shift_t = SRType_LSL; - shift_n = 0; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - m = (code.data & 0xf); - set_flags = (code.data & 0x100000) != 0; - shift_t = DecodeImmShift((code.data & 0x30) >> 4, (code.data & 0x7000) >> 10 | (code.data & 0xc0) >> 6, &shift_n); - - reject(d == 15 && set_flags, "CMP (register)"); - reject(n == 13, "SUB (SP minus register)"); - reject(d == 13 || d == 15 || n == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("sub%s%s %s,%s,%s%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), fmt_reg(n), fmt_reg(m), fmt_shift(shift_t, shift_n)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry, overflow; - const u32 shifted = Shift(context.read_gpr(m), shift_t, shift_n, context.APSR.C); - const u32 result = AddWithCarry(context.read_gpr(n), ~shifted, true, carry, overflow); - context.write_gpr(d, result, type == T1 ? 2 : 4); + const u32 shifted = Shift(cpu.read_gpr(m), shift_t, shift_n, cpu.APSR.C); + const u32 result = AddWithCarry(cpu.read_gpr(n), ~shifted, true, carry, overflow); + cpu.write_gpr(d, result, type == T1 ? 2 : 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; - context.APSR.V = overflow; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; + cpu.APSR.V = overflow; } } } -void ARMv7_instrs::SUB_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SUB_RSR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SUB_SPI(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SUB_SPI(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, d, imm32; - bool set_flags; + using args = arm_code::sub_spi; + ARG(d, op); + ARG(imm32, op); + ARG(set_flags, op, cond); - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = 13; - set_flags = false; - imm32 = (code.data & 0x7f) << 2; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - set_flags = (code.data & 0x100000) != 0; - imm32 = ThumbExpandImm((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff)); - - reject(d == 15 && set_flags, "CMP (immediate)"); - reject(d == 15, "UNPREDICTABLE"); - break; - } - case T3: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - set_flags = false; - imm32 = (code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff); - - reject(d == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("sub%s%s %s,sp,#0x%X", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d), imm32); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) + if (ConditionPassed(cpu, cond)) { bool carry, overflow; - const u32 result = AddWithCarry(context.SP, ~imm32, true, carry, overflow); - context.write_gpr(d, result, type == T1 ? 2 : 4); + const u32 result = AddWithCarry(cpu.SP, ~imm32, true, carry, overflow); + cpu.write_gpr(d, result, type == T1 ? 2 : 4); if (set_flags) { - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; - context.APSR.V = overflow; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = carry; + cpu.APSR.V = overflow; } } } -void ARMv7_instrs::SUB_SPR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SUB_SPR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SVC(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SVC(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SXTAB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SXTAB(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SXTAB16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SXTAB16(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SXTAH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SXTAH(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SXTB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SXTB(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SXTB16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SXTB16(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::SXTH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::SXTH(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::TB_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::TB_(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::TEQ_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::TEQ_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::TEQ_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::TEQ_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::TEQ_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::TEQ_RSR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::TST_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::TST_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - bool carry = context.APSR.C; - u32 cond, n, imm32; + using args = arm_code::tst_imm; + ARG(n, op); + ARG(imm32, op); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - n = (code.data & 0xf0000) >> 16; - imm32 = ThumbExpandImm_C((code.data & 0x4000000) >> 15 | (code.data & 0x7000) >> 4 | (code.data & 0xff), carry, carry); - - reject(n == 13 || n == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("tst%s %s,#0x%X", fmt_cond(cond), fmt_reg(n), imm32); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u32 result = context.read_gpr(n) & imm32; - context.APSR.N = result >> 31; - context.APSR.Z = result == 0; - context.APSR.C = carry; + const u32 result = cpu.read_gpr(n) & imm32; + cpu.APSR.N = result >> 31; + cpu.APSR.Z = result == 0; + cpu.APSR.C = args::carry::extract(op, cpu.APSR.C); } } -void ARMv7_instrs::TST_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::TST_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::TST_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::TST_RSR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UADD16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UADD16(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UADD8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UADD8(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UASX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UASX(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UBFX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UBFX(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UDIV(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UDIV(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UHADD16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UHADD16(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UHADD8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UHADD8(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UHASX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UHASX(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UHSAX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UHSAX(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UHSUB16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UHSUB16(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UHSUB8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UHSUB8(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UMAAL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UMAAL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UMLAL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UMLAL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UMULL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UMULL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, d0, d1, n, m; - bool set_flags; + using args = arm_code::umull; + ARG(d0, op); + ARG(d1, op); + ARG(n, op); + ARG(m, op); + ARG(set_flags, op, cond); - switch (type) + if (ConditionPassed(cpu, cond)) { - case T1: - { - cond = context.ITSTATE.advance(); - d0 = (code.data & 0xf000) >> 12; - d1 = (code.data & 0xf00) >> 8; - n = (code.data & 0xf0000) >> 16; - m = (code.data & 0xf); - set_flags = false; - - reject(d0 == 13 || d0 == 15 || d1 == 13 || d1 == 15 || n == 13 || n == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - reject(d0 == d1, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) - { - if (context.debug & DF_DISASM) context.fmt_debug_str("umull%s%s %s,%s,%s,%s", set_flags ? "s" : "", fmt_cond(cond), fmt_reg(d0), fmt_reg(d1), fmt_reg(n), fmt_reg(m)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - const u64 result = (u64)context.read_gpr(n) * (u64)context.read_gpr(m); - context.write_gpr(d1, (u32)(result >> 32), 4); - context.write_gpr(d0, (u32)(result), 4); + const u64 result = (u64)cpu.read_gpr(n) * (u64)cpu.read_gpr(m); + cpu.write_gpr(d1, (u32)(result >> 32), 4); + cpu.write_gpr(d0, (u32)(result), 4); if (set_flags) { - context.APSR.N = result >> 63 != 0; - context.APSR.Z = result == 0; + cpu.APSR.N = result >> 63 != 0; + cpu.APSR.Z = result == 0; } } } -void ARMv7_instrs::UQADD16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UQADD16(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UQADD8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UQADD8(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UQASX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UQASX(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UQSAX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UQSAX(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UQSUB16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UQSUB16(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UQSUB8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UQSUB8(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::USAD8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::USAD8(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::USADA8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::USADA8(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::USAT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::USAT(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::USAT16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::USAT16(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::USAX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::USAX(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::USUB16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::USUB16(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::USUB8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::USUB8(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UXTAB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UXTAB(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UXTAB16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UXTAB16(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UXTAH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UXTAH(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UXTB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UXTB(ARMv7Thread& cpu, const u32 op, const u32 cond) { - u32 cond, d, m, rot; - - switch (type) - { - case T1: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0x7); - m = (code.data & 0x38) >> 3; - rot = 0; - break; - } - case T2: - { - cond = context.ITSTATE.advance(); - d = (code.data & 0xf00) >> 8; - m = (code.data & 0xf); - rot = (code.data & 0x30) >> 1; + using args = arm_code::uxtb; + ARG(d, op); + ARG(m, op); + ARG(rotation, op); - reject(d == 13 || d == 15 || m == 13 || m == 15, "UNPREDICTABLE"); - break; - } - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } - - if (context.debug) + if (ConditionPassed(cpu, cond)) { - if (context.debug & DF_DISASM) context.fmt_debug_str("uxtb%s %s,%s%s", fmt_cond(cond), fmt_reg(d), fmt_reg(m), fmt_shift(SRType_ROR, rot)); - if (process_debug(context)) return; - } - - if (ConditionPassed(context, cond)) - { - context.write_gpr(d, (context.read_gpr(m) >> rot) & 0xff, type == T1 ? 2 : 4); + cpu.write_gpr(d, u8(cpu.read_gpr(m) >> rotation), type == T1 ? 2 : 4); } } -void ARMv7_instrs::UXTB16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UXTB16(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::UXTH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::UXTH(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VABA_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VABA_(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VABD_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VABD_(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VABD_FP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VABD_FP(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VABS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VABS(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VAC__(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VAC__(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VADD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VADD(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VADD_FP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VADD_FP(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VADDHN(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VADDHN(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VADD_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VADD_(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VAND(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VAND(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VBIC_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VBIC_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VBIC_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VBIC_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VB__(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VB__(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VCEQ_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VCEQ_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VCEQ_ZERO(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VCEQ_ZERO(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VCGE_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VCGE_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VCGE_ZERO(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VCGE_ZERO(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VCGT_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VCGT_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VCGT_ZERO(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VCGT_ZERO(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VCLE_ZERO(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VCLE_ZERO(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VCLS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VCLS(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VCLT_ZERO(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VCLT_ZERO(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VCLZ(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VCLZ(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VCMP_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VCMP_(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VCNT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VCNT(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VCVT_FIA(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VCVT_FIA(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VCVT_FIF(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VCVT_FIF(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VCVT_FFA(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VCVT_FFA(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VCVT_FFF(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VCVT_FFF(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VCVT_DF(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VCVT_DF(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VCVT_HFA(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VCVT_HFA(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VCVT_HFF(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VCVT_HFF(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VDIV(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VDIV(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VDUP_S(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VDUP_S(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VDUP_R(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VDUP_R(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VEOR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VEOR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VEXT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VEXT(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VHADDSUB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VHADDSUB(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VLD__MS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VLD__MS(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VLD1_SL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VLD1_SL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VLD1_SAL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VLD1_SAL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VLD2_SL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VLD2_SL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VLD2_SAL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VLD2_SAL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VLD3_SL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VLD3_SL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VLD3_SAL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VLD3_SAL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VLD4_SL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VLD4_SL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VLD4_SAL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VLD4_SAL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VLDM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VLDM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VLDR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VLDR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VMAXMIN(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VMAXMIN(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VMAXMIN_FP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VMAXMIN_FP(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VML__(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VML__(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VML__FP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VML__FP(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VML__S(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VML__S(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VMOV_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VMOV_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VMOV_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VMOV_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VMOV_RS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VMOV_RS(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VMOV_SR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VMOV_SR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VMOV_RF(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VMOV_RF(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VMOV_2RF(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VMOV_2RF(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VMOV_2RD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VMOV_2RD(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VMOVL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VMOVL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VMOVN(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VMOVN(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VMRS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VMRS(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VMSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VMSR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VMUL_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VMUL_(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VMUL_FP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VMUL_FP(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VMUL_S(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VMUL_S(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VMVN_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VMVN_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VMVN_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VMVN_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VNEG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VNEG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VNM__(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VNM__(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VORN_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VORN_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VORR_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VORR_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VORR_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VORR_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VPADAL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VPADAL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VPADD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VPADD(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VPADD_FP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VPADD_FP(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VPADDL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VPADDL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VPMAXMIN(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VPMAXMIN(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VPMAXMIN_FP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VPMAXMIN_FP(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VPOP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VPOP(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VPUSH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VPUSH(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VQABS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VQABS(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VQADD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VQADD(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VQDML_L(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VQDML_L(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VQDMULH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VQDMULH(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VQDMULL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VQDMULL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VQMOV_N(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VQMOV_N(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VQNEG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VQNEG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VQRDMULH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VQRDMULH(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VQRSHL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VQRSHL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VQRSHR_N(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VQRSHR_N(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VQSHL_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VQSHL_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VQSHL_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VQSHL_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VQSHR_N(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VQSHR_N(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VQSUB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VQSUB(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VRADDHN(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VRADDHN(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VRECPE(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VRECPE(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VRECPS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VRECPS(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VREV__(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VREV__(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VRHADD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VRHADD(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VRSHL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VRSHL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VRSHR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VRSHR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VRSHRN(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VRSHRN(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VRSQRTE(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VRSQRTE(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VRSQRTS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VRSQRTS(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VRSRA(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VRSRA(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VRSUBHN(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VRSUBHN(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VSHL_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VSHL_IMM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VSHL_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VSHL_REG(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VSHLL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VSHLL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VSHR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VSHR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VSHRN(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VSHRN(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VSLI(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VSLI(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VSQRT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VSQRT(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VSRA(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VSRA(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VSRI(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VSRI(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VST__MS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VST__MS(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VST1_SL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VST1_SL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VST2_SL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VST2_SL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VST3_SL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VST3_SL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VST4_SL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VST4_SL(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VSTM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VSTM(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VSTR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VSTR(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VSUB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VSUB(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VSUB_FP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VSUB_FP(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VSUBHN(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VSUBHN(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VSUB_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VSUB_(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VSWP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VSWP(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VTB_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VTB_(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VTRN(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VTRN(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VTST(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VTST(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VUZP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VUZP(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::VZIP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::VZIP(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::WFE(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::WFE(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::WFI(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::WFI(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } -void ARMv7_instrs::YIELD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) +template +void arm_interpreter::YIELD(ARMv7Thread& cpu, const u32 op, const u32 cond) { - switch (type) - { - case A1: throw EXCEPTION(""); - default: throw EXCEPTION(""); - } + throw EXCEPTION("TODO"); } + +template void arm_interpreter::HACK(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::HACK(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADC_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADC_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADC_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADC_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADC_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADC_RSR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADD_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADD_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADD_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADD_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADD_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADD_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADD_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADD_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADD_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADD_RSR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADD_SPI(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADD_SPI(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADD_SPI(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADD_SPI(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADD_SPI(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADD_SPR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADD_SPR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADD_SPR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADD_SPR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ADR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::AND_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::AND_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::AND_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::AND_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::AND_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::AND_RSR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ASR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ASR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ASR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ASR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ASR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ASR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::B(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::B(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::B(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::B(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::B(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::BFC(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::BFC(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::BFI(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::BFI(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::BIC_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::BIC_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::BIC_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::BIC_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::BIC_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::BIC_RSR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::BKPT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::BKPT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::BL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::BL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::BL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::BL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::BLX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::BLX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::BX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::BX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::CB_Z(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::CLZ(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::CLZ(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::CMN_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::CMN_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::CMN_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::CMN_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::CMN_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::CMN_RSR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::CMP_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::CMP_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::CMP_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::CMP_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::CMP_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::CMP_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::CMP_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::CMP_RSR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::DBG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::DBG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::DMB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::DMB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::DSB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::DSB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::EOR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::EOR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::EOR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::EOR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::EOR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::EOR_RSR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::IT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDMDA(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDMDB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDMDB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDMIB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDR_LIT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDR_LIT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDR_LIT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRB_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRB_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRB_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRB_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRB_LIT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRB_LIT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRB_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRB_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRB_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRD_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRD_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRD_LIT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRD_LIT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRD_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDREX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDREX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDREXB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDREXB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDREXD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDREXD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDREXH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDREXH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRH_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRH_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRH_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRH_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRH_LIT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRH_LIT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRH_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRH_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRH_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRSB_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRSB_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRSB_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRSB_LIT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRSB_LIT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRSB_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRSB_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRSB_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRSH_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRSH_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRSH_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRSH_LIT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRSH_LIT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRSH_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRSH_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LDRSH_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LSL_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LSL_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LSL_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LSL_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LSL_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LSL_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LSR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LSR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LSR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LSR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LSR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::LSR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MLA(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MLA(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MLS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MLS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MOV_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MOV_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MOV_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MOV_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MOV_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MOV_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MOV_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MOV_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MOV_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MOVT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MOVT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MRC_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MRC_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MRC_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MRC_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MRS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MRS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MSR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MSR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MSR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MUL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MUL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MUL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MVN_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MVN_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MVN_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MVN_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MVN_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::MVN_RSR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::NOP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::NOP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::NOP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ORN_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ORN_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ORR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ORR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ORR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ORR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ORR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ORR_RSR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::PKH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::PKH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::POP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::POP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::POP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::POP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::POP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::PUSH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::PUSH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::PUSH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::PUSH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::PUSH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::QADD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::QADD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::QADD16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::QADD16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::QADD8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::QADD8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::QASX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::QASX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::QDADD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::QDADD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::QDSUB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::QDSUB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::QSAX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::QSAX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::QSUB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::QSUB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::QSUB16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::QSUB16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::QSUB8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::QSUB8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::RBIT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::RBIT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::REV(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::REV(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::REV(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::REV16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::REV16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::REV16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::REVSH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::REVSH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::REVSH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ROR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ROR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ROR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ROR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::ROR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::RRX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::RRX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::RSB_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::RSB_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::RSB_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::RSB_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::RSB_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::RSB_RSR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::RSC_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::RSC_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::RSC_RSR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SADD16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SADD16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SADD8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SADD8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SASX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SASX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SBC_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SBC_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SBC_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SBC_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SBC_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SBC_RSR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SBFX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SBFX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SDIV(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SEL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SEL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SHADD16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SHADD16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SHADD8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SHADD8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SHASX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SHASX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SHSAX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SHSAX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SHSUB16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SHSUB16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SHSUB8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SHSUB8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMLA__(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMLA__(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMLAD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMLAD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMLAL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMLAL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMLAL__(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMLAL__(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMLALD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMLALD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMLAW_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMLAW_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMLSD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMLSD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMLSLD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMLSLD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMMLA(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMMLA(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMMLS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMMLS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMMUL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMMUL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMUAD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMUAD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMUL__(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMUL__(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMULL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMULL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMULW_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMULW_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMUSD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SMUSD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SSAT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SSAT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SSAT16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SSAT16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SSAX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SSAX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SSUB16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SSUB16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SSUB8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SSUB8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STMDA(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STMDB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STMDB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STMIB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STRB_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STRB_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STRB_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STRB_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STRB_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STRB_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STRB_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STRD_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STRD_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STRD_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STREX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STREX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STREXB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STREXB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STREXD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STREXD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STREXH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STREXH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STRH_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STRH_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STRH_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STRH_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STRH_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STRH_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::STRH_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SUB_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SUB_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SUB_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SUB_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SUB_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SUB_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SUB_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SUB_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SUB_RSR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SUB_SPI(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SUB_SPI(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SUB_SPI(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SUB_SPI(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SUB_SPR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SUB_SPR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SVC(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SVC(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SXTAB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SXTAB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SXTAB16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SXTAB16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SXTAH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SXTAH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SXTB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SXTB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SXTB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SXTB16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SXTB16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SXTH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SXTH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::SXTH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::TB_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::TEQ_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::TEQ_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::TEQ_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::TEQ_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::TEQ_RSR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::TST_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::TST_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::TST_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::TST_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::TST_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::TST_RSR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UADD16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UADD16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UADD8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UADD8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UASX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UASX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UBFX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UBFX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UDIV(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UHADD16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UHADD16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UHADD8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UHADD8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UHASX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UHASX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UHSAX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UHSAX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UHSUB16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UHSUB16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UHSUB8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UHSUB8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UMAAL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UMAAL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UMLAL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UMLAL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UMULL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UMULL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UQADD16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UQADD16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UQADD8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UQADD8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UQASX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UQASX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UQSAX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UQSAX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UQSUB16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UQSUB16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UQSUB8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UQSUB8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::USAD8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::USAD8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::USADA8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::USADA8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::USAT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::USAT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::USAT16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::USAT16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::USAX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::USAX(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::USUB16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::USUB16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::USUB8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::USUB8(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UXTAB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UXTAB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UXTAB16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UXTAB16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UXTAH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UXTAH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UXTB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UXTB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UXTB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UXTB16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UXTB16(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UXTH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UXTH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::UXTH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VABA_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VABA_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VABA_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VABA_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VABD_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VABD_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VABD_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VABD_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VABD_FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VABD_FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VABS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VABS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VABS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VABS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VAC__(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VAC__(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VADD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VADD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VADD_FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VADD_FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VADD_FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VADD_FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VADDHN(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VADDHN(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VADD_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VADD_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VAND(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VAND(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VBIC_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VBIC_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VBIC_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VBIC_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VB__(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VB__(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCEQ_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCEQ_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCEQ_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCEQ_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCEQ_ZERO(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCEQ_ZERO(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCGE_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCGE_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCGE_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCGE_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCGE_ZERO(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCGE_ZERO(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCGT_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCGT_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCGT_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCGT_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCGT_ZERO(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCGT_ZERO(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCLE_ZERO(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCLE_ZERO(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCLS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCLS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCLT_ZERO(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCLT_ZERO(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCLZ(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCLZ(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCMP_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCMP_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCMP_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCMP_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCNT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCNT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCVT_FIA(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCVT_FIA(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCVT_FIF(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCVT_FIF(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCVT_FFA(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCVT_FFA(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCVT_FFF(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCVT_FFF(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCVT_DF(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCVT_DF(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCVT_HFA(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCVT_HFA(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCVT_HFF(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VCVT_HFF(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VDIV(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VDIV(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VDUP_S(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VDUP_S(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VDUP_R(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VDUP_R(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VEOR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VEOR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VEXT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VEXT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VHADDSUB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VHADDSUB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLD__MS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLD__MS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLD1_SAL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLD1_SAL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLD1_SL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLD1_SL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLD2_SAL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLD2_SAL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLD2_SL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLD2_SL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLD3_SAL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLD3_SAL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLD3_SL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLD3_SL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLD4_SAL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLD4_SAL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLD4_SL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLD4_SL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLDM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLDM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLDM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLDM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLDR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLDR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLDR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VLDR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMAXMIN(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMAXMIN(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMAXMIN_FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMAXMIN_FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VML__(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VML__(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VML__(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VML__(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VML__FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VML__FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VML__FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VML__FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VML__S(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VML__S(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VML__S(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VML__S(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOV_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOV_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOV_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOV_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOV_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOV_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOV_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOV_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOV_RS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOV_RS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOV_SR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOV_SR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOV_RF(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOV_RF(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOV_2RF(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOV_2RF(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOV_2RD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOV_2RD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOVL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOVL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOVN(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMOVN(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMRS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMRS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMSR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMSR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMUL_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMUL_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMUL_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMUL_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMUL_FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMUL_FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMUL_FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMUL_FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMUL_S(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMUL_S(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMUL_S(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMUL_S(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMVN_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMVN_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMVN_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VMVN_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VNEG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VNEG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VNEG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VNEG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VNM__(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VNM__(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VNM__(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VNM__(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VORN_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VORN_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VORR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VORR_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VORR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VORR_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VPADAL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VPADAL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VPADD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VPADD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VPADD_FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VPADD_FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VPADDL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VPADDL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VPMAXMIN(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VPMAXMIN(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VPMAXMIN_FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VPMAXMIN_FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VPOP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VPOP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VPOP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VPOP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VPUSH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VPUSH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VPUSH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VPUSH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQABS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQABS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQADD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQADD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQDML_L(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQDML_L(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQDML_L(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQDML_L(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQDMULH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQDMULH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQDMULH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQDMULH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQDMULL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQDMULL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQDMULL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQDMULL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQMOV_N(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQMOV_N(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQNEG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQNEG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQRDMULH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQRDMULH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQRDMULH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQRDMULH(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQRSHL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQRSHL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQRSHR_N(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQRSHR_N(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQSHL_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQSHL_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQSHL_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQSHL_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQSHR_N(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQSHR_N(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQSUB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VQSUB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRADDHN(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRADDHN(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRECPE(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRECPE(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRECPS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRECPS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VREV__(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VREV__(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRHADD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRHADD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRSHL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRSHL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRSHR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRSHR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRSHRN(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRSHRN(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRSQRTE(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRSQRTE(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRSQRTS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRSQRTS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRSRA(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRSRA(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRSUBHN(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VRSUBHN(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSHL_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSHL_IMM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSHL_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSHL_REG(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSHLL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSHLL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSHLL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSHLL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSHR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSHR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSHRN(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSHRN(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSLI(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSLI(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSQRT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSQRT(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSRA(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSRA(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSRI(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSRI(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VST__MS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VST__MS(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VST1_SL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VST1_SL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VST2_SL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VST2_SL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VST3_SL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VST3_SL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VST4_SL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VST4_SL(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSTM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSTM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSTM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSTM(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSTR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSTR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSTR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSTR(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSUB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSUB(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSUB_FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSUB_FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSUB_FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSUB_FP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSUBHN(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSUBHN(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSUB_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSUB_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSWP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VSWP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VTB_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VTB_(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VTRN(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VTRN(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VTST(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VTST(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VUZP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VUZP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VZIP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::VZIP(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::WFE(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::WFE(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::WFE(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::WFI(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::WFI(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::WFI(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::YIELD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::YIELD(ARMv7Thread&, const u32, const u32); +template void arm_interpreter::YIELD(ARMv7Thread&, const u32, const u32); diff --git a/rpcs3/Emu/ARMv7/ARMv7Interpreter.h b/rpcs3/Emu/ARMv7/ARMv7Interpreter.h index e759f5e40b..33f3b3d622 100644 --- a/rpcs3/Emu/ARMv7/ARMv7Interpreter.h +++ b/rpcs3/Emu/ARMv7/ARMv7Interpreter.h @@ -1,455 +1,604 @@ #pragma once -union ARMv7Code +#include "ARMv7Thread.h" +#include "ARMv7Opcodes.h" + +struct arm_interpreter { - struct + template + static u32 BitCount(T x, size_t len) { - u16 code0; - u16 code1; - }; + u32 result = 0; - u32 data; -}; - -enum ARMv7_encoding -{ - T1, T2, T3, T4, A1, A2 -}; - -enum SRType : u32 -{ - SRType_LSL, - SRType_LSR, - SRType_ASR, - SRType_ROR, - SRType_RRX, -}; - -namespace ARMv7_instrs -{ - void UNK(ARMv7Context& context, const ARMv7Code code); - - void HACK(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void MRC_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void ADC_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void ADC_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void ADC_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void ADD_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void ADD_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void ADD_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void ADD_SPI(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void ADD_SPR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void ADR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void AND_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void AND_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void AND_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void ASR_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void ASR_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void B(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void BFC(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void BFI(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void BIC_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void BIC_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void BIC_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void BKPT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void BL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void BLX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void BX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void CB_Z(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void CLZ(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void CMN_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void CMN_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void CMN_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void CMP_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void CMP_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void CMP_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void DBG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void DMB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void DSB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void EOR_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void EOR_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void EOR_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void IT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void LDM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void LDMDA(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void LDMDB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void LDMIB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void LDR_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void LDR_LIT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void LDR_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void LDRB_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void LDRB_LIT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void LDRB_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void LDRD_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void LDRD_LIT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void LDRD_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void LDRH_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void LDRH_LIT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void LDRH_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void LDRSB_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void LDRSB_LIT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void LDRSB_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void LDRSH_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void LDRSH_LIT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void LDRSH_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void LDREX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void LDREXB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void LDREXD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void LDREXH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void LSL_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void LSL_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void LSR_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void LSR_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void MLA(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void MLS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void MOV_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void MOV_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void MOVT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void MRS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void MSR_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void MSR_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void MUL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void MVN_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void MVN_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void MVN_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void NOP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void ORN_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void ORN_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void ORR_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void ORR_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void ORR_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void PKH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void POP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void PUSH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void QADD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void QADD16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void QADD8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void QASX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void QDADD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void QDSUB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void QSAX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void QSUB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void QSUB16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void QSUB8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void RBIT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void REV(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void REV16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void REVSH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void ROR_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void ROR_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void RRX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void RSB_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void RSB_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void RSB_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void RSC_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void RSC_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void RSC_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void SADD16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SADD8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SASX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void SBC_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SBC_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SBC_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void SBFX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void SDIV(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void SEL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void SHADD16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SHADD8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SHASX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SHSAX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SHSUB16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SHSUB8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void SMLA__(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SMLAD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SMLAL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SMLAL__(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SMLALD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SMLAW_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SMLSD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SMLSLD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SMMLA(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SMMLS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SMMUL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SMUAD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SMUL__(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SMULL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SMULW_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SMUSD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void SSAT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SSAT16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SSAX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SSUB16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SSUB8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void STM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void STMDA(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void STMDB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void STMIB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void STR_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void STR_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void STRB_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void STRB_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void STRD_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void STRD_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void STRH_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void STRH_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void STREX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void STREXB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void STREXD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void STREXH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void SUB_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SUB_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SUB_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SUB_SPI(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SUB_SPR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void SVC(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void SXTAB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SXTAB16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SXTAH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SXTB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SXTB16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void SXTH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void TB_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void TEQ_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void TEQ_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void TEQ_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void TST_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void TST_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void TST_RSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void UADD16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UADD8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UASX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UBFX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UDIV(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UHADD16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UHADD8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UHASX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UHSAX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UHSUB16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UHSUB8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UMAAL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UMLAL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UMULL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UQADD16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UQADD8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UQASX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UQSAX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UQSUB16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UQSUB8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void USAD8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void USADA8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void USAT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void USAT16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void USAX(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void USUB16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void USUB8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UXTAB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UXTAB16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UXTAH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UXTB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UXTB16(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void UXTH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void VABA_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VABD_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VABD_FP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VABS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VAC__(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VADD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VADD_FP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VADDHN(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VADD_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VAND(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VBIC_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VBIC_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VB__(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VCEQ_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VCEQ_ZERO(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VCGE_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VCGE_ZERO(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VCGT_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VCGT_ZERO(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VCLE_ZERO(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VCLS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VCLT_ZERO(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VCLZ(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VCMP_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VCNT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VCVT_FIA(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VCVT_FIF(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VCVT_FFA(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VCVT_FFF(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VCVT_DF(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VCVT_HFA(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VCVT_HFF(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VDIV(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VDUP_S(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VDUP_R(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VEOR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VEXT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VHADDSUB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VLD__MS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VLD1_SL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VLD1_SAL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VLD2_SL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VLD2_SAL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VLD3_SL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VLD3_SAL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VLD4_SL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VLD4_SAL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VLDM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VLDR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VMAXMIN(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VMAXMIN_FP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VML__(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VML__FP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VML__S(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VMOV_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VMOV_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VMOV_RS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VMOV_SR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VMOV_RF(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VMOV_2RF(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VMOV_2RD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VMOVL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VMOVN(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VMRS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VMSR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VMUL_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VMUL_FP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VMUL_S(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VMVN_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VMVN_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VNEG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VNM__(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VORN_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VORR_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VORR_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VPADAL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VPADD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VPADD_FP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VPADDL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VPMAXMIN(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VPMAXMIN_FP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VPOP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VPUSH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VQABS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VQADD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VQDML_L(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VQDMULH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VQDMULL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VQMOV_N(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VQNEG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VQRDMULH(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VQRSHL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VQRSHR_N(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VQSHL_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VQSHL_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VQSHR_N(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VQSUB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VRADDHN(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VRECPE(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VRECPS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VREV__(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VRHADD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VRSHL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VRSHR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VRSHRN(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VRSQRTE(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VRSQRTS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VRSRA(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VRSUBHN(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VSHL_IMM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VSHL_REG(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VSHLL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VSHR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VSHRN(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VSLI(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VSQRT(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VSRA(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VSRI(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VST__MS(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VST1_SL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VST2_SL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VST3_SL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VST4_SL(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VSTM(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VSTR(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VSUB(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VSUB_FP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VSUBHN(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VSUB_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VSWP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VTB_(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VTRN(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VTST(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VUZP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void VZIP(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - void WFE(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void WFI(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - void YIELD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); + for (T mask = static_cast(1) << (len - 1); mask; mask >>= 1) + { + if (x & mask) result++; + } + + return result; + } + + static u32 DecodeImmShift(u32 type, u32 imm5, u32* shift_n) + { + using namespace arm_code; + + SRType shift_t; + + switch (type) + { + case 0: shift_t = SRType_LSL; if (shift_n) *shift_n = imm5; break; + case 1: shift_t = SRType_LSR; if (shift_n) *shift_n = imm5 == 0 ? 32 : imm5; break; + case 2: shift_t = SRType_ASR; if (shift_n) *shift_n = imm5 == 0 ? 32 : imm5; break; + case 3: + if (imm5 == 0) + { + shift_t = SRType_RRX; if (shift_n) *shift_n = 1; + } + else + { + shift_t = SRType_ROR; if (shift_n) *shift_n = imm5; + } + break; + + default: throw EXCEPTION(""); + } + + return shift_t; + } + + static u32 LSL_C(u32 x, s32 shift, bool& carry_out) + { + Expects(shift > 0); + carry_out = shift <= 32 ? (x & (1 << (32 - shift))) != 0 : false; + return shift < 32 ? x << shift : 0; + } + + static u32 LSL_(u32 x, s32 shift) + { + Expects(shift >= 0); + return shift < 32 ? x << shift : 0; + } + + static u32 LSR_C(u32 x, s32 shift, bool& carry_out) + { + Expects(shift > 0); + carry_out = shift <= 32 ? (x & (1 << (shift - 1))) != 0 : false; + return shift < 32 ? x >> shift : 0; + } + + static u32 LSR_(u32 x, s32 shift) + { + Expects(shift >= 0); + return shift < 32 ? x >> shift : 0; + } + + static s32 ASR_C(s32 x, s32 shift, bool& carry_out) + { + Expects(shift > 0); + carry_out = shift <= 32 ? (x & (1 << (shift - 1))) != 0 : x < 0; + return shift < 32 ? x >> shift : x >> 31; + } + + static s32 ASR_(s32 x, s32 shift) + { + Expects(shift >= 0); + return shift < 32 ? x >> shift : x >> 31; + } + + static u32 ROR_C(u32 x, s32 shift, bool& carry_out) + { + Expects(shift); + const u32 result = x >> shift | x << (32 - shift); + carry_out = (result >> 31) != 0; + return result; + } + + static u32 ROR_(u32 x, s32 shift) + { + return x >> shift | x << (32 - shift); + } + + static u32 RRX_C(u32 x, bool carry_in, bool& carry_out) + { + carry_out = x & 0x1; + return ((u32)carry_in << 31) | (x >> 1); + } + + static u32 RRX_(u32 x, bool carry_in) + { + return ((u32)carry_in << 31) | (x >> 1); + } + + static u32 Shift_C(u32 value, u32 type, s32 amount, bool carry_in, bool& carry_out) + { + Expects(type != arm_code::SRType_RRX || amount == 1); + + if (amount) + { + switch (type) + { + case arm_code::SRType_LSL: return LSL_C(value, amount, carry_out); + case arm_code::SRType_LSR: return LSR_C(value, amount, carry_out); + case arm_code::SRType_ASR: return ASR_C(value, amount, carry_out); + case arm_code::SRType_ROR: return ROR_C(value, amount, carry_out); + case arm_code::SRType_RRX: return RRX_C(value, carry_in, carry_out); + default: throw EXCEPTION(""); + } + } + + carry_out = carry_in; + return value; + } + + static u32 Shift(u32 value, u32 type, s32 amount, bool carry_in) + { + bool carry_out; + return Shift_C(value, type, amount, carry_in, carry_out); + } + + template static T AddWithCarry(T x, T y, bool carry_in, bool& carry_out, bool& overflow) + { + const T sign_mask = (T)1 << (sizeof(T) * 8 - 1); + + T result = x + y; + carry_out = (((x & y) | ((x ^ y) & ~result)) & sign_mask) != 0; + overflow = ((x ^ result) & (y ^ result) & sign_mask) != 0; + if (carry_in) + { + result += 1; + carry_out ^= (result == 0); + overflow ^= (result == sign_mask); + } + return result; + } + + static bool ConditionPassed(ARMv7Thread& cpu, u32 cond) + { + bool result = false; + + switch (cond >> 1) + { + case 0: result = (cpu.APSR.Z == 1); break; + case 1: result = (cpu.APSR.C == 1); break; + case 2: result = (cpu.APSR.N == 1); break; + case 3: result = (cpu.APSR.V == 1); break; + case 4: result = (cpu.APSR.C == 1) && (cpu.APSR.Z == 0); break; + case 5: result = (cpu.APSR.N == cpu.APSR.V); break; + case 6: result = (cpu.APSR.N == cpu.APSR.V) && (cpu.APSR.Z == 0); break; + case 7: return true; + } + + if (cond & 0x1) + { + return !result; + } + + return result; + } + + static void UNK(ARMv7Thread&, const u32 op, const u32 cond); + + template static void HACK(ARMv7Thread&, const u32, const u32); + template static void MRC_(ARMv7Thread&, const u32, const u32); + + template static void ADC_IMM(ARMv7Thread&, const u32, const u32); + template static void ADC_REG(ARMv7Thread&, const u32, const u32); + template static void ADC_RSR(ARMv7Thread&, const u32, const u32); + + template static void ADD_IMM(ARMv7Thread&, const u32, const u32); + template static void ADD_REG(ARMv7Thread&, const u32, const u32); + template static void ADD_RSR(ARMv7Thread&, const u32, const u32); + template static void ADD_SPI(ARMv7Thread&, const u32, const u32); + template static void ADD_SPR(ARMv7Thread&, const u32, const u32); + + template static void ADR(ARMv7Thread&, const u32, const u32); + + template static void AND_IMM(ARMv7Thread&, const u32, const u32); + template static void AND_REG(ARMv7Thread&, const u32, const u32); + template static void AND_RSR(ARMv7Thread&, const u32, const u32); + + template static void ASR_IMM(ARMv7Thread&, const u32, const u32); + template static void ASR_REG(ARMv7Thread&, const u32, const u32); + + template static void B(ARMv7Thread&, const u32, const u32); + + template static void BFC(ARMv7Thread&, const u32, const u32); + template static void BFI(ARMv7Thread&, const u32, const u32); + + template static void BIC_IMM(ARMv7Thread&, const u32, const u32); + template static void BIC_REG(ARMv7Thread&, const u32, const u32); + template static void BIC_RSR(ARMv7Thread&, const u32, const u32); + + template static void BKPT(ARMv7Thread&, const u32, const u32); + + template static void BL(ARMv7Thread&, const u32, const u32); + template static void BLX(ARMv7Thread&, const u32, const u32); + template static void BX(ARMv7Thread&, const u32, const u32); + + template static void CB_Z(ARMv7Thread&, const u32, const u32); + + template static void CLZ(ARMv7Thread&, const u32, const u32); + + template static void CMN_IMM(ARMv7Thread&, const u32, const u32); + template static void CMN_REG(ARMv7Thread&, const u32, const u32); + template static void CMN_RSR(ARMv7Thread&, const u32, const u32); + + template static void CMP_IMM(ARMv7Thread&, const u32, const u32); + template static void CMP_REG(ARMv7Thread&, const u32, const u32); + template static void CMP_RSR(ARMv7Thread&, const u32, const u32); + + template static void DBG(ARMv7Thread&, const u32, const u32); + template static void DMB(ARMv7Thread&, const u32, const u32); + template static void DSB(ARMv7Thread&, const u32, const u32); + + template static void EOR_IMM(ARMv7Thread&, const u32, const u32); + template static void EOR_REG(ARMv7Thread&, const u32, const u32); + template static void EOR_RSR(ARMv7Thread&, const u32, const u32); + + template static void IT(ARMv7Thread&, const u32, const u32); + + template static void LDM(ARMv7Thread&, const u32, const u32); + template static void LDMDA(ARMv7Thread&, const u32, const u32); + template static void LDMDB(ARMv7Thread&, const u32, const u32); + template static void LDMIB(ARMv7Thread&, const u32, const u32); + + template static void LDR_IMM(ARMv7Thread&, const u32, const u32); + template static void LDR_LIT(ARMv7Thread&, const u32, const u32); + template static void LDR_REG(ARMv7Thread&, const u32, const u32); + + template static void LDRB_IMM(ARMv7Thread&, const u32, const u32); + template static void LDRB_LIT(ARMv7Thread&, const u32, const u32); + template static void LDRB_REG(ARMv7Thread&, const u32, const u32); + + template static void LDRD_IMM(ARMv7Thread&, const u32, const u32); + template static void LDRD_LIT(ARMv7Thread&, const u32, const u32); + template static void LDRD_REG(ARMv7Thread&, const u32, const u32); + + template static void LDRH_IMM(ARMv7Thread&, const u32, const u32); + template static void LDRH_LIT(ARMv7Thread&, const u32, const u32); + template static void LDRH_REG(ARMv7Thread&, const u32, const u32); + + template static void LDRSB_IMM(ARMv7Thread&, const u32, const u32); + template static void LDRSB_LIT(ARMv7Thread&, const u32, const u32); + template static void LDRSB_REG(ARMv7Thread&, const u32, const u32); + + template static void LDRSH_IMM(ARMv7Thread&, const u32, const u32); + template static void LDRSH_LIT(ARMv7Thread&, const u32, const u32); + template static void LDRSH_REG(ARMv7Thread&, const u32, const u32); + + template static void LDREX(ARMv7Thread&, const u32, const u32); + template static void LDREXB(ARMv7Thread&, const u32, const u32); + template static void LDREXD(ARMv7Thread&, const u32, const u32); + template static void LDREXH(ARMv7Thread&, const u32, const u32); + + template static void LSL_IMM(ARMv7Thread&, const u32, const u32); + template static void LSL_REG(ARMv7Thread&, const u32, const u32); + + template static void LSR_IMM(ARMv7Thread&, const u32, const u32); + template static void LSR_REG(ARMv7Thread&, const u32, const u32); + + template static void MLA(ARMv7Thread&, const u32, const u32); + template static void MLS(ARMv7Thread&, const u32, const u32); + + template static void MOV_IMM(ARMv7Thread&, const u32, const u32); + template static void MOV_REG(ARMv7Thread&, const u32, const u32); + template static void MOVT(ARMv7Thread&, const u32, const u32); + + template static void MRS(ARMv7Thread&, const u32, const u32); + template static void MSR_IMM(ARMv7Thread&, const u32, const u32); + template static void MSR_REG(ARMv7Thread&, const u32, const u32); + + template static void MUL(ARMv7Thread&, const u32, const u32); + + template static void MVN_IMM(ARMv7Thread&, const u32, const u32); + template static void MVN_REG(ARMv7Thread&, const u32, const u32); + template static void MVN_RSR(ARMv7Thread&, const u32, const u32); + + template static void NOP(ARMv7Thread&, const u32, const u32); + + template static void ORN_IMM(ARMv7Thread&, const u32, const u32); + template static void ORN_REG(ARMv7Thread&, const u32, const u32); + + template static void ORR_IMM(ARMv7Thread&, const u32, const u32); + template static void ORR_REG(ARMv7Thread&, const u32, const u32); + template static void ORR_RSR(ARMv7Thread&, const u32, const u32); + + template static void PKH(ARMv7Thread&, const u32, const u32); + + template static void POP(ARMv7Thread&, const u32, const u32); + template static void PUSH(ARMv7Thread&, const u32, const u32); + + template static void QADD(ARMv7Thread&, const u32, const u32); + template static void QADD16(ARMv7Thread&, const u32, const u32); + template static void QADD8(ARMv7Thread&, const u32, const u32); + template static void QASX(ARMv7Thread&, const u32, const u32); + template static void QDADD(ARMv7Thread&, const u32, const u32); + template static void QDSUB(ARMv7Thread&, const u32, const u32); + template static void QSAX(ARMv7Thread&, const u32, const u32); + template static void QSUB(ARMv7Thread&, const u32, const u32); + template static void QSUB16(ARMv7Thread&, const u32, const u32); + template static void QSUB8(ARMv7Thread&, const u32, const u32); + + template static void RBIT(ARMv7Thread&, const u32, const u32); + template static void REV(ARMv7Thread&, const u32, const u32); + template static void REV16(ARMv7Thread&, const u32, const u32); + template static void REVSH(ARMv7Thread&, const u32, const u32); + + template static void ROR_IMM(ARMv7Thread&, const u32, const u32); + template static void ROR_REG(ARMv7Thread&, const u32, const u32); + + template static void RRX(ARMv7Thread&, const u32, const u32); + + template static void RSB_IMM(ARMv7Thread&, const u32, const u32); + template static void RSB_REG(ARMv7Thread&, const u32, const u32); + template static void RSB_RSR(ARMv7Thread&, const u32, const u32); + + template static void RSC_IMM(ARMv7Thread&, const u32, const u32); + template static void RSC_REG(ARMv7Thread&, const u32, const u32); + template static void RSC_RSR(ARMv7Thread&, const u32, const u32); + + template static void SADD16(ARMv7Thread&, const u32, const u32); + template static void SADD8(ARMv7Thread&, const u32, const u32); + template static void SASX(ARMv7Thread&, const u32, const u32); + + template static void SBC_IMM(ARMv7Thread&, const u32, const u32); + template static void SBC_REG(ARMv7Thread&, const u32, const u32); + template static void SBC_RSR(ARMv7Thread&, const u32, const u32); + + template static void SBFX(ARMv7Thread&, const u32, const u32); + + template static void SDIV(ARMv7Thread&, const u32, const u32); + + template static void SEL(ARMv7Thread&, const u32, const u32); + + template static void SHADD16(ARMv7Thread&, const u32, const u32); + template static void SHADD8(ARMv7Thread&, const u32, const u32); + template static void SHASX(ARMv7Thread&, const u32, const u32); + template static void SHSAX(ARMv7Thread&, const u32, const u32); + template static void SHSUB16(ARMv7Thread&, const u32, const u32); + template static void SHSUB8(ARMv7Thread&, const u32, const u32); + + template static void SMLA__(ARMv7Thread&, const u32, const u32); + template static void SMLAD(ARMv7Thread&, const u32, const u32); + template static void SMLAL(ARMv7Thread&, const u32, const u32); + template static void SMLAL__(ARMv7Thread&, const u32, const u32); + template static void SMLALD(ARMv7Thread&, const u32, const u32); + template static void SMLAW_(ARMv7Thread&, const u32, const u32); + template static void SMLSD(ARMv7Thread&, const u32, const u32); + template static void SMLSLD(ARMv7Thread&, const u32, const u32); + template static void SMMLA(ARMv7Thread&, const u32, const u32); + template static void SMMLS(ARMv7Thread&, const u32, const u32); + template static void SMMUL(ARMv7Thread&, const u32, const u32); + template static void SMUAD(ARMv7Thread&, const u32, const u32); + template static void SMUL__(ARMv7Thread&, const u32, const u32); + template static void SMULL(ARMv7Thread&, const u32, const u32); + template static void SMULW_(ARMv7Thread&, const u32, const u32); + template static void SMUSD(ARMv7Thread&, const u32, const u32); + + template static void SSAT(ARMv7Thread&, const u32, const u32); + template static void SSAT16(ARMv7Thread&, const u32, const u32); + template static void SSAX(ARMv7Thread&, const u32, const u32); + template static void SSUB16(ARMv7Thread&, const u32, const u32); + template static void SSUB8(ARMv7Thread&, const u32, const u32); + + template static void STM(ARMv7Thread&, const u32, const u32); + template static void STMDA(ARMv7Thread&, const u32, const u32); + template static void STMDB(ARMv7Thread&, const u32, const u32); + template static void STMIB(ARMv7Thread&, const u32, const u32); + + template static void STR_IMM(ARMv7Thread&, const u32, const u32); + template static void STR_REG(ARMv7Thread&, const u32, const u32); + + template static void STRB_IMM(ARMv7Thread&, const u32, const u32); + template static void STRB_REG(ARMv7Thread&, const u32, const u32); + + template static void STRD_IMM(ARMv7Thread&, const u32, const u32); + template static void STRD_REG(ARMv7Thread&, const u32, const u32); + + template static void STRH_IMM(ARMv7Thread&, const u32, const u32); + template static void STRH_REG(ARMv7Thread&, const u32, const u32); + + template static void STREX(ARMv7Thread&, const u32, const u32); + template static void STREXB(ARMv7Thread&, const u32, const u32); + template static void STREXD(ARMv7Thread&, const u32, const u32); + template static void STREXH(ARMv7Thread&, const u32, const u32); + + template static void SUB_IMM(ARMv7Thread&, const u32, const u32); + template static void SUB_REG(ARMv7Thread&, const u32, const u32); + template static void SUB_RSR(ARMv7Thread&, const u32, const u32); + template static void SUB_SPI(ARMv7Thread&, const u32, const u32); + template static void SUB_SPR(ARMv7Thread&, const u32, const u32); + + template static void SVC(ARMv7Thread&, const u32, const u32); + + template static void SXTAB(ARMv7Thread&, const u32, const u32); + template static void SXTAB16(ARMv7Thread&, const u32, const u32); + template static void SXTAH(ARMv7Thread&, const u32, const u32); + template static void SXTB(ARMv7Thread&, const u32, const u32); + template static void SXTB16(ARMv7Thread&, const u32, const u32); + template static void SXTH(ARMv7Thread&, const u32, const u32); + + template static void TB_(ARMv7Thread&, const u32, const u32); + + template static void TEQ_IMM(ARMv7Thread&, const u32, const u32); + template static void TEQ_REG(ARMv7Thread&, const u32, const u32); + template static void TEQ_RSR(ARMv7Thread&, const u32, const u32); + + template static void TST_IMM(ARMv7Thread&, const u32, const u32); + template static void TST_REG(ARMv7Thread&, const u32, const u32); + template static void TST_RSR(ARMv7Thread&, const u32, const u32); + + template static void UADD16(ARMv7Thread&, const u32, const u32); + template static void UADD8(ARMv7Thread&, const u32, const u32); + template static void UASX(ARMv7Thread&, const u32, const u32); + template static void UBFX(ARMv7Thread&, const u32, const u32); + template static void UDIV(ARMv7Thread&, const u32, const u32); + template static void UHADD16(ARMv7Thread&, const u32, const u32); + template static void UHADD8(ARMv7Thread&, const u32, const u32); + template static void UHASX(ARMv7Thread&, const u32, const u32); + template static void UHSAX(ARMv7Thread&, const u32, const u32); + template static void UHSUB16(ARMv7Thread&, const u32, const u32); + template static void UHSUB8(ARMv7Thread&, const u32, const u32); + template static void UMAAL(ARMv7Thread&, const u32, const u32); + template static void UMLAL(ARMv7Thread&, const u32, const u32); + template static void UMULL(ARMv7Thread&, const u32, const u32); + template static void UQADD16(ARMv7Thread&, const u32, const u32); + template static void UQADD8(ARMv7Thread&, const u32, const u32); + template static void UQASX(ARMv7Thread&, const u32, const u32); + template static void UQSAX(ARMv7Thread&, const u32, const u32); + template static void UQSUB16(ARMv7Thread&, const u32, const u32); + template static void UQSUB8(ARMv7Thread&, const u32, const u32); + template static void USAD8(ARMv7Thread&, const u32, const u32); + template static void USADA8(ARMv7Thread&, const u32, const u32); + template static void USAT(ARMv7Thread&, const u32, const u32); + template static void USAT16(ARMv7Thread&, const u32, const u32); + template static void USAX(ARMv7Thread&, const u32, const u32); + template static void USUB16(ARMv7Thread&, const u32, const u32); + template static void USUB8(ARMv7Thread&, const u32, const u32); + template static void UXTAB(ARMv7Thread&, const u32, const u32); + template static void UXTAB16(ARMv7Thread&, const u32, const u32); + template static void UXTAH(ARMv7Thread&, const u32, const u32); + template static void UXTB(ARMv7Thread&, const u32, const u32); + template static void UXTB16(ARMv7Thread&, const u32, const u32); + template static void UXTH(ARMv7Thread&, const u32, const u32); + + template static void VABA_(ARMv7Thread&, const u32, const u32); + template static void VABD_(ARMv7Thread&, const u32, const u32); + template static void VABD_FP(ARMv7Thread&, const u32, const u32); + template static void VABS(ARMv7Thread&, const u32, const u32); + template static void VAC__(ARMv7Thread&, const u32, const u32); + template static void VADD(ARMv7Thread&, const u32, const u32); + template static void VADD_FP(ARMv7Thread&, const u32, const u32); + template static void VADDHN(ARMv7Thread&, const u32, const u32); + template static void VADD_(ARMv7Thread&, const u32, const u32); + template static void VAND(ARMv7Thread&, const u32, const u32); + template static void VBIC_IMM(ARMv7Thread&, const u32, const u32); + template static void VBIC_REG(ARMv7Thread&, const u32, const u32); + template static void VB__(ARMv7Thread&, const u32, const u32); + template static void VCEQ_REG(ARMv7Thread&, const u32, const u32); + template static void VCEQ_ZERO(ARMv7Thread&, const u32, const u32); + template static void VCGE_REG(ARMv7Thread&, const u32, const u32); + template static void VCGE_ZERO(ARMv7Thread&, const u32, const u32); + template static void VCGT_REG(ARMv7Thread&, const u32, const u32); + template static void VCGT_ZERO(ARMv7Thread&, const u32, const u32); + template static void VCLE_ZERO(ARMv7Thread&, const u32, const u32); + template static void VCLS(ARMv7Thread&, const u32, const u32); + template static void VCLT_ZERO(ARMv7Thread&, const u32, const u32); + template static void VCLZ(ARMv7Thread&, const u32, const u32); + template static void VCMP_(ARMv7Thread&, const u32, const u32); + template static void VCNT(ARMv7Thread&, const u32, const u32); + template static void VCVT_FIA(ARMv7Thread&, const u32, const u32); + template static void VCVT_FIF(ARMv7Thread&, const u32, const u32); + template static void VCVT_FFA(ARMv7Thread&, const u32, const u32); + template static void VCVT_FFF(ARMv7Thread&, const u32, const u32); + template static void VCVT_DF(ARMv7Thread&, const u32, const u32); + template static void VCVT_HFA(ARMv7Thread&, const u32, const u32); + template static void VCVT_HFF(ARMv7Thread&, const u32, const u32); + template static void VDIV(ARMv7Thread&, const u32, const u32); + template static void VDUP_S(ARMv7Thread&, const u32, const u32); + template static void VDUP_R(ARMv7Thread&, const u32, const u32); + template static void VEOR(ARMv7Thread&, const u32, const u32); + template static void VEXT(ARMv7Thread&, const u32, const u32); + template static void VHADDSUB(ARMv7Thread&, const u32, const u32); + template static void VLD__MS(ARMv7Thread&, const u32, const u32); + template static void VLD1_SL(ARMv7Thread&, const u32, const u32); + template static void VLD1_SAL(ARMv7Thread&, const u32, const u32); + template static void VLD2_SL(ARMv7Thread&, const u32, const u32); + template static void VLD2_SAL(ARMv7Thread&, const u32, const u32); + template static void VLD3_SL(ARMv7Thread&, const u32, const u32); + template static void VLD3_SAL(ARMv7Thread&, const u32, const u32); + template static void VLD4_SL(ARMv7Thread&, const u32, const u32); + template static void VLD4_SAL(ARMv7Thread&, const u32, const u32); + template static void VLDM(ARMv7Thread&, const u32, const u32); + template static void VLDR(ARMv7Thread&, const u32, const u32); + template static void VMAXMIN(ARMv7Thread&, const u32, const u32); + template static void VMAXMIN_FP(ARMv7Thread&, const u32, const u32); + template static void VML__(ARMv7Thread&, const u32, const u32); + template static void VML__FP(ARMv7Thread&, const u32, const u32); + template static void VML__S(ARMv7Thread&, const u32, const u32); + template static void VMOV_IMM(ARMv7Thread&, const u32, const u32); + template static void VMOV_REG(ARMv7Thread&, const u32, const u32); + template static void VMOV_RS(ARMv7Thread&, const u32, const u32); + template static void VMOV_SR(ARMv7Thread&, const u32, const u32); + template static void VMOV_RF(ARMv7Thread&, const u32, const u32); + template static void VMOV_2RF(ARMv7Thread&, const u32, const u32); + template static void VMOV_2RD(ARMv7Thread&, const u32, const u32); + template static void VMOVL(ARMv7Thread&, const u32, const u32); + template static void VMOVN(ARMv7Thread&, const u32, const u32); + template static void VMRS(ARMv7Thread&, const u32, const u32); + template static void VMSR(ARMv7Thread&, const u32, const u32); + template static void VMUL_(ARMv7Thread&, const u32, const u32); + template static void VMUL_FP(ARMv7Thread&, const u32, const u32); + template static void VMUL_S(ARMv7Thread&, const u32, const u32); + template static void VMVN_IMM(ARMv7Thread&, const u32, const u32); + template static void VMVN_REG(ARMv7Thread&, const u32, const u32); + template static void VNEG(ARMv7Thread&, const u32, const u32); + template static void VNM__(ARMv7Thread&, const u32, const u32); + template static void VORN_REG(ARMv7Thread&, const u32, const u32); + template static void VORR_IMM(ARMv7Thread&, const u32, const u32); + template static void VORR_REG(ARMv7Thread&, const u32, const u32); + template static void VPADAL(ARMv7Thread&, const u32, const u32); + template static void VPADD(ARMv7Thread&, const u32, const u32); + template static void VPADD_FP(ARMv7Thread&, const u32, const u32); + template static void VPADDL(ARMv7Thread&, const u32, const u32); + template static void VPMAXMIN(ARMv7Thread&, const u32, const u32); + template static void VPMAXMIN_FP(ARMv7Thread&, const u32, const u32); + template static void VPOP(ARMv7Thread&, const u32, const u32); + template static void VPUSH(ARMv7Thread&, const u32, const u32); + template static void VQABS(ARMv7Thread&, const u32, const u32); + template static void VQADD(ARMv7Thread&, const u32, const u32); + template static void VQDML_L(ARMv7Thread&, const u32, const u32); + template static void VQDMULH(ARMv7Thread&, const u32, const u32); + template static void VQDMULL(ARMv7Thread&, const u32, const u32); + template static void VQMOV_N(ARMv7Thread&, const u32, const u32); + template static void VQNEG(ARMv7Thread&, const u32, const u32); + template static void VQRDMULH(ARMv7Thread&, const u32, const u32); + template static void VQRSHL(ARMv7Thread&, const u32, const u32); + template static void VQRSHR_N(ARMv7Thread&, const u32, const u32); + template static void VQSHL_REG(ARMv7Thread&, const u32, const u32); + template static void VQSHL_IMM(ARMv7Thread&, const u32, const u32); + template static void VQSHR_N(ARMv7Thread&, const u32, const u32); + template static void VQSUB(ARMv7Thread&, const u32, const u32); + template static void VRADDHN(ARMv7Thread&, const u32, const u32); + template static void VRECPE(ARMv7Thread&, const u32, const u32); + template static void VRECPS(ARMv7Thread&, const u32, const u32); + template static void VREV__(ARMv7Thread&, const u32, const u32); + template static void VRHADD(ARMv7Thread&, const u32, const u32); + template static void VRSHL(ARMv7Thread&, const u32, const u32); + template static void VRSHR(ARMv7Thread&, const u32, const u32); + template static void VRSHRN(ARMv7Thread&, const u32, const u32); + template static void VRSQRTE(ARMv7Thread&, const u32, const u32); + template static void VRSQRTS(ARMv7Thread&, const u32, const u32); + template static void VRSRA(ARMv7Thread&, const u32, const u32); + template static void VRSUBHN(ARMv7Thread&, const u32, const u32); + template static void VSHL_IMM(ARMv7Thread&, const u32, const u32); + template static void VSHL_REG(ARMv7Thread&, const u32, const u32); + template static void VSHLL(ARMv7Thread&, const u32, const u32); + template static void VSHR(ARMv7Thread&, const u32, const u32); + template static void VSHRN(ARMv7Thread&, const u32, const u32); + template static void VSLI(ARMv7Thread&, const u32, const u32); + template static void VSQRT(ARMv7Thread&, const u32, const u32); + template static void VSRA(ARMv7Thread&, const u32, const u32); + template static void VSRI(ARMv7Thread&, const u32, const u32); + template static void VST__MS(ARMv7Thread&, const u32, const u32); + template static void VST1_SL(ARMv7Thread&, const u32, const u32); + template static void VST2_SL(ARMv7Thread&, const u32, const u32); + template static void VST3_SL(ARMv7Thread&, const u32, const u32); + template static void VST4_SL(ARMv7Thread&, const u32, const u32); + template static void VSTM(ARMv7Thread&, const u32, const u32); + template static void VSTR(ARMv7Thread&, const u32, const u32); + template static void VSUB(ARMv7Thread&, const u32, const u32); + template static void VSUB_FP(ARMv7Thread&, const u32, const u32); + template static void VSUBHN(ARMv7Thread&, const u32, const u32); + template static void VSUB_(ARMv7Thread&, const u32, const u32); + template static void VSWP(ARMv7Thread&, const u32, const u32); + template static void VTB_(ARMv7Thread&, const u32, const u32); + template static void VTRN(ARMv7Thread&, const u32, const u32); + template static void VTST(ARMv7Thread&, const u32, const u32); + template static void VUZP(ARMv7Thread&, const u32, const u32); + template static void VZIP(ARMv7Thread&, const u32, const u32); + + template static void WFE(ARMv7Thread&, const u32, const u32); + template static void WFI(ARMv7Thread&, const u32, const u32); + template static void YIELD(ARMv7Thread&, const u32, const u32); }; diff --git a/rpcs3/Emu/ARMv7/ARMv7Module.cpp b/rpcs3/Emu/ARMv7/ARMv7Module.cpp new file mode 100644 index 0000000000..8f0f2785a6 --- /dev/null +++ b/rpcs3/Emu/ARMv7/ARMv7Module.cpp @@ -0,0 +1,578 @@ +#include "stdafx.h" +#include "Loader/ELF.h" +#include "Emu/Memory/Memory.h" +#include "Emu/System.h" +#include "Emu/IdManager.h" + +#include "ARMv7Thread.h" +#include "ARMv7Opcodes.h" +#include "ARMv7Function.h" +#include "ARMv7Module.h" + +extern void armv7_init_tls(); + +extern std::string arm_get_function_name(const std::string& module, u32 fnid); +extern std::string arm_get_variable_name(const std::string& module, u32 vnid); + +// Function lookup table. Not supposed to grow after emulation start. +std::vector g_arm_function_cache; + +extern void arm_execute_function(ARMv7Thread& cpu, u32 index) +{ + if (index < g_arm_function_cache.size()) + { + if (const auto func = g_arm_function_cache[index]) + { + const auto previous_function = cpu.last_function; // TODO: use gsl::finally or something + + try + { + func(cpu); + } + catch (const std::exception&) + { + LOG_ERROR(ARMv7, "Function '%s' aborted", cpu.last_function); + cpu.last_function = previous_function; + throw; + } + catch (EmulationStopped) + { + LOG_WARNING(ARMv7, "Function '%s' aborted", cpu.last_function); + cpu.last_function = previous_function; + throw; + } + + LOG_TRACE(ARMv7, "Function '%s' finished, r0=0x%x", cpu.last_function, cpu.GPR[0]); + cpu.last_function = previous_function; + return; + } + } + + throw fmt::exception("Function not registered (%u)" HERE, index); +} + +arm_static_module::arm_static_module(const char* name) + : name(name) +{ + arm_module_manager::register_module(this); +} + +static void arm_initialize_modules() +{ + const std::initializer_list registered + { + &arm_module_manager::SceAppMgr, + &arm_module_manager::SceAppUtil, + &arm_module_manager::SceAudio, + &arm_module_manager::SceAudiodec, + &arm_module_manager::SceAudioenc, + &arm_module_manager::SceAudioIn, + &arm_module_manager::SceCamera, + &arm_module_manager::SceCodecEngine, + &arm_module_manager::SceCommonDialog, + &arm_module_manager::SceCpu, + &arm_module_manager::SceCtrl, + &arm_module_manager::SceDbg, + &arm_module_manager::SceDebugLed, + &arm_module_manager::SceDeci4p, + &arm_module_manager::SceDeflt, + &arm_module_manager::SceDipsw, + &arm_module_manager::SceDisplay, + &arm_module_manager::SceDisplayUser, + &arm_module_manager::SceFiber, + &arm_module_manager::SceFios, + &arm_module_manager::SceFpu, + &arm_module_manager::SceGxm, + &arm_module_manager::SceHttp, + &arm_module_manager::SceIme, + &arm_module_manager::SceIofilemgr, + &arm_module_manager::SceJpeg, + &arm_module_manager::SceJpegEnc, + &arm_module_manager::SceLibc, + &arm_module_manager::SceLibKernel, + &arm_module_manager::SceLibm, + &arm_module_manager::SceLibstdcxx, + &arm_module_manager::SceLibXml, + &arm_module_manager::SceLiveArea, + &arm_module_manager::SceLocation, + &arm_module_manager::SceMd5, + &arm_module_manager::SceModulemgr, + &arm_module_manager::SceMotion, + &arm_module_manager::SceMt19937, + &arm_module_manager::SceNet, + &arm_module_manager::SceNetCtl, + &arm_module_manager::SceNgs, + &arm_module_manager::SceNpBasic, + &arm_module_manager::SceNpCommon, + &arm_module_manager::SceNpManager, + &arm_module_manager::SceNpMatching, + &arm_module_manager::SceNpScore, + &arm_module_manager::SceNpUtility, + &arm_module_manager::ScePerf, + &arm_module_manager::ScePgf, + &arm_module_manager::ScePhotoExport, + &arm_module_manager::SceProcessmgr, + &arm_module_manager::SceRazorCapture, + &arm_module_manager::SceRtc, + &arm_module_manager::SceSas, + &arm_module_manager::SceScreenShot, + &arm_module_manager::SceSfmt, + &arm_module_manager::SceSha, + &arm_module_manager::SceSqlite, + &arm_module_manager::SceSsl, + &arm_module_manager::SceStdio, + &arm_module_manager::SceSulpha, + &arm_module_manager::SceSysmem, + &arm_module_manager::SceSysmodule, + &arm_module_manager::SceSystemGesture, + &arm_module_manager::SceThreadmgr, + &arm_module_manager::SceTouch, + &arm_module_manager::SceUlt, + &arm_module_manager::SceVideodec, + &arm_module_manager::SceVoice, + &arm_module_manager::SceVoiceQoS, + }; + + // Reinitialize function cache + g_arm_function_cache = arm_function_manager::get(); + + // "Use" all the modules for correct linkage + for (auto& module : registered) + { + LOG_TRACE(LOADER, "Registered static module: %s", module->name); + + for (auto& function : module->functions) + { + LOG_TRACE(LOADER, "** 0x%08X: %s", function.first, function.second.name); + } + + for (auto& variable : module->variables) + { + LOG_TRACE(LOADER, "** &0x%08X: %s (size=0x%x, align=0x%x)", variable.first, variable.second.name, variable.second.size, variable.second.align); + variable.second.var->set(0); + } + } +} + +struct psv_moduleinfo_t +{ + le_t attr; // ??? + u8 major; // ??? + u8 minor; // ??? + char name[24]; // ??? + le_t unk0; + le_t unk1; + le_t libent_top; + le_t libent_end; + le_t libstub_top; + le_t libstub_end; + le_t data[1]; // ... +}; + +struct psv_libent_t +{ + le_t size; // ??? + le_t unk0; + le_t unk1; + le_t fcount; + le_t vcount; + le_t unk2; + le_t unk3; + le_t data[1]; // ... +}; + +struct psv_libstub_t +{ + le_t size; // 0x2C, 0x34 + le_t unk0; // (usually 1, 5 for sceLibKernel) + le_t unk1; // (usually 0) + le_t fcount; + le_t vcount; + le_t unk2; + le_t unk3; + le_t data[1]; // ... +}; + +struct psv_libcparam_t +{ + le_t size; + le_t unk0; + + vm::lcptr sceLibcHeapSize; + vm::lcptr sceLibcHeapSizeDefault; + vm::lcptr sceLibcHeapExtendedAlloc; + vm::lcptr sceLibcHeapDelayedAlloc; + + le_t unk1; + le_t unk2; + + vm::lptr __sce_libcmallocreplace; + vm::lptr __sce_libcnewreplace; +}; + +struct psv_process_param_t +{ + le_t size; // 0x00000030 + nse_t ver; // 'PSP2' + le_t unk0; // 0x00000005 + le_t unk1; + + vm::lcptr sceUserMainThreadName; + vm::lcptr sceUserMainThreadPriority; + vm::lcptr sceUserMainThreadStackSize; + vm::lcptr sceUserMainThreadAttribute; + vm::lcptr sceProcessName; + vm::lcptr sce_process_preload_disabled; + vm::lcptr sceUserMainThreadCpuAffinityMask; + + vm::lcptr sce_libcparam; +}; + +static void arm_patch_refs(u32 refs, u32 addr) +{ + auto ptr = vm::cptr::make(refs); + LOG_NOTICE(LOADER, "**** Processing refs at 0x%x:", ptr); + + if (ptr[0] != 0xff || ptr[1] != addr) + { + LOG_ERROR(LOADER, "**** Unexpected ref format ([0]=0x%x, [1]=0x%x)", ptr[0], ptr[1]); + } + else for (ptr += 2; *ptr; ptr++) + { + switch (u32 code = *ptr) + { + case 0x0000002f: // movw r*,# instruction + { + const u32 raddr = *++ptr; + vm::write16(raddr + 0, vm::read16(raddr + 0) | (addr & 0x800) >> 1 | (addr & 0xf000) >> 12); + vm::write16(raddr + 2, vm::read16(raddr + 2) | (addr & 0x700) << 4 | (addr & 0xff)); + + LOG_NOTICE(LOADER, "**** MOVW written at *0x%x", raddr); + break; + } + case 0x00000030: // movt r*,# instruction + { + const u32 raddr = *++ptr; + vm::write16(raddr + 0, vm::read16(raddr + 0) | (addr & 0x8000000) >> 17 | (addr & 0xf0000000) >> 28); + vm::write16(raddr + 2, vm::read16(raddr + 2) | (addr & 0x7000000) >> 12 | (addr & 0xff0000) >> 16); + + LOG_NOTICE(LOADER, "**** MOVT written at *0x%x", raddr); + break; + } + default: + { + LOG_ERROR(LOADER, "**** Unknown ref code found (0x%08x)", code); + } + } + } + +} + +template<> +void arm_exec_loader::load() const +{ + arm_initialize_modules(); + + vm::cptr module_info{}; + vm::cptr libent{}; + vm::cptr libstub{}; + vm::cptr proc_param{}; + + u32 entry_point{}; + u32 start_addr{}; + u32 arm_exidx{}; + u32 arm_extab{}; + u32 tls_faddr{}; + u32 tls_fsize{}; + u32 tls_vsize{}; + + for (const auto& prog : progs) + { + if (prog.p_type == 0x1 /* LOAD */ && prog.p_memsz) + { + if (!vm::falloc(prog.p_vaddr, prog.p_memsz, vm::main)) + { + throw fmt::exception("vm::falloc() failed (addr=0x%x, size=0x%x)", prog.p_vaddr, prog.p_memsz); + } + + if (prog.p_paddr) + { + module_info.set(prog.p_vaddr + (prog.p_paddr - prog.p_offset)); + LOG_NOTICE(LOADER, "Found program with p_paddr=0x%x", prog.p_paddr); + } + + if (!start_addr) + { + start_addr = prog.p_vaddr; + } + + std::memcpy(vm::base(prog.p_vaddr), prog.bin.data(), prog.p_filesz); + } + } + + if (!module_info) module_info.set(start_addr + header.e_entry); + if (!libent) libent.set(start_addr + module_info->libent_top); + if (!libstub) libstub.set(start_addr + module_info->libstub_top); + + LOG_NOTICE(LOADER, "__sce_moduleinfo(*0x%x) analysis...", module_info); + + if (module_info->data[2] == 0xffffffff) + { + arm_exidx = module_info->data[3]; + arm_extab = module_info->data[4]; + tls_faddr = module_info->data[5]; + tls_fsize = module_info->data[6]; + tls_vsize = module_info->data[7]; + } + else if (module_info->data[5] == 0xffffffff) + { + tls_faddr = module_info->data[1]; // Guess + tls_fsize = module_info->data[2]; + tls_vsize = module_info->data[3]; + arm_exidx = module_info->data[6]; + arm_extab = module_info->data[8]; + } + else + { + LOG_ERROR(LOADER, "Failed to recognize __sce_moduleinfo format"); + } + + LOG_NOTICE(LOADER, "** arm_exidx=0x%x", arm_exidx); + LOG_NOTICE(LOADER, "** arm_extab=0x%x", arm_extab); + LOG_NOTICE(LOADER, "** tls_faddr=0x%x", tls_faddr); + LOG_NOTICE(LOADER, "** tls_fsize=0x%x", tls_fsize); + LOG_NOTICE(LOADER, "** tls_vsize=0x%x", tls_vsize); + + Emu.SetTLSData(tls_faddr + start_addr, tls_fsize, tls_vsize); + + // Process exports + while (libent.addr() < start_addr + module_info->libent_end) + { + const u32 size = libent->size; + + // TODO: check addresses + if (size != 0x1c && size != 0x20) + { + LOG_ERROR(LOADER, "Unknown libent size (0x%x) at *0x%x", libent->size, libent); + } + else + { + LOG_NOTICE(LOADER, "Loading libent at *0x%x", libent); + LOG_NOTICE(LOADER, "** 0x%x, 0x%x", libent->unk0, libent->unk1); + LOG_NOTICE(LOADER, "** Functions: %u", libent->fcount); + LOG_NOTICE(LOADER, "** Variables: %u", libent->vcount); + LOG_NOTICE(LOADER, "** 0x%x, 0x%08x", libent->unk2, libent->unk3); + + const auto export_nids = vm::cptr::make(libent->data[size == 0x20 ? 2 : 1]); + const auto export_data = vm::cptr::make(libent->data[size == 0x20 ? 3 : 2]); + + for (u32 i = 0, count = export_data - export_nids; i < count; i++) + { + const u32 nid = export_nids[i]; + const u32 addr = export_data[i]; + + // Known exports + switch (nid) + { + case 0x935cd196: // set entry point + { + entry_point = addr; + break; + } + + case 0x6c2224ba: // __sce_moduleinfo + { + ASSERT(addr == module_info.addr()); + break; + } + + case 0x70fba1e7: // __sce_process_param + { + proc_param.set(addr); + break; + } + + default: + { + LOG_ERROR(LOADER, "** Unknown export '0x%08X' (*0x%x)", nid, addr); + } + } + } + } + + // Next entry + libent.set(libent.addr() + libent->size); + } + + // Process imports + while (libstub.addr() < start_addr + module_info->libstub_end) + { + const u32 size = libstub->size; + + // TODO: check addresses + if (size != 0x2c && size != 0x34) + { + LOG_ERROR(LOADER, "Unknown libstub size (0x%x) at *0x%x)", libstub->size, libstub); + } + else + { + const std::string module_name(vm::_ptr(libstub->data[size == 0x34 ? 1 : 0])); + + LOG_NOTICE(LOADER, "Loading libstub at 0x%x: %s", libstub, module_name); + + const auto _sm = arm_module_manager::get_module(module_name); + + if (!_sm) + { + LOG_ERROR(LOADER, "** Unknown module '%s'", module_name); + } + else + { + // Allocate HLE variables (TODO) + for (auto& var : _sm->variables) + { + var.second.var->set(vm::alloc(var.second.size, vm::main, std::max(var.second.align, 4096))); + LOG_WARNING(LOADER, "** Allocated variable '%s' in module '%s' at *0x%x", var.second.name, module_name, var.second.var->addr()); + } + + // Initialize HLE variables (TODO) + for (auto& var : _sm->variables) + { + var.second.init(); + } + } + + LOG_NOTICE(LOADER, "** 0x%x, 0x%x", libstub->unk0, libstub->unk1); + LOG_NOTICE(LOADER, "** Functions: %u", libstub->fcount); + LOG_NOTICE(LOADER, "** Variables: %u", libstub->vcount); + LOG_NOTICE(LOADER, "** 0x%x, 0x%08x", libstub->unk2, libstub->unk3); + + const auto fnids = vm::cptr::make(libstub->data[size == 0x34 ? 3 : 1]); + const auto fstubs = vm::cptr::make(libstub->data[size == 0x34 ? 4 : 2]); + + for (u32 j = 0; j < libstub->fcount; j++) + { + const u32 fnid = fnids[j]; + const u32 faddr = fstubs[j]; + + u32 index = 0; + + const auto fstub = vm::ptr::make(faddr); + const auto fname = arm_get_function_name(module_name, fnid); + + if (_sm && _sm->functions.count(fnid)) + { + index = _sm->functions.at(fnid).index; + LOG_NOTICE(LOADER, "** Imported function '%s' in module '%s' (*0x%x)", fname, module_name, faddr); + } + else + { + // TODO + index = ::size32(g_arm_function_cache); + g_arm_function_cache.emplace_back(); + + LOG_ERROR(LOADER, "** Unknown function '%s' in module '%s' (*0x%x) -> index %u", fname, module_name, faddr, index); + } + + // Check import stub + if (fstub[2] != 0xE1A00000) + { + LOG_ERROR(LOADER, "**** Unexpected import function stub (*0x%x, [2]=0x%08x)", faddr, fstub[2]); + } + + // Process refs + if (const u32 refs = fstub[3]) + { + arm_patch_refs(refs, faddr); + } + + // Install HACK instruction (ARM) + fstub[0] = 0xe0700090 | arm_code::hack::index::insert(index); + } + + const auto vnids = vm::cptr::make(libstub->data[size == 0x34 ? 5 : 3]); + const auto vstub = vm::cptr::make(libstub->data[size == 0x34 ? 6 : 4]); + + for (u32 j = 0; j < libstub->vcount; j++) + { + const u32 vnid = vnids[j]; + const u32 refs = vstub[j]; + + // Static variable + if (const auto _sv = _sm && _sm->variables.count(vnid) ? &_sm->variables.at(vnid) : nullptr) + { + LOG_NOTICE(LOADER, "** Imported variable '%s' in module '%s' (refs=*0x%x)", arm_get_variable_name(module_name, vnid), module_name, refs); + arm_patch_refs(refs, _sv->var->addr()); + } + else + { + LOG_FATAL(LOADER, "** Unknown variable '%s' in module '%s' (refs=*0x%x)", arm_get_variable_name(module_name, vnid), module_name, refs); + } + } + } + + // Next lib + libstub.set(libstub.addr() + size); + } + + LOG_NOTICE(LOADER, "__sce_process_param(*0x%x) analysis...", proc_param); + + ASSERT(proc_param->size >= sizeof(psv_process_param_t)); + ASSERT(proc_param->ver == "PSP2"_u32); + + LOG_NOTICE(LOADER, "*** size=0x%x; 0x%x, 0x%x, 0x%x", proc_param->size, proc_param->ver, proc_param->unk0, proc_param->unk1); + + LOG_NOTICE(LOADER, "*** &sceUserMainThreadName = 0x%x", proc_param->sceUserMainThreadName); + LOG_NOTICE(LOADER, "*** &sceUserMainThreadPriority = 0x%x", proc_param->sceUserMainThreadPriority); + LOG_NOTICE(LOADER, "*** &sceUserMainThreadStackSize = 0x%x", proc_param->sceUserMainThreadStackSize); + LOG_NOTICE(LOADER, "*** &sceUserMainThreadAttribute = 0x%x", proc_param->sceUserMainThreadAttribute); + LOG_NOTICE(LOADER, "*** &sceProcessName = 0x%x", proc_param->sceProcessName); + LOG_NOTICE(LOADER, "*** &sce_process_preload_disabled = 0x%x", proc_param->sce_process_preload_disabled); + LOG_NOTICE(LOADER, "*** &sceUserMainThreadCpuAffinityMask = 0x%x", proc_param->sceUserMainThreadCpuAffinityMask); + + const auto libc_param = proc_param->sce_libcparam; + + LOG_NOTICE(LOADER, "__sce_libcparam(*0x%x) analysis...", libc_param); + + ASSERT(libc_param->size >= 0x1c); + + LOG_NOTICE(LOADER, "*** size=0x%x; 0x%x, 0x%x, 0x%x", libc_param->size, libc_param->unk0, libc_param->unk1, libc_param->unk2); + + LOG_NOTICE(LOADER, "*** &sceLibcHeapSize = 0x%x", libc_param->sceLibcHeapSize); + LOG_NOTICE(LOADER, "*** &sceLibcHeapSizeDefault = 0x%x", libc_param->sceLibcHeapSizeDefault); + LOG_NOTICE(LOADER, "*** &sceLibcHeapExtendedAlloc = 0x%x", libc_param->sceLibcHeapExtendedAlloc); + LOG_NOTICE(LOADER, "*** &sceLibcHeapDelayedAlloc = 0x%x", libc_param->sceLibcHeapDelayedAlloc); + + const auto stop_code = vm::ptr::make(vm::alloc(3 * 4, vm::main)); + stop_code[0] = 0xf870; // HACK instruction (Thumb) + stop_code[1] = 1; // Predefined function index (HLE return) + Emu.SetCPUThreadStop(stop_code.addr()); + + armv7_init_tls(); + + const std::string& thread_name = proc_param->sceUserMainThreadName ? proc_param->sceUserMainThreadName.get_ptr() : "main_thread"; + const u32 stack_size = proc_param->sceUserMainThreadStackSize ? proc_param->sceUserMainThreadStackSize->value() : 256 * 1024; + const u32 priority = proc_param->sceUserMainThreadPriority ? proc_param->sceUserMainThreadPriority->value() : 160; + + auto thread = idm::make_ptr(thread_name); + + thread->PC = entry_point; + thread->stack_size = stack_size; + thread->prio = priority; + thread->cpu_init(); + + // Initialize args + std::vector argv_data; + + for (const auto& arg : { Emu.GetPath(), "-emu"s }) + { + argv_data.insert(argv_data.end(), arg.begin(), arg.end()); + argv_data.insert(argv_data.end(), '\0'); + + thread->GPR[0]++; // argc + } + + const u32 argv = vm::alloc(::size32(argv_data), vm::main); + std::memcpy(vm::base(argv), argv_data.data(), argv_data.size()); // copy arg list + thread->GPR[1] = argv; +} diff --git a/rpcs3/Emu/ARMv7/ARMv7Module.h b/rpcs3/Emu/ARMv7/ARMv7Module.h new file mode 100644 index 0000000000..95261f5b80 --- /dev/null +++ b/rpcs3/Emu/ARMv7/ARMv7Module.h @@ -0,0 +1,222 @@ +#pragma once + +#include "Utilities/Config.h" +#include "ARMv7Function.h" +#include "ARMv7Callback.h" +#include "ErrorCodes.h" + +namespace vm { using namespace psv; } + +// HLE function information +struct arm_static_function +{ + const char* name; + u32 index; // Index for arm_function_manager + u32 flags; +}; + +// HLE variable information +struct arm_static_variable +{ + const char* name; + vm::gvar* var; // Pointer to variable address storage + void(*init)(); // Variable initialization function + u32 size; + u32 align; +}; + +// HLE module information +class arm_static_module final +{ +public: + const std::string name; + + task_stack on_load; + task_stack on_unload; + + std::unordered_map functions; + std::unordered_map variables; + +public: + arm_static_module(const char* name); + + arm_static_module(const char* name, void(*init)()) + : arm_static_module(name) + { + init(); + } + + arm_static_module(const char* name, void(*init)(arm_static_module* _this)) + : arm_static_module(name) + { + init(this); + } +}; + +class arm_module_manager final +{ + friend class arm_static_module; + + static never_inline auto& access() + { + static std::unordered_map map; + + return map; + } + + static never_inline void register_module(arm_static_module* module) + { + access().emplace(module->name, module); + } + + static never_inline auto& access_static_function(const char* module, u32 fnid) + { + return access().at(module)->functions[fnid]; + } + + static never_inline auto& access_static_variable(const char* module, u32 vnid) + { + return access().at(module)->variables[vnid]; + } + +public: + static never_inline const arm_static_module* get_module(const std::string& name) + { + const auto& map = access(); + const auto found = map.find(name); + return found != map.end() ? found->second : nullptr; + } + + template + static void register_static_function(const char* module, const char* name, arm_function_t func, u32 fnid, u32 flags) + { + auto& info = access_static_function(module, fnid); + + info.name = name; + info.index = arm_function_manager::register_function(func); + info.flags = flags; + } + + template + static void register_static_variable(const char* module, const char* name, u32 vnid, void(*init)()) + { + static_assert(std::is_same::value, "Static variable registration: vm::gvar expected"); + + auto& info = access_static_variable(module, vnid); + + info.name = name; + info.var = reinterpret_cast*>(Var); + info.init = init ? init : [] {}; + info.size = SIZE_32(typename T::type); + info.align = ALIGN_32(typename T::type); + } + + static const arm_static_module SceAppMgr; + static const arm_static_module SceAppUtil; + static const arm_static_module SceAudio; + static const arm_static_module SceAudiodec; + static const arm_static_module SceAudioenc; + static const arm_static_module SceAudioIn; + static const arm_static_module SceCamera; + static const arm_static_module SceCodecEngine; + static const arm_static_module SceCommonDialog; + static const arm_static_module SceCpu; + static const arm_static_module SceCtrl; + static const arm_static_module SceDbg; + static const arm_static_module SceDebugLed; + static const arm_static_module SceDeci4p; + static const arm_static_module SceDeflt; + static const arm_static_module SceDipsw; + static const arm_static_module SceDisplay; + static const arm_static_module SceDisplayUser; + static const arm_static_module SceFiber; + static const arm_static_module SceFios; + static const arm_static_module SceFpu; + static const arm_static_module SceGxm; + static const arm_static_module SceHttp; + static const arm_static_module SceIme; + static const arm_static_module SceIofilemgr; + static const arm_static_module SceJpeg; + static const arm_static_module SceJpegEnc; + static const arm_static_module SceLibc; + static const arm_static_module SceLibKernel; + static const arm_static_module SceLibm; + static const arm_static_module SceLibstdcxx; + static const arm_static_module SceLibXml; + static const arm_static_module SceLiveArea; + static const arm_static_module SceLocation; + static const arm_static_module SceMd5; + static const arm_static_module SceModulemgr; + static const arm_static_module SceMotion; + static const arm_static_module SceMt19937; + static const arm_static_module SceNet; + static const arm_static_module SceNetCtl; + static const arm_static_module SceNgs; + static const arm_static_module SceNpBasic; + static const arm_static_module SceNpCommon; + static const arm_static_module SceNpManager; + static const arm_static_module SceNpMatching; + static const arm_static_module SceNpScore; + static const arm_static_module SceNpUtility; + static const arm_static_module ScePerf; + static const arm_static_module ScePgf; + static const arm_static_module ScePhotoExport; + static const arm_static_module SceProcessmgr; + static const arm_static_module SceRazorCapture; + static const arm_static_module SceRtc; + static const arm_static_module SceSas; + static const arm_static_module SceScreenShot; + static const arm_static_module SceSfmt; + static const arm_static_module SceSha; + static const arm_static_module SceSqlite; + static const arm_static_module SceSsl; + static const arm_static_module SceStdio; + static const arm_static_module SceSulpha; + static const arm_static_module SceSysmem; + static const arm_static_module SceSysmodule; + static const arm_static_module SceSystemGesture; + static const arm_static_module SceThreadmgr; + static const arm_static_module SceTouch; + static const arm_static_module SceUlt; + static const arm_static_module SceVideodec; + static const arm_static_module SceVoice; + static const arm_static_module SceVoiceQoS; +}; + +#define REG_FNID(module, nid, func, ...) arm_module_manager::register_static_function(#module, #func, BIND_FUNC(func), nid, {__VA_ARGS__}) + +#define REG_VNID(module, nid, var, ...) arm_module_manager::register_static_variable(#module, #var, nid, {__VA_ARGS__}) + +struct SceDateTime +{ + le_t year; + le_t month; + le_t day; + le_t hour; + le_t minute; + le_t second; + le_t microsecond; +}; + +struct SceFVector3 +{ + le_t x, y, z; +}; + +struct SceFQuaternion +{ + le_t x, y, z, w; +}; + +union SceUMatrix4 +{ + struct + { + le_t f[4][4]; + }; + + struct + { + le_t i[4][4]; + }; +}; diff --git a/rpcs3/Emu/ARMv7/ARMv7Opcodes.h b/rpcs3/Emu/ARMv7/ARMv7Opcodes.h index 7afe804363..61f740336e 100644 --- a/rpcs3/Emu/ARMv7/ARMv7Opcodes.h +++ b/rpcs3/Emu/ARMv7/ARMv7Opcodes.h @@ -1,2015 +1,2612 @@ #pragma once -#if 0 -#include "Emu/ARMv7/ARMv7Thread.h" -#include "Emu/ARMv7/ARMv7Interpreter.h" -using namespace ARMv7_instrs; +#include "../../../Utilities/BitField.h" -struct ARMv7_Instruction +#include + +enum class arm_encoding { - void(*func)(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - u8 size; - ARMv7_encoding type; - const char* name; + T1, T2, T3, T4, A1, A2, }; -#define ARMv7_OP_2(func, type) { func, 2, type, #func "_" #type } -#define ARMv7_OP_4(func, type) { func, 4, type, #func "_" #type } -#define ARMv7_NULL_OP { NULL_OP, 2, T1, "NULL_OP" } - - -// 0x1... -static void group_0x1(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - -static const ARMv7_Instruction g_table_0x1_main[] = +// Get Thumb instruction size +inline bool arm_op_thumb_is_32(u32 op16) { - ARMv7_OP_2(ASR_IMM, T1), // 0 0xf800 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_2(ADD_REG, T1), // 8 0xfe00 - ARMv7_NULL_OP, // 9 - ARMv7_OP_2(SUB_REG, T1), // A 0xfe00 - ARMv7_NULL_OP, // B - ARMv7_OP_2(ADD_IMM, T1), // C 0xfe00 - ARMv7_NULL_OP, // D - ARMv7_OP_2(SUB_IMM, T1) // E 0xfe00 -}; - -static const ARMv7_Instruction g_table_0x1[] = -{ - { group_0x1 } -}; - -static void group_0x1(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code0 & 0x0e00) >> 8; - - if ((thr->code.code0 & 0xf800) == 0x1000) index = 0x0; - - thr->m_last_instr_name = g_table_0x1_main[index].name; - thr->m_last_instr_size = g_table_0x1_main[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0x1_main[index].func(thr, g_table_0x1_main[index].type); + return (op16 >> 11) >= 29; } -// 0x2... -static void group_0x2(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - -static const ARMv7_Instruction g_table_0x2_main[] = +namespace arm_code { - ARMv7_OP_2(MOV_IMM, T1), // 0 0xf800 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_2(CMP_IMM, T1) // 8 0xf800 -}; - -static const ARMv7_Instruction g_table_0x2[] = -{ - { group_0x2 } -}; - -static void group_0x2(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = (thr->code.code0 & 0x0800) >> 8; - thr->m_last_instr_name = g_table_0x2_main[index].name; - thr->m_last_instr_size = g_table_0x2_main[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0x2_main[index].func(thr, g_table_0x2_main[index].type); -} - -// 0x3... -static void group_0x3(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - -static const ARMv7_Instruction g_table_0x3_main[] = -{ - ARMv7_OP_2(ADD_IMM, T2), // 0 0xf800 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_2(SUB_IMM, T2) // 8 0xf800 -}; - -static const ARMv7_Instruction g_table_0x3[] = -{ - { group_0x3 } -}; - -static void group_0x3(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = (thr->code.code0 & 0x0800) >> 8; - thr->m_last_instr_name = g_table_0x3_main[index].name; - thr->m_last_instr_size = g_table_0x3_main[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0x3_main[index].func(thr, g_table_0x3_main[index].type); -} - -// 0x4... -static void group_0x4(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0x40(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0x41(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0x42(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0x43(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0x44(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0x47(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - -static const ARMv7_Instruction g_table_0x4[] = -{ - { group_0x4 } -}; - -static const ARMv7_Instruction g_table_0x40[] = -{ - ARMv7_OP_2(AND_REG, T1), // 0 0xffc0 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_OP_2(ADC_REG, T1), // 4 0xffc0 - // ARMv7_OP_2(EOR_REG, T1), // 4 0xffc0 code(ADC_REG, T1) == code(EOR_REG, T1) ??? - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_2(LSL_REG, T1), // 8 0xffc0 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_OP_2(LSR_REG, T1) // C 0xffc0 -}; - -static void group_0x40(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = (thr->code.code0 & 0x00c0) >> 4; - thr->m_last_instr_name = g_table_0x40[index].name; - thr->m_last_instr_size = g_table_0x40[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0x40[index].func(thr, g_table_0x40[index].type); -} - -static const ARMv7_Instruction g_table_0x41[] = -{ - ARMv7_OP_2(ASR_REG, T1), // 0 0xffc0 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_2(SBC_REG, T1), // 8 0xffc0 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_OP_2(ROR_REG, T1) // C 0xffc0 -}; - -static void group_0x41(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = (thr->code.code0 & 0x00c0) >> 4; - thr->m_last_instr_name = g_table_0x41[index].name; - thr->m_last_instr_size = g_table_0x41[index].size; - g_table_0x41[index].func(thr, g_table_0x41[index].type); -} - -static const ARMv7_Instruction g_table_0x42[] = -{ - ARMv7_OP_2(TST_REG, T1), // 0 0xffc0 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_OP_2(RSB_IMM, T1), // 4 0xffc0 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_2(CMP_REG, T1), // 8 0xffc0 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_OP_2(CMN_REG, T1) // C 0xffc0 -}; - -static void group_0x42(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = (thr->code.code0 & 0x00c0) >> 4; - thr->m_last_instr_name = g_table_0x42[index].name; - thr->m_last_instr_size = g_table_0x42[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0x42[index].func(thr, g_table_0x42[index].type); -} - -static const ARMv7_Instruction g_table_0x43[] = -{ - ARMv7_OP_2(ORR_REG, T1), // 0 0xffc0 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_OP_2(MUL, T1), // 4 0xffc0 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_2(BIC_REG, T1), // 8 0xffc0 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_OP_2(MVN_REG, T1) // C 0xffc0 -}; - -static void group_0x43(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = (thr->code.code0 & 0x00c0) >> 4; - thr->m_last_instr_name = g_table_0x43[index].name; - thr->m_last_instr_size = g_table_0x43[index].size; - g_table_0x43[index].func(thr, g_table_0x43[index].type); -} - -static const ARMv7_Instruction g_table_0x44[] = -{ - ARMv7_OP_2(ADD_REG, T2), // 0 0xff00 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_OP_2(ADD_SPR, T1), // 6 0xff78 - ARMv7_NULL_OP, // 7 - ARMv7_OP_2(ADD_SPR, T2) // 8 0xff87 -}; - -static void group_0x44(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code0 & 0x0080) >> 4; - - if ((thr->code.code0 & 0xff00) == 0x4400) index = 0x0; - if ((thr->code.code0 & 0xff78) == 0x4468) index = 0x6; - - thr->m_last_instr_name = g_table_0x44[index].name; - thr->m_last_instr_size = g_table_0x44[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0x44[index].func(thr, g_table_0x44[index].type); -} - -static const ARMv7_Instruction g_table_0x47[] = -{ - ARMv7_OP_2(BX, T1), // 0 0xff87 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_2(BLX, T1) // 8 0xff80 -}; - -static void group_0x47(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = (thr->code.code0 & 0x0080) >> 4; - thr->m_last_instr_name = g_table_0x47[index].name; - thr->m_last_instr_size = g_table_0x47[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0x47[index].func(thr, g_table_0x47[index].type); -} - -static const ARMv7_Instruction g_table_0x4_main[] = -{ - { group_0x40 }, // 0 - { group_0x41 }, // 1 - { group_0x42 }, // 2 - { group_0x43 }, // 3 - { group_0x44 }, // 4 - ARMv7_OP_2(CMP_REG, T2), // 5 0xff00 - ARMv7_OP_2(MOV_REG, T1), // 6 0xff00 - { group_0x47 }, // 7 - ARMv7_OP_2(LDR_LIT, T1) // 8 0xf800 -}; - -static void group_0x4(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code0 & 0x0f00) >> 8; - - if ((index & 0xf800) == 0x4800) index = 0x8; - - thr->m_last_instr_name = g_table_0x4_main[index].name; - thr->m_last_instr_size = g_table_0x4_main[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0x4_main[index].func(thr, g_table_0x4_main[index].type); -} - -// 0x5... -static void group_0x5(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - -static const ARMv7_Instruction g_table_0x5_main[] = -{ - ARMv7_OP_2(STR_REG, T1), // 0 0xfe00 - ARMv7_NULL_OP, // 1 - ARMv7_OP_2(STRH_REG, T1), // 2 0xfe00 - ARMv7_NULL_OP, // 3 - ARMv7_OP_2(STRB_REG, T1), // 4 0xfe00 - ARMv7_NULL_OP, // 5 - ARMv7_OP_2(LDRSB_REG, T1), // 6 0xfe00 - ARMv7_NULL_OP, // 7 - ARMv7_OP_2(LDR_REG, T1), // 8 0xfe00 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_OP_2(LDRB_REG, T1), // C 0xfe00 - ARMv7_NULL_OP, // D - ARMv7_OP_2(LDRSH_REG, T1) // E 0xfe00 -}; - -static const ARMv7_Instruction g_table_0x5[] = -{ - { group_0x5 } -}; - -static void group_0x5(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = (thr->code.code0 & 0x0e00) >> 8; - thr->m_last_instr_name = g_table_0x5_main[index].name; - thr->m_last_instr_size = g_table_0x5_main[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0x5_main[index].func(thr, g_table_0x5_main[index].type); -} - -// 0x6... -static void group_0x6(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - -static const ARMv7_Instruction g_table_0x6_main[] = -{ - ARMv7_OP_2(STR_IMM, T1), // 0 0xf800 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_2(LDR_IMM, T1) // 8 0xf800 -}; - -static const ARMv7_Instruction g_table_0x6[] = -{ - { group_0x6 } -}; - -static void group_0x6(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = (thr->code.code0 & 0x0800) >> 8; - thr->m_last_instr_name = g_table_0x6_main[index].name; - thr->m_last_instr_size = g_table_0x6_main[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0x6_main[index].func(thr, g_table_0x6_main[index].type); -} - -// 0x7... -static void group_0x7(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - -static const ARMv7_Instruction g_table_0x7_main[] = -{ - ARMv7_OP_2(STRB_IMM, T1), // 0 0xf800 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_2(LDRB_IMM, T1) // 8 0xf800 -}; - -static const ARMv7_Instruction g_table_0x7[] = -{ - { group_0x7 } -}; - -static void group_0x7(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = (thr->code.code0 & 0x0800) >> 8; - thr->m_last_instr_name = g_table_0x7_main[index].name; - thr->m_last_instr_size = g_table_0x7_main[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0x7_main[index].func(thr, g_table_0x7_main[index].type); -} - -// 0x8... -static void group_0x8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - -static const ARMv7_Instruction g_table_0x8_main[] = -{ - ARMv7_OP_2(STRH_IMM, T1) // 0 0xf800 -}; - -static const ARMv7_Instruction g_table_0x8[] = -{ - { group_0x8 } -}; - -static void group_0x8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = (thr->code.code0 & 0x0800) >> 8; - thr->m_last_instr_name = g_table_0x8_main[index].name; - thr->m_last_instr_size = g_table_0x8_main[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0x8_main[index].func(thr, g_table_0x8_main[index].type); -} - -// 0x9... -static void group_0x9(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - -static const ARMv7_Instruction g_table_0x9_main[] = -{ - ARMv7_OP_2(STR_IMM, T2), // 0 0xf800 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_2(LDR_IMM, T2) // 8 0xf800 -}; - -static const ARMv7_Instruction g_table_0x9[] = -{ - { group_0x9 } -}; - -static void group_0x9(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = (thr->code.code0 & 0x0800) >> 8; - thr->m_last_instr_name = g_table_0x9_main[index].name; - thr->m_last_instr_size = g_table_0x9_main[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0x9_main[index].func(thr, g_table_0x9_main[index].type); -} - -// 0xa... -static void group_0xa(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - -static const ARMv7_Instruction g_table_0xa_main[] = -{ - ARMv7_OP_2(ADR, T1), // 0 0xf800 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_2(ADD_SPI, T1) // 8 0xf800 -}; - -static const ARMv7_Instruction g_table_0xa[] = -{ - { group_0xa } -}; - -static void group_0xa(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code0 & 0x0800) >> 8; - thr->m_last_instr_name = g_table_0xa_main[index].name; - thr->m_last_instr_size = g_table_0xa_main[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xa_main[index].func(thr, g_table_0xa_main[index].type); -} - -// 0xb... -static void group_0xb(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xb0(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xba(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - -static const ARMv7_Instruction g_table_0xb0[] = -{ - ARMv7_OP_2(ADD_SPI, T2), // 0 0xff80 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_2(SUB_SPI, T1) // 8 0xff80 -}; - -static void group_0xb0(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = (thr->code.code0 & 0x0080) >> 4; - thr->m_last_instr_name = g_table_0xb0[index].name; - thr->m_last_instr_size = g_table_0xb0[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xb0[index].func(thr, g_table_0xb0[index].type); -} - -static const ARMv7_Instruction g_table_0xba[] = -{ - ARMv7_OP_2(REV, T1), // 0 0xffc0 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_OP_2(REV16, T1), // 4 0xffc0 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_OP_2(REVSH, T1) // C 0xffc0 -}; - -static void group_0xba(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = (thr->code.code0 & 0x00c0) >> 4; // mask 0xffc0 - thr->m_last_instr_name = g_table_0xba[index].name; - thr->m_last_instr_size = g_table_0xba[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xba[index].func(thr, g_table_0xba[index].type); -} - -static const ARMv7_Instruction g_table_0xb_main[] = -{ - { group_0xb0 }, // 0 - ARMv7_OP_2(CB_Z, T1), // 1 0xf500 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_OP_2(PUSH, T1), // 4 0xfe00 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - { group_0xba }, // A - ARMv7_NULL_OP, // B - ARMv7_OP_2(POP, T1), // C 0xfe00 - ARMv7_NULL_OP, // D - ARMv7_OP_2(BKPT, T1), // E 0xff00 - ARMv7_OP_2(NOP, T1), // F 0xffff - ARMv7_OP_2(IT, T1), // 10 0xff00 -}; - -static const ARMv7_Instruction g_table_0xb[] = -{ - { group_0xb } -}; - -static void group_0xb(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code0 & 0x0e00) >> 8; - - if ((thr->code.code0 & 0xf500) == 0xb100) index = 0x1; // CB_Z, T1 - if ((thr->code.code0 & 0xff00) == 0xbe00) index = 0xe; // BKPT, T1 - if ((thr->code.code0 & 0xffff) == 0xbf00) index = 0xf; // NOP, T1 - if ((thr->code.code0 & 0xff00) == 0xbf00) index = 0x10; // IT, T1 - - thr->m_last_instr_name = g_table_0xb_main[index].name; - thr->m_last_instr_size = g_table_0xb_main[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xb_main[index].func(thr, g_table_0xb_main[index].type); -} - -// 0xc... -static void group_0xc(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - -static const ARMv7_Instruction g_table_0xc_main[] = -{ - ARMv7_OP_2(STM, T1), // 0 0xf800 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_2(LDM, T1) // 8 0xf800 -}; - -static const ARMv7_Instruction g_table_0xc[] = -{ - { group_0xc } -}; - -static void group_0xc(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = (thr->code.code0 & 0x0800) >> 8; - thr->m_last_instr_name = g_table_0xc_main[index].name; - thr->m_last_instr_size = g_table_0xc_main[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xc_main[index].func(thr, g_table_0xc_main[index].type); -} - -// 0xd... -static void group_0xd(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - -static const ARMv7_Instruction g_table_0xd_main[] = -{ - ARMv7_OP_2(B, T1), // 0 0xf000 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_NULL_OP, // C - ARMv7_NULL_OP, // D - ARMv7_NULL_OP, // E - ARMv7_OP_2(SVC, T1) // F 0xff00 -}; - -static const ARMv7_Instruction g_table_0xd[] = -{ - { group_0xd } -}; - -static void group_0xd(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - //u32 index = (thr->code.code0 & 0x0f00) >> 8; - //if ((thr->code.code0 & 0xf000) == 0xd000) index = 0; - - const u32 index = (thr->code.code0 & 0xff00) == 0xdf00 ? 0xf : 0x0; // check me - thr->m_last_instr_name = g_table_0xd_main[index].name; - thr->m_last_instr_size = g_table_0xd_main[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xd_main[index].func(thr, g_table_0xd_main[index].type); -} - -// 0xe... -static void group_0xe(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xe85(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xe8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xe9(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xea(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xea4(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xea4f(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xea4f0000(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xea4f0030(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xea6(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xeb(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xeb0(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xeba(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - - -static const ARMv7_Instruction g_table_0xe85[] = -{ - ARMv7_OP_4(LDRD_IMM, T1), // 0 0xfe50, 0x0000 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_NULL_OP, // C - ARMv7_NULL_OP, // D - ARMv7_NULL_OP, // E - ARMv7_OP_4(LDRD_LIT, T1) // F 0xfe7f, 0x0000 -}; - -static void group_0xe85(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - //u32 index = thr->code.code0 & 0x000f; - //if ((thr->code.code0 & 0xfe50) == 0xe850) index = 0x0; - - const u32 index = (thr->code.code0 & 0xfe7f) == 0xe85f ? 0xf : 0x0; // check me - thr->m_last_instr_name = g_table_0xe85[index].name; - thr->m_last_instr_size = g_table_0xe85[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xe85[index].func(thr, g_table_0xe85[index].type); -}; - -static const ARMv7_Instruction g_table_0xe8[] = -{ - ARMv7_NULL_OP, // 0 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_OP_4(STRD_IMM, T1), // 4 0xfe50, 0x0000 - { group_0xe85 }, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_4(STM, T2), // 8 0xffd0, 0xa000 - ARMv7_OP_4(LDM, T2), // 9 0xffd0, 0x2000 - ARMv7_NULL_OP, // A - ARMv7_OP_4(POP, T2), // B 0xffff, 0x0000 - ARMv7_NULL_OP, // C - ARMv7_OP_4(TB_, T1) // D 0xfff0, 0xffe0 -}; - -static void group_0xe8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code0 & 0x00f0) >> 4; - - if ((thr->code.code0 & 0xfe50) == 0xe840) index = 0x4; - if ((thr->code.code0 & 0xffd0) == 0xe880) index = 0x8; - if ((thr->code.code0 & 0xffd0) == 0xe890) index = 0x9; - - thr->m_last_instr_name = g_table_0xe8[index].name; - thr->m_last_instr_size = g_table_0xe8[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xe8[index].func(thr, g_table_0xe8[index].type); -} - -static const ARMv7_Instruction g_table_0xe9[] = -{ - ARMv7_OP_4(STMDB, T1), // 0 0xffd0, 0xa000 - ARMv7_OP_4(LDMDB, T1), // 1 0xffd0, 0x2000 - ARMv7_OP_4(PUSH, T2) // 2 0xffff, 0x0000 -}; - -static void group_0xe9(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code0 & 0x00d0) >> 4; - - if ((thr->code.code0 & 0xffff) == 0xe92d) index = 0x2; - - thr->m_last_instr_name = g_table_0xe9[index].name; - thr->m_last_instr_size = g_table_0xe9[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xe9[index].func(thr, g_table_0xe9[index].type); -} - -static const ARMv7_Instruction g_table_0xea4[] = -{ - ARMv7_OP_4(ORR_REG, T2), // 0 0xffe0, 0x8000 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_NULL_OP, // C - ARMv7_NULL_OP, // D - ARMv7_NULL_OP, // E - { group_0xea4f } // F -}; - -static void group_0xea4(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = 0x0; - if ((thr->code.code0 & 0xffef) == 0xea4f) index = 0xf; // check me - - thr->m_last_instr_name = g_table_0xea4[index].name; - thr->m_last_instr_size = g_table_0xea4[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xea4[index].func(thr, g_table_0xea4[index].type); -} - -static const ARMv7_Instruction g_table_0xea4f[] = -{ - { group_0xea4f0000 }, // 0 - ARMv7_OP_4(ASR_IMM, T2), // 1 0xffef, 0x8030 - ARMv7_OP_4(ASR_IMM, T2), // 2 0xffef, 0x8030 - { group_0xea4f0030 } // 3 -}; - -static void group_0xea4f(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = (thr->code.code1 & 0x0030) >> 4; - thr->m_last_instr_name = g_table_0xea4f[index].name; - thr->m_last_instr_size = g_table_0xea4f[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xea4f[index].func(thr, g_table_0xea4f[index].type); -} - -static const ARMv7_Instruction g_table_0xea4f0000[] = -{ - ARMv7_OP_4(MOV_REG, T3), // 0 0xffef, 0xf0f0 - ARMv7_OP_4(LSL_IMM, T2) // 1 0xffef, 0x8030 -}; - -static void group_0xea4f0000(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = thr->code.code1 & 0x8030 ? 0x0 : 0x1; - thr->m_last_instr_name = g_table_0xea4f0000[index].name; - thr->m_last_instr_size = g_table_0xea4f0000[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xea4f0000[index].func(thr, g_table_0xea4f0000[index].type); -} - -static const ARMv7_Instruction g_table_0xea4f0030[] = -{ - ARMv7_OP_4(RRX, T1), // 1 0xffef, 0xf0f0 - ARMv7_OP_4(ROR_IMM, T1) // 2 0xffef, 0x8030 -}; - -static void group_0xea4f0030(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = thr->code.code1 & 0x8030 ? 0x0 : 0x1; - thr->m_last_instr_name = g_table_0xea4f0030[index].name; - thr->m_last_instr_size = g_table_0xea4f0030[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xea4f0030[index].func(thr, g_table_0xea4f0030[index].type); -} - -static const ARMv7_Instruction g_table_0xea6[] = -{ - ARMv7_OP_4(ORN_REG, T1), // 0 0xffe0, 0x8000 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_NULL_OP, // C - ARMv7_NULL_OP, // D - ARMv7_NULL_OP, // E - ARMv7_OP_4(MVN_REG, T2) // F 0xffef, 0x8000 -}; - -static void group_0xea6(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = thr->code.code0 & 0x000f; - - if ((thr->m_arg & 0xffe08000) == 0xea600000) index = 0x0; - - thr->m_last_instr_name = g_table_0xea6[index].name; - thr->m_last_instr_size = g_table_0xea6[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xea6[index].func(thr, g_table_0xea6[index].type); -} - -static const ARMv7_Instruction g_table_0xea[] = -{ - ARMv7_OP_4(AND_REG, T2), // 0 0xffe0, 0x8000 - ARMv7_OP_4(TST_REG, T2), // 1 0xfff0, 0x8f00 - ARMv7_OP_4(BIC_REG, T2), // 2 0xffe0, 0x8000 - ARMv7_NULL_OP, // 3 - { group_0xea4 }, // 4 - ARMv7_NULL_OP, // 5 - { group_0xea6 }, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_4(EOR_REG, T2), // 8 0xffe0, 0x8000 - ARMv7_OP_4(TEQ_REG, T1), // 9 0xfff0, 0x8f00 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_OP_4(PKH, T1) // C 0xfff0, 0x8010 -}; - -static void group_0xea(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code0 & 0x00e0) >> 4; - - if ((thr->m_arg & 0xfff08f00) == 0xea100f00) index = 0x1; - if ((thr->m_arg & 0xfff08f00) == 0xea900f00) index = 0x9; - if ((thr->m_arg & 0xfff08010) == 0xeac00000) index = 0xc; - - thr->m_last_instr_name = g_table_0xea[index].name; - thr->m_last_instr_size = g_table_0xea[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xea[index].func(thr, g_table_0xea[index].type); -} - -static const ARMv7_Instruction g_table_0xeb0[] = -{ - ARMv7_OP_4(ADD_REG, T3), // 0 0xffe0, 0x8000 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_NULL_OP, // C - ARMv7_OP_4(ADD_SPR, T3) // D 0xffef, 0x8000 -}; - -static void group_0xeb0(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = thr->code.code0 & 0x000f; - - if ((thr->m_arg & 0xffe08000) == 0xeb000000) index = 0x0; - - thr->m_last_instr_name = g_table_0xeb0[index].name; - thr->m_last_instr_size = g_table_0xeb0[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xeb0[index].func(thr, g_table_0xeb0[index].type); -} - -static const ARMv7_Instruction g_table_0xeba[] = -{ - ARMv7_OP_4(SUB_REG, T2), // 0 0xffe0, 0x8000 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_NULL_OP, // C - ARMv7_OP_4(SUB_SPR, T1) // D 0xffef, 0x8000 -}; - -static void group_0xeba(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = thr->code.code0 & 0x000f; - - if ((thr->m_arg & 0xffe08000) == 0xeba00000) index = 0x0; - - thr->m_last_instr_name = g_table_0xeba[index].name; - thr->m_last_instr_size = g_table_0xeba[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xeba[index].func(thr, g_table_0xeba[index].type); -} - -static const ARMv7_Instruction g_table_0xeb[] = -{ - { group_0xeb0 }, // 0 0xffe0 - ARMv7_OP_4(CMN_REG, T2), // 1 0xfff0, 0x8f00 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_OP_4(ADC_REG, T2), // 4 0xffe0, 0x8000 - ARMv7_NULL_OP, // 5 - ARMv7_OP_4(SBC_REG, T2), // 6 0xffe0, 0x8000 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - { group_0xeba }, // A 0xffe0 - ARMv7_OP_4(CMP_REG, T3), // B 0xfff0, 0x8f00 - ARMv7_OP_4(RSB_REG, T1) // C 0xffe0, 0x8000 -}; - -static void group_0xeb(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code0 & 0x00e0) >> 4; - - if ((thr->m_arg & 0xfff08f00) == 0xeb100f00) index = 0x1; - if ((thr->m_arg & 0xfff08f00) == 0xebb00f00) index = 0xb; - - thr->m_last_instr_name = g_table_0xeb[index].name; - thr->m_last_instr_size = g_table_0xeb[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xeb[index].func(thr, g_table_0xeb[index].type); -} - -static const ARMv7_Instruction g_table_0xe_main[] = -{ - ARMv7_OP_2(B, T2), // 0 0xf800 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - { group_0xe8 }, // 8 - { group_0xe9 }, // 9 - { group_0xea }, // A - { group_0xeb }, // B - ARMv7_NULL_OP, // C - ARMv7_NULL_OP, // D - ARMv7_NULL_OP, // E - ARMv7_NULL_OP, // F -}; - -static const ARMv7_Instruction g_table_0xe[] = -{ - { group_0xe } -}; - -static void group_0xe(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code0 & 0x0f00) >> 8; - - if ((thr->code.code0 & 0xf800) == 0xe000) index = 0x0; - - thr->m_last_instr_name = g_table_0xe_main[index].name; - thr->m_last_instr_size = g_table_0xe_main[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xe_main[index].func(thr, g_table_0xe_main[index].type); -} - -// 0xf... -static void group_0xf(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf000(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf04(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf06(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf0(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf1(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf1a(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf10(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf20(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf2a(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf2(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf36(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf3(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf810(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf800(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf81(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf820(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf840(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf84(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf850(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf85(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf910(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf91(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf930(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf93(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xf9(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xfa00(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xfa90(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); -static void group_0xfa(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type); - -static const ARMv7_Instruction g_table_0xf000[] = -{ - ARMv7_OP_4(AND_IMM, T1), // 0 0xfbe0, 0x8000 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_4(B, T3), // 8 0xf800, 0xd000 - ARMv7_OP_4(B, T4), // 9 0xf800, 0xd000 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_OP_4(BLX, T2), // C 0xf800, 0xc001 - ARMv7_OP_4(BL, T1) // D 0xf800, 0xd000 -}; - -static void group_0xf000(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code1 & 0xd000) >> 12; - - if ((thr->code.code1 & 0x8000) == 0x0000) index = 0x0; - if ((thr->code.code1 & 0xc001) == 0xc000) index = 0xc; - - thr->m_last_instr_size = g_table_0xf000[index].size; - thr->m_last_instr_name = g_table_0xf000[index].name; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf000[index].func(thr, g_table_0xf000[index].type); -} - -static const ARMv7_Instruction g_table_0xf04[] = -{ - ARMv7_OP_4(ORR_IMM, T1), // 0 0xfbe0, 0x8000 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_NULL_OP, // C - ARMv7_NULL_OP, // D - ARMv7_NULL_OP, // E - ARMv7_OP_4(MOV_IMM, T2) // F 0xfbef, 0x8000 -}; - -static void group_0xf04(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = thr->code.code0 & 0x000f; - - if ((thr->m_arg & 0xfbe08000) == 0xf0400000) index = 0x0; - - thr->m_last_instr_size = g_table_0xf04[index].size; - thr->m_last_instr_name = g_table_0xf04[index].name; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf04[index].func(thr, g_table_0xf04[index].type); -} - -static const ARMv7_Instruction g_table_0xf06[] = -{ - ARMv7_OP_4(ORN_IMM, T1), // 0 0xfbe0, 0x8000 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_NULL_OP, // C - ARMv7_NULL_OP, // D - ARMv7_NULL_OP, // E - ARMv7_OP_4(MVN_IMM, T1) // F 0xfbef, 0x8000 -}; - -static void group_0xf06(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = thr->code.code0 & 0x000f; - - if ((thr->m_arg & 0xfbe08000) == 0xf0600000) index = 0x0; - - thr->m_last_instr_size = g_table_0xf06[index].size; - thr->m_last_instr_name = g_table_0xf06[index].name; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf06[index].func(thr, g_table_0xf06[index].type); -} - -static const ARMv7_Instruction g_table_0xf0[] = -{ - /* - { group_0xf000 }, // 0 0xfbe0 - ARMv7_OP_4(TST_IMM, T1), // 1 0xfbf0, 0x8f00 - ARMv7_OP_4(BIC_IMM, T1), // 2 0xfbe0, 0x8000 - ARMv7_NULL_OP, // 3 - { group_0xf04 }, // 4 0xfbef - ARMv7_NULL_OP, // 5 - { group_0xf06 }, // 6 0xfbef - ARMv7_NULL_OP, // 7 - ARMv7_OP_4(EOR_IMM, T1), // 8 0xfbe0, 0x8000 - ARMv7_OP_4(TEQ_IMM, T1) // 9 0xfbf0, 0x8f00 - */ - - ARMv7_OP_4(AND_IMM, T1), // f0 000 // 0 - ARMv7_OP_4(B, T3), // f0 008 // 1 - ARMv7_OP_4(B, T4), // f0 009 // 2 - ARMv7_OP_4(BLX, T2), // f0 00C // 3 - ARMv7_OP_4(BL, T1), // f0 00D // 4 - - ARMv7_OP_4(TST_IMM, T1), // f0 1 // 5 - ARMv7_OP_4(BIC_IMM, T1), // f0 2 // 6 - ARMv7_NULL_OP, // f0 3 // 7 - - - ARMv7_OP_4(ORR_IMM, T1), // f0 40 // 8 - ARMv7_OP_4(MOV_IMM, T2), // f0 4F // 9 - - ARMv7_NULL_OP, // f0 5 // A - - ARMv7_OP_4(ORN_IMM, T1), // f0 60 // B - ARMv7_OP_4(MVN_IMM, T1), // f0 6F // C - - ARMv7_NULL_OP, // f0 7 // D - ARMv7_OP_4(EOR_IMM, T1), // f0 8 // E - ARMv7_OP_4(TEQ_IMM, T1) // f0 9 // F - -}; - -static void group_0xf0(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) // TODO: optimize this group -{ - u32 index = 0; - if ((thr->m_arg & 0xfbe08000) == 0xf0000000) index = 0x0; - if ((thr->m_arg & 0xf800d000) == 0xf0008000) index = 0x1; - if ((thr->m_arg & 0xf800d000) == 0xf0009000) index = 0x2; - if ((thr->m_arg & 0xf800c001) == 0xf000c000) index = 0x3; - if ((thr->m_arg & 0xf800d000) == 0xf000d000) index = 0x4; - if ((thr->m_arg & 0xfbf08f00) == 0xf0100f00) index = 0x5; - if ((thr->m_arg & 0xfbe08000) == 0xf0200000) index = 0x6; - if ((thr->m_arg & 0xfbe08000) == 0xf0400000) index = 0x8; - if ((thr->m_arg & 0xfbef8000) == 0xf04f0000) index = 0x9; - if ((thr->m_arg & 0xfbe08000) == 0xf0600000) index = 0xb; - if ((thr->m_arg & 0xfbef8000) == 0xf06f0000) index = 0xc; - if ((thr->m_arg & 0xfbe08000) == 0xf0800000) index = 0xe; - if ((thr->m_arg & 0xfbf08f00) == 0xf0900f00) index = 0xf; - - /* - u32 index = (thr->code.code0 & 0x00e0) >> 4; // 0xfbef - - if ((thr->code.code0 & 0xfbf0) == 0xf010) index = 0x1; - if ((thr->code.code0 & 0xfbf0) == 0xf090) index = 0x9; - */ - - thr->m_last_instr_size = g_table_0xf0[index].size; - thr->m_last_instr_name = g_table_0xf0[index].name; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf0[index].func(thr, g_table_0xf0[index].type); -} - -static const ARMv7_Instruction g_table_0xf10[] = -{ - ARMv7_OP_4(ADD_IMM, T3), // 0 0xfbe0, 0x8000 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_NULL_OP, // C - ARMv7_OP_4(ADD_SPI, T3) // D 0xfbef, 0x8000 -}; - -static void group_0xf10(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = thr->code.code0 & 0x000f; - - if ((thr->m_arg & 0xfbe08000) == 0xf1000000) index = 0x0; - - thr->m_last_instr_name = g_table_0xf10[index].name; - thr->m_last_instr_size = g_table_0xf10[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf10[index].func(thr, g_table_0xf10[index].type); -} - -static const ARMv7_Instruction g_table_0xf1a[] = -{ - ARMv7_OP_4(SUB_IMM, T3), // 0 0xfbe0, 0x8000 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_NULL_OP, // C - ARMv7_OP_4(SUB_SPI, T2) // D 0xfbef, 0x8000 -}; - -static void group_0xf1a(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = thr->code.code0 & 0x000f; - - if ((thr->m_arg & 0xfbe08000) == 0xf1a00000) index = 0x0; - - thr->m_last_instr_name = g_table_0xf1a[index].name; - thr->m_last_instr_size = g_table_0xf1a[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf1a[index].func(thr, g_table_0xf1a[index].type); -} - -static const ARMv7_Instruction g_table_0xf1[] = -{ - { group_0xf10 }, // 0 - ARMv7_OP_4(CMN_IMM, T1), // 1 0xfbf0, 0x8f00 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_OP_4(ADC_IMM, T1), // 4 0xfbe0, 0x8000 - ARMv7_NULL_OP, // 5 - ARMv7_OP_4(SBC_IMM, T1), // 6 0xfbe0, 0x8000 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - { group_0xf1a }, // A - ARMv7_OP_4(CMP_IMM, T2), // B 0xfbf0, 0x8f00 - ARMv7_OP_4(RSB_IMM, T2) // C 0xfbe0, 0x8000 -}; - -static void group_0xf1(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code0 & 0x00e0) >> 4; - - if ((thr->m_arg & 0xfbf08f00) == 0xf1100f00) index = 0x1; - if ((thr->m_arg & 0xfbf08f00) == 0xf1b00f00) index = 0xb; - - thr->m_last_instr_name = g_table_0xf1[index].name; - thr->m_last_instr_size = g_table_0xf1[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf1[index].func(thr, g_table_0xf1[index].type); -} - -static const ARMv7_Instruction g_table_0xf20[] = -{ - ARMv7_OP_4(ADD_IMM, T4), // 0 0xfbf0, 0x8000 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_NULL_OP, // C - ARMv7_OP_4(ADD_SPI, T4), // D 0xfbff, 0x8000 - ARMv7_NULL_OP, // E - ARMv7_OP_4(ADR, T3) // F 0xfbff, 0x8000 -}; - -static void group_0xf20(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = thr->code.code0 & 0x000f; - - if ((thr->m_arg & 0xfbf08000) == 0xf2000000) index = 0x0; - - thr->m_last_instr_name = g_table_0xf20[index].name; - thr->m_last_instr_size = g_table_0xf20[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf20[index].func(thr, g_table_0xf20[index].type); -} - -static const ARMv7_Instruction g_table_0xf2a[] = -{ - ARMv7_OP_4(SUB_IMM, T4), // 0 0xfbf0, 0x8000 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_NULL_OP, // C - ARMv7_OP_4(SUB_SPI, T3), // D 0xfbff, 0x8000 - ARMv7_NULL_OP, // E - ARMv7_OP_4(ADR, T2) // F 0xfbff, 0x8000 -}; - -static void group_0xf2a(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = thr->code.code0 & 0x000f; - - if ((thr->m_arg & 0xfbf08000) == 0xf2a00000) index = 0x0; - - thr->m_last_instr_name = g_table_0xf2a[index].name; - thr->m_last_instr_size = g_table_0xf2a[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf2a[index].func(thr, g_table_0xf2a[index].type); -} - -static const ARMv7_Instruction g_table_0xf2[] = -{ - { group_0xf20 }, // 0 0xfbff - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_OP_4(MOV_IMM, T3), // 4 0xfbf0, 0x8000 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - { group_0xf2a }, // A 0xfbff - ARMv7_NULL_OP, // B - ARMv7_OP_4(MOVT, T1) // C 0xfbf0, 0x8000 -}; - -static void group_0xf2(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = (thr->code.code0 & 0x00f0) >> 4; // mask 0xfbf0 - thr->m_last_instr_name = g_table_0xf2[index].name; - thr->m_last_instr_size = g_table_0xf2[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf2[index].func(thr, g_table_0xf2[index].type); -} - -static const ARMv7_Instruction g_table_0xf36[] = -{ - ARMv7_OP_4(BFI, T1), // 0 0xfff0, 0x8020 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_NULL_OP, // C - ARMv7_NULL_OP, // C - ARMv7_NULL_OP, // E - ARMv7_OP_4(BFC, T1) // F 0xffff, 0x8020 -}; - -static void group_0xf36(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = thr->code.code0 & 0x000f; - - if ((thr->m_arg & 0xfff08020) == 0xf3600000) index = 0x0; - - thr->m_last_instr_name = g_table_0xf36[index].name; - thr->m_last_instr_size = g_table_0xf36[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf36[index].func(thr, g_table_0xf36[index].type); -} - -static const ARMv7_Instruction g_table_0xf3[] = -{ - ARMv7_NULL_OP, // 0 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_OP_4(SBFX, T1), // 4 0xfff0, 0x8020 - ARMv7_NULL_OP, // 5 - { group_0xf36 }, // 6 0xffff - ARMv7_NULL_OP, // 7 - ARMv7_OP_4(MSR_REG, T1), // 8 0xfff0, 0xf3ff - ARMv7_NULL_OP, // 9 - ARMv7_OP_4(NOP, T2), // A 0xffff, 0xffff - ARMv7_NULL_OP, // B - ARMv7_NULL_OP, // C - ARMv7_NULL_OP, // D - ARMv7_OP_4(MRS, T1), // E 0xffff, 0xf0ff -}; - -static void group_0xf3(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = (thr->code.code0 & 0x00f0) >> 4; - thr->m_last_instr_name = g_table_0xf3[index].name; - thr->m_last_instr_size = g_table_0xf3[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf3[index].func(thr, g_table_0xf3[index].type); -} - -static const ARMv7_Instruction g_table_0xf800[] = -{ - ARMv7_OP_4(STRB_REG, T2), // 0 0xfff0, 0x0fc0 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_4(STRB_IMM, T3) // 8 0xfff0, 0x0800 -}; - -static void group_0xf800(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code1 & 0x0f00) >> 8; - - if ((thr->code.code1 & 0x0800) == 0x0800) index = 0x8; - - thr->m_last_instr_name = g_table_0xf800[index].name; - thr->m_last_instr_size = g_table_0xf800[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf800[index].func(thr, g_table_0xf800[index].type); -} - -static const ARMv7_Instruction g_table_0xf810[] = -{ - ARMv7_OP_4(LDRB_REG, T2), // 0 0xfff0, 0x0fc0 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_4(LDRB_IMM, T3) // 8 0xfff0, 0x0800 -}; - -static void group_0xf810(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code1 & 0x0f00) >> 8; - - if ((thr->code.code1 & 0x0800) == 0x0800) index = 0x8; - - thr->m_last_instr_name = g_table_0xf810[index].name; - thr->m_last_instr_size = g_table_0xf810[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf810[index].func(thr, g_table_0xf810[index].type); -} - -static const ARMv7_Instruction g_table_0xf81[] = -{ - { group_0xf810 }, // 0 0xfff0 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_NULL_OP, // C - ARMv7_NULL_OP, // C - ARMv7_NULL_OP, // E - ARMv7_OP_4(LDRB_LIT, T1) // F 0xff7f, 0x0000 -}; - -static void group_0xf81(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = thr->code.code0 & 0x000f; - - if (((thr->m_arg & 0xfff00fc0) == 0xf8100000) || ((thr->m_arg & 0xfff00800) == 0xf8100800)) index = 0x0; - - thr->m_last_instr_name = g_table_0xf81[index].name; - thr->m_last_instr_size = g_table_0xf81[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf81[index].func(thr, g_table_0xf81[index].type); -} - -static const ARMv7_Instruction g_table_0xf820[] = -{ - ARMv7_OP_4(STRH_REG, T2), // 0 0xfff0, 0x0fc0 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_4(STRH_IMM, T3) // 8 0xfff0, 0x0800 -}; - -static void group_0xf820(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code1 & 0x0f00) >> 8; - - if ((thr->code.code1 & 0x0800) == 0x0800) index = 0x8; - - thr->m_last_instr_name = g_table_0xf820[index].name; - thr->m_last_instr_size = g_table_0xf820[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf820[index].func(thr, g_table_0xf820[index].type); -} - -static const ARMv7_Instruction g_table_0xf840[] = -{ - ARMv7_OP_4(STR_REG, T2), // 0 0xfff0, 0x0fc0 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_4(STR_IMM, T4) // 8 0xfff0, 0x0800 -}; - -static void group_0xf840(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code1 & 0x0f00) >> 8; - - if ((thr->code.code1 & 0x0800) == 0x0800) index = 0x8; - - thr->m_last_instr_name = g_table_0xf840[index].name; - thr->m_last_instr_size = g_table_0xf840[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf840[index].func(thr, g_table_0xf840[index].type); -} - -static const ARMv7_Instruction g_table_0xf84[] = -{ - { group_0xf840 }, // 0 0xfff0 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_NULL_OP, // C - ARMv7_OP_4(PUSH, T3) // D 0xffff, 0x0fff -}; - -static void group_0xf84(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = thr->code.code0 & 0x000f; - - if (((thr->m_arg & 0xfff00fc0) == 0xf8400000) || ((thr->m_arg & 0xfff00800) == 0xf8400800)) index = 0x0; - - thr->m_last_instr_name = g_table_0xf84[index].name; - thr->m_last_instr_size = g_table_0xf84[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf84[index].func(thr, g_table_0xf84[index].type); -} - -static const ARMv7_Instruction g_table_0xf850[] = -{ - ARMv7_OP_4(LDR_REG, T2), // 0 0xfff0, 0x0fc0 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_4(LDR_IMM, T4) // 8 0xfff0, 0x0800 -}; - -static void group_0xf850(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code1 & 0x0f00) >> 8; - - if ((thr->code.code1 & 0x0800) == 0x0800) index = 0x8; - - thr->m_last_instr_name = g_table_0xf850[index].name; - thr->m_last_instr_size = g_table_0xf850[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf850[index].func(thr, g_table_0xf850[index].type); -} - -static const ARMv7_Instruction g_table_0xf85[] = -{ - { group_0xf850 }, // 0 0xfff0 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_NULL_OP, // C - ARMv7_OP_4(POP, T3), // D 0xffff, 0x0fff - ARMv7_NULL_OP, // C - ARMv7_OP_4(LDR_LIT, T2) // F 0xff7f, 0x0000 -}; - -static void group_0xf85(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = thr->code.code0 & 0x000f; - - if (((thr->m_arg & 0xfff00fc0) == 0xf8500000) || ((thr->m_arg & 0xfff00800) == 0xf8500800)) index = 0x0; - - thr->m_last_instr_name = g_table_0xf85[index].name; - thr->m_last_instr_size = g_table_0xf85[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf85[index].func(thr, g_table_0xf85[index].type); -} - -static const ARMv7_Instruction g_table_0xf8[] = -{ - { group_0xf800 }, // 0 0xfff0 - { group_0xf81 }, // 1 0xfff0 - { group_0xf820 }, // 2 0xfff0 - ARMv7_NULL_OP, // 3 - { group_0xf84 }, // 4 0xfff0 - { group_0xf85 }, // 5 0xfff0 - ARMv7_NULL_OP, // 6 - ARMv7_OP_4(HACK, T1), // 7 0xffff, 0x0000 - ARMv7_OP_4(STRB_IMM, T2), // 8 0xfff0, 0x0000 - ARMv7_OP_4(LDRB_IMM, T2), // 9 0xfff0, 0x0000 - ARMv7_OP_4(STRH_IMM, T2), // A 0xfff0, 0x0000 - ARMv7_NULL_OP, // B - ARMv7_OP_4(STR_IMM, T3), // C 0xfff0, 0x0000 - ARMv7_OP_4(LDR_IMM, T3) // D 0xfff0, 0x0000 -}; - -static void group_0xf8(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = (thr->code.code0 & 0x00f0) >> 4; - thr->m_last_instr_name = g_table_0xf8[index].name; - thr->m_last_instr_size = g_table_0xf8[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf8[index].func(thr, g_table_0xf8[index].type); -} - -static const ARMv7_Instruction g_table_0xf910[] = -{ - ARMv7_OP_4(LDRSB_REG, T2), // 0 0xfff0, 0x0fc0 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_4(LDRSB_IMM, T2) // 8 0xfff0, 0x0800 -}; - -static void group_0xf910(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code1 & 0x0f00) >> 8; - - if ((thr->code.code1 & 0x0800) == 0x0800) index = 0x8; - - thr->m_last_instr_name = g_table_0xf910[index].name; - thr->m_last_instr_size = g_table_0xf910[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf910[index].func(thr, g_table_0xf910[index].type); -} - -static const ARMv7_Instruction g_table_0xf91[] = -{ - { group_0xf910 }, // 0 0xfff0 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_NULL_OP, // C - ARMv7_NULL_OP, // D - ARMv7_NULL_OP, // C - ARMv7_OP_4(LDRSB_LIT, T1) // F 0xff7f, 0x0000 -}; - -static void group_0xf91(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = thr->code.code0 & 0x000f; - - if (((thr->m_arg & 0xfff00fc0) == 0xf9100000) || ((thr->m_arg & 0xfff00800) == 0xf9100800)) index = 0x0; - - thr->m_last_instr_name = g_table_0xf91[index].name; - thr->m_last_instr_size = g_table_0xf91[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf91[index].func(thr, g_table_0xf91[index].type); -} - -static const ARMv7_Instruction g_table_0xf930[] = -{ - ARMv7_OP_4(LDRSH_REG, T2), // 0 0xfff0, 0x0fc0 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_4(LDRSH_IMM, T2) // 8 0xfff0, 0x0800 -}; - -static void group_0xf930(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code1 & 0x0f00) >> 8; - - if ((thr->code.code1 & 0x0800) == 0x0800) index = 0x8; - - thr->m_last_instr_name = g_table_0xf930[index].name; - thr->m_last_instr_size = g_table_0xf930[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf930[index].func(thr, g_table_0xf930[index].type); -} - -static const ARMv7_Instruction g_table_0xf93[] = -{ - { group_0xf930 }, // 0 0xfff0 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_NULL_OP, // C - ARMv7_NULL_OP, // D - ARMv7_NULL_OP, // C - ARMv7_OP_4(LDRSH_LIT, T1) // F 0xff7f, 0x0000 -}; - -static void group_0xf93(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = thr->code.code0 & 0x000f; - - if (((thr->m_arg & 0xfff00fc0) == 0xf9300000) || ((thr->m_arg & 0xfff00800) == 0xf9300800)) index = 0x0; - - thr->m_last_instr_name = g_table_0xf93[index].name; - thr->m_last_instr_size = g_table_0xf93[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf93[index].func(thr, g_table_0xf93[index].type); -} - -static const ARMv7_Instruction g_table_0xf9[] = -{ - ARMv7_NULL_OP, // 0 - { group_0xf91 }, // 1 0xff7f - ARMv7_NULL_OP, // 2 - { group_0xf93 }, // 3 0xff7f - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_OP_4(LDRSB_IMM, T1), // 9 0xfff0, 0x0000 - ARMv7_NULL_OP, // A - ARMv7_OP_4(LDRSH_IMM, T1), // B 0xfff0, 0x0000 -}; - -static void group_0xf9(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code0 & 0x00f0) >> 4; - - if ((thr->code.code0 & 0xff7) == 0xf91) index = 0x1; // check me - if ((thr->code.code0 & 0xff7) == 0xf93) index = 0x3; - - thr->m_last_instr_name = g_table_0xf9[index].name; - thr->m_last_instr_size = g_table_0xf9[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf9[index].func(thr, g_table_0xf9[index].type); -} - -static const ARMv7_Instruction g_table_0xfa00[] = -{ - ARMv7_OP_4(BLX, A2), // 0 0xfe00, 0x0000 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - ARMv7_NULL_OP, // 9 - ARMv7_NULL_OP, // A - ARMv7_NULL_OP, // B - ARMv7_NULL_OP, // C - ARMv7_NULL_OP, // D - ARMv7_NULL_OP, // E - ARMv7_OP_4(LSL_REG, T2) // F 0xffe0, 0xf0f0 -}; - -static void group_0xfa00(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = (thr->code.code1 & 0xf0f0) == 0xf000 ? 0xf : 0x0; - thr->m_last_instr_name = g_table_0xfa00[index].name; - thr->m_last_instr_size = g_table_0xfa00[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xfa00[index].func(thr, g_table_0xfa00[index].type); -} - -static const ARMv7_Instruction g_table_0xfa90[] = -{ - ARMv7_NULL_OP, // 0 - ARMv7_NULL_OP, // 1 - ARMv7_NULL_OP, // 2 - ARMv7_NULL_OP, // 3 - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - ARMv7_OP_4(REV, T2), // 8 0xfff0, 0xf0f0 - ARMv7_OP_4(REV16, T2), // 9 0xfff0, 0xf0f0 - ARMv7_OP_4(RBIT, T1), // A 0xfff0, 0xf0f0 - ARMv7_OP_4(REVSH, T2) // B 0xfff0, 0xf0f0 -}; - -static void group_0xfa90(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - const u32 index = (thr->code.code1 & 0x00f0) >> 4; - thr->m_last_instr_name = g_table_0xfa90[index].name; - thr->m_last_instr_size = g_table_0xfa90[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xfa90[index].func(thr, g_table_0xfa90[index].type); -} - -static const ARMv7_Instruction g_table_0xfa[] = -{ - { group_0xfa00 }, // 0 0xffe0 - ARMv7_NULL_OP, // 1 - ARMv7_OP_4(LSR_REG, T2), // 2 0xffe0, 0xf0f0 - ARMv7_NULL_OP, // 3 - ARMv7_OP_4(ASR_REG, T2), // 4 0xffe0, 0xf0f0 - ARMv7_NULL_OP, // 5 - ARMv7_OP_4(ROR_REG, T2), // 6 0xffe0, 0xf0f0 - ARMv7_NULL_OP, // 7 - ARMv7_NULL_OP, // 8 - { group_0xfa90 }, // 9 0xfff0 - ARMv7_OP_4(SEL, T1), // A 0xfff0, 0xf0f0 - ARMv7_OP_4(CLZ, T1) // B 0xfff0, 0xf0f0 -}; - -static void group_0xfa(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code0 & 0x00e0) >> 4; - - switch ((thr->code.code0 & 0x00f0) >> 4) + inline namespace arm_encoding_alias { - case 0x9: index = 0x9; break; - case 0xa: index = 0xa; break; - case 0xb: index = 0xb; break; - - default: break; + constexpr auto T1 = arm_encoding ::T1; + constexpr auto T2 = arm_encoding ::T2; + constexpr auto T3 = arm_encoding ::T3; + constexpr auto T4 = arm_encoding ::T4; + constexpr auto A1 = arm_encoding ::A1; + constexpr auto A2 = arm_encoding ::A2; } - thr->m_last_instr_name = g_table_0xfa[index].name; - thr->m_last_instr_size = g_table_0xfa[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xfa[index].func(thr, g_table_0xfa[index].type); + // Bitfield aliases (because only u32 base type is used) + template using bf = bf_t; + template using sf = bf_t; + template using ff = ff_t; + + template using cf = cf_t; + + // Nullary op + template + struct nullary + { + static inline u32 extract() + { + return F::extract(0); + } + }; + + // Pair op: first field selection + template + struct from_first + { + static inline u32 extract(u32 first, u32) + { + return F::extract(first); + } + }; + + // Pair op: second field selection + template + struct from_second + { + static inline u32 extract(u32, u32 second) + { + return F::extract(second); + } + }; + + // No operation + struct nopf + { + static inline u32 extract(u32 value) + { + return value; + } + }; + + // Negate unary op + template + struct negatef : bf_base + { + static inline u32 extract(u32 value) + { + return (0u - F::extract(value)) & (~0u >> (32 - N)); + } + }; + + // NOT unary op + template + struct notf : bf_base + { + static inline u32 extract(u32 value) + { + return F::extract(value) ^ (~0u >> (32 - N)); + } + }; + + // XOR binary op + template + struct xorf : bf_base + { + static inline u32 extract(u32 value) + { + return F1::extract(value) ^ F2::extract(value); + } + }; + + // AND binary op + template + struct andf : bf_base + { + static inline u32 extract(u32 value) + { + return F1::extract(value) & F2::extract(value); + } + }; + + // OR binary op + template + struct orf : bf_base + { + static inline u32 extract(u32 value) + { + return F1::extract(value) | F2::extract(value); + } + }; + + // SHL binary op + template + struct shlf : bf_base + { + static inline u32 extract(u32 value) + { + return F1::extract(value) << F2::extract(value); + } + }; + + // EQ with constant binary op + template + struct eqcf : bf_base + { + static inline u32 extract(u32 value) + { + return F1::extract(value) == C; + } + }; + + using imm12i38 = cf, bf<12, 3>, bf<0, 8>>; + + // ThumbExpandImm(...) + struct thumb_expand_imm + { + static constexpr uint bitsize() + { + return 32; + } + + static u32 extract(u32 value) + { + const u32 imm12 = imm12i38::extract(value); + + if ((imm12 & 0xc00) >> 10) + { + const u32 x = (imm12 & 0x7f) | 0x80; + const u32 s = (imm12 & 0xf80) >> 7; + const u32 r = x >> s | x << (32 - s); // Rotate + return r; + } + else + { + const u32 imm8 = imm12 & 0xff; + switch ((imm12 & 0x300) >> 8) + { + case 0: return imm8; + case 1: return imm8 << 16 | imm8; + case 2: return imm8 << 24 | imm8 << 8; + default: return imm8 << 24 | imm8 << 16 | imm8 << 8 | imm8; + } + } + } + }; + + // ThumbExpandImm_C(..., carry) -> carry + struct thumb_expand_imm_c + { + static u32 extract(u32 value, u32 carry_in) + { + const u32 imm12 = imm12i38::extract(value); + + if ((imm12 & 0xc00) >> 10) + { + const u32 x = (imm12 & 0x7f) | 0x80; + const u32 s = (imm12 & 0xf80) >> 7; + const u32 r = x >> s | x << (32 - s); // Rotate + return (s ? r >> 31 : carry_in) & 1; + } + else + { + return carry_in & 1; + } + } + }; + + // ARMExpandImm(...) + struct arm_expand_imm + { + static constexpr uint bitsize() + { + return 32; + } + + static u32 extract(u32 value) + { + const u32 imm12 = bf<0, 12>::extract(value); + + const u32 x = imm12 & 0xff; + const u32 s = (imm12 & 0xf00) >> 7; + const u32 r = x >> s | x << (32 - s); // Rotate + + return r; + } + }; + + // ARMExpandImm_C(..., carry) -> carry + struct arm_expand_imm_c + { + static u32 extract(u32 value, u32 carry_in) + { + const u32 imm12 = bf<0, 12>::extract(value); + + const u32 x = imm12 & 0xff; + const u32 s = (imm12 & 0xf00) >> 7; + const u32 r = x >> s | x << (32 - s); // Rotate + + return (s ? r >> 31 : carry_in) & 1; + } + }; + + // !InITBlock() + struct not_in_it_block + { + static u32 extract(u32 value, u32 cond) + { + return cond != 0xf; + } + }; + + enum SRType : u32 + { + SRType_LSL, + SRType_LSR, + SRType_ASR, + SRType_ROR, + SRType_RRX, + }; + + template + struct decode_imm_shift_type + { + static u32 extract(u32 value) + { + const u32 type = T::extract(value); + const u32 imm5 = N::extract(value); + + return type < SRType_ROR ? type : (imm5 ? SRType_ROR : SRType_RRX); + } + }; + + template + struct decode_imm_shift_num + { + static u32 extract(u32 value) + { + const u32 type = T::extract(value); + const u32 imm5 = N::extract(value); + + return imm5 || type == SRType_LSL ? imm5 : (type < SRType_ROR ? 32 : 1); + } + }; + + using decode_imm_shift_type_thumb = decode_imm_shift_type, cf, bf<6, 2>>>; + using decode_imm_shift_num_thumb = decode_imm_shift_num, cf, bf<6, 2>>>; + using decode_imm_shift_type_arm = decode_imm_shift_type, bf<7, 5>>; + using decode_imm_shift_num_arm = decode_imm_shift_num, bf<7, 5>>; + + template struct it; // + + template<> struct it + { + using mask = bf<0, 4>; + using first = bf<4, 4>; + + using skip_if = eqcf; // Skip if mask==0 + }; + + template struct hack; // + + template<> struct hack + { + using index = bf<0, 16>; + + using skip_if = void; + }; + + template<> struct hack + { + using index = cf, bf<0, 4>>; + + using skip_if = void; + }; + + template struct mrc; // + + template<> struct mrc + { + using t = bf<12, 4>; + using cp = bf<8, 4>; + using opc1 = bf<21, 3>; + using opc2 = bf<5, 3>; + using cn = bf<16, 4>; + using cm = bf<0, 4>; + + using skip_if = eqcf, 5>; + }; + + template<> struct mrc : mrc + { + using skip_if = void; + }; + + template<> struct mrc : mrc + { + using skip_if = eqcf, 5>; + }; + + template<> struct mrc : mrc + { + using skip_if = void; + }; + + template struct add_imm; // + + template<> struct add_imm + { + using d = bf<0, 3>; + using n = bf<3, 3>; + using set_flags = not_in_it_block; + using imm32 = bf<6, 3>; + + using skip_if = void; + }; + + template<> struct add_imm + { + using d = bf<8, 3>; + using n = d; + using set_flags = not_in_it_block; + using imm32 = bf<0, 8>; + + using skip_if = void; + }; + + template<> struct add_imm + { + using d = bf<8, 4>; + using n = bf<16, 4>; + using set_flags = from_first>; + using imm32 = thumb_expand_imm; + + using skip_if = orf, bf<20, 1>>, eqcf>; + }; + + template<> struct add_imm : add_imm + { + using add_imm::n; + using set_flags = from_first>; + using imm32 = imm12i38; + + using skip_if = orf, eqcf>; + }; + + template<> struct add_imm + { + using d = bf<12, 4>; + using n = bf<16, 4>; + using set_flags = from_first>; + using imm32 = arm_expand_imm; + + using skip_if = orf, notf>>, eqcf>, andf, bf<20, 1>>>; + }; + + template struct add_reg; // + + template<> struct add_reg + { + using d = bf<0, 3>; + using n = bf<3, 3>; + using m = bf<6, 3>; + using set_flags = not_in_it_block; + using shift_t = ff; + using shift_n = ff<0u>; + + using skip_if = void; + }; + + template<> struct add_reg + { + using d = cf, bf<0, 3>>; + using n = d; + using m = bf<3, 4>; + using set_flags = from_first>; + using shift_t = ff; + using shift_n = ff<0u>; + + using skip_if = orf, eqcf>; + }; + + template<> struct add_reg + { + using d = bf<8, 4>; + using n = bf<16, 4>; + using m = bf<0, 4>; + using set_flags = from_first>; + using shift_t = decode_imm_shift_type_thumb; + using shift_n = decode_imm_shift_num_thumb; + + using skip_if = orf, bf<20, 1>>, eqcf>; + }; + + template<> struct add_reg : add_reg + { + using d = bf<12, 4>; + using n = bf<16, 4>; + using shift_t = decode_imm_shift_type_arm; + using shift_n = decode_imm_shift_num_arm; + + using skip_if = orf, bf<20, 1>>, eqcf>; + }; + + template struct add_spi; // + + template<> struct add_spi + { + using d = bf<8, 3>; + using set_flags = from_first>; + using imm32 = cf, ff<0u, 2>>; + + using skip_if = void; + }; + + template<> struct add_spi + { + using d = ff<13u>; + using set_flags = from_first>; + using imm32 = cf, ff<0u, 2>>; + + using skip_if = void; + }; + + template<> struct add_spi + { + using d = bf<8, 4>; + using set_flags = from_first>; + using imm32 = thumb_expand_imm; + + using skip_if = andf, bf<20, 1>>; + }; + + template<> struct add_spi + { + using d = bf<8, 4>; + using set_flags = from_first>; + using imm32 = imm12i38; + + using skip_if = void; + }; + + template<> struct add_spi + { + using d = bf<12, 4>; + using set_flags = from_first>; + using imm32 = arm_expand_imm; + + using skip_if = andf, bf<20, 1>>; + }; + + template struct add_spr; // + + template<> struct add_spr + { + using d = cf, bf<0, 3>>; + using m = d; + using set_flags = from_first>; + using shift_t = ff; + using shift_n = ff<0u>; + + using skip_if = void; + }; + + template<> struct add_spr + { + using d = ff<13u>; + using m = bf<3, 4>; + using set_flags = from_first>; + using shift_t = ff; + using shift_n = ff<0u>; + + using skip_if = eqcf; + }; + + template<> struct add_spr + { + using d = bf<8, 4>; + using m = bf<0, 4>; + using set_flags = from_first>; + using shift_t = decode_imm_shift_type_thumb; + using shift_n = decode_imm_shift_num_thumb; + + using skip_if = void; + }; + + template<> struct add_spr + { + using d = bf<12, 4>; + using m = bf<0, 4>; + using set_flags = from_first>; + using shift_t = decode_imm_shift_type_arm; + using shift_n = decode_imm_shift_num_arm; + + using skip_if = andf, bf<20, 1>>; + }; + + template struct adc_imm; // + + template<> struct adc_imm : add_imm + { + using skip_if = void; + }; + + template<> struct adc_imm : add_imm + { + using skip_if = void; + }; + + template struct adc_reg; // + + template<> struct adc_reg + { + using d = bf<0, 3>; + using n = d; + using m = bf<3, 3>; + using set_flags = not_in_it_block; + using shift_t = ff; + using shift_n = ff<0u>; + + using skip_if = void; + }; + + template<> struct adc_reg : add_reg + { + using skip_if = void; + }; + + template<> struct adc_reg : add_reg + { + using add_reg::d; + + using skip_if = andf, bf<20, 1>>; + }; + + template struct adr; // + + template<> struct adr + { + using d = bf<8, 3>; + using i = cf, ff<0u, 2>>; + + using skip_if = void; + }; + + template<> struct adr + { + using d = bf<8, 4>; + using i = negatef; + + using skip_if = void; + }; + + template<> struct adr + { + using d = bf<8, 4>; + using i = imm12i38; + + using skip_if = void; + }; + + template<> struct adr + { + using d = bf<12, 4>; + using i = arm_expand_imm; + + using skip_if = void; + }; + + template<> struct adr + { + using d = bf<12, 4>; + using i = negatef; + + using skip_if = void; + }; + + template struct and_imm; // + + template<> struct and_imm + { + using d = bf<8, 4>; + using n = bf<16, 4>; + using set_flags = from_first>; + using imm32 = thumb_expand_imm; + using carry = thumb_expand_imm_c; + + using skip_if = andf, bf<20, 1>>; + }; + + template<> struct and_imm : and_imm + { + using d = bf<12, 4>; + using imm32 = arm_expand_imm; + using carry = arm_expand_imm_c; + + using skip_if = andf, bf<20, 1>>; + }; + + template struct and_reg; // + + template<> struct and_reg : adc_reg + { + using skip_if = void; + }; + + template<> struct and_reg : adc_reg + { + using adc_reg::d; + + using skip_if = andf, bf<20, 1>>; + }; + + template<> struct and_reg : adc_reg + { + using adc_reg::d; + + using skip_if = andf, bf<20, 1>>; + }; + + template struct b; // + + template<> struct b + { + using imm32 = cf, ff<0u, 1>>; + using cond = from_first>; + + using skip_if = eqcf; + }; + + template<> struct b + { + using imm32 = cf, ff<0u, 1>>; + using cond = from_second<>; + + using skip_if = void; + }; + + template<> struct b + { + using imm32 = cf, bf<11, 1>, bf<13, 1>, bf<16, 6>, bf<0, 11>, ff<0u, 1>>; + using cond = from_first>; + + using skip_if = eqcf, 7>; + }; + + template<> struct b + { + using imm32 = cf, notf, bf<26, 1>>>, notf, bf<26, 1>>>, bf<16, 10>, bf<0, 11>, ff<0u, 1>>; + using cond = from_second<>; + + using skip_if = void; + }; + + template<> struct b + { + using imm32 = cf, ff<0u, 2>>; + using cond = from_second<>; + + using skip_if = void; + }; + + template struct bic_imm; // + + template<> struct bic_imm : and_imm + { + using skip_if = void; + }; + + template<> struct bic_imm : and_imm + { + using and_imm::d; + + using skip_if = andf, bf<20, 1>>; + }; + + template struct bic_reg; // + + template<> struct bic_reg : adc_reg + { + using skip_if = void; + }; + + template<> struct bic_reg : adc_reg + { + using skip_if = void; + }; + + template<> struct bic_reg : adc_reg + { + using adc_reg::d; + + using skip_if = andf, bf<20, 1>>; + }; + + template struct bl; // + + template<> struct bl + { + using imm32 = b::imm32; + using to_arm = nullary>; + + using skip_if = void; + }; + + template<> struct bl + { + using imm32 = cf, notf, bf<26, 1>>>, notf, bf<26, 1>>>, bf<16, 10>, bf<1, 10>, ff<0u, 2>>; + using to_arm = nullary>; + + using skip_if = void; + }; + + template<> struct bl + { + using imm32 = b::imm32; + using to_arm = nullary>; + + using skip_if = void; + }; + + template<> struct bl + { + using imm32 = cf, bf<24, 1>, ff<0u, 1>>; + using to_arm = nullary>; + + using skip_if = void; + }; + + template struct blx; // + + template<> struct blx + { + using m = bf<3, 4>; + + using skip_if = void; + }; + + template<> struct blx + { + using m = bf<0, 4>; + + using skip_if = void; + }; + + template struct bx; // + + template<> struct bx : blx + { + using skip_if = void; + }; + + template<> struct bx : blx + { + using skip_if = void; + }; + + template struct cb_z; // + + template<> struct cb_z + { + using n = bf<0, 3>; + using imm32 = cf, bf<3, 5>, ff<0u, 1>>; + using nonzero = bf<11, 1>; + + using skip_if = void; + }; + + template struct clz; // + + template<> struct clz + { + using d = bf<8, 4>; + using m = bf<0, 4>; + + using skip_if = void; + }; + + template<> struct clz + { + using d = bf<12, 4>; + using m = bf<0, 4>; + + using skip_if = void; + }; + + template struct cmp_imm; // + + template<> struct cmp_imm + { + using n = bf<8, 3>; + using imm32 = bf<0, 8>; + + using skip_if = void; + }; + + template<> struct cmp_imm + { + using n = bf<16, 4>; + using imm32 = thumb_expand_imm; + + using skip_if = void; + }; + + template<> struct cmp_imm + { + using n = bf<16, 4>; + using imm32 = arm_expand_imm; + + using skip_if = void; + }; + + template struct cmp_reg; // + + template<> struct cmp_reg + { + using n = bf<0, 3>; + using m = bf<3, 3>; + using shift_t = ff; + using shift_n = ff<0u>; + + using skip_if = void; + }; + + template<> struct cmp_reg : cmp_reg + { + using n = cf, bf<0, 3>>; + using m = bf<3, 4>; + + using skip_if = void; + }; + + template<> struct cmp_reg + { + using n = bf<16, 4>; + using m = bf<0, 4>; + using shift_t = decode_imm_shift_type_thumb; + using shift_n = decode_imm_shift_num_thumb; + + using skip_if = void; + }; + + template<> struct cmp_reg : cmp_reg + { + using shift_t = decode_imm_shift_type_arm; + using shift_n = decode_imm_shift_num_arm; + + using skip_if = void; + }; + + template struct eor_imm; // + + template<> struct eor_imm : and_imm + { + using and_imm::d; + + using skip_if = andf, bf<20, 1>>; + }; + + template<> struct eor_imm : and_imm + { + using and_imm::d; + + using skip_if = andf, bf<20, 1>>; + }; + + template struct eor_reg; // + + template<> struct eor_reg : adc_reg + { + using skip_if = void; + }; + + template<> struct eor_reg : adc_reg + { + using adc_reg::d; + + using skip_if = andf, bf<20, 1>>; + }; + + template<> struct eor_reg : adc_reg + { + using adc_reg::d; + + using skip_if = andf, bf<20, 1>>; + }; + + template struct ldm; // + + template<> struct ldm + { + using n = bf<8, 3>; + using registers = bf<0, 8>; + using wback = ff; // TODO + + using skip_if = void; + }; + + template<> struct ldm + { + using n = bf<16, 4>; + using registers = andf, ff<0xdfffu, 16>>; // TODO + using wback = bf<21, 1>; + + using skip_if = andf>; + }; + + template<> struct ldm : ldm + { + using registers = bf<0, 16>; + + using skip_if = class TODO; + }; + + template struct ldr_imm; // + + template<> struct ldr_imm + { + using t = bf<0, 3>; + using n = bf<3, 3>; + using imm32 = cf, ff<0u, 2>>; + using index = ff; + using add = ff; + using wback = ff; + + using skip_if = void; + }; + + template<> struct ldr_imm : ldr_imm + { + using t = bf<8, 3>; + using n = ff<13u>; + using imm32 = cf, ff<0u, 2>>; + + using skip_if = void; + }; + + template<> struct ldr_imm : ldr_imm + { + using t = bf<12, 4>; + using n = bf<16, 4>; + using imm32 = bf<0, 12>; + + using skip_if = eqcf; + }; + + template<> struct ldr_imm + { + using t = bf<12, 4>; + using n = bf<16, 4>; + using imm32 = bf<0, 8>; + using index = bf<10, 1>; + using add = bf<9, 1>; + using wback = bf<8, 1>; + + using skip_if = orf, orf, 6>, andf, eqcf, 512 + 256 + 4>>>>; + }; + + template<> struct ldr_imm : ldr_imm + { + using imm32 = bf<0, 12>; + using index = bf<24, 1>; + using add = bf<23, 1>; + using wback = orf>, bf<21, 1>>; + + using skip_if = class TODO; + }; + + template struct ldr_lit; // + + template<> struct ldr_lit + { + using t = bf<8, 3>; + using imm32 = cf, ff<0u, 2>>; + using add = ff; + + using skip_if = void; + }; + + template<> struct ldr_lit + { + using t = bf<12, 4>; + using imm32 = bf<0, 12>; + using add = bf<23, 1>; + + using skip_if = void; + }; + + template<> struct ldr_lit : ldr_lit + { + using skip_if = void; + }; + + template struct ldr_reg; // + + template<> struct ldr_reg + { + using t = bf<0, 3>; + using n = bf<3, 3>; + using m = bf<6, 3>; + using index = ff; + using add = ff; + using wback = ff; + using shift_t = ff; + using shift_n = ff<0u>; + + using skip_if = void; + }; + + template<> struct ldr_reg : ldr_reg + { + using t = bf<12, 4>; + using n = bf<16, 4>; + using m = bf<0, 4>; + using shift_n = bf<4, 2>; + + using skip_if = eqcf; + }; + + template<> struct ldr_reg : ldr_reg + { + using index = bf<24, 1>; + using add = bf<23, 1>; + using wback = orf>, bf<21, 1>>; + using shift_t = decode_imm_shift_type_arm; + using shift_n = decode_imm_shift_num_arm; + + using skip_if = class TODO; + }; + + template struct ldrb_imm; // + + template<> struct ldrb_imm : ldr_imm + { + using imm32 = bf<6, 5>; + + using skip_if = void; + }; + + template<> struct ldrb_imm : ldr_imm + { + using ldr_imm::t; + using ldr_imm::n; + + using skip_if = orf, eqcf>; + }; + + template<> struct ldrb_imm : ldr_imm + { + using ldr_imm::t; + using ldr_imm::n; + + using skip_if = orf, eqcf, 4>>, orf, eqcf, 6>>>; + }; + + template<> struct ldrb_imm : ldr_imm + { + using skip_if = class TODO; + }; + + template struct ldrb_reg; // + + template<> struct ldrb_reg : ldr_reg + { + using skip_if = void; + }; + + template<> struct ldrb_reg : ldr_reg + { + using ldr_reg::t; + using ldr_reg::n; + + using skip_if = orf, eqcf>; + }; + + template<> struct ldrb_reg : ldr_reg + { + using skip_if = class TODO; + }; + + template struct ldrd_imm; // + + template<> struct ldrd_imm + { + using t = bf<12, 4>; + using t2 = bf<8, 4>; + using n = bf<16, 4>; + using imm32 = cf, ff<0u, 2>>; + using index = bf<24, 1>; + using add = bf<23, 1>; + using wback = bf<21, 1>; + }; + + template<> struct ldrd_imm : ldrd_imm + { + using t2 = orf, ff<1u, 4>>; // t+1 for even t + using imm32 = cf, bf<0, 4>>; + using wback = orf>, bf<21, 1>>; + }; + + template struct ldrd_lit; // + + template<> struct ldrd_lit + { + using t = bf<12, 4>; + using t2 = bf<8, 4>; + using imm32 = cf, ff<0u, 2>>; + using add = bf<23, 1>; + }; + + template<> struct ldrd_lit : ldrd_lit + { + using t2 = orf, ff<1u, 4>>; // t+1 for even t + using imm32 = cf, bf<0, 4>>; + }; + + template struct ldrh_imm; // + + template<> struct ldrh_imm : ldr_imm + { + using imm32 = cf, ff<0u, 1>>; + }; + + template<> struct ldrh_imm : ldr_imm {}; + template<> struct ldrh_imm : ldr_imm {}; + + template<> struct ldrh_imm : ldr_imm + { + using imm32 = cf, bf<0, 4>>; + }; + + template struct ldrh_reg; // + + template<> struct ldrh_reg : ldr_reg {}; + template<> struct ldrh_reg : ldr_reg {}; + + template<> struct ldrh_reg : ldr_reg + { + using shift_t = ff; // ??? + using shift_n = ff<0u>; + }; + + template struct ldrsb_imm; // + + template<> struct ldrsb_imm : ldr_imm {}; + template<> struct ldrsb_imm : ldr_imm {}; + template<> struct ldrsb_imm : ldrh_imm {}; + + template struct ldrex; // + + template<> struct ldrex + { + using t = bf<12, 4>; + using n = bf<16, 4>; + using imm32 = cf, ff<0u, 2>>; + }; + + template<> struct ldrex : ldrex + { + using imm32 = ff<0u>; // Zero offset + }; + + template struct _shift_imm; // + + template struct _shift_imm + { + using d = bf<0, 3>; + using m = bf<3, 3>; + using set_flags = not_in_it_block; + using shift_n = decode_imm_shift_num, bf<6, 5>>; + }; + + template struct _shift_imm + { + using d = bf<8, 4>; + using m = bf<0, 4>; + using set_flags = from_first>; + using shift_n = decode_imm_shift_num, cf, bf<6, 2>>>; + }; + + template struct _shift_imm : _shift_imm + { + using d = bf<12, 4>; + using shift_n = decode_imm_shift_num, bf<7, 5>>; + }; + + template struct lsl_imm : _shift_imm {}; // + template struct lsr_imm : _shift_imm {}; // + template struct asr_imm : _shift_imm {}; // + + template struct lsl_reg; // + + template<> struct lsl_reg + { + using d = bf<0, 3>; + using n = d; + using m = bf<3, 3>; + using set_flags = not_in_it_block; + }; + + template<> struct lsl_reg + { + using d = bf<8, 4>; + using n = bf<16, 4>; + using m = bf<0, 4>; + using set_flags = from_first>; + }; + + template<> struct lsl_reg : lsl_reg + { + using d = bf<12, 4>; + using n = bf<0, 4>; + using m = bf<8, 4>; + }; + + template struct lsr_reg; // + + template<> struct lsr_reg : lsl_reg {}; + template<> struct lsr_reg : lsl_reg {}; + template<> struct lsr_reg : lsl_reg {}; + + //template struct asr_reg; // + + //template<> struct asr_reg : lsl_reg {}; + //template<> struct asr_reg : lsl_reg {}; + //template<> struct asr_reg : lsl_reg {}; + + template struct mov_imm; // + + template<> struct mov_imm + { + using d = bf<8, 3>; + using set_flags = not_in_it_block; + using imm32 = bf<0, 8>; + using carry = from_second<>; + }; + + template<> struct mov_imm + { + using d = bf<8, 4>; + using set_flags = from_first>; + using imm32 = thumb_expand_imm; + using carry = thumb_expand_imm_c; + }; + + template<> struct mov_imm + { + using d = bf<8, 4>; + using set_flags = from_first>; + using imm32 = cf, imm12i38>; + using carry = from_second<>; + }; + + template<> struct mov_imm + { + using d = bf<12, 4>; + using set_flags = from_first>; + using imm32 = arm_expand_imm; + using carry = arm_expand_imm_c; + }; + + template<> struct mov_imm + { + using d = bf<12, 4>; + using set_flags = from_first>; + using imm32 = cf, bf<0, 12>>; + using carry = from_second<>; + }; + + template struct mov_reg; // + + template<> struct mov_reg + { + using d = cf, bf<0, 3>>; + using m = bf<3, 4>; + using set_flags = from_first>; + }; + + template<> struct mov_reg + { + using d = bf<0, 3>; + using m = bf<3, 3>; + using set_flags = from_first>; + }; + + template<> struct mov_reg + { + using d = bf<8, 4>; + using m = bf<0, 4>; + using set_flags = from_first>; + }; + + template<> struct mov_reg : mov_reg + { + using d = bf<12, 4>; + }; + + template struct movt; // + + template<> struct movt + { + using d = bf<8, 4>; + using imm16 = cf, imm12i38>; + }; + + template<> struct movt + { + using d = bf<12, 4>; + using imm16 = cf, bf<0, 12>>; + }; + + template struct mul; // + + template<> struct mul + { + using d = bf<0, 3>; + using n = bf<3, 3>; + using m = d; + using set_flags = not_in_it_block; + }; + + template<> struct mul + { + using d = bf<8, 4>; + using n = bf<16, 4>; + using m = bf<0, 4>; + using set_flags = from_first>; + }; + + template<> struct mul + { + using d = bf<16, 4>; + using n = bf<0, 4>; + using m = bf<8, 4>; + using set_flags = from_first>; + }; + + template struct mvn_imm; // + + template<> struct mvn_imm : mov_imm {}; + template<> struct mvn_imm : mov_imm {}; + + template struct mvn_reg; // + + template<> struct mvn_reg + { + using d = bf<0, 3>; + using m = bf<3, 3>; + using set_flags = not_in_it_block; + using shift_t = ff; + using shift_n = ff<0u>; + }; + + template<> struct mvn_reg + { + using d = bf<8, 4>; + using m = bf<0, 4>; + using set_flags = from_first>; + using shift_t = decode_imm_shift_type_thumb; + using shift_n = decode_imm_shift_num_thumb; + }; + + template<> struct mvn_reg : mvn_reg + { + using d = bf<12, 4>; + using shift_t = decode_imm_shift_type_arm; + using shift_n = decode_imm_shift_num_arm; + }; + + template struct orr_imm; // + + template<> struct orr_imm : and_imm {}; + template<> struct orr_imm : and_imm {}; + + template struct orr_reg; // + + template<> struct orr_reg : adc_reg {}; + template<> struct orr_reg : adc_reg {}; + template<> struct orr_reg : adc_reg {}; + + template struct pop; // + + template<> struct pop + { + using registers = cf, ff<0u, 7>, bf<0, 8>>; + }; + + template<> struct pop + { + using registers = andf, ff<0xdfffu, 16>>; + }; + + template<> struct pop + { + using registers = shlf, bf<12, 4>>; // 1 << Rt + }; + + template<> struct pop + { + using registers = bf<0, 16>; + }; + + template<> struct pop : pop + { + }; + + template struct push; // + + template<> struct push + { + using registers = cf, ff<0u, 6>, bf<0, 8>>; + }; + + template<> struct push + { + using registers = andf, ff<0x5fffu, 16>>; + }; + + template<> struct push : pop {}; + template<> struct push : pop {}; + template<> struct push : pop {}; + + template struct rev; // + + template<> struct rev + { + using d = bf<0, 3>; + using m = bf<3, 3>; + }; + + template<> struct rev : clz {}; + template<> struct rev : clz {}; + + template struct ror_imm; // + + template<> struct ror_imm : _shift_imm {}; + template<> struct ror_imm : _shift_imm {}; + + template struct ror_reg; // + + template<> struct ror_reg : lsl_reg {}; + template<> struct ror_reg : lsl_reg {}; + template<> struct ror_reg : lsl_reg {}; + + template struct rsb_imm; // + + template<> struct rsb_imm : add_imm + { + using imm32 = ff<0u>; + }; + + template<> struct rsb_imm : add_imm {}; + template<> struct rsb_imm : add_imm {}; + + template struct stm; // + + template<> struct stm : ldm + { + using wback = ff; + }; + + template<> struct stm : ldm + { + using registers = andf, ff<0x5fffu, 16>>; // TODO + }; + + template<> struct stm : ldm {}; + + template struct str_imm; // + + template<> struct str_imm : ldr_imm {}; + template<> struct str_imm : ldr_imm {}; + template<> struct str_imm : ldr_imm {}; + template<> struct str_imm : ldr_imm {}; + template<> struct str_imm : ldr_imm {}; + + template struct str_reg; // + + template<> struct str_reg : ldr_reg {}; + template<> struct str_reg : ldr_reg {}; + template<> struct str_reg : ldr_reg {}; + + template struct strb_imm; // + + template<> struct strb_imm : ldrb_imm {}; + template<> struct strb_imm : ldrb_imm {}; + template<> struct strb_imm : ldrb_imm {}; + template<> struct strb_imm : ldrb_imm {}; + + template struct strb_reg; // + + template<> struct strb_reg : ldrb_reg {}; + template<> struct strb_reg : ldrb_reg {}; + template<> struct strb_reg : ldrb_reg {}; + + template struct strd_imm; // + + template<> struct strd_imm : ldrd_imm {}; + template<> struct strd_imm : ldrd_imm {}; + + template struct strh_imm; // + + template<> struct strh_imm : ldrh_imm {}; + template<> struct strh_imm : ldrh_imm {}; + template<> struct strh_imm : ldrh_imm {}; + template<> struct strh_imm : ldrh_imm {}; + + template struct strh_reg; // + + template<> struct strh_reg : ldrh_reg {}; + template<> struct strh_reg : ldrh_reg {}; + template<> struct strh_reg : ldrh_reg {}; + + template struct strex; // + + template<> struct strex + { + using d = bf<8, 4>; + using t = bf<12, 4>; + using n = bf<16, 4>; + using imm32 = cf, ff<0u, 2>>; + }; + + template<> struct strex + { + using d = bf<12, 4>; + using t = bf<0, 4>; + using n = bf<16, 4>; + using imm32 = ff<0u>; // Zero offset + }; + + template struct sub_imm; // + + template<> struct sub_imm : add_imm {}; + template<> struct sub_imm : add_imm {}; + template<> struct sub_imm : add_imm {}; + template<> struct sub_imm : add_imm {}; + template<> struct sub_imm : add_imm {}; + + template struct sub_reg; // + + template<> struct sub_reg : add_reg {}; + template<> struct sub_reg : add_reg {}; + template<> struct sub_reg : add_reg {}; + + template struct sub_spi; // + + template<> struct sub_spi : add_spi {}; + template<> struct sub_spi : add_spi {}; + template<> struct sub_spi : add_spi {}; + template<> struct sub_spi : add_spi {}; + + template struct tst_imm; // + + template<> struct tst_imm + { + using n = bf<16, 4>; + using imm32 = thumb_expand_imm; + using carry = thumb_expand_imm_c; + }; + + template<> struct tst_imm + { + using n = bf<16, 4>; + using imm32 = arm_expand_imm; + using carry = arm_expand_imm_c; + }; + + template struct umull; // + + template<> struct umull + { + using d0 = bf<12, 4>; + using d1 = bf<8, 4>; + using n = bf<16, 4>; + using m = bf<0, 4>; + using set_flags = from_first>; + }; + + template<> struct umull + { + using d0 = bf<12, 4>; + using d1 = bf<16, 4>; + using n = bf<0, 4>; + using m = bf<8, 4>; + using set_flags = from_first>; + }; + + template struct uxtb; // + + template<> struct uxtb + { + using d = bf<0, 3>; + using m = bf<3, 3>; + using rotation = ff<0u, 5>; + }; + + template<> struct uxtb + { + using d = bf<8, 4>; + using m = bf<0, 4>; + using rotation = cf, ff<0u, 3>>; + }; + + template<> struct uxtb + { + using d = bf<12, 4>; + using m = bf<0, 4>; + using rotation = cf, ff<0u, 3>>; + }; } -static const ARMv7_Instruction g_table_0xf_main[] = -{ - { group_0xf0 }, // 0 0xfbef - { group_0xf1 }, // 1 0xfbef - { group_0xf2 }, // 2 0xfbff - { group_0xf3 }, // 3 0xffff - ARMv7_NULL_OP, // 4 - ARMv7_NULL_OP, // 5 - ARMv7_NULL_OP, // 6 - ARMv7_NULL_OP, // 7 - { group_0xf8 }, // 8 0xfff0 - { group_0xf9 }, // 9 0xfff0 - { group_0xfa }, // A 0xfff0 +// TODO +#define SKIP_IF(cond) [](u32 c) -> bool { return cond; } +#define BF(start, end) ((c << (31 - (end))) >> ((start) + 31 - (end))) +#define BT(pos) ((c >> (pos)) & 1) +// ARMv7 decoder object. D provides function templates. T is function pointer type returned. +template +class arm_decoder +{ + // Fast lookup table for 2-byte Thumb instructions + std::array m_op16_table{}; + + // Fix for std::initializer_list (???) + static inline T fix(T ptr) + { + return ptr; + } + + struct instruction_info + { + u32 mask; + u32 code; + T pointer; + bool(*skip)(u32 code); // TODO (if not nullptr, must be specified yet) + + bool match(u32 op) const + { + return (op & mask) == code && (!skip || !skip(op)); + } + }; + + // Lookup table for 4-byte Thumb instructions (points to the best appropriate position in sorted vector) + std::array::const_iterator, 0x10000> m_op32_table{}; + + std::vector m_op16_list; + std::vector m_op32_list; + std::vector m_arm_list; + +public: + arm_decoder() + { + using namespace arm_code::arm_encoding_alias; + + m_op16_list.assign( + { + { 0xffc0, 0x4140, fix(&D:: template ADC_REG), nullptr }, + { 0xfe00, 0x1c00, fix(&D:: template ADD_IMM), nullptr }, + { 0xf800, 0x3000, fix(&D:: template ADD_IMM), nullptr }, + { 0xfe00, 0x1800, fix(&D:: template ADD_REG), nullptr }, + { 0xff00, 0x4400, fix(&D:: template ADD_REG), SKIP_IF((c & 0x87) == 0x85 || BF(3, 6) == 13) }, + { 0xf800, 0xa800, fix(&D:: template ADD_SPI), nullptr }, + { 0xff80, 0xb000, fix(&D:: template ADD_SPI), nullptr }, + { 0xff78, 0x4468, fix(&D:: template ADD_SPR), nullptr }, + { 0xff87, 0x4485, fix(&D:: template ADD_SPR), SKIP_IF(BF(3, 6) == 13) }, + { 0xf800, 0xa000, fix(&D:: template ADR), nullptr }, + { 0xffc0, 0x4000, fix(&D:: template AND_REG), nullptr }, + { 0xf800, 0x1000, fix(&D:: template ASR_IMM), nullptr }, + { 0xffc0, 0x4100, fix(&D:: template ASR_REG), nullptr }, + { 0xf000, 0xd000, fix(&D:: template B), SKIP_IF(BF(9, 11) == 0x7) }, + { 0xf800, 0xe000, fix(&D:: template B), nullptr }, + { 0xffc0, 0x4380, fix(&D:: template BIC_REG), nullptr }, + { 0xff00, 0xbe00, fix(&D:: template BKPT), nullptr }, + { 0xff80, 0x4780, fix(&D:: template BLX), nullptr }, + { 0xff87, 0x4700, fix(&D:: template BX), nullptr }, + { 0xf500, 0xb100, fix(&D:: template CB_Z), nullptr }, + { 0xffc0, 0x42c0, fix(&D:: template CMN_REG), nullptr }, + { 0xf800, 0x2800, fix(&D:: template CMP_IMM), nullptr }, + { 0xffc0, 0x4280, fix(&D:: template CMP_REG), nullptr }, + { 0xff00, 0x4500, fix(&D:: template CMP_REG), nullptr }, + { 0xffc0, 0x4040, fix(&D:: template EOR_REG), nullptr }, + { 0xff00, 0xbf00, fix(&D:: template IT), SKIP_IF(BF(0, 3) == 0) }, + { 0xf800, 0xc800, fix(&D:: template LDM), nullptr }, + { 0xf800, 0x6800, fix(&D:: template LDR_IMM), nullptr }, + { 0xf800, 0x9800, fix(&D:: template LDR_IMM), nullptr }, + { 0xf800, 0x4800, fix(&D:: template LDR_LIT), nullptr }, + { 0xfe00, 0x5800, fix(&D:: template LDR_REG), nullptr }, + { 0xf800, 0x7800, fix(&D:: template LDRB_IMM) }, + { 0xfe00, 0x5c00, fix(&D:: template LDRB_REG) }, + { 0xf800, 0x8800, fix(&D:: template LDRH_IMM) }, + { 0xfe00, 0x5a00, fix(&D:: template LDRH_REG) }, + { 0xfe00, 0x5600, fix(&D:: template LDRSB_REG) }, + { 0xfe00, 0x5e00, fix(&D:: template LDRSH_REG) }, + { 0xf800, 0x0000, fix(&D:: template LSL_IMM) }, + { 0xffc0, 0x4080, fix(&D:: template LSL_REG) }, + { 0xf800, 0x0800, fix(&D:: template LSR_IMM) }, + { 0xffc0, 0x40c0, fix(&D:: template LSR_REG) }, + { 0xf800, 0x2000, fix(&D:: template MOV_IMM) }, + { 0xff00, 0x4600, fix(&D:: template MOV_REG) }, + { 0xffc0, 0x0000, fix(&D:: template MOV_REG) }, + { 0xffc0, 0x4340, fix(&D:: template MUL) }, + { 0xffc0, 0x43c0, fix(&D:: template MVN_REG) }, + { 0xffff, 0xbf00, fix(&D:: template NOP) }, + { 0xffc0, 0x4300, fix(&D:: template ORR_REG) }, + { 0xfe00, 0xbc00, fix(&D:: template POP) }, + { 0xfe00, 0xb400, fix(&D:: template PUSH) }, + { 0xffc0, 0xba00, fix(&D:: template REV) }, + { 0xffc0, 0xba40, fix(&D:: template REV16) }, + { 0xffc0, 0xbac0, fix(&D:: template REVSH) }, + { 0xffc0, 0x41c0, fix(&D:: template ROR_REG) }, + { 0xffc0, 0x4240, fix(&D:: template RSB_IMM) }, + { 0xffc0, 0x4180, fix(&D:: template SBC_REG) }, + { 0xf800, 0xc000, fix(&D:: template STM) }, + { 0xf800, 0x6000, fix(&D:: template STR_IMM) }, + { 0xf800, 0x9000, fix(&D:: template STR_IMM) }, + { 0xfe00, 0x5000, fix(&D:: template STR_REG) }, + { 0xf800, 0x7000, fix(&D:: template STRB_IMM) }, + { 0xfe00, 0x5400, fix(&D:: template STRB_REG) }, + { 0xf800, 0x8000, fix(&D:: template STRH_IMM) }, + { 0xfe00, 0x5200, fix(&D:: template STRH_REG) }, + { 0xfe00, 0x1e00, fix(&D:: template SUB_IMM) }, + { 0xf800, 0x3800, fix(&D:: template SUB_IMM) }, + { 0xfe00, 0x1a00, fix(&D:: template SUB_REG) }, + { 0xff80, 0xb080, fix(&D:: template SUB_SPI) }, + { 0xff00, 0xdf00, fix(&D:: template SVC) }, + { 0xffc0, 0xb240, fix(&D:: template SXTB) }, + { 0xffc0, 0xb200, fix(&D:: template SXTH) }, + { 0xffc0, 0x4200, fix(&D:: template TST_REG) }, + { 0xffc0, 0xb2c0, fix(&D:: template UXTB) }, + { 0xffc0, 0xb280, fix(&D:: template UXTH) }, + { 0xffff, 0xbf20, fix(&D:: template WFE) }, + { 0xffff, 0xbf30, fix(&D:: template WFI) }, + { 0xffff, 0xbf10, fix(&D:: template YIELD) }, + }); + + m_op32_list.assign( + { + { 0xffff0000, 0xf8700000, fix(&D:: template HACK), nullptr }, // "Undefined" Thumb opcode used + { 0xfbe08000, 0xf1400000, fix(&D:: template ADC_IMM), nullptr }, + { 0xffe08000, 0xeb400000, fix(&D:: template ADC_REG), nullptr }, + { 0xfbe08000, 0xf1000000, fix(&D:: template ADD_IMM), SKIP_IF((BF(8, 11) == 15 && BT(20)) || BF(16, 19) == 13) }, + { 0xfbf08000, 0xf2000000, fix(&D:: template ADD_IMM), SKIP_IF((BF(16, 19) & 13) == 13) }, + { 0xffe08000, 0xeb000000, fix(&D:: template ADD_REG), SKIP_IF((BF(8, 11) == 15 && BT(20)) || BF(16, 19) == 13) }, + { 0xfbef8000, 0xf10d0000, fix(&D:: template ADD_SPI), SKIP_IF(BF(8, 11) == 15 && BT(20)) }, + { 0xfbff8000, 0xf20d0000, fix(&D:: template ADD_SPI), nullptr }, + { 0xffef8000, 0xeb0d0000, fix(&D:: template ADD_SPR), nullptr }, + { 0xfbff8000, 0xf2af0000, fix(&D:: template ADR), nullptr }, + { 0xfbff8000, 0xf20f0000, fix(&D:: template ADR), nullptr }, + { 0xfbe08000, 0xf0000000, fix(&D:: template AND_IMM), SKIP_IF(BF(8, 11) == 15 && BT(20)) }, + { 0xffe08000, 0xea000000, fix(&D:: template AND_REG), SKIP_IF(BF(8, 11) == 15 && BT(20)) }, + { 0xffef8030, 0xea4f0020, fix(&D:: template ASR_IMM), nullptr }, + { 0xffe0f0f0, 0xfa40f000, fix(&D:: template ASR_REG), nullptr }, + { 0xf800d000, 0xf0008000, fix(&D:: template B), SKIP_IF(BF(23, 25) == 0x7) }, + { 0xf800d000, 0xf0009000, fix(&D:: template B), nullptr }, + { 0xffff8020, 0xf36f0000, fix(&D:: template BFC), nullptr }, + { 0xfff08020, 0xf3600000, fix(&D:: template BFI), SKIP_IF(BF(16, 19) == 15) }, + { 0xfbe08000, 0xf0200000, fix(&D:: template BIC_IMM), nullptr }, + { 0xffe08000, 0xea200000, fix(&D:: template BIC_REG), nullptr }, + { 0xf800d000, 0xf000d000, fix(&D:: template BL), nullptr }, + { 0xf800c001, 0xf000c000, fix(&D:: template BL), nullptr }, + { 0xfff0f0f0, 0xfab0f080, fix(&D:: template CLZ), nullptr }, + { 0xfbf08f00, 0xf1100f00, fix(&D:: template CMN_IMM), nullptr }, + { 0xfff08f00, 0xeb100f00, fix(&D:: template CMN_REG), nullptr }, + { 0xfbf08f00, 0xf1b00f00, fix(&D:: template CMP_IMM), nullptr }, + { 0xfff08f00, 0xebb00f00, fix(&D:: template CMP_REG), nullptr }, + { 0xfffffff0, 0xf3af80f0, fix(&D:: template DBG), nullptr }, + { 0xfffffff0, 0xf3bf8f50, fix(&D:: template DMB), nullptr }, + { 0xfffffff0, 0xf3bf8f40, fix(&D:: template DSB), nullptr }, + { 0xfbe08000, 0xf0800000, fix(&D:: template EOR_IMM), SKIP_IF(BF(8, 11) == 15 && BT(20)) }, + { 0xffe08000, 0xea800000, fix(&D:: template EOR_REG), SKIP_IF(BF(8, 11) == 15 && BT(20)) }, + { 0xffd02000, 0xe8900000, fix(&D:: template LDM), SKIP_IF(BT(21) && BF(16, 19) == 13) }, + { 0xffd02000, 0xe9100000, fix(&D:: template LDMDB), nullptr }, + { 0xfff00000, 0xf8d00000, fix(&D:: template LDR_IMM), SKIP_IF(BF(16, 19) == 15) }, + { 0xfff00800, 0xf8500800, fix(&D:: template LDR_IMM), SKIP_IF(BF(16, 19) == 15 || BF(8, 10) == 6 || (c & 0xf07ff) == 0xd0304 || (c & 0x500) == 0) }, + { 0xff7f0000, 0xf85f0000, fix(&D:: template LDR_LIT), nullptr }, + { 0xfff00fc0, 0xf8500000, fix(&D:: template LDR_REG), SKIP_IF(BF(16, 19) == 15) }, + { 0xfff00000, 0xf8900000, fix(&D:: template LDRB_IMM) }, + { 0xfff00800, 0xf8100800, fix(&D:: template LDRB_IMM) }, + { 0xff7f0000, 0xf81f0000, fix(&D:: template LDRB_LIT) }, + { 0xfff00fc0, 0xf8100000, fix(&D:: template LDRB_REG) }, + { 0xfe500000, 0xe8500000, fix(&D:: template LDRD_IMM), SKIP_IF((!BT(21) && !BT(24)) || BF(16, 19) == 15) }, + { 0xfe7f0000, 0xe85f0000, fix(&D:: template LDRD_LIT) }, + { 0xfff00f00, 0xe8500f00, fix(&D:: template LDREX) }, + { 0xfff00fff, 0xe8d00f4f, fix(&D:: template LDREXB) }, + { 0xfff000ff, 0xe8d0007f, fix(&D:: template LDREXD) }, + { 0xfff00fff, 0xe8d00f5f, fix(&D:: template LDREXH) }, + { 0xfff00000, 0xf8b00000, fix(&D:: template LDRH_IMM) }, + { 0xfff00800, 0xf8300800, fix(&D:: template LDRH_IMM) }, + { 0xff7f0000, 0xf83f0000, fix(&D:: template LDRH_LIT) }, + { 0xfff00fc0, 0xf8300000, fix(&D:: template LDRH_REG) }, + { 0xfff00000, 0xf9900000, fix(&D:: template LDRSB_IMM) }, + { 0xfff00800, 0xf9100800, fix(&D:: template LDRSB_IMM) }, + { 0xff7f0000, 0xf91f0000, fix(&D:: template LDRSB_LIT) }, + { 0xfff00fc0, 0xf9100000, fix(&D:: template LDRSB_REG) }, + { 0xfff00000, 0xf9b00000, fix(&D:: template LDRSH_IMM) }, + { 0xfff00800, 0xf9300800, fix(&D:: template LDRSH_IMM) }, + { 0xff7f0000, 0xf93f0000, fix(&D:: template LDRSH_LIT) }, + { 0xfff00fc0, 0xf9300000, fix(&D:: template LDRSH_REG) }, + { 0xffef8030, 0xea4f0000, fix(&D:: template LSL_IMM) }, + { 0xffe0f0f0, 0xfa00f000, fix(&D:: template LSL_REG) }, + { 0xffef8030, 0xea4f0010, fix(&D:: template LSR_IMM) }, + { 0xffe0f0f0, 0xfa20f000, fix(&D:: template LSR_REG) }, + { 0xfff000f0, 0xfb000000, fix(&D:: template MLA), SKIP_IF(BF(12, 15) == 15) }, + { 0xfff000f0, 0xfb000010, fix(&D:: template MLS) }, + { 0xfbef8000, 0xf04f0000, fix(&D:: template MOV_IMM) }, + { 0xfbf08000, 0xf2400000, fix(&D:: template MOV_IMM) }, + { 0xffeff0f0, 0xea4f0000, fix(&D:: template MOV_REG) }, + { 0xfbf08000, 0xf2c00000, fix(&D:: template MOVT) }, + { 0xff100010, 0xee100010, fix(&D:: template MRC_) }, + { 0xff100010, 0xfe100010, fix(&D:: template MRC_) }, + { 0xfffff0ff, 0xf3ef8000, fix(&D:: template MRS) }, + { 0xfff0f3ff, 0xf3808000, fix(&D:: template MSR_REG) }, + { 0xfff0f0f0, 0xfb00f000, fix(&D:: template MUL) }, + { 0xfbef8000, 0xf06f0000, fix(&D:: template MVN_IMM) }, + { 0xffef8000, 0xea6f0000, fix(&D:: template MVN_REG) }, + { 0xffffffff, 0xf3af8000, fix(&D:: template NOP) }, + { 0xfbe08000, 0xf0600000, fix(&D:: template ORN_IMM) }, + { 0xffe08000, 0xea600000, fix(&D:: template ORN_REG) }, + { 0xfbe08000, 0xf0400000, fix(&D:: template ORR_IMM) }, + { 0xffe08000, 0xea400000, fix(&D:: template ORR_REG), SKIP_IF(BF(16, 19) == 15) }, + { 0xfff08010, 0xeac00000, fix(&D:: template PKH) }, + { 0xffff0000, 0xe8bd0000, fix(&D:: template POP) }, + { 0xffff0fff, 0xf85d0b04, fix(&D:: template POP) }, + { 0xffff0000, 0xe92d0000, fix(&D:: template PUSH) }, // had an error in arch ref + { 0xffff0fff, 0xf84d0d04, fix(&D:: template PUSH) }, + { 0xfff0f0f0, 0xfa80f080, fix(&D:: template QADD) }, + { 0xfff0f0f0, 0xfa90f010, fix(&D:: template QADD16) }, + { 0xfff0f0f0, 0xfa80f010, fix(&D:: template QADD8) }, + { 0xfff0f0f0, 0xfaa0f010, fix(&D:: template QASX) }, + { 0xfff0f0f0, 0xfa80f090, fix(&D:: template QDADD) }, + { 0xfff0f0f0, 0xfa80f0b0, fix(&D:: template QDSUB) }, + { 0xfff0f0f0, 0xfae0f010, fix(&D:: template QSAX) }, + { 0xfff0f0f0, 0xfa80f0a0, fix(&D:: template QSUB) }, + { 0xfff0f0f0, 0xfad0f010, fix(&D:: template QSUB16) }, + { 0xfff0f0f0, 0xfac0f010, fix(&D:: template QSUB8) }, + { 0xfff0f0f0, 0xfa90f0a0, fix(&D:: template RBIT) }, + { 0xfff0f0f0, 0xfa90f080, fix(&D:: template REV) }, + { 0xfff0f0f0, 0xfa90f090, fix(&D:: template REV16) }, + { 0xfff0f0f0, 0xfa90f0b0, fix(&D:: template REVSH) }, + { 0xffef8030, 0xea4f0030, fix(&D:: template ROR_IMM) }, + { 0xffe0f0f0, 0xfa60f000, fix(&D:: template ROR_REG) }, + { 0xffeff0f0, 0xea4f0030, fix(&D:: template RRX) }, + { 0xfbe08000, 0xf1c00000, fix(&D:: template RSB_IMM) }, + { 0xffe08000, 0xebc00000, fix(&D:: template RSB_REG) }, + { 0xfff0f0f0, 0xfa90f000, fix(&D:: template SADD16) }, + { 0xfff0f0f0, 0xfa80f000, fix(&D:: template SADD8) }, + { 0xfff0f0f0, 0xfaa0f000, fix(&D:: template SASX) }, + { 0xfbe08000, 0xf1600000, fix(&D:: template SBC_IMM) }, + { 0xffe08000, 0xeb600000, fix(&D:: template SBC_REG) }, + { 0xfff08020, 0xf3400000, fix(&D:: template SBFX) }, + { 0xfff0f0f0, 0xfb90f0f0, fix(&D:: template SDIV) }, // ??? + { 0xfff0f0f0, 0xfaa0f080, fix(&D:: template SEL) }, + { 0xfff0f0f0, 0xfa90f020, fix(&D:: template SHADD16) }, + { 0xfff0f0f0, 0xfa80f020, fix(&D:: template SHADD8) }, + { 0xfff0f0f0, 0xfaa0f020, fix(&D:: template SHASX) }, + { 0xfff0f0f0, 0xfae0f020, fix(&D:: template SHSAX) }, + { 0xfff0f0f0, 0xfad0f020, fix(&D:: template SHSUB16) }, + { 0xfff0f0f0, 0xfac0f020, fix(&D:: template SHSUB8) }, + { 0xfff000c0, 0xfb100000, fix(&D:: template SMLA__) }, + { 0xfff000e0, 0xfb200000, fix(&D:: template SMLAD) }, + { 0xfff000f0, 0xfbc00000, fix(&D:: template SMLAL) }, + { 0xfff000c0, 0xfbc00080, fix(&D:: template SMLAL__) }, + { 0xfff000e0, 0xfbc000c0, fix(&D:: template SMLALD) }, + { 0xfff000e0, 0xfb300000, fix(&D:: template SMLAW_) }, + { 0xfff000e0, 0xfb400000, fix(&D:: template SMLSD) }, + { 0xfff000e0, 0xfbd000c0, fix(&D:: template SMLSLD) }, + { 0xfff000e0, 0xfb500000, fix(&D:: template SMMLA) }, + { 0xfff000e0, 0xfb600000, fix(&D:: template SMMLS) }, + { 0xfff0f0e0, 0xfb50f000, fix(&D:: template SMMUL) }, + { 0xfff0f0e0, 0xfb20f000, fix(&D:: template SMUAD) }, + { 0xfff0f0c0, 0xfb10f000, fix(&D:: template SMUL__) }, + { 0xfff000f0, 0xfb800000, fix(&D:: template SMULL) }, + { 0xfff0f0e0, 0xfb30f000, fix(&D:: template SMULW_) }, + { 0xfff0f0e0, 0xfb40f000, fix(&D:: template SMUSD) }, + { 0xffd08020, 0xf3000000, fix(&D:: template SSAT) }, + { 0xfff0f0e0, 0xf3200000, fix(&D:: template SSAT16) }, + { 0xfff0f0f0, 0xfae0f000, fix(&D:: template SSAX) }, + { 0xfff0f0f0, 0xfad0f000, fix(&D:: template SSUB16) }, + { 0xfff0f0f0, 0xfac0f000, fix(&D:: template SSUB8) }, + { 0xffd0a000, 0xe8800000, fix(&D:: template STM) }, + { 0xffd0a000, 0xe9000000, fix(&D:: template STMDB) }, + { 0xfff00000, 0xf8c00000, fix(&D:: template STR_IMM) }, + { 0xfff00800, 0xf8400800, fix(&D:: template STR_IMM) }, + { 0xfff00fc0, 0xf8400000, fix(&D:: template STR_REG) }, + { 0xfff00000, 0xf8800000, fix(&D:: template STRB_IMM) }, + { 0xfff00800, 0xf8000800, fix(&D:: template STRB_IMM) }, + { 0xfff00fc0, 0xf8000000, fix(&D:: template STRB_REG) }, + { 0xfe500000, 0xe8400000, fix(&D:: template STRD_IMM), SKIP_IF(!BT(21) && !BT(24)) }, + { 0xfff00000, 0xe8400000, fix(&D:: template STREX) }, + { 0xfff00ff0, 0xe8c00f40, fix(&D:: template STREXB) }, + { 0xfff000f0, 0xe8c00070, fix(&D:: template STREXD) }, + { 0xfff00ff0, 0xe8c00f50, fix(&D:: template STREXH) }, + { 0xfff00000, 0xf8a00000, fix(&D:: template STRH_IMM) }, + { 0xfff00800, 0xf8200800, fix(&D:: template STRH_IMM) }, + { 0xfff00fc0, 0xf8200000, fix(&D:: template STRH_REG) }, + { 0xfbe08000, 0xf1a00000, fix(&D:: template SUB_IMM), SKIP_IF((BF(8, 11) == 15 && BT(20)) || BF(16, 19) == 13) }, + { 0xfbf08000, 0xf2a00000, fix(&D:: template SUB_IMM) }, + { 0xffe08000, 0xeba00000, fix(&D:: template SUB_REG), SKIP_IF((BF(8, 11) == 15 && BT(20)) || BF(16, 19) == 13) }, + { 0xfbef8000, 0xf1ad0000, fix(&D:: template SUB_SPI) }, + { 0xfbff8000, 0xf2ad0000, fix(&D:: template SUB_SPI) }, + { 0xffef8000, 0xebad0000, fix(&D:: template SUB_SPR) }, + { 0xfff0f0c0, 0xfa40f080, fix(&D:: template SXTAB) }, + { 0xfff0f0c0, 0xfa20f080, fix(&D:: template SXTAB16) }, + { 0xfff0f0c0, 0xfa00f080, fix(&D:: template SXTAH) }, + { 0xfffff0c0, 0xfa4ff080, fix(&D:: template SXTB) }, + { 0xfffff0c0, 0xfa2ff080, fix(&D:: template SXTB16) }, + { 0xfffff0c0, 0xfa0ff080, fix(&D:: template SXTH) }, + { 0xfff0ffe0, 0xe8d0f000, fix(&D:: template TB_) }, + { 0xfbf08f00, 0xf0900f00, fix(&D:: template TEQ_IMM) }, + { 0xfff08f00, 0xea900f00, fix(&D:: template TEQ_REG) }, + { 0xfbf08f00, 0xf0100f00, fix(&D:: template TST_IMM) }, + { 0xfff08f00, 0xea100f00, fix(&D:: template TST_REG) }, + { 0xfff0f0f0, 0xfa90f040, fix(&D:: template UADD16) }, + { 0xfff0f0f0, 0xfa80f040, fix(&D:: template UADD8) }, + { 0xfff0f0f0, 0xfaa0f040, fix(&D:: template UASX) }, + { 0xfff08020, 0xf3c00000, fix(&D:: template UBFX) }, + { 0xfff0f0f0, 0xfbb0f0f0, fix(&D:: template UDIV) }, // ??? + { 0xfff0f0f0, 0xfa90f060, fix(&D:: template UHADD16) }, + { 0xfff0f0f0, 0xfa80f060, fix(&D:: template UHADD8) }, + { 0xfff0f0f0, 0xfaa0f060, fix(&D:: template UHASX) }, + { 0xfff0f0f0, 0xfae0f060, fix(&D:: template UHSAX) }, + { 0xfff0f0f0, 0xfad0f060, fix(&D:: template UHSUB16) }, + { 0xfff0f0f0, 0xfac0f060, fix(&D:: template UHSUB8) }, + { 0xfff000f0, 0xfbe00060, fix(&D:: template UMAAL) }, + { 0xfff000f0, 0xfbe00000, fix(&D:: template UMLAL) }, + { 0xfff000f0, 0xfba00000, fix(&D:: template UMULL) }, + { 0xfff0f0f0, 0xfa90f050, fix(&D:: template UQADD16) }, + { 0xfff0f0f0, 0xfa80f050, fix(&D:: template UQADD8) }, + { 0xfff0f0f0, 0xfaa0f050, fix(&D:: template UQASX) }, + { 0xfff0f0f0, 0xfae0f050, fix(&D:: template UQSAX) }, + { 0xfff0f0f0, 0xfad0f050, fix(&D:: template UQSUB16) }, + { 0xfff0f0f0, 0xfac0f050, fix(&D:: template UQSUB8) }, + { 0xfff0f0f0, 0xfb70f000, fix(&D:: template USAD8) }, + { 0xfff000f0, 0xfb700000, fix(&D:: template USADA8) }, + { 0xffd08020, 0xf3800000, fix(&D:: template USAT) }, + { 0xfff0f0e0, 0xf3a00000, fix(&D:: template USAT16) }, + { 0xfff0f0f0, 0xfae0f040, fix(&D:: template USAX) }, + { 0xfff0f0f0, 0xfad0f040, fix(&D:: template USUB16) }, + { 0xfff0f0f0, 0xfac0f040, fix(&D:: template USUB8) }, + { 0xfff0f0c0, 0xfa50f080, fix(&D:: template UXTAB), SKIP_IF(BF(16, 19) == 15) }, + { 0xfff0f0c0, 0xfa30f080, fix(&D:: template UXTAB16) }, + { 0xfff0f0c0, 0xfa10f080, fix(&D:: template UXTAH) }, + { 0xfffff0c0, 0xfa5ff080, fix(&D:: template UXTB) }, + { 0xfffff0c0, 0xfa3ff080, fix(&D:: template UXTB16) }, + { 0xfffff0c0, 0xfa1ff080, fix(&D:: template UXTH) }, + { 0xef800f10, 0xef000710, fix(&D:: template VABA_) }, + { 0xef800f50, 0xef800500, fix(&D:: template VABA_) }, + { 0xef800f10, 0xef000700, fix(&D:: template VABD_) }, + { 0xef800f50, 0xef800700, fix(&D:: template VABD_) }, + { 0xffa00f10, 0xff200d00, fix(&D:: template VABD_FP) }, + { 0xffb30b90, 0xffb10300, fix(&D:: template VABS) }, + { 0xffbf0ed0, 0xeeb00ac0, fix(&D:: template VABS) }, + { 0xff800f10, 0xff000e10, fix(&D:: template VAC__) }, + { 0xff800f10, 0xef000800, fix(&D:: template VADD) }, + { 0xffa00f10, 0xef000d00, fix(&D:: template VADD_FP) }, + { 0xffb00e50, 0xee300a00, fix(&D:: template VADD_FP) }, + { 0xff800f50, 0xef800400, fix(&D:: template VADDHN) }, + { 0xef800e50, 0xef800000, fix(&D:: template VADD_) }, + { 0xffb00f10, 0xef000110, fix(&D:: template VAND) }, + { 0xefb800b0, 0xef800030, fix(&D:: template VBIC_IMM) }, + { 0xffb00f10, 0xef100110, fix(&D:: template VBIC_REG) }, + { 0xff800f10, 0xff000110, fix(&D:: template VB__) }, + { 0xff800f10, 0xff000810, fix(&D:: template VCEQ_REG) }, + { 0xffa00f10, 0xef000e00, fix(&D:: template VCEQ_REG) }, + { 0xffb30b90, 0xffb10100, fix(&D:: template VCEQ_ZERO) }, + { 0xef800f10, 0xef000310, fix(&D:: template VCGE_REG) }, + { 0xffa00f10, 0xff000e00, fix(&D:: template VCGE_REG) }, + { 0xffb30b90, 0xffb10080, fix(&D:: template VCGE_ZERO) }, + { 0xef800f10, 0xef000300, fix(&D:: template VCGT_REG) }, + { 0xffa00f10, 0xff200e00, fix(&D:: template VCGT_REG) }, + { 0xffb30b90, 0xffb10000, fix(&D:: template VCGT_ZERO) }, + { 0xffb30b90, 0xffb10180, fix(&D:: template VCLE_ZERO) }, + { 0xffb30f90, 0xffb00400, fix(&D:: template VCLS) }, + { 0xffb30b90, 0xffb10200, fix(&D:: template VCLT_ZERO) }, + { 0xffb30f90, 0xffb00480, fix(&D:: template VCLZ) }, + { 0xffbf0e50, 0xeeb40a40, fix(&D:: template VCMP_) }, + { 0xffbf0e7f, 0xeeb50a40, fix(&D:: template VCMP_) }, + { 0xffb30f90, 0xffb00500, fix(&D:: template VCNT) }, + { 0xffb30e10, 0xffb30600, fix(&D:: template VCVT_FIA) }, + { 0xffb80e50, 0xeeb80a40, fix(&D:: template VCVT_FIF) }, + { 0xef800e90, 0xef800e10, fix(&D:: template VCVT_FFA) }, + { 0xffba0e50, 0xeeba0a40, fix(&D:: template VCVT_FFF) }, + { 0xffbf0ed0, 0xeeb70ac0, fix(&D:: template VCVT_DF) }, + { 0xffb30ed0, 0xffb20600, fix(&D:: template VCVT_HFA) }, + { 0xffbe0f50, 0xeeb20a40, fix(&D:: template VCVT_HFF) }, + { 0xffb00e50, 0xee800a00, fix(&D:: template VDIV) }, + { 0xffb00f90, 0xffb00c00, fix(&D:: template VDUP_S) }, + { 0xff900f5f, 0xee800b10, fix(&D:: template VDUP_R) }, + { 0xffb00f10, 0xff000110, fix(&D:: template VEOR) }, + { 0xffb00010, 0xefb00000, fix(&D:: template VEXT) }, + { 0xef800b10, 0xef000000, fix(&D:: template VHADDSUB) }, + { 0xffb00000, 0xf9200000, fix(&D:: template VLD__MS) }, // VLD1, VLD2, VLD3, VLD4 + { 0xffb00f00, 0xf9a00c00, fix(&D:: template VLD1_SAL) }, + { 0xffb00300, 0xf9a00000, fix(&D:: template VLD1_SL) }, + { 0xffb00f00, 0xf9a00d00, fix(&D:: template VLD2_SAL) }, + { 0xffb00300, 0xf9a00100, fix(&D:: template VLD2_SL) }, + { 0xffb00f00, 0xf9a00e00, fix(&D:: template VLD3_SAL) }, + { 0xffb00300, 0xf9a00200, fix(&D:: template VLD3_SL) }, + { 0xffb00f00, 0xf9a00f00, fix(&D:: template VLD4_SAL) }, + { 0xffb00300, 0xf9a00300, fix(&D:: template VLD4_SL) }, + { 0xfe100f00, 0xec100b00, fix(&D:: template VLDM) }, + { 0xfe100f00, 0xec100a00, fix(&D:: template VLDM) }, + { 0xff300f00, 0xed100b00, fix(&D:: template VLDR) }, + { 0xff300f00, 0xed100a00, fix(&D:: template VLDR) }, + { 0xef800f00, 0xef000600, fix(&D:: template VMAXMIN) }, + { 0xff800f10, 0xef000f00, fix(&D:: template VMAXMIN_FP) }, + { 0xef800f10, 0xef000900, fix(&D:: template VML__) }, + { 0xef800d50, 0xef800800, fix(&D:: template VML__) }, + { 0xff800f10, 0xef000d10, fix(&D:: template VML__FP) }, + { 0xffb00e10, 0xee000a00, fix(&D:: template VML__FP) }, + { 0xef800a50, 0xef800040, fix(&D:: template VML__S) }, + { 0xef800b50, 0xef800240, fix(&D:: template VML__S) }, + { 0xefb80090, 0xef800010, fix(&D:: template VMOV_IMM) }, + { 0xffb00ef0, 0xeeb00a00, fix(&D:: template VMOV_IMM) }, + { 0xffb00f10, 0xef200110, fix(&D:: template VMOV_REG) }, + { 0xffbf0ed0, 0xeeb00a40, fix(&D:: template VMOV_REG) }, + { 0xff900f1f, 0xee000b10, fix(&D:: template VMOV_RS) }, + { 0xff100f1f, 0xee100b10, fix(&D:: template VMOV_SR) }, + { 0xffe00f7f, 0xee000a10, fix(&D:: template VMOV_RF) }, + { 0xffe00fd0, 0xec400a10, fix(&D:: template VMOV_2RF) }, + { 0xffe00fd0, 0xec400b10, fix(&D:: template VMOV_2RD) }, + { 0xef870fd0, 0xef800a10, fix(&D:: template VMOVL) }, + { 0xffb30fd0, 0xffb20200, fix(&D:: template VMOVN) }, + { 0xffff0fff, 0xeef10a10, fix(&D:: template VMRS) }, + { 0xffff0fff, 0xeee10a10, fix(&D:: template VMSR) }, + { 0xef800f10, 0xef000910, fix(&D:: template VMUL_) }, + { 0xef800d50, 0xef800c00, fix(&D:: template VMUL_) }, + { 0xffa00f10, 0xff000d10, fix(&D:: template VMUL_FP) }, + { 0xffb00e50, 0xee200a00, fix(&D:: template VMUL_FP) }, + { 0xef800e50, 0xef800840, fix(&D:: template VMUL_S) }, + { 0xef800f50, 0xef800a40, fix(&D:: template VMUL_S) }, + { 0xefb800b0, 0xef800030, fix(&D:: template VMVN_IMM) }, + { 0xffb30f90, 0xffb00580, fix(&D:: template VMVN_REG) }, + { 0xffb30b90, 0xffb10380, fix(&D:: template VNEG) }, + { 0xffbf0ed0, 0xeeb10a40, fix(&D:: template VNEG) }, + { 0xffb00e10, 0xee100a00, fix(&D:: template VNM__) }, + { 0xffb00e50, 0xee200a40, fix(&D:: template VNM__) }, + { 0xffb00f10, 0xef300110, fix(&D:: template VORN_REG) }, + { 0xefb800b0, 0xef800010, fix(&D:: template VORR_IMM) }, + { 0xffb00f10, 0xef200110, fix(&D:: template VORR_REG) }, + { 0xffb30f10, 0xffb00600, fix(&D:: template VPADAL) }, + { 0xff800f10, 0xef000b10, fix(&D:: template VPADD) }, + { 0xffa00f10, 0xff000d00, fix(&D:: template VPADD_FP) }, + { 0xffb30f10, 0xffb00200, fix(&D:: template VPADDL) }, + { 0xef800f00, 0xef000a00, fix(&D:: template VPMAXMIN) }, + { 0xff800f10, 0xff000f00, fix(&D:: template VPMAXMIN_FP) }, + { 0xffbf0f00, 0xecbd0b00, fix(&D:: template VPOP) }, + { 0xffbf0f00, 0xecbd0a00, fix(&D:: template VPOP) }, + { 0xffbf0f00, 0xed2d0b00, fix(&D:: template VPUSH) }, + { 0xffbf0f00, 0xed2d0a00, fix(&D:: template VPUSH) }, + { 0xffb30f90, 0xffb00700, fix(&D:: template VQABS) }, + { 0xef800f10, 0xef000010, fix(&D:: template VQADD) }, + { 0xff800d50, 0xef800900, fix(&D:: template VQDML_L) }, + { 0xff800b50, 0xef800340, fix(&D:: template VQDML_L) }, + { 0xff800f10, 0xef000b00, fix(&D:: template VQDMULH) }, + { 0xef800f50, 0xef800c40, fix(&D:: template VQDMULH) }, + { 0xff800f50, 0xef800d00, fix(&D:: template VQDMULL) }, + { 0xff800f50, 0xef800b40, fix(&D:: template VQDMULL) }, + { 0xffb30f10, 0xffb20200, fix(&D:: template VQMOV_N) }, + { 0xffb30f90, 0xffb00780, fix(&D:: template VQNEG) }, + { 0xff800f10, 0xff000b00, fix(&D:: template VQRDMULH) }, + { 0xef800f50, 0xef800d40, fix(&D:: template VQRDMULH) }, + { 0xef800f10, 0xef000510, fix(&D:: template VQRSHL) }, + { 0xef800ed0, 0xef800850, fix(&D:: template VQRSHR_N) }, + { 0xef800f10, 0xef000410, fix(&D:: template VQSHL_REG) }, + { 0xef800e10, 0xef800610, fix(&D:: template VQSHL_IMM) }, + { 0xef800ed0, 0xef800810, fix(&D:: template VQSHR_N) }, + { 0xef800f10, 0xef000210, fix(&D:: template VQSUB) }, + { 0xff800f50, 0xff800400, fix(&D:: template VRADDHN) }, + { 0xffb30e90, 0xffb30400, fix(&D:: template VRECPE) }, + { 0xffa00f10, 0xef000f10, fix(&D:: template VRECPS) }, + { 0xffb30e10, 0xffb00000, fix(&D:: template VREV__) }, + { 0xef800f10, 0xef000100, fix(&D:: template VRHADD) }, + { 0xef800f10, 0xef000500, fix(&D:: template VRSHL) }, + { 0xef800f10, 0xef800210, fix(&D:: template VRSHR) }, + { 0xff800fd0, 0xef800850, fix(&D:: template VRSHRN) }, + { 0xffb30e90, 0xffb30480, fix(&D:: template VRSQRTE) }, + { 0xffa00f10, 0xef200f10, fix(&D:: template VRSQRTS) }, + { 0xef800f10, 0xef800310, fix(&D:: template VRSRA) }, + { 0xff800f50, 0xff800600, fix(&D:: template VRSUBHN) }, + { 0xff800f10, 0xef800510, fix(&D:: template VSHL_IMM) }, + { 0xef800f10, 0xef000400, fix(&D:: template VSHL_REG) }, + { 0xef800fd0, 0xef800a10, fix(&D:: template VSHLL) }, + { 0xffb30fd0, 0xffb20300, fix(&D:: template VSHLL) }, + { 0xef800f10, 0xef800010, fix(&D:: template VSHR) }, + { 0xff800fd0, 0xef800810, fix(&D:: template VSHRN) }, + { 0xff800f10, 0xff800510, fix(&D:: template VSLI) }, + { 0xffbf0ed0, 0xeeb10ac0, fix(&D:: template VSQRT) }, + { 0xef800f10, 0xef800110, fix(&D:: template VSRA) }, + { 0xff800f10, 0xff800410, fix(&D:: template VSRI) }, + { 0xffb00000, 0xf9000000, fix(&D:: template VST__MS) }, // VST1, VST2, VST3, VST4 + { 0xffb00300, 0xf9800000, fix(&D:: template VST1_SL) }, + { 0xffb00300, 0xf9800100, fix(&D:: template VST2_SL) }, + { 0xffb00300, 0xf9800200, fix(&D:: template VST3_SL) }, + { 0xffb00300, 0xf9800300, fix(&D:: template VST4_SL) }, + { 0xfe100f00, 0xec000b00, fix(&D:: template VSTM) }, + { 0xfe100f00, 0xec000a00, fix(&D:: template VSTM) }, + { 0xff300f00, 0xed000b00, fix(&D:: template VSTR) }, + { 0xff300f00, 0xed000a00, fix(&D:: template VSTR) }, + { 0xff800f10, 0xff000800, fix(&D:: template VSUB) }, + { 0xffa00f10, 0xef200d00, fix(&D:: template VSUB_FP) }, + { 0xffb00e50, 0xee300a40, fix(&D:: template VSUB_FP) }, + { 0xff800f50, 0xef800600, fix(&D:: template VSUBHN) }, + { 0xef800e50, 0xef800200, fix(&D:: template VSUB_) }, + { 0xffb30f90, 0xffb20000, fix(&D:: template VSWP) }, + { 0xffb00c10, 0xffb00800, fix(&D:: template VTB_) }, + { 0xffb30f90, 0xffb20080, fix(&D:: template VTRN) }, + { 0xff800f10, 0xef000810, fix(&D:: template VTST) }, + { 0xffb30f90, 0xffb20100, fix(&D:: template VUZP) }, + { 0xffb30f90, 0xffb20180, fix(&D:: template VZIP) }, + { 0xffffffff, 0xf3af8002, fix(&D:: template WFE) }, + { 0xffffffff, 0xf3af8003, fix(&D:: template WFI) }, + { 0xffffffff, 0xf3af8001, fix(&D:: template YIELD) }, + }); + + m_arm_list.assign( + { + { 0x0ff000f0, 0x00700090, fix(&D:: template HACK), nullptr }, // "Undefined" ARM opcode used + { 0x0ffffff0, 0x012fff10, fix(&D:: template BX), nullptr }, + + { 0x0fe00000, 0x02a00000, fix(&D:: template ADC_IMM) }, + { 0x0fe00010, 0x00a00000, fix(&D:: template ADC_REG) }, + { 0x0fe00090, 0x00a00010, fix(&D:: template ADC_RSR) }, + { 0x0fe00000, 0x02800000, fix(&D:: template ADD_IMM) }, + { 0x0fe00010, 0x00800000, fix(&D:: template ADD_REG) }, + { 0x0fe00090, 0x00800010, fix(&D:: template ADD_RSR) }, + { 0x0fef0000, 0x028d0000, fix(&D:: template ADD_SPI) }, + { 0x0fef0010, 0x008d0000, fix(&D:: template ADD_SPR) }, + { 0x0fff0000, 0x028f0000, fix(&D:: template ADR) }, + { 0x0fff0000, 0x024f0000, fix(&D:: template ADR) }, + { 0x0fe00000, 0x02000000, fix(&D:: template AND_IMM) }, + { 0x0fe00010, 0x00000000, fix(&D:: template AND_REG) }, + { 0x0fe00090, 0x00000010, fix(&D:: template AND_RSR) }, + { 0x0fef0070, 0x01a00040, fix(&D:: template ASR_IMM) }, + { 0x0fef00f0, 0x01a00050, fix(&D:: template ASR_REG) }, + { 0x0f000000, 0x0a000000, fix(&D:: template B) }, + { 0x0fe0007f, 0x07c0001f, fix(&D:: template BFC) }, + { 0x0fe00070, 0x07c00010, fix(&D:: template BFI) }, + { 0x0fe00000, 0x03c00000, fix(&D:: template BIC_IMM) }, + { 0x0fe00010, 0x01c00000, fix(&D:: template BIC_REG) }, + { 0x0fe00090, 0x01c00010, fix(&D:: template BIC_RSR) }, + { 0x0ff000f0, 0x01200070, fix(&D:: template BKPT) }, + { 0x0f000000, 0x0b000000, fix(&D:: template BL) }, + { 0xfe000000, 0xfa000000, fix(&D:: template BL) }, + { 0x0ffffff0, 0x012fff30, fix(&D:: template BLX) }, + { 0x0fff0ff0, 0x016f0f10, fix(&D:: template CLZ) }, + { 0x0ff0f000, 0x03700000, fix(&D:: template CMN_IMM) }, + { 0x0ff0f010, 0x01700000, fix(&D:: template CMN_REG) }, + { 0x0ff0f090, 0x01700010, fix(&D:: template CMN_RSR) }, + { 0x0ff0f000, 0x03500000, fix(&D:: template CMP_IMM) }, + { 0x0ff0f010, 0x01500000, fix(&D:: template CMP_REG) }, + { 0x0ff0f090, 0x01500010, fix(&D:: template CMP_RSR) }, + { 0x0ffffff0, 0x0320f0f0, fix(&D:: template DBG) }, + { 0xfffffff0, 0xf57ff050, fix(&D:: template DMB) }, + { 0xfffffff0, 0xf57ff040, fix(&D:: template DSB) }, + { 0x0fe00000, 0x02200000, fix(&D:: template EOR_IMM) }, + { 0x0fe00010, 0x00200000, fix(&D:: template EOR_REG) }, + { 0x0fe00090, 0x00200010, fix(&D:: template EOR_RSR) }, + { 0x0fd00000, 0x08900000, fix(&D:: template LDM) }, + { 0x0fd00000, 0x08100000, fix(&D:: template LDMDA) }, + { 0x0fd00000, 0x09100000, fix(&D:: template LDMDB) }, + { 0x0fd00000, 0x09900000, fix(&D:: template LDMIB) }, + { 0x0e500000, 0x04100000, fix(&D:: template LDR_IMM) }, + { 0x0f7f0000, 0x051f0000, fix(&D:: template LDR_LIT) }, + { 0x0e500010, 0x06100000, fix(&D:: template LDR_REG) }, + { 0x0e500000, 0x04500000, fix(&D:: template LDRB_IMM) }, + { 0x0f7f0000, 0x055f0000, fix(&D:: template LDRB_LIT) }, + { 0x0e500010, 0x06500000, fix(&D:: template LDRB_REG) }, + { 0x0e5000f0, 0x004000d0, fix(&D:: template LDRD_IMM) }, + { 0x0f7f00f0, 0x014f00d0, fix(&D:: template LDRD_LIT) }, + { 0x0e500ff0, 0x000000d0, fix(&D:: template LDRD_REG) }, + { 0x0ff00fff, 0x01900f9f, fix(&D:: template LDREX) }, + { 0x0ff00fff, 0x01d00f9f, fix(&D:: template LDREXB) }, + { 0x0ff00fff, 0x01b00f9f, fix(&D:: template LDREXD) }, + { 0x0ff00fff, 0x01f00f9f, fix(&D:: template LDREXH) }, + { 0x0e5000f0, 0x005000b0, fix(&D:: template LDRH_IMM) }, + { 0x0f7f00f0, 0x015f00b0, fix(&D:: template LDRH_LIT) }, + { 0x0e500ff0, 0x001000b0, fix(&D:: template LDRH_REG) }, + { 0x0e5000f0, 0x005000d0, fix(&D:: template LDRSB_IMM) }, + { 0x0f7f00f0, 0x015f00d0, fix(&D:: template LDRSB_LIT) }, + { 0x0e500ff0, 0x001000d0, fix(&D:: template LDRSB_REG) }, + { 0x0e5000f0, 0x005000f0, fix(&D:: template LDRSH_IMM) }, + { 0x0f7f00f0, 0x015f00f0, fix(&D:: template LDRSH_LIT) }, + { 0x0e500ff0, 0x001000f0, fix(&D:: template LDRSH_REG) }, + { 0x0fef0070, 0x01a00000, fix(&D:: template LSL_IMM) }, + { 0x0fef00f0, 0x01a00010, fix(&D:: template LSL_REG) }, + { 0x0fef0030, 0x01a00020, fix(&D:: template LSR_IMM) }, + { 0x0fef00f0, 0x01a00030, fix(&D:: template LSR_REG) }, + { 0x0fe000f0, 0x00200090, fix(&D:: template MLA) }, + { 0x0ff000f0, 0x00600090, fix(&D:: template MLS) }, + { 0x0fef0000, 0x03a00000, fix(&D:: template MOV_IMM) }, + { 0x0ff00000, 0x03000000, fix(&D:: template MOV_IMM) }, + { 0x0fef0ff0, 0x01a00000, fix(&D:: template MOV_REG) }, + { 0x0ff00000, 0x03400000, fix(&D:: template MOVT) }, + { 0x0f100010, 0x0e100010, fix(&D:: template MRC_) }, + { 0xff100010, 0xfe100010, fix(&D:: template MRC_) }, + { 0x0fff0fff, 0x010f0000, fix(&D:: template MRS) }, + { 0x0ff3f000, 0x0320f000, fix(&D:: template MSR_IMM) }, + { 0x0ff3fff0, 0x0120f000, fix(&D:: template MSR_REG) }, + { 0x0fe0f0f0, 0x00000090, fix(&D:: template MUL) }, + { 0x0fef0000, 0x03e00000, fix(&D:: template MVN_IMM) }, + { 0xffef0010, 0x01e00000, fix(&D:: template MVN_REG) }, + { 0x0fef0090, 0x01e00010, fix(&D:: template MVN_RSR) }, + { 0x0fffffff, 0x0320f000, fix(&D:: template NOP) }, + { 0x0fe00000, 0x03800000, fix(&D:: template ORR_IMM) }, + { 0x0fe00010, 0x01800000, fix(&D:: template ORR_REG) }, + { 0x0fe00090, 0x01800010, fix(&D:: template ORR_RSR) }, + { 0x0ff00030, 0x06800010, fix(&D:: template PKH) }, + { 0x0fff0000, 0x08bd0000, fix(&D:: template POP) }, + { 0x0fff0fff, 0x049d0004, fix(&D:: template POP) }, + { 0x0fff0000, 0x092d0000, fix(&D:: template PUSH) }, + { 0x0fff0fff, 0x052d0004, fix(&D:: template PUSH) }, + { 0x0ff00ff0, 0x01000050, fix(&D:: template QADD) }, + { 0x0ff00ff0, 0x06200f10, fix(&D:: template QADD16) }, + { 0x0ff00ff0, 0x06200f90, fix(&D:: template QADD8) }, + { 0x0ff00ff0, 0x06200f30, fix(&D:: template QASX) }, + { 0x0ff00ff0, 0x01400050, fix(&D:: template QDADD) }, + { 0x0ff00ff0, 0x01600050, fix(&D:: template QDSUB) }, + { 0x0ff00ff0, 0x06200f50, fix(&D:: template QSAX) }, + { 0x0ff00ff0, 0x01200050, fix(&D:: template QSUB) }, + { 0x0ff00ff0, 0x06200f70, fix(&D:: template QSUB16) }, + { 0x0ff00ff0, 0x06200ff0, fix(&D:: template QSUB8) }, + { 0x0fff0ff0, 0x06ff0f30, fix(&D:: template RBIT) }, + { 0x0fff0ff0, 0x06bf0f30, fix(&D:: template REV) }, + { 0x0fff0ff0, 0x06bf0fb0, fix(&D:: template REV16) }, + { 0x0fff0ff0, 0x06ff0fb0, fix(&D:: template REVSH) }, + { 0x0fef0070, 0x01a00060, fix(&D:: template ROR_IMM) }, + { 0x0fef00f0, 0x01a00070, fix(&D:: template ROR_REG) }, + { 0x0fef0ff0, 0x01a00060, fix(&D:: template RRX) }, + { 0x0fe00000, 0x02600000, fix(&D:: template RSB_IMM) }, + { 0x0fe00010, 0x00600000, fix(&D:: template RSB_REG) }, + { 0x0fe00090, 0x00600010, fix(&D:: template RSB_RSR) }, + { 0x0fe00000, 0x02e00000, fix(&D:: template RSC_IMM) }, + { 0x0fe00010, 0x00e00000, fix(&D:: template RSC_REG) }, + { 0x0fe00090, 0x00e00010, fix(&D:: template RSC_RSR) }, + { 0x0ff00ff0, 0x06100f10, fix(&D:: template SADD16) }, + { 0x0ff00ff0, 0x06100f90, fix(&D:: template SADD8) }, + { 0x0ff00ff0, 0x06100f30, fix(&D:: template SASX) }, + { 0x0fe00000, 0x02c00000, fix(&D:: template SBC_IMM) }, + { 0x0fe00010, 0x00c00000, fix(&D:: template SBC_REG) }, + { 0x0fe00090, 0x00c00010, fix(&D:: template SBC_RSR) }, + { 0x0fe00070, 0x07a00050, fix(&D:: template SBFX) }, + { 0x0ff00ff0, 0x06800fb0, fix(&D:: template SEL) }, + { 0x0ff00ff0, 0x06300f10, fix(&D:: template SHADD16) }, + { 0x0ff00ff0, 0x06300f90, fix(&D:: template SHADD8) }, + { 0x0ff00ff0, 0x06300f30, fix(&D:: template SHASX) }, + { 0x0ff00ff0, 0x06300f50, fix(&D:: template SHSAX) }, + { 0x0ff00ff0, 0x06300f70, fix(&D:: template SHSUB16) }, + { 0x0ff00ff0, 0x06300ff0, fix(&D:: template SHSUB8) }, + { 0x0ff00090, 0x01000080, fix(&D:: template SMLA__) }, + { 0x0ff000d0, 0x07000010, fix(&D:: template SMLAD) }, + { 0x0fe000f0, 0x00e00090, fix(&D:: template SMLAL) }, + { 0x0ff00090, 0x01400080, fix(&D:: template SMLAL__) }, + { 0x0ff000d0, 0x07400010, fix(&D:: template SMLALD) }, + { 0x0ff000b0, 0x01200080, fix(&D:: template SMLAW_) }, + { 0x0ff000d0, 0x07000050, fix(&D:: template SMLSD) }, + { 0x0ff000d0, 0x07400050, fix(&D:: template SMLSLD) }, + { 0x0ff000d0, 0x07500010, fix(&D:: template SMMLA) }, + { 0x0ff000d0, 0x075000d0, fix(&D:: template SMMLS) }, + { 0x0ff0f0d0, 0x0750f010, fix(&D:: template SMMUL) }, + { 0x0ff0f0d0, 0x0700f010, fix(&D:: template SMUAD) }, + { 0x0ff0f090, 0x01600080, fix(&D:: template SMUL__) }, + { 0x0fe000f0, 0x00c00090, fix(&D:: template SMULL) }, + { 0x0ff0f0b0, 0x012000a0, fix(&D:: template SMULW_) }, + { 0x0ff0f0d0, 0x0700f050, fix(&D:: template SMUSD) }, + { 0x0fe00030, 0x06a00010, fix(&D:: template SSAT) }, + { 0x0ff00ff0, 0x06a00f30, fix(&D:: template SSAT16) }, + { 0x0ff00ff0, 0x06100f50, fix(&D:: template SSAX) }, + { 0x0ff00ff0, 0x06100f70, fix(&D:: template SSUB16) }, + { 0x0ff00ff0, 0x06100ff0, fix(&D:: template SSUB8) }, + { 0x0fd00000, 0x08800000, fix(&D:: template STM) }, + { 0x0fd00000, 0x08000000, fix(&D:: template STMDA) }, + { 0x0fd00000, 0x09000000, fix(&D:: template STMDB) }, + { 0x0fd00000, 0x09800000, fix(&D:: template STMIB) }, + { 0x0e500000, 0x04000000, fix(&D:: template STR_IMM) }, + { 0x0e500010, 0x06000000, fix(&D:: template STR_REG) }, + { 0x0e500000, 0x04400000, fix(&D:: template STRB_IMM) }, + { 0x0e500010, 0x06400000, fix(&D:: template STRB_REG) }, + { 0x0e5000f0, 0x004000f0, fix(&D:: template STRD_IMM) }, + { 0x0e500ff0, 0x000000f0, fix(&D:: template STRD_REG) }, + { 0x0ff00ff0, 0x01800f90, fix(&D:: template STREX) }, + { 0x0ff00ff0, 0x01c00f90, fix(&D:: template STREXB) }, + { 0x0ff00ff0, 0x01a00f90, fix(&D:: template STREXD) }, + { 0x0ff00ff0, 0x01e00f90, fix(&D:: template STREXH) }, + { 0x0e5000f0, 0x004000b0, fix(&D:: template STRH_IMM) }, + { 0x0e500ff0, 0x000000b0, fix(&D:: template STRH_REG) }, + { 0x0fe00000, 0x02400000, fix(&D:: template SUB_IMM) }, + { 0x0fe00010, 0x00400000, fix(&D:: template SUB_REG) }, + { 0x0fe00090, 0x00400010, fix(&D:: template SUB_RSR) }, + { 0x0fef0000, 0x024d0000, fix(&D:: template SUB_SPI) }, + { 0x0fef0010, 0x004d0000, fix(&D:: template SUB_SPR) }, + { 0x0f000000, 0x0f000000, fix(&D:: template SVC) }, + { 0x0ff003f0, 0x06a00070, fix(&D:: template SXTAB) }, + { 0x0ff003f0, 0x06800070, fix(&D:: template SXTAB16) }, + { 0x0ff003f0, 0x06b00070, fix(&D:: template SXTAH) }, + { 0x0fff03f0, 0x06af0070, fix(&D:: template SXTB) }, + { 0x0fff03f0, 0x068f0070, fix(&D:: template SXTB16) }, + { 0x0fff03f0, 0x06bf0070, fix(&D:: template SXTH) }, + { 0x0ff0f000, 0x03300000, fix(&D:: template TEQ_IMM) }, + { 0x0ff0f010, 0x01300000, fix(&D:: template TEQ_REG) }, + { 0x0ff0f090, 0x01300010, fix(&D:: template TEQ_RSR) }, + { 0x0ff0f000, 0x03100000, fix(&D:: template TST_IMM) }, + { 0x0ff0f010, 0x01100000, fix(&D:: template TST_REG) }, + { 0x0ff0f090, 0x01100010, fix(&D:: template TST_RSR) }, + { 0x0ff00ff0, 0x06500f10, fix(&D:: template UADD16) }, + { 0x0ff00ff0, 0x06500f90, fix(&D:: template UADD8) }, + { 0x0ff00ff0, 0x06500f30, fix(&D:: template UASX) }, + { 0x0fe00070, 0x07e00050, fix(&D:: template UBFX) }, + { 0x0ff00ff0, 0x06700f10, fix(&D:: template UHADD16) }, + { 0x0ff00ff0, 0x06700f90, fix(&D:: template UHADD8) }, + { 0x0ff00ff0, 0x06700f30, fix(&D:: template UHASX) }, + { 0x0ff00ff0, 0x06700f50, fix(&D:: template UHSAX) }, + { 0x0ff00ff0, 0x06700f70, fix(&D:: template UHSUB16) }, + { 0x0ff00ff0, 0x06700ff0, fix(&D:: template UHSUB8) }, + { 0x0ff000f0, 0x00400090, fix(&D:: template UMAAL) }, + { 0x0fe000f0, 0x00a00090, fix(&D:: template UMLAL) }, + { 0x0fe000f0, 0x00800090, fix(&D:: template UMULL) }, + { 0x0ff00ff0, 0x06600f10, fix(&D:: template UQADD16) }, + { 0x0ff00ff0, 0x06600f90, fix(&D:: template UQADD8) }, + { 0x0ff00ff0, 0x06600f30, fix(&D:: template UQASX) }, + { 0x0ff00ff0, 0x06600f50, fix(&D:: template UQSAX) }, + { 0x0ff00ff0, 0x06600f70, fix(&D:: template UQSUB16) }, + { 0x0ff00ff0, 0x06600ff0, fix(&D:: template UQSUB8) }, + { 0x0ff0f0f0, 0x0780f010, fix(&D:: template USAD8) }, + { 0x0ff000f0, 0x07800010, fix(&D:: template USADA8) }, + { 0x0fe00030, 0x06e00010, fix(&D:: template USAT) }, + { 0x0ff00ff0, 0x06e00f30, fix(&D:: template USAT16) }, + { 0x0ff00ff0, 0x06500f50, fix(&D:: template USAX) }, + { 0x0ff00ff0, 0x06500f70, fix(&D:: template USUB16) }, + { 0x0ff00ff0, 0x06500ff0, fix(&D:: template USUB8) }, + { 0x0ff003f0, 0x06e00070, fix(&D:: template UXTAB), SKIP_IF(BF(16, 19) == 15) }, + { 0x0ff003f0, 0x06c00070, fix(&D:: template UXTAB16) }, + { 0x0ff003f0, 0x06f00070, fix(&D:: template UXTAH) }, + { 0x0fff03f0, 0x06ef0070, fix(&D:: template UXTB) }, + { 0x0fff03f0, 0x06cf0070, fix(&D:: template UXTB16) }, + { 0x0fff03f0, 0x06ff0070, fix(&D:: template UXTH) }, + { 0xfe800f10, 0xf2000710, fix(&D:: template VABA_) }, + { 0xfe800f50, 0xf2800500, fix(&D:: template VABA_) }, + { 0xfe800f10, 0xf2000700, fix(&D:: template VABD_) }, + { 0xfe800f50, 0xf2800700, fix(&D:: template VABD_) }, + { 0xffa00f10, 0xf3200d00, fix(&D:: template VABD_FP) }, + { 0xffb30b90, 0xf3b10300, fix(&D:: template VABS) }, + { 0x0fbf0ed0, 0x0eb00ac0, fix(&D:: template VABS) }, + { 0xff800f10, 0xf3000e10, fix(&D:: template VAC__) }, + { 0xff800f10, 0xf2000800, fix(&D:: template VADD) }, + { 0xffa00f10, 0xf2000d00, fix(&D:: template VADD_FP) }, + { 0x0fb00e50, 0x0e300a00, fix(&D:: template VADD_FP) }, + { 0xff800f50, 0xf2800400, fix(&D:: template VADDHN) }, + { 0xfe800e50, 0xf2800000, fix(&D:: template VADD_) }, + { 0xffb00f10, 0xf2000110, fix(&D:: template VAND) }, + { 0xfeb000b0, 0xf2800030, fix(&D:: template VBIC_IMM) }, + { 0xffb00f10, 0xf2100110, fix(&D:: template VBIC_REG) }, + { 0xff800f10, 0xf3000110, fix(&D:: template VB__) }, + { 0xff800f10, 0xf3000810, fix(&D:: template VCEQ_REG) }, + { 0xffa00f10, 0xf2000e00, fix(&D:: template VCEQ_REG) }, + { 0xffb30b90, 0xf3b10100, fix(&D:: template VCEQ_ZERO) }, + { 0xfe800f10, 0xf2000310, fix(&D:: template VCGE_REG) }, + { 0xffa00f10, 0xf3000e00, fix(&D:: template VCGE_REG) }, + { 0xffb30b90, 0xf3b10080, fix(&D:: template VCGE_ZERO) }, + { 0xfe800f10, 0xf2000300, fix(&D:: template VCGT_REG) }, + { 0xffa00f10, 0xf3200e00, fix(&D:: template VCGT_REG) }, + { 0xffb30b90, 0xf3b10000, fix(&D:: template VCGT_ZERO) }, + { 0xffb30b90, 0xf3b10180, fix(&D:: template VCLE_ZERO) }, + { 0xffb30f90, 0xf3b00400, fix(&D:: template VCLS) }, + { 0xffb30b90, 0xf3b10200, fix(&D:: template VCLT_ZERO) }, + { 0xffb30f90, 0xf3b00480, fix(&D:: template VCLZ) }, + { 0x0fbf0e50, 0x0eb40a40, fix(&D:: template VCMP_) }, + { 0x0fbf0e7f, 0x0eb50a40, fix(&D:: template VCMP_) }, + { 0xffb30f90, 0xf3b00500, fix(&D:: template VCNT) }, + { 0xffb30e10, 0xf3b30600, fix(&D:: template VCVT_FIA) }, + { 0x0fb80e50, 0x0eb80a40, fix(&D:: template VCVT_FIF) }, + { 0xfe800e90, 0xf2800e10, fix(&D:: template VCVT_FFA) }, + { 0x0fba0e50, 0x0eba0a40, fix(&D:: template VCVT_FFF) }, + { 0x0fbf0ed0, 0x0eb70ac0, fix(&D:: template VCVT_DF) }, + { 0xffb30ed0, 0xf3b20600, fix(&D:: template VCVT_HFA) }, + { 0x0fbe0f50, 0x0eb20a40, fix(&D:: template VCVT_HFF) }, + { 0x0fb00e50, 0x0e800a00, fix(&D:: template VDIV) }, + { 0xffb00f90, 0xf3b00c00, fix(&D:: template VDUP_S) }, + { 0x0f900f5f, 0x0e800b10, fix(&D:: template VDUP_R) }, + { 0xffb00f10, 0xf3000110, fix(&D:: template VEOR) }, + { 0xffb00010, 0xf2b00000, fix(&D:: template VEXT) }, + { 0xfe800b10, 0xf2000000, fix(&D:: template VHADDSUB) }, + { 0xffb00000, 0xf4200000, fix(&D:: template VLD__MS) }, + { 0xffb00f00, 0xf4a00c00, fix(&D:: template VLD1_SAL) }, + { 0xffb00300, 0xf4a00000, fix(&D:: template VLD1_SL) }, + { 0xffb00f00, 0xf4a00d00, fix(&D:: template VLD2_SAL) }, + { 0xffb00300, 0xf4a00100, fix(&D:: template VLD2_SL) }, + { 0xffb00f00, 0xf4a00e00, fix(&D:: template VLD3_SAL) }, + { 0xffb00300, 0xf4a00200, fix(&D:: template VLD3_SL) }, + { 0xffb00f00, 0xf4a00f00, fix(&D:: template VLD4_SAL) }, + { 0xffb00300, 0xf4a00300, fix(&D:: template VLD4_SL) }, + { 0x0e100f00, 0x0c100b00, fix(&D:: template VLDM) }, + { 0x0e100f00, 0x0c100a00, fix(&D:: template VLDM) }, + { 0x0f300f00, 0x0d100b00, fix(&D:: template VLDR) }, + { 0x0f300f00, 0x0d100a00, fix(&D:: template VLDR) }, + { 0xfe800f00, 0xf2000600, fix(&D:: template VMAXMIN) }, + { 0xff800f10, 0xf2000f00, fix(&D:: template VMAXMIN_FP) }, + { 0xfe800f10, 0xf2000900, fix(&D:: template VML__) }, + { 0xfe800d50, 0xf2800800, fix(&D:: template VML__) }, + { 0xff800f10, 0xf2000d10, fix(&D:: template VML__FP) }, + { 0x0fb00e10, 0x0e000a00, fix(&D:: template VML__FP) }, + { 0xfe800a50, 0xf2800040, fix(&D:: template VML__S) }, + { 0xfe800b50, 0xf2800240, fix(&D:: template VML__S) }, + { 0xfeb80090, 0xf2800010, fix(&D:: template VMOV_IMM) }, + { 0x0fb00ef0, 0x0eb00a00, fix(&D:: template VMOV_IMM) }, + { 0xffb00f10, 0xf2200110, fix(&D:: template VMOV_REG) }, + { 0x0fbf0ed0, 0x0eb00a40, fix(&D:: template VMOV_REG) }, + { 0x0f900f1f, 0x0e000b10, fix(&D:: template VMOV_RS) }, + { 0x0f100f1f, 0x0e100b10, fix(&D:: template VMOV_SR) }, + { 0x0fe00f7f, 0x0e000a10, fix(&D:: template VMOV_RF) }, + { 0x0fe00fd0, 0x0c400a10, fix(&D:: template VMOV_2RF) }, + { 0x0fe00fd0, 0x0c400b10, fix(&D:: template VMOV_2RD) }, + { 0xfe870fd0, 0xf2800a10, fix(&D:: template VMOVL) }, + { 0xffb30fd0, 0xf3b20200, fix(&D:: template VMOVN) }, + { 0x0fff0fff, 0x0ef10a10, fix(&D:: template VMRS) }, + { 0x0fff0fff, 0x0ee10a10, fix(&D:: template VMSR) }, + { 0xfe800f10, 0xf2000910, fix(&D:: template VMUL_) }, + { 0xfe800d50, 0xf2800c00, fix(&D:: template VMUL_) }, + { 0xffa00f10, 0xf3000d10, fix(&D:: template VMUL_FP) }, + { 0x0fb00e50, 0x0e200a00, fix(&D:: template VMUL_FP) }, + { 0xfe800e50, 0xf2800840, fix(&D:: template VMUL_S) }, + { 0xfe800f50, 0xf2800a40, fix(&D:: template VMUL_S) }, + { 0xfeb800b0, 0xf2800030, fix(&D:: template VMVN_IMM) }, + { 0xffb30f90, 0xf3b00580, fix(&D:: template VMVN_REG) }, + { 0xffb30b90, 0xf3b10380, fix(&D:: template VNEG) }, + { 0x0fbf0ed0, 0x0eb10a40, fix(&D:: template VNEG) }, + { 0x0fb00e10, 0x0e100a00, fix(&D:: template VNM__) }, + { 0x0fb00e50, 0x0e200a40, fix(&D:: template VNM__) }, + { 0xffb00f10, 0xf2300110, fix(&D:: template VORN_REG) }, + { 0xfeb800b0, 0xf2800010, fix(&D:: template VORR_IMM) }, + { 0xffb00f10, 0xf2200110, fix(&D:: template VORR_REG) }, + { 0xffb30f10, 0xf3b00600, fix(&D:: template VPADAL) }, + { 0xff800f10, 0xf2000b10, fix(&D:: template VPADD) }, + { 0xffa00f10, 0xf3000d00, fix(&D:: template VPADD_FP) }, + { 0xffb30f10, 0xf3b00200, fix(&D:: template VPADDL) }, + { 0xfe800f00, 0xf2000a00, fix(&D:: template VPMAXMIN) }, + { 0xff800f10, 0xf3000f00, fix(&D:: template VPMAXMIN_FP) }, + { 0x0fbf0f00, 0x0cbd0b00, fix(&D:: template VPOP) }, + { 0x0fbf0f00, 0x0cbd0a00, fix(&D:: template VPOP) }, + { 0x0fbf0f00, 0x0d2d0b00, fix(&D:: template VPUSH) }, + { 0x0fbf0f00, 0x0d2d0a00, fix(&D:: template VPUSH) }, + // TODO: VQ* instructions + { 0xff800f50, 0xf3800400, fix(&D:: template VRADDHN) }, + { 0xffb30e90, 0xf3b30400, fix(&D:: template VRECPE) }, + { 0xffa00f10, 0xf2000f10, fix(&D:: template VRECPS) }, + { 0xffb30e10, 0xf3b00000, fix(&D:: template VREV__) }, + { 0xfe800f10, 0xf2000100, fix(&D:: template VRHADD) }, + { 0xfe800f10, 0xf2000500, fix(&D:: template VRSHL) }, + { 0xfe800f10, 0xf2800210, fix(&D:: template VRSHR) }, + { 0xff800fd0, 0xf2800850, fix(&D:: template VRSHRN) }, + { 0xffb30e90, 0xf3b30480, fix(&D:: template VRSQRTE) }, + { 0xffa00f10, 0xf2200f10, fix(&D:: template VRSQRTS) }, + { 0xfe800f10, 0xf2800310, fix(&D:: template VRSRA) }, + { 0xff800f50, 0xf3800600, fix(&D:: template VRSUBHN) }, + { 0xff800f10, 0xf2800510, fix(&D:: template VSHL_IMM) }, + { 0xfe800f10, 0xf2000400, fix(&D:: template VSHL_REG) }, + { 0xfe800fd0, 0xf2800a10, fix(&D:: template VSHLL) }, + { 0xffb30fd0, 0xf3b20300, fix(&D:: template VSHLL) }, + { 0xfe800f10, 0xf2800010, fix(&D:: template VSHR) }, + { 0xff800fd0, 0xf2800810, fix(&D:: template VSHRN) }, + { 0xff800f10, 0xf3800510, fix(&D:: template VSLI) }, + { 0x0fbf0ed0, 0x0eb10ac0, fix(&D:: template VSQRT) }, + { 0xfe800f10, 0xf2800110, fix(&D:: template VSRA) }, + { 0xff800f10, 0xf3800410, fix(&D:: template VSRI) }, + { 0xffb00000, 0xf4000000, fix(&D:: template VST__MS) }, + { 0xffb00300, 0xf4800000, fix(&D:: template VST1_SL) }, + { 0xffb00300, 0xf4800100, fix(&D:: template VST2_SL) }, + { 0xffb00300, 0xf4800200, fix(&D:: template VST3_SL) }, + { 0xffb00300, 0xf4800300, fix(&D:: template VST4_SL) }, + { 0x0e100f00, 0x0c000b00, fix(&D:: template VSTM) }, + { 0x0e100f00, 0x0c000a00, fix(&D:: template VSTM) }, + { 0x0f300f00, 0x0d000b00, fix(&D:: template VSTR) }, + { 0x0f300f00, 0x0d000a00, fix(&D:: template VSTR) }, + { 0xff800f10, 0xf3000800, fix(&D:: template VSUB) }, + { 0xffa00f10, 0xf2200d00, fix(&D:: template VSUB_FP) }, + { 0x0fb00e50, 0x0e300a40, fix(&D:: template VSUB_FP) }, + { 0xff800f50, 0xf2800600, fix(&D:: template VSUBHN) }, + { 0xfe800e50, 0xf2800200, fix(&D:: template VSUB_) }, + { 0xffb30f90, 0xf3b20000, fix(&D:: template VSWP) }, + { 0xffb00c10, 0xf3b00800, fix(&D:: template VTB_) }, + { 0xffb30f90, 0xf3b20080, fix(&D:: template VTRN) }, + { 0xff800f10, 0xf2000810, fix(&D:: template VTST) }, + { 0xffb30f90, 0xf3b20100, fix(&D:: template VUZP) }, + { 0xffb30f90, 0xf3b20180, fix(&D:: template VZIP) }, + { 0x0fffffff, 0x0320f002, fix(&D:: template WFE) }, + { 0x0fffffff, 0x0320f003, fix(&D:: template WFI) }, + { 0x0fffffff, 0x0320f001, fix(&D:: template YIELD) }, + }); + + m_op32_table.fill(m_op32_list.cbegin()); + + for (u32 i = 0; i < 0x10000; i++) + { + for (auto& opcode : m_op16_list) + { + if (opcode.match(i)) + { + m_op16_table[i] = opcode.pointer; + break; + } + } + + if (!m_op16_table[i] && !arm_op_thumb_is_32(i)) + { + m_op16_table[i] = &D::UNK; + } + } + + std::set> result; + + for (u32 i = 0xe800; i < 0x10000; i++) + { + if (m_op16_table[i]) LOG_ERROR(ARMv7, "Invalid m_op16_table entry 0x%04x", i); + + //std::set matches; + + //for (u32 j = 0; j < 0x10000; j++) + //{ + // for (auto& o : m_op32_list) + // { + // if (o.match(i << 16 | j)) + // { + // matches.emplace(&o); + // break; + // } + // } + //} + + //result.emplace(std::move(matches)); + } + + for (const auto& s : result) + { + LOG_NOTICE(ARMv7, "Set found (%u):", s.size()); + for (const auto& e : s) + { + LOG_NOTICE(ARMv7, "** 0x%08x, 0x%08x", e->mask, e->code); + } + } + } + + // First chance + T decode_thumb(u16 op16) const + { + return m_op16_table[op16]; + } + + // Second step + T decode_thumb(u32 op32) const + { + for (auto i = m_op32_table[op32 >> 16], end = m_op32_list.end(); i != end; i++) + { + if (i->match(op32)) + { + return i->pointer; + } + } + + return &D::UNK; + } + + T decode_arm(u32 op) const + { + for (auto& i : m_arm_list) + { + if (i.match(op)) + { + return i.pointer; + } + } + + return &D::UNK; + } }; -static void group_0xf(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type) -{ - u32 index = (thr->code.code0 & 0x0b00) >> 8; - - switch ((thr->m_arg & 0x0800d000) >> 12) - { - case 0x8: // B, T3 - case 0x9: // B, T4 - case 0xd: index = 0x0; break; // BL, T1 - - default: break; - } - - if ((thr->m_arg & 0xf800c001) == 0xf000c000) index = 0x0; // BLX, T2 - - switch ((thr->code.code0 & 0x0f00) >> 8) - { - case 0x3: index = 0x3; break; - case 0x8: index = 0x8; break; - case 0x9: index = 0x9; break; - case 0xa: index = 0xa; break; - - default: break; - } - - thr->m_last_instr_name = g_table_0xf_main[index].name; - thr->m_last_instr_size = g_table_0xf_main[index].size; - thr->code.data = thr->m_last_instr_size == 2 ? thr->code.code0 : thr->m_arg; - g_table_0xf_main[index].func(thr, g_table_0xf_main[index].type); -} - -static const ARMv7_Instruction g_table_0xf[] = -{ - { group_0xf } -}; - - -static void execute_main_group(ARMv7Thread* thr) -{ - switch ((thr->code.code0 & 0xf000) >> 12) - { - //case 0x0: (*g_table_0x0).func(thr, (*g_table_0x0).type); break; // TODO - case 0x1: (*g_table_0x1).func(thr, (*g_table_0x1).type); break; - case 0x2: (*g_table_0x2).func(thr, (*g_table_0x2).type); break; - case 0x3: (*g_table_0x3).func(thr, (*g_table_0x3).type); break; - case 0x4: (*g_table_0x4).func(thr, (*g_table_0x4).type); break; - case 0x5: (*g_table_0x5).func(thr, (*g_table_0x5).type); break; - case 0x6: (*g_table_0x6).func(thr, (*g_table_0x6).type); break; - case 0x7: (*g_table_0x7).func(thr, (*g_table_0x7).type); break; - case 0x8: (*g_table_0x8).func(thr, (*g_table_0x8).type); break; - case 0x9: (*g_table_0x9).func(thr, (*g_table_0x9).type); break; - case 0xa: (*g_table_0xa).func(thr, (*g_table_0xa).type); break; - case 0xb: (*g_table_0xb).func(thr, (*g_table_0xb).type); break; - case 0xc: (*g_table_0xc).func(thr, (*g_table_0xc).type); break; - case 0xd: (*g_table_0xd).func(thr, (*g_table_0xd).type); break; - case 0xe: (*g_table_0xe).func(thr, (*g_table_0xe).type); break; - case 0xf: (*g_table_0xf).func(thr, (*g_table_0xf).type); break; - - default: LOG_ERROR(ARMv7, "ARMv7Decoder: unknown group 0x%x", (thr->code.code0 & 0xf000) >> 12); Emu.Pause(); break; - } -} - -#undef ARMv7_OP_2 -#undef ARMv7_OP_4 -#undef ARMv7_NULL_OP -#endif +#undef SKIP_IF +#undef BF +#undef BT diff --git a/rpcs3/Emu/ARMv7/ARMv7Thread.cpp b/rpcs3/Emu/ARMv7/ARMv7Thread.cpp index a7cae52e4d..a240c216a3 100644 --- a/rpcs3/Emu/ARMv7/ARMv7Thread.cpp +++ b/rpcs3/Emu/ARMv7/ARMv7Thread.cpp @@ -1,25 +1,20 @@ #include "stdafx.h" #include "Emu/Memory/Memory.h" #include "Emu/System.h" -#include "Emu/state.h" -#include "Emu/IdManager.h" -#include "Emu/ARMv7/PSVFuncList.h" #include "ARMv7Thread.h" -#include "ARMv7Decoder.h" -#include "ARMv7DisAsm.h" +#include "ARMv7Opcodes.h" #include "ARMv7Interpreter.h" -void ARMv7Context::fast_call(u32 addr) -{ - return static_cast(this)->fast_call(addr); -} +namespace vm { using namespace psv; } + +const arm_decoder s_arm_interpreter; #define TLS_MAX 128 u32 g_armv7_tls_start; -std::array, TLS_MAX> g_armv7_tls_owners; +std::array, TLS_MAX> g_armv7_tls_owners; void armv7_init_tls() { @@ -48,8 +43,7 @@ u32 armv7_get_tls(u32 thread) for (u32 i = 0; i < TLS_MAX; i++) { - u32 old = 0; - if (g_armv7_tls_owners[i].compare_exchange_strong(old, thread)) + if (g_armv7_tls_owners[i].compare_and_swap_test(0, thread)) { const u32 addr = g_armv7_tls_start + i * Emu.GetTLSMemsz(); // get TLS address std::memcpy(vm::base(addr), vm::base(Emu.GetTLSAddr()), Emu.GetTLSFilesz()); // initialize from TLS image @@ -70,57 +64,38 @@ void armv7_free_tls(u32 thread) for (auto& v : g_armv7_tls_owners) { - u32 old = thread; - if (v.compare_exchange_strong(old, 0)) + if (v.compare_and_swap_test(thread, 0)) { return; } } } -ARMv7Thread::ARMv7Thread(const std::string& name) - : CPUThread(CPU_THREAD_ARMv7, name) - , ARMv7Context({}) -{ -} - -ARMv7Thread::~ARMv7Thread() -{ - close_stack(); - armv7_free_tls(m_id); -} - std::string ARMv7Thread::get_name() const { - return fmt::format("ARMv7 Thread[0x%x] (%s)[0x%08x]", m_id, CPUThread::get_name(), PC); + return fmt::format("ARMv7[0x%x] Thread (%s)", id, name); } -void ARMv7Thread::dump_info() const +std::string ARMv7Thread::dump() const { - if (hle_func) + std::string result = "Registers:\n=========\n"; + for(int i=0; i<15; ++i) { - const auto func = get_psv_func_by_nid(hle_func); - - LOG_SUCCESS(HLE, "Last function: %s (0x%x)", func ? func->name : "?????????", hle_func); + result += fmt::format("r%u\t= 0x%08x\n", i, GPR[i]); } - CPUThread::dump_info(); + result += fmt::format("APSR\t= 0x%08x [N: %d, Z: %d, C: %d, V: %d, Q: %d]\n", + APSR.APSR, + u32{ APSR.N }, + u32{ APSR.Z }, + u32{ APSR.C }, + u32{ APSR.V }, + u32{ APSR.Q }); + + return result; } -void ARMv7Thread::init_regs() -{ - memset(GPR, 0, sizeof(GPR)); - APSR.APSR = 0; - IPSR.IPSR = 0; - ISET = PC & 1 ? Thumb : ARM; // select instruction set - PC = PC & ~1; // and fix PC - ITSTATE.IT = 0; - SP = stack_addr + stack_size; - TLS = armv7_get_tls(m_id); - debug = DF_DISASM | DF_PRINT; -} - -void ARMv7Thread::init_stack() +void ARMv7Thread::cpu_init() { if (!stack_addr) { @@ -136,60 +111,15 @@ void ARMv7Thread::init_stack() throw EXCEPTION("Out of stack memory"); } } -} -void ARMv7Thread::close_stack() -{ - if (stack_addr) - { - vm::dealloc_verbose_nothrow(stack_addr, vm::main); - stack_addr = 0; - } -} - -std::string ARMv7Thread::RegsToString() const -{ - std::string result = "Registers:\n=========\n"; - for(int i=0; i<15; ++i) - { - result += fmt::format("%s\t= 0x%08x\n", g_arm_reg_name[i], GPR[i]); - } - - result += fmt::format("APSR\t= 0x%08x [N: %d, Z: %d, C: %d, V: %d, Q: %d]\n", - APSR.APSR, - u32{ APSR.N }, - u32{ APSR.Z }, - u32{ APSR.C }, - u32{ APSR.V }, - u32{ APSR.Q }); - - return result; -} - -std::string ARMv7Thread::ReadRegString(const std::string& reg) const -{ - return ""; -} - -bool ARMv7Thread::WriteRegString(const std::string& reg, std::string value) -{ - return true; -} - -void ARMv7Thread::do_run() -{ - m_dec.reset(); - - switch((int)rpcs3::state.config.core.ppu_decoder.value()) - { - case 0: - case 1: - m_dec.reset(new ARMv7Decoder(*this)); - break; - default: - LOG_ERROR(ARMv7, "Invalid CPU decoder mode: %d", (int)rpcs3::state.config.core.ppu_decoder.value()); - Emu.Pause(); - } + memset(GPR, 0, sizeof(GPR)); + APSR.APSR = 0; + IPSR.IPSR = 0; + ISET = PC & 1 ? Thumb : ARM; // select instruction set + PC = PC & ~1; // and fix PC + ITSTATE.IT = 0; + SP = stack_addr + stack_size; + TLS = armv7_get_tls(id); } void ARMv7Thread::cpu_task() @@ -201,10 +131,54 @@ void ARMv7Thread::cpu_task() return custom_task(*this); } - while (!m_state || !check_status()) + _log::g_tls_make_prefix = [](const auto&, auto, const auto&) { - // decode instruction using specified decoder - PC += m_dec->DecodeMemory(PC); + const auto cpu = static_cast(get_current_cpu_thread()); + + return fmt::format("%s [0x%08x]", cpu->get_name(), cpu->PC); + }; + + while (!state.load() || !check_status()) + { + if (ISET == Thumb) + { + const u16 op16 = vm::read16(PC); + const u32 cond = ITSTATE.advance(); + + if (const auto func16 = s_arm_interpreter.decode_thumb(op16)) + { + func16(*this, op16, cond); + PC += 2; + } + else + { + const u32 op32 = (op16 << 16) | vm::read16(PC + 2); + + s_arm_interpreter.decode_thumb(op32)(*this, op32, cond); + PC += 4; + } + } + else if (ISET == ARM) + { + const u32 op = vm::read32(PC); + + s_arm_interpreter.decode_arm(op)(*this, op, op >> 28); + PC += 4; + } + else + { + throw fmt::exception("Invalid instruction set" HERE); + } + } +} + +ARMv7Thread::~ARMv7Thread() +{ + armv7_free_tls(id); + + if (stack_addr) + { + vm::dealloc_verbose_nothrow(stack_addr, vm::main); } } @@ -228,11 +202,13 @@ void ARMv7Thread::fast_call(u32 addr) { cpu_task(); } - catch (CPUThreadReturn) + catch (cpu_state _s) { + state += _s; + if (_s != cpu_state::ret) throw; } - m_state &= ~CPU_STATE_RETURN; + state -= cpu_state::ret; PC = old_PC; @@ -244,67 +220,3 @@ void ARMv7Thread::fast_call(u32 addr) LR = old_LR; custom_task = std::move(old_task); } - -void ARMv7Thread::fast_stop() -{ - m_state |= CPU_STATE_RETURN; -} - -armv7_thread::armv7_thread(u32 entry, const std::string& name, u32 stack_size, s32 prio) -{ - std::shared_ptr armv7 = idm::make_ptr(name); - - armv7->PC = entry; - armv7->stack_size = stack_size; - armv7->prio = prio; - - thread = std::move(armv7); - - argc = 0; -} - -cpu_thread& armv7_thread::args(std::initializer_list values) -{ - assert(argc == 0); - - if (!values.size()) - { - return *this; - } - - std::vector argv_data; - u32 argv_size = 0; - - for (auto& arg : values) - { - const u32 arg_size = arg.size(); // get arg size - - for (char c : arg) - { - argv_data.push_back(c); // append characters - } - - argv_data.push_back('\0'); // append null terminator - - argv_size += arg_size + 1; - argc++; - } - - argv = vm::alloc(argv_size, vm::main); // allocate arg list - std::memcpy(vm::base(argv), argv_data.data(), argv_size); // copy arg list - - return *this; -} - -cpu_thread& armv7_thread::run() -{ - auto& armv7 = static_cast(*thread); - - armv7.run(); - - // set arguments - armv7.GPR[0] = argc; - armv7.GPR[1] = argv; - - return *this; -} diff --git a/rpcs3/Emu/ARMv7/ARMv7Thread.h b/rpcs3/Emu/ARMv7/ARMv7Thread.h index 878afb1aa6..1b6743c2da 100644 --- a/rpcs3/Emu/ARMv7/ARMv7Thread.h +++ b/rpcs3/Emu/ARMv7/ARMv7Thread.h @@ -1,44 +1,271 @@ #pragma once -#include "Emu/CPU/CPUThread.h" -#include "ARMv7Context.h" -class ARMv7Thread final : public CPUThread, public ARMv7Context +#include "Emu/CPU/CPUThread.h" +#include "Emu/Memory/vm.h" + +enum ARMv7InstructionSet +{ + ARM, + Thumb, + Jazelle, + ThumbEE +}; + +class ARMv7Thread final : public cpu_thread { public: - std::function custom_task; - -public: - ARMv7Thread(const std::string& name); - virtual ~ARMv7Thread() override; - virtual std::string get_name() const override; - virtual void dump_info() const override; - virtual u32 get_pc() const override { return PC; } - virtual u32 get_offset() const override { return 0; } - virtual void do_run() override; + virtual std::string dump() const override; + virtual void cpu_init() override; virtual void cpu_task() override; - virtual void init_regs() override; - virtual void init_stack() override; - virtual void close_stack() override; - u32 get_stack_arg(u32 pos); + ARMv7Thread(const std::string& name) + : cpu_thread(cpu_type::arm, name) + { + } + + virtual ~ARMv7Thread() override; + + union + { + u32 GPR[15]; + + struct + { + u32 pad[13]; + + union + { + u32 SP; + + struct { u16 SP_main, SP_process; }; + }; + + u32 LR; + + union + { + struct + { + u32 reserved0 : 16; + u32 GE : 4; + u32 reserved1 : 4; + u32 dummy : 3; + u32 Q : 1; // Set to 1 if an SSAT or USAT instruction changes (saturates) the input value for the signed or unsigned range of the result + u32 V : 1; // Overflow condition code flag + u32 C : 1; // Carry condition code flag + u32 Z : 1; // Zero condition code flag + u32 N : 1; // Negative condition code flag + }; + + u32 APSR; + + } APSR; + }; + + struct + { + u64 GPR_D[8]; + }; + }; + + union + { + struct + { + u32 dummy : 24; + u32 exception : 8; + }; + + u32 IPSR; + + } IPSR; + + ARMv7InstructionSet ISET; + + union + { + struct + { + u8 shift_state : 5; + u8 cond_base : 3; + }; + + struct + { + u8 check_state : 4; + u8 condition : 4; + }; + + u8 IT; + + u32 advance() + { + // 0xf is "always true" and indicates that this instruction was not in IT block. + // 0xe is "always true" too and represents the AL condition of IT block. + // This makes a significant difference in some instructions. + const u32 res = check_state ? condition : 0xf; + + shift_state <<= 1; + if (!check_state) + { + IT = 0; // clear + } + + return res; + } + + operator bool() const + { + return check_state != 0; + } + + } ITSTATE; + + u32 TLS = 0; + + struct perf_counter + { + u32 event; + u32 value; + }; + + std::array counters{}; + + u32 PC = 0; + s32 prio = 0; + u32 stack_addr = 0; + u32 stack_size = 0; + + std::function custom_task; + + const char* last_function = nullptr; + + void write_pc(u32 value, u32 size) + { + ISET = value & 1 ? Thumb : ARM; + PC = (value & ~1) - size; + } + + u32 read_pc() + { + return ISET == ARM ? PC + 8 : PC + 4; + } + + u32 get_stack_arg(u32 pos) + { + return vm::psv::read32(SP + sizeof(u32) * (pos - 5)); + } + + void write_gpr(u32 n, u32 value, u32 size) + { + Expects(n < 16); + + if (n < 15) + { + GPR[n] = value; + } + else + { + write_pc(value, size); + } + } + + u32 read_gpr(u32 n) + { + Expects(n < 16); + + if (n < 15) + { + return GPR[n]; + } + + return read_pc(); + } + + // function for processing va_args in printf-like functions + u32 get_next_gpr_arg(u32& g_count) + { + if (g_count < 4) + { + return GPR[g_count++]; + } + else + { + return get_stack_arg(g_count++); + } + } + void fast_call(u32 addr); - void fast_stop(); - - virtual std::string RegsToString() const override; - virtual std::string ReadRegString(const std::string& reg) const override; - virtual bool WriteRegString(const std::string& reg, std::string value) override; }; -class armv7_thread : cpu_thread +template +struct arm_gpr_cast_impl { - u32 argv; - u32 argc; - -public: - armv7_thread(u32 entry, const std::string& name, u32 stack_size, s32 prio); - - cpu_thread& args(std::initializer_list values) override; - - cpu_thread& run() override; + static_assert(!sizeof(T), "Invalid type for arm_gpr_cast<>"); }; + +template +struct arm_gpr_cast_impl::value || std::is_enum::value>> +{ + static_assert(sizeof(T) <= 4, "Too big integral type for arm_gpr_cast<>()"); + static_assert(std::is_same::value == false, "bool type is deprecated in arm_gpr_cast<>(), use b8 instead"); + + static inline u32 to(const T& value) + { + return static_cast(value); + } + + static inline T from(const u32 reg) + { + return static_cast(reg); + } +}; + +template<> +struct arm_gpr_cast_impl +{ + static inline u32 to(const b8& value) + { + return value; + } + + static inline b8 from(const u32 reg) + { + return reg != 0; + } +}; + +template +struct arm_gpr_cast_impl, void> +{ + static inline u32 to(const vm::_ptr_base& value) + { + return arm_gpr_cast_impl::to(value.addr()); + } + + static inline vm::_ptr_base from(const u32 reg) + { + return{ arm_gpr_cast_impl::from(reg), vm::addr }; + } +}; + +template +struct arm_gpr_cast_impl, void> +{ + static inline u32 to(const vm::_ref_base& value) + { + return arm_gpr_cast_impl::to(value.addr()); + } + + static inline vm::_ref_base from(const u32 reg) + { + return{ arm_gpr_cast_impl::from(reg), vm::addr }; + } +}; + +template +inline To arm_gpr_cast(const From& value) +{ + return arm_gpr_cast_impl::from(arm_gpr_cast_impl::to(value)); +} diff --git a/rpcs3/Emu/ARMv7/ErrorCodes.h b/rpcs3/Emu/ARMv7/ErrorCodes.h new file mode 100644 index 0000000000..7cba3359e8 --- /dev/null +++ b/rpcs3/Emu/ARMv7/ErrorCodes.h @@ -0,0 +1,350 @@ +#pragma once + +#define ERROR_CODE(code) static_cast(code) + +enum SceOk : s32 +{ + SCE_OK = 0, +}; + +enum SceError : s32 +{ + SCE_ERROR_ERRNO_EPERM = ERROR_CODE(0x80010001), + SCE_ERROR_ERRNO_ENOENT = ERROR_CODE(0x80010002), + SCE_ERROR_ERRNO_ESRCH = ERROR_CODE(0x80010003), + SCE_ERROR_ERRNO_EINTR = ERROR_CODE(0x80010004), + SCE_ERROR_ERRNO_EIO = ERROR_CODE(0x80010005), + SCE_ERROR_ERRNO_ENXIO = ERROR_CODE(0x80010006), + SCE_ERROR_ERRNO_E2BIG = ERROR_CODE(0x80010007), + SCE_ERROR_ERRNO_ENOEXEC = ERROR_CODE(0x80010008), + SCE_ERROR_ERRNO_EBADF = ERROR_CODE(0x80010009), + SCE_ERROR_ERRNO_ECHILD = ERROR_CODE(0x8001000A), + SCE_ERROR_ERRNO_EAGAIN = ERROR_CODE(0x8001000B), + SCE_ERROR_ERRNO_ENOMEM = ERROR_CODE(0x8001000C), + SCE_ERROR_ERRNO_EACCES = ERROR_CODE(0x8001000D), + SCE_ERROR_ERRNO_EFAULT = ERROR_CODE(0x8001000E), + SCE_ERROR_ERRNO_ENOTBLK = ERROR_CODE(0x8001000F), + SCE_ERROR_ERRNO_EBUSY = ERROR_CODE(0x80010010), + SCE_ERROR_ERRNO_EEXIST = ERROR_CODE(0x80010011), + SCE_ERROR_ERRNO_EXDEV = ERROR_CODE(0x80010012), + SCE_ERROR_ERRNO_ENODEV = ERROR_CODE(0x80010013), + SCE_ERROR_ERRNO_ENOTDIR = ERROR_CODE(0x80010014), + SCE_ERROR_ERRNO_EISDIR = ERROR_CODE(0x80010015), + SCE_ERROR_ERRNO_EINVAL = ERROR_CODE(0x80010016), + SCE_ERROR_ERRNO_ENFILE = ERROR_CODE(0x80010017), + SCE_ERROR_ERRNO_EMFILE = ERROR_CODE(0x80010018), + SCE_ERROR_ERRNO_ENOTTY = ERROR_CODE(0x80010019), + SCE_ERROR_ERRNO_ETXTBSY = ERROR_CODE(0x8001001A), + SCE_ERROR_ERRNO_EFBIG = ERROR_CODE(0x8001001B), + SCE_ERROR_ERRNO_ENOSPC = ERROR_CODE(0x8001001C), + SCE_ERROR_ERRNO_ESPIPE = ERROR_CODE(0x8001001D), + SCE_ERROR_ERRNO_EROFS = ERROR_CODE(0x8001001E), + SCE_ERROR_ERRNO_EMLINK = ERROR_CODE(0x8001001F), + SCE_ERROR_ERRNO_EPIPE = ERROR_CODE(0x80010020), + SCE_ERROR_ERRNO_EDOM = ERROR_CODE(0x80010021), + SCE_ERROR_ERRNO_ERANGE = ERROR_CODE(0x80010022), + SCE_ERROR_ERRNO_ENOMSG = ERROR_CODE(0x80010023), + SCE_ERROR_ERRNO_EIDRM = ERROR_CODE(0x80010024), + SCE_ERROR_ERRNO_ECHRNG = ERROR_CODE(0x80010025), + SCE_ERROR_ERRNO_EL2NSYNC = ERROR_CODE(0x80010026), + SCE_ERROR_ERRNO_EL3HLT = ERROR_CODE(0x80010027), + SCE_ERROR_ERRNO_EL3RST = ERROR_CODE(0x80010028), + SCE_ERROR_ERRNO_ELNRNG = ERROR_CODE(0x80010029), + SCE_ERROR_ERRNO_EUNATCH = ERROR_CODE(0x8001002A), + SCE_ERROR_ERRNO_ENOCSI = ERROR_CODE(0x8001002B), + SCE_ERROR_ERRNO_EL2HLT = ERROR_CODE(0x8001002C), + SCE_ERROR_ERRNO_EDEADLK = ERROR_CODE(0x8001002D), + SCE_ERROR_ERRNO_ENOLCK = ERROR_CODE(0x8001002E), + SCE_ERROR_ERRNO_EFORMAT = ERROR_CODE(0x8001002F), + SCE_ERROR_ERRNO_EUNSUP = ERROR_CODE(0x80010030), + SCE_ERROR_ERRNO_EBADE = ERROR_CODE(0x80010032), + SCE_ERROR_ERRNO_EBADR = ERROR_CODE(0x80010033), + SCE_ERROR_ERRNO_EXFULL = ERROR_CODE(0x80010034), + SCE_ERROR_ERRNO_ENOANO = ERROR_CODE(0x80010035), + SCE_ERROR_ERRNO_EBADRQC = ERROR_CODE(0x80010036), + SCE_ERROR_ERRNO_EBADSLT = ERROR_CODE(0x80010037), + SCE_ERROR_ERRNO_EDEADLOCK = ERROR_CODE(0x80010038), + SCE_ERROR_ERRNO_EBFONT = ERROR_CODE(0x80010039), + SCE_ERROR_ERRNO_ENOSTR = ERROR_CODE(0x8001003C), + SCE_ERROR_ERRNO_ENODATA = ERROR_CODE(0x8001003D), + SCE_ERROR_ERRNO_ETIME = ERROR_CODE(0x8001003E), + SCE_ERROR_ERRNO_ENOSR = ERROR_CODE(0x8001003F), + SCE_ERROR_ERRNO_ENONET = ERROR_CODE(0x80010040), + SCE_ERROR_ERRNO_ENOPKG = ERROR_CODE(0x80010041), + SCE_ERROR_ERRNO_EREMOTE = ERROR_CODE(0x80010042), + SCE_ERROR_ERRNO_ENOLINK = ERROR_CODE(0x80010043), + SCE_ERROR_ERRNO_EADV = ERROR_CODE(0x80010044), + SCE_ERROR_ERRNO_ESRMNT = ERROR_CODE(0x80010045), + SCE_ERROR_ERRNO_ECOMM = ERROR_CODE(0x80010046), + SCE_ERROR_ERRNO_EPROTO = ERROR_CODE(0x80010047), + SCE_ERROR_ERRNO_EMULTIHOP = ERROR_CODE(0x8001004A), + SCE_ERROR_ERRNO_ELBIN = ERROR_CODE(0x8001004B), + SCE_ERROR_ERRNO_EDOTDOT = ERROR_CODE(0x8001004C), + SCE_ERROR_ERRNO_EBADMSG = ERROR_CODE(0x8001004D), + SCE_ERROR_ERRNO_EFTYPE = ERROR_CODE(0x8001004F), + SCE_ERROR_ERRNO_ENOTUNIQ = ERROR_CODE(0x80010050), + SCE_ERROR_ERRNO_EBADFD = ERROR_CODE(0x80010051), + SCE_ERROR_ERRNO_EREMCHG = ERROR_CODE(0x80010052), + SCE_ERROR_ERRNO_ELIBACC = ERROR_CODE(0x80010053), + SCE_ERROR_ERRNO_ELIBBAD = ERROR_CODE(0x80010054), + SCE_ERROR_ERRNO_ELIBSCN = ERROR_CODE(0x80010055), + SCE_ERROR_ERRNO_ELIBMAX = ERROR_CODE(0x80010056), + SCE_ERROR_ERRNO_ELIBEXEC = ERROR_CODE(0x80010057), + SCE_ERROR_ERRNO_ENOSYS = ERROR_CODE(0x80010058), + SCE_ERROR_ERRNO_ENMFILE = ERROR_CODE(0x80010059), + SCE_ERROR_ERRNO_ENOTEMPTY = ERROR_CODE(0x8001005A), + SCE_ERROR_ERRNO_ENAMETOOLONG = ERROR_CODE(0x8001005B), + SCE_ERROR_ERRNO_ELOOP = ERROR_CODE(0x8001005C), + SCE_ERROR_ERRNO_EOPNOTSUPP = ERROR_CODE(0x8001005F), + SCE_ERROR_ERRNO_EPFNOSUPPORT = ERROR_CODE(0x80010060), + SCE_ERROR_ERRNO_ECONNRESET = ERROR_CODE(0x80010068), + SCE_ERROR_ERRNO_ENOBUFS = ERROR_CODE(0x80010069), + SCE_ERROR_ERRNO_EAFNOSUPPORT = ERROR_CODE(0x8001006A), + SCE_ERROR_ERRNO_EPROTOTYPE = ERROR_CODE(0x8001006B), + SCE_ERROR_ERRNO_ENOTSOCK = ERROR_CODE(0x8001006C), + SCE_ERROR_ERRNO_ENOPROTOOPT = ERROR_CODE(0x8001006D), + SCE_ERROR_ERRNO_ESHUTDOWN = ERROR_CODE(0x8001006E), + SCE_ERROR_ERRNO_ECONNREFUSED = ERROR_CODE(0x8001006F), + SCE_ERROR_ERRNO_EADDRINUSE = ERROR_CODE(0x80010070), + SCE_ERROR_ERRNO_ECONNABORTED = ERROR_CODE(0x80010071), + SCE_ERROR_ERRNO_ENETUNREACH = ERROR_CODE(0x80010072), + SCE_ERROR_ERRNO_ENETDOWN = ERROR_CODE(0x80010073), + SCE_ERROR_ERRNO_ETIMEDOUT = ERROR_CODE(0x80010074), + SCE_ERROR_ERRNO_EHOSTDOWN = ERROR_CODE(0x80010075), + SCE_ERROR_ERRNO_EHOSTUNREACH = ERROR_CODE(0x80010076), + SCE_ERROR_ERRNO_EINPROGRESS = ERROR_CODE(0x80010077), + SCE_ERROR_ERRNO_EALREADY = ERROR_CODE(0x80010078), + SCE_ERROR_ERRNO_EDESTADDRREQ = ERROR_CODE(0x80010079), + SCE_ERROR_ERRNO_EMSGSIZE = ERROR_CODE(0x8001007A), + SCE_ERROR_ERRNO_EPROTONOSUPPORT = ERROR_CODE(0x8001007B), + SCE_ERROR_ERRNO_ESOCKTNOSUPPORT = ERROR_CODE(0x8001007C), + SCE_ERROR_ERRNO_EADDRNOTAVAIL = ERROR_CODE(0x8001007D), + SCE_ERROR_ERRNO_ENETRESET = ERROR_CODE(0x8001007E), + SCE_ERROR_ERRNO_EISCONN = ERROR_CODE(0x8001007F), + SCE_ERROR_ERRNO_ENOTCONN = ERROR_CODE(0x80010080), + SCE_ERROR_ERRNO_ETOOMANYREFS = ERROR_CODE(0x80010081), + SCE_ERROR_ERRNO_EPROCLIM = ERROR_CODE(0x80010082), + SCE_ERROR_ERRNO_EUSERS = ERROR_CODE(0x80010083), + SCE_ERROR_ERRNO_EDQUOT = ERROR_CODE(0x80010084), + SCE_ERROR_ERRNO_ESTALE = ERROR_CODE(0x80010085), + SCE_ERROR_ERRNO_ENOTSUP = ERROR_CODE(0x80010086), + SCE_ERROR_ERRNO_ENOMEDIUM = ERROR_CODE(0x80010087), + SCE_ERROR_ERRNO_ENOSHARE = ERROR_CODE(0x80010088), + SCE_ERROR_ERRNO_ECASECLASH = ERROR_CODE(0x80010089), + SCE_ERROR_ERRNO_EILSEQ = ERROR_CODE(0x8001008A), + SCE_ERROR_ERRNO_EOVERFLOW = ERROR_CODE(0x8001008B), + SCE_ERROR_ERRNO_ECANCELED = ERROR_CODE(0x8001008C), + SCE_ERROR_ERRNO_ENOTRECOVERABLE = ERROR_CODE(0x8001008D), + SCE_ERROR_ERRNO_EOWNERDEAD = ERROR_CODE(0x8001008E), +}; + +// Special return type signaling on errors +struct arm_error_code +{ + s32 value; + + // Print error message, error code is returned + static s32 report(s32 error, const char* text); + + // Must be specialized for specific tag type T + template + static const char* print(T code) + { + return nullptr; + } + + template + s32 error_check(T code) + { + if (const auto text = print(code)) + { + return report(code, text); + } + + return code; + } + + arm_error_code() = default; + + // General error check + template::value>> + arm_error_code(T value) + : value(error_check(value)) + { + } + + // Force error reporting with a message specified + arm_error_code(s32 value, const char* text) + : value(report(value, text)) + { + } + + // Silence any error + constexpr arm_error_code(s32 value, const std::nothrow_t&) + : value(value) + { + } + + // Conversion + constexpr operator s32() const + { + return value; + } +}; + +// Helper macro for silencing possible error checks on returning arm_error_code values +#define NOT_AN_ERROR(value) { static_cast(value), std::nothrow } + +template +struct arm_gpr_cast_impl; + +template<> +struct arm_gpr_cast_impl +{ + static inline u32 to(const arm_error_code& code) + { + return code; + } + + static inline arm_error_code from(const u32 reg) + { + return NOT_AN_ERROR(reg); + } +}; + +template<> +inline const char* arm_error_code::print(SceError error) +{ + switch (error) + { + STR_CASE(SCE_ERROR_ERRNO_EPERM); + STR_CASE(SCE_ERROR_ERRNO_ENOENT); + STR_CASE(SCE_ERROR_ERRNO_ESRCH); + STR_CASE(SCE_ERROR_ERRNO_EINTR); + STR_CASE(SCE_ERROR_ERRNO_EIO); + STR_CASE(SCE_ERROR_ERRNO_ENXIO); + STR_CASE(SCE_ERROR_ERRNO_E2BIG); + STR_CASE(SCE_ERROR_ERRNO_ENOEXEC); + STR_CASE(SCE_ERROR_ERRNO_EBADF); + STR_CASE(SCE_ERROR_ERRNO_ECHILD); + STR_CASE(SCE_ERROR_ERRNO_EAGAIN); + STR_CASE(SCE_ERROR_ERRNO_ENOMEM); + STR_CASE(SCE_ERROR_ERRNO_EACCES); + STR_CASE(SCE_ERROR_ERRNO_EFAULT); + STR_CASE(SCE_ERROR_ERRNO_ENOTBLK); + STR_CASE(SCE_ERROR_ERRNO_EBUSY); + STR_CASE(SCE_ERROR_ERRNO_EEXIST); + STR_CASE(SCE_ERROR_ERRNO_EXDEV); + STR_CASE(SCE_ERROR_ERRNO_ENODEV); + STR_CASE(SCE_ERROR_ERRNO_ENOTDIR); + STR_CASE(SCE_ERROR_ERRNO_EISDIR); + STR_CASE(SCE_ERROR_ERRNO_EINVAL); + STR_CASE(SCE_ERROR_ERRNO_ENFILE); + STR_CASE(SCE_ERROR_ERRNO_EMFILE); + STR_CASE(SCE_ERROR_ERRNO_ENOTTY); + STR_CASE(SCE_ERROR_ERRNO_ETXTBSY); + STR_CASE(SCE_ERROR_ERRNO_EFBIG); + STR_CASE(SCE_ERROR_ERRNO_ENOSPC); + STR_CASE(SCE_ERROR_ERRNO_ESPIPE); + STR_CASE(SCE_ERROR_ERRNO_EROFS); + STR_CASE(SCE_ERROR_ERRNO_EMLINK); + STR_CASE(SCE_ERROR_ERRNO_EPIPE); + STR_CASE(SCE_ERROR_ERRNO_EDOM); + STR_CASE(SCE_ERROR_ERRNO_ERANGE); + STR_CASE(SCE_ERROR_ERRNO_ENOMSG); + STR_CASE(SCE_ERROR_ERRNO_EIDRM); + STR_CASE(SCE_ERROR_ERRNO_ECHRNG); + STR_CASE(SCE_ERROR_ERRNO_EL2NSYNC); + STR_CASE(SCE_ERROR_ERRNO_EL3HLT); + STR_CASE(SCE_ERROR_ERRNO_EL3RST); + STR_CASE(SCE_ERROR_ERRNO_ELNRNG); + STR_CASE(SCE_ERROR_ERRNO_EUNATCH); + STR_CASE(SCE_ERROR_ERRNO_ENOCSI); + STR_CASE(SCE_ERROR_ERRNO_EL2HLT); + STR_CASE(SCE_ERROR_ERRNO_EDEADLK); + STR_CASE(SCE_ERROR_ERRNO_ENOLCK); + STR_CASE(SCE_ERROR_ERRNO_EFORMAT); + STR_CASE(SCE_ERROR_ERRNO_EUNSUP); + STR_CASE(SCE_ERROR_ERRNO_EBADE); + STR_CASE(SCE_ERROR_ERRNO_EBADR); + STR_CASE(SCE_ERROR_ERRNO_EXFULL); + STR_CASE(SCE_ERROR_ERRNO_ENOANO); + STR_CASE(SCE_ERROR_ERRNO_EBADRQC); + STR_CASE(SCE_ERROR_ERRNO_EBADSLT); + STR_CASE(SCE_ERROR_ERRNO_EDEADLOCK); + STR_CASE(SCE_ERROR_ERRNO_EBFONT); + STR_CASE(SCE_ERROR_ERRNO_ENOSTR); + STR_CASE(SCE_ERROR_ERRNO_ENODATA); + STR_CASE(SCE_ERROR_ERRNO_ETIME); + STR_CASE(SCE_ERROR_ERRNO_ENOSR); + STR_CASE(SCE_ERROR_ERRNO_ENONET); + STR_CASE(SCE_ERROR_ERRNO_ENOPKG); + STR_CASE(SCE_ERROR_ERRNO_EREMOTE); + STR_CASE(SCE_ERROR_ERRNO_ENOLINK); + STR_CASE(SCE_ERROR_ERRNO_EADV); + STR_CASE(SCE_ERROR_ERRNO_ESRMNT); + STR_CASE(SCE_ERROR_ERRNO_ECOMM); + STR_CASE(SCE_ERROR_ERRNO_EPROTO); + STR_CASE(SCE_ERROR_ERRNO_EMULTIHOP); + STR_CASE(SCE_ERROR_ERRNO_ELBIN); + STR_CASE(SCE_ERROR_ERRNO_EDOTDOT); + STR_CASE(SCE_ERROR_ERRNO_EBADMSG); + STR_CASE(SCE_ERROR_ERRNO_EFTYPE); + STR_CASE(SCE_ERROR_ERRNO_ENOTUNIQ); + STR_CASE(SCE_ERROR_ERRNO_EBADFD); + STR_CASE(SCE_ERROR_ERRNO_EREMCHG); + STR_CASE(SCE_ERROR_ERRNO_ELIBACC); + STR_CASE(SCE_ERROR_ERRNO_ELIBBAD); + STR_CASE(SCE_ERROR_ERRNO_ELIBSCN); + STR_CASE(SCE_ERROR_ERRNO_ELIBMAX); + STR_CASE(SCE_ERROR_ERRNO_ELIBEXEC); + STR_CASE(SCE_ERROR_ERRNO_ENOSYS); + STR_CASE(SCE_ERROR_ERRNO_ENMFILE); + STR_CASE(SCE_ERROR_ERRNO_ENOTEMPTY); + STR_CASE(SCE_ERROR_ERRNO_ENAMETOOLONG); + STR_CASE(SCE_ERROR_ERRNO_ELOOP); + STR_CASE(SCE_ERROR_ERRNO_EOPNOTSUPP); + STR_CASE(SCE_ERROR_ERRNO_EPFNOSUPPORT); + STR_CASE(SCE_ERROR_ERRNO_ECONNRESET); + STR_CASE(SCE_ERROR_ERRNO_ENOBUFS); + STR_CASE(SCE_ERROR_ERRNO_EAFNOSUPPORT); + STR_CASE(SCE_ERROR_ERRNO_EPROTOTYPE); + STR_CASE(SCE_ERROR_ERRNO_ENOTSOCK); + STR_CASE(SCE_ERROR_ERRNO_ENOPROTOOPT); + STR_CASE(SCE_ERROR_ERRNO_ESHUTDOWN); + STR_CASE(SCE_ERROR_ERRNO_ECONNREFUSED); + STR_CASE(SCE_ERROR_ERRNO_EADDRINUSE); + STR_CASE(SCE_ERROR_ERRNO_ECONNABORTED); + STR_CASE(SCE_ERROR_ERRNO_ENETUNREACH); + STR_CASE(SCE_ERROR_ERRNO_ENETDOWN); + STR_CASE(SCE_ERROR_ERRNO_ETIMEDOUT); + STR_CASE(SCE_ERROR_ERRNO_EHOSTDOWN); + STR_CASE(SCE_ERROR_ERRNO_EHOSTUNREACH); + STR_CASE(SCE_ERROR_ERRNO_EINPROGRESS); + STR_CASE(SCE_ERROR_ERRNO_EALREADY); + STR_CASE(SCE_ERROR_ERRNO_EDESTADDRREQ); + STR_CASE(SCE_ERROR_ERRNO_EMSGSIZE); + STR_CASE(SCE_ERROR_ERRNO_EPROTONOSUPPORT); + STR_CASE(SCE_ERROR_ERRNO_ESOCKTNOSUPPORT); + STR_CASE(SCE_ERROR_ERRNO_EADDRNOTAVAIL); + STR_CASE(SCE_ERROR_ERRNO_ENETRESET); + STR_CASE(SCE_ERROR_ERRNO_EISCONN); + STR_CASE(SCE_ERROR_ERRNO_ENOTCONN); + STR_CASE(SCE_ERROR_ERRNO_ETOOMANYREFS); + STR_CASE(SCE_ERROR_ERRNO_EPROCLIM); + STR_CASE(SCE_ERROR_ERRNO_EUSERS); + STR_CASE(SCE_ERROR_ERRNO_EDQUOT); + STR_CASE(SCE_ERROR_ERRNO_ESTALE); + STR_CASE(SCE_ERROR_ERRNO_ENOTSUP); + STR_CASE(SCE_ERROR_ERRNO_ENOMEDIUM); + STR_CASE(SCE_ERROR_ERRNO_ENOSHARE); + STR_CASE(SCE_ERROR_ERRNO_ECASECLASH); + STR_CASE(SCE_ERROR_ERRNO_EILSEQ); + STR_CASE(SCE_ERROR_ERRNO_EOVERFLOW); + STR_CASE(SCE_ERROR_ERRNO_ECANCELED); + STR_CASE(SCE_ERROR_ERRNO_ENOTRECOVERABLE); + STR_CASE(SCE_ERROR_ERRNO_EOWNERDEAD); + } + + return nullptr; +} diff --git a/rpcs3/Emu/ARMv7/Modules/sceAppMgr.cpp b/rpcs3/Emu/ARMv7/Modules/sceAppMgr.cpp index bc0d63c2b0..1dee409ee3 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceAppMgr.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceAppMgr.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceAppMgr.h" +LOG_CHANNEL(sceAppMgr); + s32 sceAppMgrReceiveEventNum(vm::ptr eventNum) { throw EXCEPTION(""); @@ -25,15 +27,10 @@ s32 sceAppMgrReleaseBgmPort() } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceAppMgr, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceAppMgrUser, nid, name) -psv_log_base sceAppMgr("SceAppMgr", []() +DECLARE(arm_module_manager::SceAppMgr)("SceAppMgrUser", []() { - sceAppMgr.on_load = nullptr; - sceAppMgr.on_unload = nullptr; - sceAppMgr.on_stop = nullptr; - sceAppMgr.on_error = nullptr; - REG_FUNC(0x47E5DD7D, sceAppMgrReceiveEventNum); REG_FUNC(0xCFAD5A3A, sceAppMgrReceiveEvent); REG_FUNC(0xF3D65520, sceAppMgrAcquireBgmPort); diff --git a/rpcs3/Emu/ARMv7/Modules/sceAppMgr.h b/rpcs3/Emu/ARMv7/Modules/sceAppMgr.h index 8329b62e14..8768ba0c2a 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceAppMgr.h +++ b/rpcs3/Emu/ARMv7/Modules/sceAppMgr.h @@ -6,5 +6,3 @@ struct SceAppMgrEvent le_t appId; char param[56]; }; - -extern psv_log_base sceAppMgr; diff --git a/rpcs3/Emu/ARMv7/Modules/sceAppUtil.cpp b/rpcs3/Emu/ARMv7/Modules/sceAppUtil.cpp index f05c91b0ec..6d63c2bf94 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceAppUtil.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceAppUtil.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceAppUtil.h" +LOG_CHANNEL(sceAppUtil); + s32 sceAppUtilInit(vm::cptr initParam, vm::ptr bootParam) { throw EXCEPTION(""); @@ -70,15 +72,10 @@ s32 sceAppUtilLoadSafeMemory(vm::ptr buf, u32 bufSize, s64 offset) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceAppUtil, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceAppUtil, nid, name) -psv_log_base sceAppUtil("SceAppUtil", []() +DECLARE(arm_module_manager::SceAppUtil)("SceAppUtil", []() { - sceAppUtil.on_load = nullptr; - sceAppUtil.on_unload = nullptr; - sceAppUtil.on_stop = nullptr; - sceAppUtil.on_error = nullptr; - REG_FUNC(0xDAFFE671, sceAppUtilInit); REG_FUNC(0xB220B00B, sceAppUtilShutdown); REG_FUNC(0x7E8FE96A, sceAppUtilSaveDataSlotCreate); diff --git a/rpcs3/Emu/ARMv7/Modules/sceAppUtil.h b/rpcs3/Emu/ARMv7/Modules/sceAppUtil.h index b3e9fc4448..3e3ef55694 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceAppUtil.h +++ b/rpcs3/Emu/ARMv7/Modules/sceAppUtil.h @@ -65,5 +65,3 @@ struct SceAppUtilSaveDataFileSlot vm::lptr slotParam; char reserved[32]; }; - -extern psv_log_base sceAppUtil; diff --git a/rpcs3/Emu/ARMv7/Modules/sceAudio.cpp b/rpcs3/Emu/ARMv7/Modules/sceAudio.cpp index c4107eef55..0261c2e89b 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceAudio.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceAudio.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceAudio.h" +LOG_CHANNEL(sceAudio); + s32 sceAudioOutOpenPort(s32 portType, s32 len, s32 freq, s32 param) { throw EXCEPTION(""); @@ -45,15 +47,10 @@ s32 sceAudioOutGetAdopt(s32 portType) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceAudio, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceAudio, nid, name) -psv_log_base sceAudio("SceAudio", []() +DECLARE(arm_module_manager::SceAudio)("SceAudio", []() { - sceAudio.on_load = nullptr; - sceAudio.on_unload = nullptr; - sceAudio.on_stop = nullptr; - sceAudio.on_error = nullptr; - REG_FUNC(0x5BC341E4, sceAudioOutOpenPort); REG_FUNC(0x69E2E6B5, sceAudioOutReleasePort); REG_FUNC(0x02DB3F5F, sceAudioOutOutput); diff --git a/rpcs3/Emu/ARMv7/Modules/sceAudio.h b/rpcs3/Emu/ARMv7/Modules/sceAudio.h index f6c654b5d0..6f70f09bee 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceAudio.h +++ b/rpcs3/Emu/ARMv7/Modules/sceAudio.h @@ -1,3 +1 @@ #pragma once - -extern psv_log_base sceAudio; diff --git a/rpcs3/Emu/ARMv7/Modules/sceAudioIn.cpp b/rpcs3/Emu/ARMv7/Modules/sceAudioIn.cpp index 03523adbd2..b97a8c6988 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceAudioIn.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceAudioIn.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceAudioIn.h" +LOG_CHANNEL(sceAudioIn); + s32 sceAudioInOpenPort(s32 portType, s32 grain, s32 freq, s32 param) { throw EXCEPTION(""); @@ -20,15 +22,10 @@ s32 sceAudioInInput(s32 port, vm::ptr destPtr) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceAudioIn, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceAudioIn, nid, name) -psv_log_base sceAudioIn("SceAudioIn", []() +DECLARE(arm_module_manager::SceAudioIn)("SceAudioIn", []() { - sceAudioIn.on_load = nullptr; - sceAudioIn.on_unload = nullptr; - sceAudioIn.on_stop = nullptr; - sceAudioIn.on_error = nullptr; - REG_FUNC(0x638ADD2D, sceAudioInInput); REG_FUNC(0x39B50DC1, sceAudioInOpenPort); REG_FUNC(0x3A61B8C4, sceAudioInReleasePort); diff --git a/rpcs3/Emu/ARMv7/Modules/sceAudioIn.h b/rpcs3/Emu/ARMv7/Modules/sceAudioIn.h index ff85239855..6f70f09bee 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceAudioIn.h +++ b/rpcs3/Emu/ARMv7/Modules/sceAudioIn.h @@ -1,3 +1 @@ #pragma once - -extern psv_log_base sceAudioIn; diff --git a/rpcs3/Emu/ARMv7/Modules/sceAudiodec.cpp b/rpcs3/Emu/ARMv7/Modules/sceAudiodec.cpp index abb147a619..bce2640203 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceAudiodec.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceAudiodec.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceAudiodec.h" +LOG_CHANNEL(sceAudiodec); + s32 sceAudiodecInitLibrary(u32 codecType, vm::ptr pInitParam) { throw EXCEPTION(""); @@ -40,15 +42,10 @@ s32 sceAudiodecGetInternalError(vm::ptr pCtrl, vm::ptr pIn } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceAudiodec, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceAudiodecUser, nid, name) -psv_log_base sceAudiodec("SceAudiodec", []() +DECLARE(arm_module_manager::SceAudiodec)("SceAudiodecUser", []() { - sceAudiodec.on_load = nullptr; - sceAudiodec.on_unload = nullptr; - sceAudiodec.on_stop = nullptr; - sceAudiodec.on_error = nullptr; - REG_FUNC(0x445C2CEF, sceAudiodecInitLibrary); REG_FUNC(0x45719B9D, sceAudiodecTermLibrary); REG_FUNC(0x4DFD3AAA, sceAudiodecCreateDecoder); diff --git a/rpcs3/Emu/ARMv7/Modules/sceAudiodec.h b/rpcs3/Emu/ARMv7/Modules/sceAudiodec.h index cfa6c12b80..eb8c29bd3c 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceAudiodec.h +++ b/rpcs3/Emu/ARMv7/Modules/sceAudiodec.h @@ -79,5 +79,3 @@ struct SceAudiodecCtrl le_t wordLength; vm::lptr pInfo; }; - -extern psv_log_base sceAudiodec; diff --git a/rpcs3/Emu/ARMv7/Modules/sceAudioenc.cpp b/rpcs3/Emu/ARMv7/Modules/sceAudioenc.cpp index 73cdfe8b5a..ca7bc17aec 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceAudioenc.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceAudioenc.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceAudioenc.h" +LOG_CHANNEL(sceAudioenc); + s32 sceAudioencInitLibrary(u32 codecType, vm::ptr pInitParam) { throw EXCEPTION(""); @@ -45,15 +47,10 @@ s32 sceAudioencGetInternalError(vm::ptr pCtrl, vm::ptr pIn } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceAudioenc, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceAudioencUser, nid, name) -psv_log_base sceAudioenc("SceAudioenc", []() +DECLARE(arm_module_manager::SceAudioenc)("SceAudioencUser", []() { - sceAudioenc.on_load = nullptr; - sceAudioenc.on_unload = nullptr; - sceAudioenc.on_stop = nullptr; - sceAudioenc.on_error = nullptr; - REG_FUNC(0x76EE4DC6, sceAudioencInitLibrary); REG_FUNC(0xAB32D022, sceAudioencTermLibrary); REG_FUNC(0x64C04AE8, sceAudioencCreateEncoder); diff --git a/rpcs3/Emu/ARMv7/Modules/sceAudioenc.h b/rpcs3/Emu/ARMv7/Modules/sceAudioenc.h index 9b361005e0..b67cf8eb24 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceAudioenc.h +++ b/rpcs3/Emu/ARMv7/Modules/sceAudioenc.h @@ -55,5 +55,3 @@ struct SceAudioencCtrl vm::lptr pInfo; vm::lptr pOptInfo; }; - -extern psv_log_base sceAudioenc; diff --git a/rpcs3/Emu/ARMv7/Modules/sceCamera.cpp b/rpcs3/Emu/ARMv7/Modules/sceCamera.cpp index d5ff9d996d..766b450b4f 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceCamera.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceCamera.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceCamera.h" +LOG_CHANNEL(sceCamera); + s32 sceCameraOpen(s32 devnum, vm::ptr pInfo) { throw EXCEPTION(""); @@ -210,15 +212,10 @@ void sceCameraUseCacheMemoryForTrial(s32 isCache) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceCamera, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceCamera, nid, name) -psv_log_base sceCamera("SceCamera", []() +DECLARE(arm_module_manager::SceCamera)("SceCamera", []() { - sceCamera.on_load = nullptr; - sceCamera.on_unload = nullptr; - sceCamera.on_stop = nullptr; - sceCamera.on_error = nullptr; - REG_FUNC(0xA462F801, sceCameraOpen); REG_FUNC(0xCD6E1CFC, sceCameraClose); REG_FUNC(0xA8FEAE35, sceCameraStart); diff --git a/rpcs3/Emu/ARMv7/Modules/sceCamera.h b/rpcs3/Emu/ARMv7/Modules/sceCamera.h index b0edcf3b77..20a735db31 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceCamera.h +++ b/rpcs3/Emu/ARMv7/Modules/sceCamera.h @@ -36,5 +36,3 @@ struct SceCameraRead vm::lptr pvUBase; vm::lptr pvVBase; }; - -extern psv_log_base sceCamera; diff --git a/rpcs3/Emu/ARMv7/Modules/sceCodecEngine.cpp b/rpcs3/Emu/ARMv7/Modules/sceCodecEngine.cpp index cfb84e9cfe..0fb17012d2 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceCodecEngine.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceCodecEngine.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceCodecEngine.h" +LOG_CHANNEL(sceCodecEngine); + s32 sceCodecEnginePmonStart() { throw EXCEPTION(""); @@ -25,15 +27,10 @@ s32 sceCodecEnginePmonReset() } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceCodecEngine, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceCodecEngine, nid, name) -psv_log_base sceCodecEngine("SceCodecEngine", []() +DECLARE(arm_module_manager::SceCodecEngine)("SceCodecEngine", []() { - sceCodecEngine.on_load = nullptr; - sceCodecEngine.on_unload = nullptr; - sceCodecEngine.on_stop = nullptr; - sceCodecEngine.on_error = nullptr; - REG_FUNC(0x3E718890, sceCodecEnginePmonStart); REG_FUNC(0x268B1EF5, sceCodecEnginePmonStop); REG_FUNC(0x859E4A68, sceCodecEnginePmonGetProcessorLoad); diff --git a/rpcs3/Emu/ARMv7/Modules/sceCodecEngine.h b/rpcs3/Emu/ARMv7/Modules/sceCodecEngine.h index 9cd72d5598..95cb73031a 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceCodecEngine.h +++ b/rpcs3/Emu/ARMv7/Modules/sceCodecEngine.h @@ -5,5 +5,3 @@ struct SceCodecEnginePmonProcessorLoad le_t size; le_t average; }; - -extern psv_log_base sceCodecEngine; diff --git a/rpcs3/Emu/ARMv7/Modules/sceCommonDialog.cpp b/rpcs3/Emu/ARMv7/Modules/sceCommonDialog.cpp index b63dd9d202..c3c290dc53 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceCommonDialog.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceCommonDialog.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceCommonDialog.h" +LOG_CHANNEL(sceCommonDialog); + s32 sceCommonDialogUpdate(vm::cptr updateParam) { throw EXCEPTION(""); @@ -205,15 +207,10 @@ s32 scePhotoReviewDialogAbort() } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceCommonDialog, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceCommonDialog, nid, name) -psv_log_base sceCommonDialog("SceCommonDialog", []() +DECLARE(arm_module_manager::SceCommonDialog)("SceCommonDialog", []() { - sceCommonDialog.on_load = nullptr; - sceCommonDialog.on_unload = nullptr; - sceCommonDialog.on_stop = nullptr; - sceCommonDialog.on_error = nullptr; - REG_FUNC(0x90530F2F, sceCommonDialogUpdate); REG_FUNC(0x755FF270, sceMsgDialogInit); REG_FUNC(0x4107019E, sceMsgDialogGetStatus); diff --git a/rpcs3/Emu/ARMv7/Modules/sceCommonDialog.h b/rpcs3/Emu/ARMv7/Modules/sceCommonDialog.h index 564c9eabea..1fcbcdb578 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceCommonDialog.h +++ b/rpcs3/Emu/ARMv7/Modules/sceCommonDialog.h @@ -298,5 +298,3 @@ struct ScePhotoReviewDialogResult le_t result; char reserved[32]; }; - -extern psv_log_base sceCommonDialog; diff --git a/rpcs3/Emu/ARMv7/Modules/sceCtrl.cpp b/rpcs3/Emu/ARMv7/Modules/sceCtrl.cpp index 3dc74100c4..1351e97738 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceCtrl.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceCtrl.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceCtrl.h" +LOG_CHANNEL(sceCtrl); + s32 sceCtrlSetSamplingMode(u32 uiMode) { throw EXCEPTION(""); @@ -45,15 +47,10 @@ s32 sceCtrlClearRapidFire(s32 port, s32 idx) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceCtrl, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceCtrl, nid, name) -psv_log_base sceCtrl("SceCtrl", []() +DECLARE(arm_module_manager::SceCtrl)("SceCtrl", []() { - sceCtrl.on_load = nullptr; - sceCtrl.on_unload = nullptr; - sceCtrl.on_stop = nullptr; - sceCtrl.on_error = nullptr; - REG_FUNC(0xA497B150, sceCtrlSetSamplingMode); REG_FUNC(0xEC752AAF, sceCtrlGetSamplingMode); REG_FUNC(0xA9C3CED6, sceCtrlPeekBufferPositive); diff --git a/rpcs3/Emu/ARMv7/Modules/sceCtrl.h b/rpcs3/Emu/ARMv7/Modules/sceCtrl.h index 278e478b78..3039299611 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceCtrl.h +++ b/rpcs3/Emu/ARMv7/Modules/sceCtrl.h @@ -20,5 +20,3 @@ struct SceCtrlRapidFireRule le_t uiMake; le_t uiBreak; }; - -extern psv_log_base sceCtrl; diff --git a/rpcs3/Emu/ARMv7/Modules/sceDbg.cpp b/rpcs3/Emu/ARMv7/Modules/sceDbg.cpp index 262b0ea7d9..3617d18e07 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceDbg.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceDbg.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceDbg.h" +LOG_CHANNEL(sceDbg); + s32 sceDbgSetMinimumLogLevel(s32 minimumLogLevel) { throw EXCEPTION(""); @@ -14,26 +16,21 @@ s32 sceDbgSetBreakOnErrorState(SceDbgBreakOnErrorState state) throw EXCEPTION(""); } -s32 sceDbgAssertionHandler(vm::cptr pFile, s32 line, b8 stop, vm::cptr pComponent, vm::cptr pMessage, armv7_va_args_t va_args) +s32 sceDbgAssertionHandler(vm::cptr pFile, s32 line, b8 stop, vm::cptr pComponent, vm::cptr pMessage, arm_va_args_t va_args) { throw EXCEPTION(""); } -s32 sceDbgLoggingHandler(vm::cptr pFile, s32 line, s32 severity, vm::cptr pComponent, vm::cptr pMessage, armv7_va_args_t va_args) +s32 sceDbgLoggingHandler(vm::cptr pFile, s32 line, s32 severity, vm::cptr pComponent, vm::cptr pMessage, arm_va_args_t va_args) { throw EXCEPTION(""); } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceDbg, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceDbg, nid, name) -psv_log_base sceDbg("SceDbg", []() +DECLARE(arm_module_manager::SceDbg)("SceDbg", []() { - sceDbg.on_load = nullptr; - sceDbg.on_unload = nullptr; - sceDbg.on_stop = nullptr; - sceDbg.on_error = nullptr; - REG_FUNC(0x941622FA, sceDbgSetMinimumLogLevel); REG_FUNC(0x1AF3678B, sceDbgAssertionHandler); REG_FUNC(0x6605AB19, sceDbgLoggingHandler); diff --git a/rpcs3/Emu/ARMv7/Modules/sceDbg.h b/rpcs3/Emu/ARMv7/Modules/sceDbg.h index c9136a4c0f..dbc556af2c 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceDbg.h +++ b/rpcs3/Emu/ARMv7/Modules/sceDbg.h @@ -5,5 +5,3 @@ enum SceDbgBreakOnErrorState : s32 SCE_DBG_DISABLE_BREAK_ON_ERROR = 0, SCE_DBG_ENABLE_BREAK_ON_ERROR }; - -extern psv_log_base sceDbg; diff --git a/rpcs3/Emu/ARMv7/Modules/sceDeci4p.cpp b/rpcs3/Emu/ARMv7/Modules/sceDeci4p.cpp index 1553aa4bf3..abacc1199e 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceDeci4p.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceDeci4p.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceDeci4p.h" +LOG_CHANNEL(sceDeci4p); + s32 sceKernelDeci4pOpen(vm::cptr protoname, u32 protonum, u32 bufsize) { throw EXCEPTION(""); @@ -30,15 +32,10 @@ s32 sceKernelDeci4pRegisterCallback(s32 socketid, s32 cbid) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceDeci4p, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceDeci4pUserp, nid, name) -psv_log_base sceDeci4p("SceDeci4pUserp", []() +DECLARE(arm_module_manager::SceDeci4p)("SceDeci4pUserp", []() { - sceDeci4p.on_load = nullptr; - sceDeci4p.on_unload = nullptr; - sceDeci4p.on_stop = nullptr; - sceDeci4p.on_error = nullptr; - REG_FUNC(0x28578FE8, sceKernelDeci4pOpen); REG_FUNC(0x63B0C50F, sceKernelDeci4pClose); REG_FUNC(0x971E1C66, sceKernelDeci4pRead); diff --git a/rpcs3/Emu/ARMv7/Modules/sceDeci4p.h b/rpcs3/Emu/ARMv7/Modules/sceDeci4p.h index 98f9e59faa..4393fdcf88 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceDeci4p.h +++ b/rpcs3/Emu/ARMv7/Modules/sceDeci4p.h @@ -1,5 +1,3 @@ #pragma once using SceKernelDeci4pCallback = s32(s32 notifyId, s32 notifyCount, s32 notifyArg, vm::ptr pCommon); - -extern psv_log_base sceDeci4p; diff --git a/rpcs3/Emu/ARMv7/Modules/sceDeflt.cpp b/rpcs3/Emu/ARMv7/Modules/sceDeflt.cpp index 2aa496213c..dc70310c59 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceDeflt.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceDeflt.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceDeflt.h" +LOG_CHANNEL(sceDeflt); + s32 sceGzipIsValid(vm::cptr pSrcGzip) { throw EXCEPTION(""); @@ -70,15 +72,10 @@ s32 sceZipGetInfo(vm::cptr pSrc, vm::cpptr ppvExtra, vm::ptr pu } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceDeflt, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceDeflt, nid, name) -psv_log_base sceDeflt("SceDeflt", []() +DECLARE(arm_module_manager::SceDeflt)("SceDeflt", []() { - sceDeflt.on_load = nullptr; - sceDeflt.on_unload = nullptr; - sceDeflt.on_stop = nullptr; - sceDeflt.on_error = nullptr; - REG_FUNC(0xCD83A464, sceZlibAdler32); REG_FUNC(0x110D5050, sceDeflateDecompress); REG_FUNC(0xE3CB51A3, sceGzipDecompress); diff --git a/rpcs3/Emu/ARMv7/Modules/sceDeflt.h b/rpcs3/Emu/ARMv7/Modules/sceDeflt.h index 1d61e9f7b1..6f70f09bee 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceDeflt.h +++ b/rpcs3/Emu/ARMv7/Modules/sceDeflt.h @@ -1,3 +1 @@ #pragma once - -extern psv_log_base sceDeflt; diff --git a/rpcs3/Emu/ARMv7/Modules/sceDisplay.cpp b/rpcs3/Emu/ARMv7/Modules/sceDisplay.cpp index 48e1eed48a..b9f978e3b0 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceDisplay.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceDisplay.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceDisplay.h" +LOG_CHANNEL(sceDisplay); + s32 sceDisplayGetRefreshRate(vm::ptr pFps) { throw EXCEPTION(""); @@ -75,20 +77,16 @@ s32 sceDisplayUnregisterVblankStartCallback(s32 uid) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceDisplay, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceDisplay, nid, name) -psv_log_base sceDisplay("SceDisplay", []() +DECLARE(arm_module_manager::SceDisplayUser)("SceDisplayUser", []() { - sceDisplay.on_load = nullptr; - sceDisplay.on_unload = nullptr; - sceDisplay.on_stop = nullptr; - sceDisplay.on_error = nullptr; + REG_FNID(SceDisplayUser, 0x7A410B64, sceDisplaySetFrameBuf); + REG_FNID(SceDisplayUser, 0x42AE6BBC, sceDisplayGetFrameBuf); +}); - // SceDisplayUser - REG_FUNC(0x7A410B64, sceDisplaySetFrameBuf); - REG_FUNC(0x42AE6BBC, sceDisplayGetFrameBuf); - - // SceDisplay +DECLARE(arm_module_manager::SceDisplay)("SceDisplay", []() +{ REG_FUNC(0xA08CA60D, sceDisplayGetRefreshRate); REG_FUNC(0xB6FDE0BA, sceDisplayGetVcount); REG_FUNC(0x5795E898, sceDisplayWaitVblankStart); diff --git a/rpcs3/Emu/ARMv7/Modules/sceDisplay.h b/rpcs3/Emu/ARMv7/Modules/sceDisplay.h index cce29c9e38..9835022740 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceDisplay.h +++ b/rpcs3/Emu/ARMv7/Modules/sceDisplay.h @@ -9,5 +9,3 @@ struct SceDisplayFrameBuf le_t width; le_t height; }; - -extern psv_log_base sceDisplay; diff --git a/rpcs3/Emu/ARMv7/Modules/sceFiber.cpp b/rpcs3/Emu/ARMv7/Modules/sceFiber.cpp index 44fab30de3..bc769383df 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceFiber.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceFiber.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceFiber.h" +LOG_CHANNEL(sceFiber); + s32 _sceFiberInitializeImpl(vm::ptr fiber, vm::cptr name, vm::ptr entry, u32 argOnInitialize, vm::ptr addrContext, u32 sizeContext, vm::cptr optParam, u32 buildVersion) { throw EXCEPTION(""); @@ -45,15 +47,10 @@ s32 sceFiberGetInfo(vm::ptr fiber, vm::ptr fiberInfo) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceFiber, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceFiber, nid, name) -psv_log_base sceFiber("SceFiber", []() +DECLARE(arm_module_manager::SceFiber)("SceFiber", []() { - sceFiber.on_load = nullptr; - sceFiber.on_unload = nullptr; - sceFiber.on_stop = nullptr; - sceFiber.on_error = nullptr; - REG_FUNC(0xF24A298C, _sceFiberInitializeImpl); //REG_FUNC(0xC6A3F9BB, _sceFiberInitializeWithInternalOptionImpl); //REG_FUNC(0x7D0C7DDB, _sceFiberAttachContextAndRun); diff --git a/rpcs3/Emu/ARMv7/Modules/sceFiber.h b/rpcs3/Emu/ARMv7/Modules/sceFiber.h index 11e40b0476..cbc65d6547 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceFiber.h +++ b/rpcs3/Emu/ARMv7/Modules/sceFiber.h @@ -27,5 +27,3 @@ struct alignas(8) SceFiberInfo }; CHECK_SIZE_ALIGN(SceFiberInfo, 128, 8); - -extern psv_log_base sceFiber; diff --git a/rpcs3/Emu/ARMv7/Modules/sceFios.cpp b/rpcs3/Emu/ARMv7/Modules/sceFios.cpp index 1ee3a319aa..67420d112f 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceFios.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceFios.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceFios.h" +LOG_CHANNEL(sceFios); + s32 sceFiosInitialize(vm::cptr pParameters) { throw EXCEPTION(""); @@ -119,7 +121,7 @@ s32 sceFiosPathncmp(vm::cptr pA, vm::cptr pB, u32 n) throw EXCEPTION(""); } -s32 sceFiosPrintf(vm::cptr pFormat, armv7_va_args_t va_args) +s32 sceFiosPrintf(vm::cptr pFormat, arm_va_args_t va_args) { throw EXCEPTION(""); } @@ -684,15 +686,10 @@ void sceFiosIOFilterPsarcDearchiver() throw EXCEPTION(""); } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceFios, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceFios2, nid, name) -psv_log_base sceFios("SceFios2", []() +DECLARE(arm_module_manager::SceFios)("SceFios2", []() { - sceFios.on_load = nullptr; - sceFios.on_unload = nullptr; - sceFios.on_stop = nullptr; - sceFios.on_error = nullptr; - REG_FUNC(0x15857180, sceFiosArchiveGetMountBufferSize); REG_FUNC(0xDF3352FC, sceFiosArchiveGetMountBufferSizeSync); //REG_FUNC(0x92E76BBD, sceFiosArchiveMount); diff --git a/rpcs3/Emu/ARMv7/Modules/sceFios.h b/rpcs3/Emu/ARMv7/Modules/sceFios.h index 0babf0ac0f..569c663893 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceFios.h +++ b/rpcs3/Emu/ARMv7/Modules/sceFios.h @@ -1,7 +1,7 @@ #pragma once using SceFiosOpCallback = s32(vm::ptr pContext, s32 op, u8 event, s32 err); -using SceFiosVprintfCallback = s32(vm::cptr fmt, armv7_va_args_t ap /* va_list */); +using SceFiosVprintfCallback = s32(vm::cptr fmt, arm_va_args_t ap /* va_list */); using SceFiosMemcpyCallback = vm::ptr(vm::ptr dst, vm::cptr src, u32 len); enum SceFiosWhence : s32 @@ -109,5 +109,3 @@ struct SceFiosPsarcDearchiverContext vm::lptr pWorkBuffer; le_t reserved[4]; }; - -extern psv_log_base sceFios; diff --git a/rpcs3/Emu/ARMv7/Modules/sceFpu.cpp b/rpcs3/Emu/ARMv7/Modules/sceFpu.cpp index 27b7c6e5c7..9dda61cf8e 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceFpu.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceFpu.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceFpu.h" +LOG_CHANNEL(sceFpu); + float sceFpuSinf(float x) { throw EXCEPTION(""); @@ -76,15 +78,10 @@ float sceFpuPowf(float x, float y) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceFpu, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceFpu, nid, name) -psv_log_base sceFpu("SceFpu", []() +DECLARE(arm_module_manager::SceFpu)("SceFpu", []() { - sceFpu.on_load = nullptr; - sceFpu.on_unload = nullptr; - sceFpu.on_stop = nullptr; - sceFpu.on_error = nullptr; - //REG_FUNC(0x33E1AC14, sceFpuSinf); //REG_FUNC(0xDB66BA89, sceFpuCosf); //REG_FUNC(0x6FBDA1C9, sceFpuTanf); diff --git a/rpcs3/Emu/ARMv7/Modules/sceFpu.h b/rpcs3/Emu/ARMv7/Modules/sceFpu.h index 2df62880d4..6f70f09bee 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceFpu.h +++ b/rpcs3/Emu/ARMv7/Modules/sceFpu.h @@ -1,3 +1 @@ #pragma once - -extern psv_log_base sceFpu; diff --git a/rpcs3/Emu/ARMv7/Modules/sceGxm.cpp b/rpcs3/Emu/ARMv7/Modules/sceGxm.cpp index ae0f51a416..22fb6d3a92 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceGxm.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceGxm.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceGxm.h" +LOG_CHANNEL(sceGxm); + s32 sceGxmInitialize(vm::cptr params) { throw EXCEPTION(""); @@ -1067,15 +1069,10 @@ s32 sceGxmSetUniformDataF(vm::ptr uniformBuffer, vm::cptr hostMemSize; le_t driverMemBlock; }; - -extern psv_log_base sceGxm; diff --git a/rpcs3/Emu/ARMv7/Modules/sceHttp.cpp b/rpcs3/Emu/ARMv7/Modules/sceHttp.cpp index 6d7417ffea..1889742d60 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceHttp.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceHttp.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceHttp.h" +LOG_CHANNEL(sceHttp); + s32 sceHttpInit(u32 poolSize) { throw EXCEPTION(""); @@ -280,15 +282,10 @@ s32 sceHttpsFreeCaList(vm::ptr caList) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceHttp, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceHttp, nid, name) -psv_log_base sceHttp("SceHttp", []() +DECLARE(arm_module_manager::SceHttp)("SceHttp", []() { - sceHttp.on_load = nullptr; - sceHttp.on_unload = nullptr; - sceHttp.on_stop = nullptr; - sceHttp.on_error = nullptr; - REG_FUNC(0x214926D9, sceHttpInit); REG_FUNC(0xC9076666, sceHttpTerm); REG_FUNC(0xF98CDFA9, sceHttpGetMemoryPoolStats); diff --git a/rpcs3/Emu/ARMv7/Modules/sceHttp.h b/rpcs3/Emu/ARMv7/Modules/sceHttp.h index 69e027bb06..1736330349 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceHttp.h +++ b/rpcs3/Emu/ARMv7/Modules/sceHttp.h @@ -70,5 +70,3 @@ struct SceHttpsCaList }; using SceHttpsCallback = s32(u32 verifyEsrr, vm::cptr> sslCert, s32 certNum, vm::ptr userArg); - -extern psv_log_base sceHttp; diff --git a/rpcs3/Emu/ARMv7/Modules/sceIme.cpp b/rpcs3/Emu/ARMv7/Modules/sceIme.cpp index c903c58309..7404b7d5d5 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceIme.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceIme.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceIme.h" +LOG_CHANNEL(sceIme); + s32 sceImeOpen(vm::ptr param) { throw EXCEPTION(""); @@ -30,15 +32,10 @@ s32 sceImeClose() } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceIme, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceIme, nid, name) -psv_log_base sceIme("SceIme", []() +DECLARE(arm_module_manager::SceIme)("SceIme", []() { - sceIme.on_load = nullptr; - sceIme.on_unload = nullptr; - sceIme.on_stop = nullptr; - sceIme.on_error = nullptr; - REG_FUNC(0x0E050613, sceImeOpen); REG_FUNC(0x71D6898A, sceImeUpdate); REG_FUNC(0x889A8421, sceImeClose); diff --git a/rpcs3/Emu/ARMv7/Modules/sceIme.h b/rpcs3/Emu/ARMv7/Modules/sceIme.h index 27aaf63987..40b98c9e3e 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceIme.h +++ b/rpcs3/Emu/ARMv7/Modules/sceIme.h @@ -66,5 +66,3 @@ struct SceImeParam le_t reserved0; le_t reserved1; }; - -extern psv_log_base sceIme; diff --git a/rpcs3/Emu/ARMv7/Modules/sceJpeg.cpp b/rpcs3/Emu/ARMv7/Modules/sceJpeg.cpp index c09b1a15ad..cc003a075a 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceJpeg.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceJpeg.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceJpeg.h" +LOG_CHANNEL(sceJpeg); + s32 sceJpegInitMJpeg(s32 maxSplitDecoder) { throw EXCEPTION(""); @@ -77,15 +79,10 @@ s32 sceJpegSplitDecodeMJpeg(vm::ptr pCtrl) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceJpeg, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceJpegUser, nid, name) -psv_log_base sceJpeg("SceJpeg", []() +DECLARE(arm_module_manager::SceJpeg)("SceJpegUser", []() { - sceJpeg.on_load = nullptr; - sceJpeg.on_unload = nullptr; - sceJpeg.on_stop = nullptr; - sceJpeg.on_error = nullptr; - REG_FUNC(0xB030773B, sceJpegInitMJpeg); REG_FUNC(0x62842598, sceJpegFinishMJpeg); REG_FUNC(0x6215B095, sceJpegDecodeMJpeg); diff --git a/rpcs3/Emu/ARMv7/Modules/sceJpeg.h b/rpcs3/Emu/ARMv7/Modules/sceJpeg.h index 9b24acff5b..fcb273e9d4 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceJpeg.h +++ b/rpcs3/Emu/ARMv7/Modules/sceJpeg.h @@ -34,5 +34,3 @@ struct SceJpegSplitDecodeCtrl le_t internalData[3]; }; - -extern psv_log_base sceJpeg; diff --git a/rpcs3/Emu/ARMv7/Modules/sceJpegEnc.cpp b/rpcs3/Emu/ARMv7/Modules/sceJpegEnc.cpp index ef6bd1bccc..6146d926ba 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceJpegEnc.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceJpegEnc.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceJpegEnc.h" +LOG_CHANNEL(sceJpegEnc); + s32 sceJpegEncoderGetContextSize() { throw EXCEPTION(""); @@ -73,15 +75,10 @@ s32 sceJpegEncoderCsc( } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceJpegEnc, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceJpegEncUser, nid, name) -psv_log_base sceJpegEnc("SceJpegEnc", []() +DECLARE(arm_module_manager::SceJpegEnc)("SceJpegEncUser", []() { - sceJpegEnc.on_load = nullptr; - sceJpegEnc.on_unload = nullptr; - sceJpegEnc.on_stop = nullptr; - sceJpegEnc.on_error = nullptr; - REG_FUNC(0x2B55844D, sceJpegEncoderGetContextSize); REG_FUNC(0x88DA92B4, sceJpegEncoderInit); REG_FUNC(0xC60DE94C, sceJpegEncoderEncode); diff --git a/rpcs3/Emu/ARMv7/Modules/sceJpegEnc.h b/rpcs3/Emu/ARMv7/Modules/sceJpegEnc.h index 4a046f6f52..513ea5a222 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceJpegEnc.h +++ b/rpcs3/Emu/ARMv7/Modules/sceJpegEnc.h @@ -1,5 +1,3 @@ #pragma once using SceJpegEncoderContext = vm::ptr; - -extern psv_log_base sceJpegEnc; diff --git a/rpcs3/Emu/ARMv7/Modules/sceLibKernel.cpp b/rpcs3/Emu/ARMv7/Modules/sceLibKernel.cpp index 4d2f8f1bd1..2a00e9c5c1 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceLibKernel.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceLibKernel.cpp @@ -1,14 +1,12 @@ #include "stdafx.h" #include "Emu/System.h" #include "Emu/IdManager.h" -#include "Emu/ARMv7/PSVFuncList.h" -#include "Emu/ARMv7/PSVObjectList.h" - -#include "Emu/SysCalls/Callback.h" -#include "Emu/ARMv7/ARMv7Thread.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceLibKernel.h" +LOG_CHANNEL(sceLibKernel); + extern u64 get_system_time(); s32 sceKernelAllocMemBlock(vm::cptr name, s32 type, u32 vsize, vm::ptr pOpt) @@ -31,22 +29,22 @@ s32 sceKernelGetMemBlockInfoByAddr(vm::ptr vbase, vm::ptr pName, vm::ptr entry, s32 initPriority, u32 stackSize, u32 attr, s32 cpuAffinityMask, vm::cptr pOptParam) +arm_error_code sceKernelCreateThread(vm::cptr pName, vm::ptr entry, s32 initPriority, u32 stackSize, u32 attr, s32 cpuAffinityMask, vm::cptr pOptParam) { sceLibKernel.warning("sceKernelCreateThread(pName=*0x%x, entry=*0x%x, initPriority=%d, stackSize=0x%x, attr=0x%x, cpuAffinityMask=0x%x, pOptParam=*0x%x)", pName, entry, initPriority, stackSize, attr, cpuAffinityMask, pOptParam); - auto armv7 = idm::make_ptr(pName.get_ptr()); + const auto thread = idm::make_ptr(pName.get_ptr()); - armv7->PC = entry.addr(); - armv7->prio = initPriority; - armv7->stack_size = stackSize; - armv7->run(); + thread->PC = entry.addr(); + thread->prio = initPriority; + thread->stack_size = stackSize; + thread->cpu_init(); - return armv7->get_id(); + return NOT_AN_ERROR(thread->id); } -s32 sceKernelStartThread(s32 threadId, u32 argSize, vm::cptr pArgBlock) +arm_error_code sceKernelStartThread(s32 threadId, u32 argSize, vm::cptr pArgBlock) { sceLibKernel.warning("sceKernelStartThread(threadId=0x%x, argSize=0x%x, pArgBlock=*0x%x)", threadId, argSize, pArgBlock); @@ -72,21 +70,22 @@ s32 sceKernelStartThread(s32 threadId, u32 argSize, vm::cptr pArgBlock) thread->GPR[0] = argSize; thread->GPR[1] = pos; - thread->exec(); + thread->state -= cpu_state::stop; + thread->safe_notify(); return SCE_OK; } -s32 sceKernelExitThread(ARMv7Thread& context, s32 exitStatus) +arm_error_code sceKernelExitThread(ARMv7Thread& cpu, s32 exitStatus) { sceLibKernel.warning("sceKernelExitThread(exitStatus=0x%x)", exitStatus); - // exit status is stored in r0 - context.exit(); + // Exit status is stored in r0 + cpu.state += cpu_state::exit; return SCE_OK; } -s32 sceKernelDeleteThread(s32 threadId) +arm_error_code sceKernelDeleteThread(s32 threadId) { sceLibKernel.warning("sceKernelDeleteThread(threadId=0x%x)", threadId); @@ -108,15 +107,14 @@ s32 sceKernelDeleteThread(s32 threadId) return SCE_OK; } -s32 sceKernelExitDeleteThread(ARMv7Thread& context, s32 exitStatus) +arm_error_code sceKernelExitDeleteThread(ARMv7Thread& cpu, s32 exitStatus) { sceLibKernel.warning("sceKernelExitDeleteThread(exitStatus=0x%x)", exitStatus); - // exit status is stored in r0 - context.stop(); + //cpu.state += cpu_state::stop; - // current thread should be deleted - idm::remove(context.get_id()); + // Delete current thread; exit status is stored in r0 + idm::remove(cpu.id); return SCE_OK; } @@ -149,11 +147,11 @@ s32 sceKernelGetThreadCurrentPriority() throw EXCEPTION(""); } -u32 sceKernelGetThreadId(ARMv7Thread& context) +u32 sceKernelGetThreadId(ARMv7Thread& cpu) { sceLibKernel.trace("sceKernelGetThreadId()"); - return context.get_id(); + return cpu.id; } s32 sceKernelChangeCurrentThreadAttr(u32 clearAttr, u32 setAttr) @@ -205,24 +203,17 @@ s32 sceKernelGetSystemInfo(vm::ptr pInfo) throw EXCEPTION(""); } -s32 sceKernelGetThreadmgrUIDClass(s32 uid) +arm_error_code sceKernelGetThreadmgrUIDClass(s32 uid) { sceLibKernel.error("sceKernelGetThreadmgrUIDClass(uid=0x%x)", uid); - const auto type = idm::get_type(uid); - - if (!type) - { - return SCE_KERNEL_ERROR_INVALID_UID; - } - - if (*type == typeid(ARMv7Thread)) return SCE_KERNEL_THREADMGR_UID_CLASS_THREAD; - if (*type == typeid(psv_semaphore_t)) return SCE_KERNEL_THREADMGR_UID_CLASS_SEMA; - if (*type == typeid(psv_event_flag_t)) return SCE_KERNEL_THREADMGR_UID_CLASS_EVENT_FLAG; - if (*type == typeid(psv_mutex_t)) return SCE_KERNEL_THREADMGR_UID_CLASS_MUTEX; - if (*type == typeid(psv_cond_t)) return SCE_KERNEL_THREADMGR_UID_CLASS_COND; + if (idm::check(uid)) return SCE_KERNEL_THREADMGR_UID_CLASS_THREAD; + if (idm::check(uid)) return SCE_KERNEL_THREADMGR_UID_CLASS_SEMA; + if (idm::check(uid)) return SCE_KERNEL_THREADMGR_UID_CLASS_EVENT_FLAG; + if (idm::check(uid)) return SCE_KERNEL_THREADMGR_UID_CLASS_MUTEX; + if (idm::check(uid)) return SCE_KERNEL_THREADMGR_UID_CLASS_COND; - throw EXCEPTION("Unknown UID class (type='%s')", type->name()); + return SCE_KERNEL_ERROR_INVALID_UID; } s32 sceKernelChangeThreadVfpException(s32 clearMask, s32 setMask) @@ -253,7 +244,7 @@ s32 sceKernelDelayThreadCB(u32 usec) throw EXCEPTION(""); } -s32 sceKernelWaitThreadEnd(s32 threadId, vm::ptr pExitStatus, vm::ptr pTimeout) +arm_error_code sceKernelWaitThreadEnd(s32 threadId, vm::ptr pExitStatus, vm::ptr pTimeout) { sceLibKernel.warning("sceKernelWaitThreadEnd(threadId=0x%x, pExitStatus=*0x%x, pTimeout=*0x%x)", threadId, pExitStatus, pTimeout); @@ -268,7 +259,7 @@ s32 sceKernelWaitThreadEnd(s32 threadId, vm::ptr pExitStatus, vm::ptr { } - while (thread->is_alive()) + while (!(thread->state & cpu_state::exit)) { CHECK_EMU_STATUS; @@ -381,14 +372,14 @@ s32 sceKernelWaitMultipleEventsCB(vm::ptr pWaitEventList, s3 // Event flag functions -s32 sceKernelCreateEventFlag(vm::cptr pName, u32 attr, u32 initPattern, vm::cptr pOptParam) +arm_error_code sceKernelCreateEventFlag(vm::cptr pName, u32 attr, u32 initPattern, vm::cptr pOptParam) { sceLibKernel.error("sceKernelCreateEventFlag(pName=*0x%x, attr=0x%x, initPattern=0x%x, pOptParam=*0x%x)", pName, attr, initPattern, pOptParam); - return idm::make(pName.get_ptr(), attr, initPattern); + return NOT_AN_ERROR(idm::make(pName.get_ptr(), attr, initPattern)); } -s32 sceKernelDeleteEventFlag(s32 evfId) +arm_error_code sceKernelDeleteEventFlag(s32 evfId) { sceLibKernel.error("sceKernelDeleteEventFlag(evfId=0x%x)", evfId); @@ -408,7 +399,7 @@ s32 sceKernelDeleteEventFlag(s32 evfId) return SCE_OK; } -s32 sceKernelOpenEventFlag(vm::cptr pName) +arm_error_code sceKernelOpenEventFlag(vm::cptr pName) { sceLibKernel.error("sceKernelOpenEventFlag(pName=*0x%x)", pName); @@ -419,14 +410,14 @@ s32 sceKernelOpenEventFlag(vm::cptr pName) if (evf->name == pName.get_ptr() && evf->ref.atomic_op(ipc_ref_try_inc)) { - return idm::import(evf); + return NOT_AN_ERROR(idm::import_existing(evf)); } } return SCE_KERNEL_ERROR_UID_CANNOT_FIND_BY_NAME; } -s32 sceKernelCloseEventFlag(s32 evfId) +arm_error_code sceKernelCloseEventFlag(s32 evfId) { sceLibKernel.error("sceKernelCloseEventFlag(evfId=0x%x)", evfId); @@ -446,7 +437,7 @@ s32 sceKernelCloseEventFlag(s32 evfId) return SCE_OK; } -s32 sceKernelWaitEventFlag(ARMv7Thread& context, s32 evfId, u32 bitPattern, u32 waitMode, vm::ptr pResultPat, vm::ptr pTimeout) +arm_error_code sceKernelWaitEventFlag(ARMv7Thread& cpu, s32 evfId, u32 bitPattern, u32 waitMode, vm::ptr pResultPat, vm::ptr pTimeout) { sceLibKernel.error("sceKernelWaitEventFlag(evfId=0x%x, bitPattern=0x%x, waitMode=0x%x, pResultPat=*0x%x, pTimeout=*0x%x)", evfId, bitPattern, waitMode, pResultPat, pTimeout); @@ -462,7 +453,7 @@ s32 sceKernelWaitEventFlag(ARMv7Thread& context, s32 evfId, u32 bitPattern, u32 std::unique_lock lock(evf->mutex); - const u32 result = evf->pattern.atomic_op(event_flag_try_poll, bitPattern, waitMode); + const u32 result = evf->pattern.fetch_op(event_flag_try_poll, bitPattern, waitMode); if (event_flag_test(result, bitPattern, waitMode)) { @@ -472,13 +463,13 @@ s32 sceKernelWaitEventFlag(ARMv7Thread& context, s32 evfId, u32 bitPattern, u32 } // fixup register values for external use - context.GPR[1] = bitPattern; - context.GPR[2] = waitMode; + cpu.GPR[1] = bitPattern; + cpu.GPR[2] = waitMode; // add waiter; attributes are ignored in current implementation - sleep_queue_entry_t waiter(context, evf->sq); + sleep_entry waiter(evf->sq, cpu); - while (!context.unsignal()) + while (!cpu.state.test_and_reset(cpu_state::signal)) { CHECK_EMU_STATUS; @@ -488,33 +479,33 @@ s32 sceKernelWaitEventFlag(ARMv7Thread& context, s32 evfId, u32 bitPattern, u32 if (passed >= timeout) { - context.GPR[0] = SCE_KERNEL_ERROR_WAIT_TIMEOUT; - context.GPR[1] = evf->pattern; + cpu.GPR[0] = SCE_KERNEL_ERROR_WAIT_TIMEOUT; + cpu.GPR[1] = evf->pattern; break; } - context.cv.wait_for(lock, std::chrono::microseconds(timeout - passed)); + cpu.cv.wait_for(lock, std::chrono::microseconds(timeout - passed)); } else { - context.cv.wait(lock); + cpu.cv.wait(lock); } } - if (pResultPat) *pResultPat = context.GPR[1]; + if (pResultPat) *pResultPat = cpu.GPR[1]; if (pTimeout) *pTimeout = static_cast(std::max(0, timeout - (get_system_time() - start_time))); - return context.GPR[0]; + return NOT_AN_ERROR(cpu.GPR[0]); } -s32 sceKernelWaitEventFlagCB(ARMv7Thread& context, s32 evfId, u32 bitPattern, u32 waitMode, vm::ptr pResultPat, vm::ptr pTimeout) +arm_error_code sceKernelWaitEventFlagCB(ARMv7Thread& cpu, s32 evfId, u32 bitPattern, u32 waitMode, vm::ptr pResultPat, vm::ptr pTimeout) { sceLibKernel.todo("sceKernelWaitEventFlagCB(evfId=0x%x, bitPattern=0x%x, waitMode=0x%x, pResultPat=*0x%x, pTimeout=*0x%x)", evfId, bitPattern, waitMode, pResultPat, pTimeout); - return sceKernelWaitEventFlag(context, evfId, bitPattern, waitMode, pResultPat, pTimeout); + return sceKernelWaitEventFlag(cpu, evfId, bitPattern, waitMode, pResultPat, pTimeout); } -s32 sceKernelPollEventFlag(s32 evfId, u32 bitPattern, u32 waitMode, vm::ptr pResultPat) +arm_error_code sceKernelPollEventFlag(s32 evfId, u32 bitPattern, u32 waitMode, vm::ptr pResultPat) { sceLibKernel.error("sceKernelPollEventFlag(evfId=0x%x, bitPattern=0x%x, waitMode=0x%x, pResultPat=*0x%x)", evfId, bitPattern, waitMode, pResultPat); @@ -527,7 +518,7 @@ s32 sceKernelPollEventFlag(s32 evfId, u32 bitPattern, u32 waitMode, vm::ptr std::lock_guard lock(evf->mutex); - const u32 result = evf->pattern.atomic_op(event_flag_try_poll, bitPattern, waitMode); + const u32 result = evf->pattern.fetch_op(event_flag_try_poll, bitPattern, waitMode); if (!event_flag_test(result, bitPattern, waitMode)) { @@ -539,7 +530,7 @@ s32 sceKernelPollEventFlag(s32 evfId, u32 bitPattern, u32 waitMode, vm::ptr return SCE_OK; } -s32 sceKernelSetEventFlag(s32 evfId, u32 bitPattern) +arm_error_code sceKernelSetEventFlag(s32 evfId, u32 bitPattern) { sceLibKernel.error("sceKernelSetEventFlag(evfId=0x%x, bitPattern=0x%x)", evfId, bitPattern); @@ -554,24 +545,25 @@ s32 sceKernelSetEventFlag(s32 evfId, u32 bitPattern) evf->pattern |= bitPattern; - auto pred = [&](sleep_queue_t::value_type& thread) -> bool + auto pred = [&](cpu_thread* thread) -> bool { - auto& context = static_cast(*thread); + auto& cpu = static_cast(*thread); // load pattern and mode from registers - const u32 pattern = context.GPR[1]; - const u32 mode = context.GPR[2]; + const u32 pattern = cpu.GPR[1]; + const u32 mode = cpu.GPR[2]; // check specific pattern - const u32 result = evf->pattern.atomic_op(event_flag_try_poll, pattern, mode); + const u32 result = evf->pattern.fetch_op(event_flag_try_poll, pattern, mode); if (event_flag_test(result, pattern, mode)) { // save pattern - context.GPR[0] = SCE_OK; - context.GPR[1] = result; + cpu.GPR[0] = SCE_OK; + cpu.GPR[1] = result; - context.signal(); + thread->state += cpu_state::signal; + thread->cv.notify_one(); return true; } @@ -584,7 +576,7 @@ s32 sceKernelSetEventFlag(s32 evfId, u32 bitPattern) return SCE_OK; } -s32 sceKernelClearEventFlag(s32 evfId, u32 bitPattern) +arm_error_code sceKernelClearEventFlag(s32 evfId, u32 bitPattern) { sceLibKernel.error("sceKernelClearEventFlag(evfId=0x%x, bitPattern=0x%x)", evfId, bitPattern); @@ -602,7 +594,7 @@ s32 sceKernelClearEventFlag(s32 evfId, u32 bitPattern) return SCE_OK; } -s32 sceKernelCancelEventFlag(s32 evfId, u32 setPattern, vm::ptr pNumWaitThreads) +arm_error_code sceKernelCancelEventFlag(s32 evfId, u32 setPattern, vm::ptr pNumWaitThreads) { sceLibKernel.error("sceKernelCancelEventFlag(evfId=0x%x, setPattern=0x%x, pNumWaitThreads=*0x%x)", evfId, setPattern, pNumWaitThreads); @@ -619,7 +611,8 @@ s32 sceKernelCancelEventFlag(s32 evfId, u32 setPattern, vm::ptr pNumWaitThr { static_cast(*thread).GPR[0] = SCE_KERNEL_ERROR_WAIT_CANCEL; static_cast(*thread).GPR[1] = setPattern; - thread->signal(); + thread->state += cpu_state::signal; + thread->cv.notify_one(); } *pNumWaitThreads = static_cast(evf->sq.size()); @@ -630,7 +623,7 @@ s32 sceKernelCancelEventFlag(s32 evfId, u32 setPattern, vm::ptr pNumWaitThr return SCE_OK; } -s32 sceKernelGetEventFlagInfo(s32 evfId, vm::ptr pInfo) +arm_error_code sceKernelGetEventFlagInfo(s32 evfId, vm::ptr pInfo) { sceLibKernel.error("sceKernelGetEventFlagInfo(evfId=0x%x, pInfo=*0x%x)", evfId, pInfo); @@ -658,14 +651,14 @@ s32 sceKernelGetEventFlagInfo(s32 evfId, vm::ptr pInfo) // Semaphore functions -s32 sceKernelCreateSema(vm::cptr pName, u32 attr, s32 initCount, s32 maxCount, vm::cptr pOptParam) +arm_error_code sceKernelCreateSema(vm::cptr pName, u32 attr, s32 initCount, s32 maxCount, vm::cptr pOptParam) { sceLibKernel.error("sceKernelCreateSema(pName=*0x%x, attr=0x%x, initCount=%d, maxCount=%d, pOptParam=*0x%x)", pName, attr, initCount, maxCount, pOptParam); - return idm::make(pName.get_ptr(), attr, initCount, maxCount); + return NOT_AN_ERROR(idm::make(pName.get_ptr(), attr, initCount, maxCount)); } -s32 sceKernelDeleteSema(s32 semaId) +arm_error_code sceKernelDeleteSema(s32 semaId) { sceLibKernel.error("sceKernelDeleteSema(semaId=0x%x)", semaId); @@ -691,7 +684,7 @@ s32 sceKernelCloseSema(s32 semaId) throw EXCEPTION(""); } -s32 sceKernelWaitSema(s32 semaId, s32 needCount, vm::ptr pTimeout) +arm_error_code sceKernelWaitSema(s32 semaId, s32 needCount, vm::ptr pTimeout) { sceLibKernel.error("sceKernelWaitSema(semaId=0x%x, needCount=%d, pTimeout=*0x%x)", semaId, needCount, pTimeout); @@ -734,14 +727,14 @@ s32 sceKernelGetSemaInfo(s32 semaId, vm::ptr pInfo) // Mutex functions -s32 sceKernelCreateMutex(vm::cptr pName, u32 attr, s32 initCount, vm::cptr pOptParam) +arm_error_code sceKernelCreateMutex(vm::cptr pName, u32 attr, s32 initCount, vm::cptr pOptParam) { sceLibKernel.error("sceKernelCreateMutex(pName=*0x%x, attr=0x%x, initCount=%d, pOptParam=*0x%x)", pName, attr, initCount, pOptParam); - return idm::make(pName.get_ptr(), attr, initCount); + return NOT_AN_ERROR(idm::make(pName.get_ptr(), attr, initCount)); } -s32 sceKernelDeleteMutex(s32 mutexId) +arm_error_code sceKernelDeleteMutex(s32 mutexId) { sceLibKernel.error("sceKernelDeleteMutex(mutexId=0x%x)", mutexId); @@ -841,7 +834,7 @@ s32 sceKernelGetLwMutexInfoById(s32 lwMutexId, vm::ptr pIn // Condition variable functions -s32 sceKernelCreateCond(vm::cptr pName, u32 attr, s32 mutexId, vm::cptr pOptParam) +arm_error_code sceKernelCreateCond(vm::cptr pName, u32 attr, s32 mutexId, vm::cptr pOptParam) { sceLibKernel.error("sceKernelCreateCond(pName=*0x%x, attr=0x%x, mutexId=0x%x, pOptParam=*0x%x)", pName, attr, mutexId, pOptParam); @@ -852,10 +845,10 @@ s32 sceKernelCreateCond(vm::cptr pName, u32 attr, s32 mutexId, vm::cptr(pName.get_ptr(), attr, mutex); + return NOT_AN_ERROR(idm::make(pName.get_ptr(), attr, mutex)); } -s32 sceKernelDeleteCond(s32 condId) +arm_error_code sceKernelDeleteCond(s32 condId) { sceLibKernel.error("sceKernelDeleteCond(condId=0x%x)", condId); @@ -1227,15 +1220,10 @@ s32 sceIoGetstat(vm::cptr name, vm::ptr buf) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceLibKernel, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceLibKernel, nid, name) -psv_log_base sceLibKernel("sceLibKernel", []() +DECLARE(arm_module_manager::SceLibKernel)("SceLibKernel", []() { - sceLibKernel.on_load = nullptr; - sceLibKernel.on_unload = nullptr; - sceLibKernel.on_stop = nullptr; - //sceLibKernel.on_error = nullptr; // keep default error handler - // REG_FUNC(???, sceKernelGetEventInfo); //REG_FUNC(0x023EAA62, sceKernelPuts); @@ -1544,62 +1532,91 @@ psv_log_base sceLibKernel("sceLibKernel", []() //REG_FUNC(0x963F4A99, sceSblACMgrIsGameProgram); //REG_FUNC(0x261E2C34, sceKernelGetOpenPsId); - /* SceModulemgr */ - //REG_FUNC(0x36585DAF, sceKernelGetModuleInfo); - //REG_FUNC(0x2EF2581F, sceKernelGetModuleList); - //REG_FUNC(0xF5798C7C, sceKernelGetModuleIdByAddr); - - /* SceProcessmgr */ - //REG_FUNC(0xCD248267, sceKernelGetCurrentProcess); - //REG_FUNC(0x2252890C, sceKernelPowerTick); - //REG_FUNC(0x9E45DA09, sceKernelLibcClock); - //REG_FUNC(0x0039BE45, sceKernelLibcTime); - //REG_FUNC(0x4B879059, sceKernelLibcGettimeofday); - //REG_FUNC(0xC1727F59, sceKernelGetStdin); - //REG_FUNC(0xE5AA625C, sceKernelGetStdout); - //REG_FUNC(0xFA5E3ADA, sceKernelGetStderr); - //REG_FUNC(0xE6E9FCA3, sceKernelGetRemoteProcessTime); - //REG_FUNC(0xD37A8437, sceKernelGetProcessTime); - //REG_FUNC(0xF5D0D4C6, sceKernelGetProcessTimeLow); - //REG_FUNC(0x89DA0967, sceKernelGetProcessTimeWide); - //REG_FUNC(0x2BE3E066, sceKernelGetProcessParam); - - /* SceStdio */ - //REG_FUNC(0x54237407, sceKernelStdin); - //REG_FUNC(0x9033E9BD, sceKernelStdout); - //REG_FUNC(0x35EE7CF5, sceKernelStderr); - - /* SceSysmem */ - REG_FUNC(0xB9D5EBDE, sceKernelAllocMemBlock); - REG_FUNC(0xA91E15EE, sceKernelFreeMemBlock); - REG_FUNC(0xB8EF5818, sceKernelGetMemBlockBase); - //REG_FUNC(0x3B29E0F5, sceKernelRemapMemBlock); - //REG_FUNC(0xA33B99D1, sceKernelFindMemBlockByAddr); - REG_FUNC(0x4010AD65, sceKernelGetMemBlockInfoByAddr); - - /* SceCpu */ - //REG_FUNC(0x2704CFEE, sceKernelCpuId); - - /* SceDipsw */ - //REG_FUNC(0x1C783FB2, sceKernelCheckDipsw); - //REG_FUNC(0x817053D4, sceKernelSetDipsw); - //REG_FUNC(0x800EDCC1, sceKernelClearDipsw); - - /* SceThreadmgr */ - REG_FUNC(0x0C8A38E1, sceKernelExitThread); - REG_FUNC(0x1D17DECF, sceKernelExitDeleteThread); - REG_FUNC(0x4B675D05, sceKernelDelayThread); - REG_FUNC(0x9C0180E1, sceKernelDelayThreadCB); - //REG_FUNC(0x001173F8, sceKernelChangeActiveCpuMask); - REG_FUNC(0x01414F0B, sceKernelGetThreadCurrentPriority); - REG_FUNC(0x751C9B7A, sceKernelChangeCurrentThreadAttr); - REG_FUNC(0xD9BD74EB, sceKernelCheckWaitableStatus); - REG_FUNC(0x9DCB4B7A, sceKernelGetProcessId); - REG_FUNC(0xE53E41F6, sceKernelCheckCallback); - REG_FUNC(0xF4EE4FA9, sceKernelGetSystemTimeWide); - REG_FUNC(0x47F6DE49, sceKernelGetSystemTimeLow); - //REG_FUNC(0xC0FAF6A3, sceKernelCreateThreadForUser); - - /* SceDebugLed */ - //REG_FUNC(0x78E702D3, sceKernelSetGPO); + //REG_FUNC(0x4C4672BF, sceKernelGetProcessTime); // !!! +}); + +DECLARE(arm_module_manager::SceIofilemgr)("SceIofilemgr", []() +{ + REG_FNID(SceIofilemgr, 0x34EFD876, sceIoWrite); // !!! + REG_FNID(SceIofilemgr, 0xC70B8886, sceIoClose); // !!! + REG_FNID(SceIofilemgr, 0xFDB32293, sceIoRead); // !!! +}); + +DECLARE(arm_module_manager::SceModulemgr)("SceModulemgr", []() +{ + //REG_FNID(SceModulemgr, 0x36585DAF, sceKernelGetModuleInfo); + //REG_FNID(SceModulemgr, 0x2EF2581F, sceKernelGetModuleList); + //REG_FNID(SceModulemgr, 0xF5798C7C, sceKernelGetModuleIdByAddr); +}); + +DECLARE(arm_module_manager::SceProcessmgr)("SceProcessmgr", []() +{ + //REG_FNID(SceProcessmgr, 0xCD248267, sceKernelGetCurrentProcess); + //REG_FNID(SceProcessmgr, 0x2252890C, sceKernelPowerTick); + //REG_FNID(SceProcessmgr, 0x9E45DA09, sceKernelLibcClock); + //REG_FNID(SceProcessmgr, 0x0039BE45, sceKernelLibcTime); + //REG_FNID(SceProcessmgr, 0x4B879059, sceKernelLibcGettimeofday); + //REG_FNID(SceProcessmgr, 0xC1727F59, sceKernelGetStdin); + //REG_FNID(SceProcessmgr, 0xE5AA625C, sceKernelGetStdout); + //REG_FNID(SceProcessmgr, 0xFA5E3ADA, sceKernelGetStderr); + //REG_FNID(SceProcessmgr, 0xE6E9FCA3, sceKernelGetRemoteProcessTime); + //REG_FNID(SceProcessmgr, 0xD37A8437, sceKernelGetProcessTime); + //REG_FNID(SceProcessmgr, 0xF5D0D4C6, sceKernelGetProcessTimeLow); + //REG_FNID(SceProcessmgr, 0x89DA0967, sceKernelGetProcessTimeWide); + //REG_FNID(SceProcessmgr, 0x2BE3E066, sceKernelGetProcessParam); +}); + +DECLARE(arm_module_manager::SceStdio)("SceStdio", []() +{ + //REG_FNID(SceStdio, 0x54237407, sceKernelStdin); + //REG_FNID(SceStdio, 0x9033E9BD, sceKernelStdout); + //REG_FNID(SceStdio, 0x35EE7CF5, sceKernelStderr); +}); + +DECLARE(arm_module_manager::SceSysmem)("SceSysmem", []() +{ + REG_FNID(SceSysmem, 0xB9D5EBDE, sceKernelAllocMemBlock); + REG_FNID(SceSysmem, 0xA91E15EE, sceKernelFreeMemBlock); + REG_FNID(SceSysmem, 0xB8EF5818, sceKernelGetMemBlockBase); + //REG_FNID(SceSysmem, 0x3B29E0F5, sceKernelRemapMemBlock); + //REG_FNID(SceSysmem, 0xA33B99D1, sceKernelFindMemBlockByAddr); + REG_FNID(SceSysmem, 0x4010AD65, sceKernelGetMemBlockInfoByAddr); +}); + +DECLARE(arm_module_manager::SceCpu)("SceCpu", []() +{ + //REG_FNID(SceCpu, 0x2704CFEE, sceKernelCpuId); +}); + +DECLARE(arm_module_manager::SceDipsw)("SceDipsw", []() +{ + //REG_FNID(SceDipsw, 0x1C783FB2, sceKernelCheckDipsw); + //REG_FNID(SceDipsw, 0x817053D4, sceKernelSetDipsw); + //REG_FNID(SceDipsw, 0x800EDCC1, sceKernelClearDipsw); +}); + +DECLARE(arm_module_manager::SceThreadmgr)("SceThreadmgr", []() +{ + REG_FNID(SceThreadmgr, 0x0C8A38E1, sceKernelExitThread); + REG_FNID(SceThreadmgr, 0x1D17DECF, sceKernelExitDeleteThread); + REG_FNID(SceThreadmgr, 0x4B675D05, sceKernelDelayThread); + REG_FNID(SceThreadmgr, 0x9C0180E1, sceKernelDelayThreadCB); + REG_FNID(SceThreadmgr, 0x1BBDE3D9, sceKernelDeleteThread); // !!! + //REG_FNID(SceThreadmgr, 0x001173F8, sceKernelChangeActiveCpuMask); + REG_FNID(SceThreadmgr, 0x01414F0B, sceKernelGetThreadCurrentPriority); + REG_FNID(SceThreadmgr, 0x751C9B7A, sceKernelChangeCurrentThreadAttr); + REG_FNID(SceThreadmgr, 0xD9BD74EB, sceKernelCheckWaitableStatus); + REG_FNID(SceThreadmgr, 0x9DCB4B7A, sceKernelGetProcessId); + REG_FNID(SceThreadmgr, 0xB19CF7E9, sceKernelCreateCallback); // !!! + REG_FNID(SceThreadmgr, 0xD469676B, sceKernelDeleteCallback); // !!! + REG_FNID(SceThreadmgr, 0xE53E41F6, sceKernelCheckCallback); + REG_FNID(SceThreadmgr, 0xF4EE4FA9, sceKernelGetSystemTimeWide); + REG_FNID(SceThreadmgr, 0x47F6DE49, sceKernelGetSystemTimeLow); + //REG_FNID(SceThreadmgr, 0xC0FAF6A3, sceKernelCreateThreadForUser); + REG_FNID(SceThreadmgr, 0xF1AE5654, sceKernelGetThreadCpuAffinityMask); // !!! +}); + +DECLARE(arm_module_manager::SceDebugLed)("SceDebugLed", []() +{ + //REG_FNID(SceDebugLed, 0x78E702D3, sceKernelSetGPO); }); diff --git a/rpcs3/Emu/ARMv7/Modules/sceLibKernel.h b/rpcs3/Emu/ARMv7/Modules/sceLibKernel.h index 1ba6f3a4ca..a94a7ba760 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceLibKernel.h +++ b/rpcs3/Emu/ARMv7/Modules/sceLibKernel.h @@ -1,258 +1,540 @@ #pragma once #include "Utilities/SleepQueue.h" +#include "Emu/ARMv7/ErrorCodes.h" // Error Codes -enum +enum SceLibKernelError : s32 { - SCE_KERNEL_ERROR_ERROR = 0x80020001, - SCE_KERNEL_ERROR_NOT_IMPLEMENTED = 0x80020002, - SCE_KERNEL_ERROR_INVALID_ARGUMENT = 0x80020003, - SCE_KERNEL_ERROR_INVALID_ARGUMENT_SIZE = 0x80020004, - SCE_KERNEL_ERROR_INVALID_FLAGS = 0x80020005, - SCE_KERNEL_ERROR_ILLEGAL_SIZE = 0x80020006, - SCE_KERNEL_ERROR_ILLEGAL_ADDR = 0x80020007, - SCE_KERNEL_ERROR_UNSUP = 0x80020008, - SCE_KERNEL_ERROR_ILLEGAL_MODE = 0x80020009, - SCE_KERNEL_ERROR_ILLEGAL_ALIGNMENT = 0x8002000A, - SCE_KERNEL_ERROR_NOSYS = 0x8002000B, - SCE_KERNEL_ERROR_DEBUG_ERROR = 0x80021000, - SCE_KERNEL_ERROR_ILLEGAL_DIPSW_NUMBER = 0x80021001, - SCE_KERNEL_ERROR_CPU_ERROR = 0x80022000, - SCE_KERNEL_ERROR_MMU_ILLEGAL_L1_TYPE = 0x80022001, - SCE_KERNEL_ERROR_MMU_L2_INDEX_OVERFLOW = 0x80022002, - SCE_KERNEL_ERROR_MMU_L2_SIZE_OVERFLOW = 0x80022003, - SCE_KERNEL_ERROR_INVALID_CPU_AFFINITY = 0x80022004, - SCE_KERNEL_ERROR_INVALID_MEMORY_ACCESS = 0x80022005, - SCE_KERNEL_ERROR_INVALID_MEMORY_ACCESS_PERMISSION = 0x80022006, - SCE_KERNEL_ERROR_VA2PA_FAULT = 0x80022007, - SCE_KERNEL_ERROR_VA2PA_MAPPED = 0x80022008, - SCE_KERNEL_ERROR_VALIDATION_CHECK_FAILED = 0x80022009, - SCE_KERNEL_ERROR_SYSMEM_ERROR = 0x80024000, - SCE_KERNEL_ERROR_INVALID_PROCESS_CONTEXT = 0x80024001, - SCE_KERNEL_ERROR_UID_NAME_TOO_LONG = 0x80024002, - SCE_KERNEL_ERROR_VARANGE_IS_NOT_PHYSICAL_CONTINUOUS = 0x80024003, - SCE_KERNEL_ERROR_PHYADDR_ERROR = 0x80024100, - SCE_KERNEL_ERROR_NO_PHYADDR = 0x80024101, - SCE_KERNEL_ERROR_PHYADDR_USED = 0x80024102, - SCE_KERNEL_ERROR_PHYADDR_NOT_USED = 0x80024103, - SCE_KERNEL_ERROR_NO_IOADDR = 0x80024104, - SCE_KERNEL_ERROR_PHYMEM_ERROR = 0x80024300, - SCE_KERNEL_ERROR_ILLEGAL_PHYPAGE_STATUS = 0x80024301, - SCE_KERNEL_ERROR_NO_FREE_PHYSICAL_PAGE = 0x80024302, - SCE_KERNEL_ERROR_NO_FREE_PHYSICAL_PAGE_UNIT = 0x80024303, - SCE_KERNEL_ERROR_PHYMEMPART_NOT_EMPTY = 0x80024304, - SCE_KERNEL_ERROR_NO_PHYMEMPART_LPDDR2 = 0x80024305, - SCE_KERNEL_ERROR_NO_PHYMEMPART_CDRAM = 0x80024306, - SCE_KERNEL_ERROR_FIXEDHEAP_ERROR = 0x80024400, - SCE_KERNEL_ERROR_FIXEDHEAP_ILLEGAL_SIZE = 0x80024401, - SCE_KERNEL_ERROR_FIXEDHEAP_ILLEGAL_INDEX = 0x80024402, - SCE_KERNEL_ERROR_FIXEDHEAP_INDEX_OVERFLOW = 0x80024403, - SCE_KERNEL_ERROR_FIXEDHEAP_NO_CHUNK = 0x80024404, - SCE_KERNEL_ERROR_UID_ERROR = 0x80024500, - SCE_KERNEL_ERROR_INVALID_UID = 0x80024501, - SCE_KERNEL_ERROR_SYSMEM_UID_INVALID_ARGUMENT = 0x80024502, - SCE_KERNEL_ERROR_SYSMEM_INVALID_UID_RANGE = 0x80024503, - SCE_KERNEL_ERROR_SYSMEM_NO_VALID_UID = 0x80024504, - SCE_KERNEL_ERROR_SYSMEM_CANNOT_ALLOCATE_UIDENTRY = 0x80024505, - SCE_KERNEL_ERROR_NOT_PROCESS_UID = 0x80024506, - SCE_KERNEL_ERROR_NOT_KERNEL_UID = 0x80024507, - SCE_KERNEL_ERROR_INVALID_UID_CLASS = 0x80024508, - SCE_KERNEL_ERROR_INVALID_UID_SUBCLASS = 0x80024509, - SCE_KERNEL_ERROR_UID_CANNOT_FIND_BY_NAME = 0x8002450A, - SCE_KERNEL_ERROR_VIRPAGE_ERROR = 0x80024600, - SCE_KERNEL_ERROR_ILLEGAL_VIRPAGE_TYPE = 0x80024601, - SCE_KERNEL_ERROR_BLOCK_ERROR = 0x80024700, - SCE_KERNEL_ERROR_ILLEGAL_BLOCK_ID = 0x80024701, - SCE_KERNEL_ERROR_ILLEGAL_BLOCK_TYPE = 0x80024702, - SCE_KERNEL_ERROR_BLOCK_IN_USE = 0x80024703, - SCE_KERNEL_ERROR_PARTITION_ERROR = 0x80024800, - SCE_KERNEL_ERROR_ILLEGAL_PARTITION_ID = 0x80024801, - SCE_KERNEL_ERROR_ILLEGAL_PARTITION_INDEX = 0x80024802, - SCE_KERNEL_ERROR_NO_L2PAGETABLE = 0x80024803, - SCE_KERNEL_ERROR_HEAPLIB_ERROR = 0x80024900, - SCE_KERNEL_ERROR_ILLEGAL_HEAP_ID = 0x80024901, - SCE_KERNEL_ERROR_OUT_OF_RANG = 0x80024902, - SCE_KERNEL_ERROR_HEAPLIB_NOMEM = 0x80024903, - SCE_KERNEL_ERROR_SYSMEM_ADDRESS_SPACE_ERROR = 0x80024A00, - SCE_KERNEL_ERROR_INVALID_ADDRESS_SPACE_ID = 0x80024A01, - SCE_KERNEL_ERROR_INVALID_PARTITION_INDEX = 0x80024A02, - SCE_KERNEL_ERROR_ADDRESS_SPACE_CANNOT_FIND_PARTITION_BY_ADDR = 0x80024A03, - SCE_KERNEL_ERROR_SYSMEM_MEMBLOCK_ERROR = 0x80024B00, - SCE_KERNEL_ERROR_ILLEGAL_MEMBLOCK_TYPE = 0x80024B01, - SCE_KERNEL_ERROR_ILLEGAL_MEMBLOCK_REMAP_TYPE = 0x80024B02, - SCE_KERNEL_ERROR_NOT_PHY_CONT_MEMBLOCK = 0x80024B03, - SCE_KERNEL_ERROR_ILLEGAL_MEMBLOCK_CODE = 0x80024B04, - SCE_KERNEL_ERROR_ILLEGAL_MEMBLOCK_SIZE = 0x80024B05, - SCE_KERNEL_ERROR_ILLEGAL_USERMAP_SIZE = 0x80024B06, - SCE_KERNEL_ERROR_MEMBLOCK_TYPE_FOR_KERNEL_PROCESS = 0x80024B07, - SCE_KERNEL_ERROR_PROCESS_CANNOT_REMAP_MEMBLOCK = 0x80024B08, - SCE_KERNEL_ERROR_SYSMEM_PHYMEMLOW_ERROR = 0x80024C00, - SCE_KERNEL_ERROR_CANNOT_ALLOC_PHYMEMLOW = 0x80024C01, - SCE_KERNEL_ERROR_UNKNOWN_PHYMEMLOW_TYPE = 0x80024C02, - SCE_KERNEL_ERROR_SYSMEM_BITHEAP_ERROR = 0x80024D00, - SCE_KERNEL_ERROR_CANNOT_ALLOC_BITHEAP = 0x80024D01, - SCE_KERNEL_ERROR_LOADCORE_ERROR = 0x80025000, - SCE_KERNEL_ERROR_ILLEGAL_ELF_HEADER = 0x80025001, - SCE_KERNEL_ERROR_ILLEGAL_SELF_HEADER = 0x80025002, - SCE_KERNEL_ERROR_EXCPMGR_ERROR = 0x80027000, - SCE_KERNEL_ERROR_ILLEGAL_EXCPCODE = 0x80027001, - SCE_KERNEL_ERROR_ILLEGAL_EXCPHANDLER = 0x80027002, - SCE_KERNEL_ERROR_NOTFOUND_EXCPHANDLER = 0x80027003, - SCE_KERNEL_ERROR_CANNOT_RELEASE_EXCPHANDLER = 0x80027004, - SCE_KERNEL_ERROR_INTRMGR_ERROR = 0x80027100, - SCE_KERNEL_ERROR_ILLEGAL_CONTEXT = 0x80027101, - SCE_KERNEL_ERROR_ILLEGAL_INTRCODE = 0x80027102, - SCE_KERNEL_ERROR_ILLEGAL_INTRPARAM = 0x80027103, - SCE_KERNEL_ERROR_ILLEGAL_INTRPRIORITY = 0x80027104, - SCE_KERNEL_ERROR_ILLEGAL_TARGET_CPU = 0x80027105, - SCE_KERNEL_ERROR_ILLEGAL_INTRFILTER = 0x80027106, - SCE_KERNEL_ERROR_ILLEGAL_INTRTYPE = 0x80027107, - SCE_KERNEL_ERROR_ILLEGAL_HANDLER = 0x80027108, - SCE_KERNEL_ERROR_FOUND_HANDLER = 0x80027109, - SCE_KERNEL_ERROR_NOTFOUND_HANDLER = 0x8002710A, - SCE_KERNEL_ERROR_NO_MEMORY = 0x8002710B, - SCE_KERNEL_ERROR_DMACMGR_ERROR = 0x80027200, - SCE_KERNEL_ERROR_ALREADY_QUEUED = 0x80027201, - SCE_KERNEL_ERROR_NOT_QUEUED = 0x80027202, - SCE_KERNEL_ERROR_NOT_SETUP = 0x80027203, - SCE_KERNEL_ERROR_ON_TRANSFERRING = 0x80027204, - SCE_KERNEL_ERROR_NOT_INITIALIZED = 0x80027205, - SCE_KERNEL_ERROR_TRANSFERRED = 0x80027206, - SCE_KERNEL_ERROR_NOT_UNDER_CONTROL = 0x80027207, - SCE_KERNEL_ERROR_SYSTIMER_ERROR = 0x80027300, - SCE_KERNEL_ERROR_NO_FREE_TIMER = 0x80027301, - SCE_KERNEL_ERROR_TIMER_NOT_ALLOCATED = 0x80027302, - SCE_KERNEL_ERROR_TIMER_COUNTING = 0x80027303, - SCE_KERNEL_ERROR_TIMER_STOPPED = 0x80027304, - SCE_KERNEL_ERROR_THREADMGR_ERROR = 0x80028000, - SCE_KERNEL_ERROR_DORMANT = 0x80028001, - SCE_KERNEL_ERROR_NOT_DORMANT = 0x80028002, - SCE_KERNEL_ERROR_UNKNOWN_THID = 0x80028003, - SCE_KERNEL_ERROR_CAN_NOT_WAIT = 0x80028004, - SCE_KERNEL_ERROR_ILLEGAL_THID = 0x80028005, - SCE_KERNEL_ERROR_THREAD_TERMINATED = 0x80028006, - SCE_KERNEL_ERROR_DELETED = 0x80028007, - SCE_KERNEL_ERROR_WAIT_TIMEOUT = 0x80028008, - SCE_KERNEL_ERROR_NOTIFY_CALLBACK = 0x80028009, - SCE_KERNEL_ERROR_WAIT_DELETE = 0x8002800A, - SCE_KERNEL_ERROR_ILLEGAL_ATTR = 0x8002800B, - SCE_KERNEL_ERROR_EVF_MULTI = 0x8002800C, - SCE_KERNEL_ERROR_WAIT_CANCEL = 0x8002800D, - SCE_KERNEL_ERROR_EVF_COND = 0x8002800E, - SCE_KERNEL_ERROR_ILLEGAL_COUNT = 0x8002800F, - SCE_KERNEL_ERROR_ILLEGAL_PRIORITY = 0x80028010, - SCE_KERNEL_ERROR_MUTEX_RECURSIVE = 0x80028011, - SCE_KERNEL_ERROR_MUTEX_LOCK_OVF = 0x80028012, - SCE_KERNEL_ERROR_MUTEX_NOT_OWNED = 0x80028013, - SCE_KERNEL_ERROR_MUTEX_UNLOCK_UDF = 0x80028014, - SCE_KERNEL_ERROR_MUTEX_FAILED_TO_OWN = 0x80028015, - SCE_KERNEL_ERROR_FAST_MUTEX_RECURSIVE = 0x80028016, - SCE_KERNEL_ERROR_FAST_MUTEX_LOCK_OVF = 0x80028017, - SCE_KERNEL_ERROR_FAST_MUTEX_FAILED_TO_OWN = 0x80028018, - SCE_KERNEL_ERROR_FAST_MUTEX_NOT_OWNED = 0x80028019, - SCE_KERNEL_ERROR_FAST_MUTEX_OWNED = 0x8002801A, - SCE_KERNEL_ERROR_ALARM_CAN_NOT_CANCEL = 0x8002801B, - SCE_KERNEL_ERROR_INVALID_OBJECT_TYPE = 0x8002801C, - SCE_KERNEL_ERROR_KERNEL_TLS_FULL = 0x8002801D, - SCE_KERNEL_ERROR_ILLEGAL_KERNEL_TLS_INDEX = 0x8002801E, - SCE_KERNEL_ERROR_KERNEL_TLS_BUSY = 0x8002801F, - SCE_KERNEL_ERROR_DIFFERENT_UID_CLASS = 0x80028020, - SCE_KERNEL_ERROR_UNKNOWN_UID = 0x80028021, - SCE_KERNEL_ERROR_SEMA_ZERO = 0x80028022, - SCE_KERNEL_ERROR_SEMA_OVF = 0x80028023, - SCE_KERNEL_ERROR_PMON_NOT_THREAD_MODE = 0x80028024, - SCE_KERNEL_ERROR_PMON_NOT_CPU_MODE = 0x80028025, - SCE_KERNEL_ERROR_ALREADY_REGISTERED = 0x80028026, - SCE_KERNEL_ERROR_INVALID_THREAD_ID = 0x80028027, - SCE_KERNEL_ERROR_ALREADY_DEBUG_SUSPENDED = 0x80028028, - SCE_KERNEL_ERROR_NOT_DEBUG_SUSPENDED = 0x80028029, - SCE_KERNEL_ERROR_CAN_NOT_USE_VFP = 0x8002802A, - SCE_KERNEL_ERROR_RUNNING = 0x8002802B, - SCE_KERNEL_ERROR_EVENT_COND = 0x8002802C, - SCE_KERNEL_ERROR_MSG_PIPE_FULL = 0x8002802D, - SCE_KERNEL_ERROR_MSG_PIPE_EMPTY = 0x8002802E, - SCE_KERNEL_ERROR_ALREADY_SENT = 0x8002802F, - SCE_KERNEL_ERROR_CAN_NOT_SUSPEND = 0x80028030, - SCE_KERNEL_ERROR_FAST_MUTEX_ALREADY_INITIALIZED = 0x80028031, - SCE_KERNEL_ERROR_FAST_MUTEX_NOT_INITIALIZED = 0x80028032, - SCE_KERNEL_ERROR_THREAD_STOPPED = 0x80028033, - SCE_KERNEL_ERROR_THREAD_SUSPENDED = 0x80028034, - SCE_KERNEL_ERROR_NOT_SUSPENDED = 0x80028035, - SCE_KERNEL_ERROR_WAIT_DELETE_MUTEX = 0x80028036, - SCE_KERNEL_ERROR_WAIT_CANCEL_MUTEX = 0x80028037, - SCE_KERNEL_ERROR_WAIT_DELETE_COND = 0x80028038, - SCE_KERNEL_ERROR_WAIT_CANCEL_COND = 0x80028039, - SCE_KERNEL_ERROR_LW_MUTEX_NOT_OWNED = 0x8002803A, - SCE_KERNEL_ERROR_LW_MUTEX_LOCK_OVF = 0x8002803B, - SCE_KERNEL_ERROR_LW_MUTEX_UNLOCK_UDF = 0x8002803C, - SCE_KERNEL_ERROR_LW_MUTEX_RECURSIVE = 0x8002803D, - SCE_KERNEL_ERROR_LW_MUTEX_FAILED_TO_OWN = 0x8002803E, - SCE_KERNEL_ERROR_WAIT_DELETE_LW_MUTEX = 0x8002803F, - SCE_KERNEL_ERROR_ILLEGAL_STACK_SIZE = 0x80028040, - SCE_KERNEL_ERROR_RW_LOCK_RECURSIVE = 0x80028041, - SCE_KERNEL_ERROR_RW_LOCK_LOCK_OVF = 0x80028042, - SCE_KERNEL_ERROR_RW_LOCK_NOT_OWNED = 0x80028043, - SCE_KERNEL_ERROR_RW_LOCK_UNLOCK_UDF = 0x80028044, - SCE_KERNEL_ERROR_RW_LOCK_FAILED_TO_LOCK = 0x80028045, - SCE_KERNEL_ERROR_RW_LOCK_FAILED_TO_UNLOCK = 0x80028046, - - SCE_KERNEL_ERROR_PROCESSMGR_ERROR = 0x80029000, - SCE_KERNEL_ERROR_INVALID_PID = 0x80029001, - SCE_KERNEL_ERROR_INVALID_PROCESS_TYPE = 0x80029002, - SCE_KERNEL_ERROR_PLS_FULL = 0x80029003, - SCE_KERNEL_ERROR_INVALID_PROCESS_STATUS = 0x80029004, - SCE_KERNEL_ERROR_INVALID_BUDGET_ID = 0x80029005, - SCE_KERNEL_ERROR_INVALID_BUDGET_SIZE = 0x80029006, - SCE_KERNEL_ERROR_CP14_DISABLED = 0x80029007, - SCE_KERNEL_ERROR_EXCEEDED_MAX_PROCESSES = 0x80029008, - SCE_KERNEL_ERROR_PROCESS_REMAINING = 0x80029009, - SCE_KERNEL_ERROR_IOFILEMGR_ERROR = 0x8002A000, - SCE_KERNEL_ERROR_IO_NAME_TOO_LONG = 0x8002A001, - SCE_KERNEL_ERROR_IO_REG_DEV = 0x8002A002, - SCE_KERNEL_ERROR_IO_ALIAS_USED = 0x8002A003, - SCE_KERNEL_ERROR_IO_DEL_DEV = 0x8002A004, - SCE_KERNEL_ERROR_IO_WOULD_BLOCK = 0x8002A005, - SCE_KERNEL_ERROR_MODULEMGR_START_FAILED = 0x8002D000, - SCE_KERNEL_ERROR_MODULEMGR_STOP_FAIL = 0x8002D001, - SCE_KERNEL_ERROR_MODULEMGR_IN_USE = 0x8002D002, - SCE_KERNEL_ERROR_MODULEMGR_NO_LIB = 0x8002D003, - SCE_KERNEL_ERROR_MODULEMGR_SYSCALL_REG = 0x8002D004, - SCE_KERNEL_ERROR_MODULEMGR_NOMEM_LIB = 0x8002D005, - SCE_KERNEL_ERROR_MODULEMGR_NOMEM_STUB = 0x8002D006, - SCE_KERNEL_ERROR_MODULEMGR_NOMEM_SELF = 0x8002D007, - SCE_KERNEL_ERROR_MODULEMGR_NOMEM = 0x8002D008, - SCE_KERNEL_ERROR_MODULEMGR_INVALID_LIB = 0x8002D009, - SCE_KERNEL_ERROR_MODULEMGR_INVALID_STUB = 0x8002D00A, - SCE_KERNEL_ERROR_MODULEMGR_NO_FUNC_NID = 0x8002D00B, - SCE_KERNEL_ERROR_MODULEMGR_NO_VAR_NID = 0x8002D00C, - SCE_KERNEL_ERROR_MODULEMGR_INVALID_TYPE = 0x8002D00D, - SCE_KERNEL_ERROR_MODULEMGR_NO_MOD_ENTRY = 0x8002D00E, - SCE_KERNEL_ERROR_MODULEMGR_INVALID_PROC_PARAM = 0x8002D00F, - SCE_KERNEL_ERROR_MODULEMGR_NO_MODOBJ = 0x8002D010, - SCE_KERNEL_ERROR_MODULEMGR_NO_MOD = 0x8002D011, - SCE_KERNEL_ERROR_MODULEMGR_NO_PROCESS = 0x8002D012, - SCE_KERNEL_ERROR_MODULEMGR_OLD_LIB = 0x8002D013, - SCE_KERNEL_ERROR_MODULEMGR_STARTED = 0x8002D014, - SCE_KERNEL_ERROR_MODULEMGR_NOT_STARTED = 0x8002D015, - SCE_KERNEL_ERROR_MODULEMGR_NOT_STOPPED = 0x8002D016, - SCE_KERNEL_ERROR_MODULEMGR_INVALID_PROCESS_UID = 0x8002D017, - SCE_KERNEL_ERROR_MODULEMGR_CANNOT_EXPORT_LIB_TO_SHARED = 0x8002D018, - SCE_KERNEL_ERROR_MODULEMGR_INVALID_REL_INFO = 0x8002D019, - SCE_KERNEL_ERROR_MODULEMGR_INVALID_REF_INFO = 0x8002D01A, - SCE_KERNEL_ERROR_MODULEMGR_ELINK = 0x8002D01B, - SCE_KERNEL_ERROR_MODULEMGR_NOENT = 0x8002D01C, - SCE_KERNEL_ERROR_MODULEMGR_BUSY = 0x8002D01D, - SCE_KERNEL_ERROR_MODULEMGR_NOEXEC = 0x8002D01E, - SCE_KERNEL_ERROR_MODULEMGR_NAMETOOLONG = 0x8002D01F, - SCE_KERNEL_ERROR_LIBRARYDB_NOENT = 0x8002D080, - SCE_KERNEL_ERROR_LIBRARYDB_NO_LIB = 0x8002D081, - SCE_KERNEL_ERROR_LIBRARYDB_NO_MOD = 0x8002D082, - SCE_KERNEL_ERROR_AUTHFAIL = 0x8002F000, - SCE_KERNEL_ERROR_NO_AUTH = 0x8002F001, + SCE_KERNEL_ERROR_ERROR = ERROR_CODE(0x80020001), + SCE_KERNEL_ERROR_NOT_IMPLEMENTED = ERROR_CODE(0x80020002), + SCE_KERNEL_ERROR_INVALID_ARGUMENT = ERROR_CODE(0x80020003), + SCE_KERNEL_ERROR_INVALID_ARGUMENT_SIZE = ERROR_CODE(0x80020004), + SCE_KERNEL_ERROR_INVALID_FLAGS = ERROR_CODE(0x80020005), + SCE_KERNEL_ERROR_ILLEGAL_SIZE = ERROR_CODE(0x80020006), + SCE_KERNEL_ERROR_ILLEGAL_ADDR = ERROR_CODE(0x80020007), + SCE_KERNEL_ERROR_UNSUP = ERROR_CODE(0x80020008), + SCE_KERNEL_ERROR_ILLEGAL_MODE = ERROR_CODE(0x80020009), + SCE_KERNEL_ERROR_ILLEGAL_ALIGNMENT = ERROR_CODE(0x8002000A), + SCE_KERNEL_ERROR_NOSYS = ERROR_CODE(0x8002000B), + SCE_KERNEL_ERROR_DEBUG_ERROR = ERROR_CODE(0x80021000), + SCE_KERNEL_ERROR_ILLEGAL_DIPSW_NUMBER = ERROR_CODE(0x80021001), + SCE_KERNEL_ERROR_CPU_ERROR = ERROR_CODE(0x80022000), + SCE_KERNEL_ERROR_MMU_ILLEGAL_L1_TYPE = ERROR_CODE(0x80022001), + SCE_KERNEL_ERROR_MMU_L2_INDEX_OVERFLOW = ERROR_CODE(0x80022002), + SCE_KERNEL_ERROR_MMU_L2_SIZE_OVERFLOW = ERROR_CODE(0x80022003), + SCE_KERNEL_ERROR_INVALID_CPU_AFFINITY = ERROR_CODE(0x80022004), + SCE_KERNEL_ERROR_INVALID_MEMORY_ACCESS = ERROR_CODE(0x80022005), + SCE_KERNEL_ERROR_INVALID_MEMORY_ACCESS_PERMISSION = ERROR_CODE(0x80022006), + SCE_KERNEL_ERROR_VA2PA_FAULT = ERROR_CODE(0x80022007), + SCE_KERNEL_ERROR_VA2PA_MAPPED = ERROR_CODE(0x80022008), + SCE_KERNEL_ERROR_VALIDATION_CHECK_FAILED = ERROR_CODE(0x80022009), + SCE_KERNEL_ERROR_SYSMEM_ERROR = ERROR_CODE(0x80024000), + SCE_KERNEL_ERROR_INVALID_PROCESS_CONTEXT = ERROR_CODE(0x80024001), + SCE_KERNEL_ERROR_UID_NAME_TOO_LONG = ERROR_CODE(0x80024002), + SCE_KERNEL_ERROR_VARANGE_IS_NOT_PHYSICAL_CONTINUOUS = ERROR_CODE(0x80024003), + SCE_KERNEL_ERROR_PHYADDR_ERROR = ERROR_CODE(0x80024100), + SCE_KERNEL_ERROR_NO_PHYADDR = ERROR_CODE(0x80024101), + SCE_KERNEL_ERROR_PHYADDR_USED = ERROR_CODE(0x80024102), + SCE_KERNEL_ERROR_PHYADDR_NOT_USED = ERROR_CODE(0x80024103), + SCE_KERNEL_ERROR_NO_IOADDR = ERROR_CODE(0x80024104), + SCE_KERNEL_ERROR_PHYMEM_ERROR = ERROR_CODE(0x80024300), + SCE_KERNEL_ERROR_ILLEGAL_PHYPAGE_STATUS = ERROR_CODE(0x80024301), + SCE_KERNEL_ERROR_NO_FREE_PHYSICAL_PAGE = ERROR_CODE(0x80024302), + SCE_KERNEL_ERROR_NO_FREE_PHYSICAL_PAGE_UNIT = ERROR_CODE(0x80024303), + SCE_KERNEL_ERROR_PHYMEMPART_NOT_EMPTY = ERROR_CODE(0x80024304), + SCE_KERNEL_ERROR_NO_PHYMEMPART_LPDDR2 = ERROR_CODE(0x80024305), + SCE_KERNEL_ERROR_NO_PHYMEMPART_CDRAM = ERROR_CODE(0x80024306), + SCE_KERNEL_ERROR_FIXEDHEAP_ERROR = ERROR_CODE(0x80024400), + SCE_KERNEL_ERROR_FIXEDHEAP_ILLEGAL_SIZE = ERROR_CODE(0x80024401), + SCE_KERNEL_ERROR_FIXEDHEAP_ILLEGAL_INDEX = ERROR_CODE(0x80024402), + SCE_KERNEL_ERROR_FIXEDHEAP_INDEX_OVERFLOW = ERROR_CODE(0x80024403), + SCE_KERNEL_ERROR_FIXEDHEAP_NO_CHUNK = ERROR_CODE(0x80024404), + SCE_KERNEL_ERROR_UID_ERROR = ERROR_CODE(0x80024500), + SCE_KERNEL_ERROR_INVALID_UID = ERROR_CODE(0x80024501), + SCE_KERNEL_ERROR_SYSMEM_UID_INVALID_ARGUMENT = ERROR_CODE(0x80024502), + SCE_KERNEL_ERROR_SYSMEM_INVALID_UID_RANGE = ERROR_CODE(0x80024503), + SCE_KERNEL_ERROR_SYSMEM_NO_VALID_UID = ERROR_CODE(0x80024504), + SCE_KERNEL_ERROR_SYSMEM_CANNOT_ALLOCATE_UIDENTRY = ERROR_CODE(0x80024505), + SCE_KERNEL_ERROR_NOT_PROCESS_UID = ERROR_CODE(0x80024506), + SCE_KERNEL_ERROR_NOT_KERNEL_UID = ERROR_CODE(0x80024507), + SCE_KERNEL_ERROR_INVALID_UID_CLASS = ERROR_CODE(0x80024508), + SCE_KERNEL_ERROR_INVALID_UID_SUBCLASS = ERROR_CODE(0x80024509), + SCE_KERNEL_ERROR_UID_CANNOT_FIND_BY_NAME = ERROR_CODE(0x8002450A), + SCE_KERNEL_ERROR_VIRPAGE_ERROR = ERROR_CODE(0x80024600), + SCE_KERNEL_ERROR_ILLEGAL_VIRPAGE_TYPE = ERROR_CODE(0x80024601), + SCE_KERNEL_ERROR_BLOCK_ERROR = ERROR_CODE(0x80024700), + SCE_KERNEL_ERROR_ILLEGAL_BLOCK_ID = ERROR_CODE(0x80024701), + SCE_KERNEL_ERROR_ILLEGAL_BLOCK_TYPE = ERROR_CODE(0x80024702), + SCE_KERNEL_ERROR_BLOCK_IN_USE = ERROR_CODE(0x80024703), + SCE_KERNEL_ERROR_PARTITION_ERROR = ERROR_CODE(0x80024800), + SCE_KERNEL_ERROR_ILLEGAL_PARTITION_ID = ERROR_CODE(0x80024801), + SCE_KERNEL_ERROR_ILLEGAL_PARTITION_INDEX = ERROR_CODE(0x80024802), + SCE_KERNEL_ERROR_NO_L2PAGETABLE = ERROR_CODE(0x80024803), + SCE_KERNEL_ERROR_HEAPLIB_ERROR = ERROR_CODE(0x80024900), + SCE_KERNEL_ERROR_ILLEGAL_HEAP_ID = ERROR_CODE(0x80024901), + SCE_KERNEL_ERROR_OUT_OF_RANG = ERROR_CODE(0x80024902), + SCE_KERNEL_ERROR_HEAPLIB_NOMEM = ERROR_CODE(0x80024903), + SCE_KERNEL_ERROR_SYSMEM_ADDRESS_SPACE_ERROR = ERROR_CODE(0x80024A00), + SCE_KERNEL_ERROR_INVALID_ADDRESS_SPACE_ID = ERROR_CODE(0x80024A01), + SCE_KERNEL_ERROR_INVALID_PARTITION_INDEX = ERROR_CODE(0x80024A02), + SCE_KERNEL_ERROR_ADDRESS_SPACE_CANNOT_FIND_PARTITION_BY_ADDR = ERROR_CODE(0x80024A03), + SCE_KERNEL_ERROR_SYSMEM_MEMBLOCK_ERROR = ERROR_CODE(0x80024B00), + SCE_KERNEL_ERROR_ILLEGAL_MEMBLOCK_TYPE = ERROR_CODE(0x80024B01), + SCE_KERNEL_ERROR_ILLEGAL_MEMBLOCK_REMAP_TYPE = ERROR_CODE(0x80024B02), + SCE_KERNEL_ERROR_NOT_PHY_CONT_MEMBLOCK = ERROR_CODE(0x80024B03), + SCE_KERNEL_ERROR_ILLEGAL_MEMBLOCK_CODE = ERROR_CODE(0x80024B04), + SCE_KERNEL_ERROR_ILLEGAL_MEMBLOCK_SIZE = ERROR_CODE(0x80024B05), + SCE_KERNEL_ERROR_ILLEGAL_USERMAP_SIZE = ERROR_CODE(0x80024B06), + SCE_KERNEL_ERROR_MEMBLOCK_TYPE_FOR_KERNEL_PROCESS = ERROR_CODE(0x80024B07), + SCE_KERNEL_ERROR_PROCESS_CANNOT_REMAP_MEMBLOCK = ERROR_CODE(0x80024B08), + SCE_KERNEL_ERROR_SYSMEM_PHYMEMLOW_ERROR = ERROR_CODE(0x80024C00), + SCE_KERNEL_ERROR_CANNOT_ALLOC_PHYMEMLOW = ERROR_CODE(0x80024C01), + SCE_KERNEL_ERROR_UNKNOWN_PHYMEMLOW_TYPE = ERROR_CODE(0x80024C02), + SCE_KERNEL_ERROR_SYSMEM_BITHEAP_ERROR = ERROR_CODE(0x80024D00), + SCE_KERNEL_ERROR_CANNOT_ALLOC_BITHEAP = ERROR_CODE(0x80024D01), + SCE_KERNEL_ERROR_LOADCORE_ERROR = ERROR_CODE(0x80025000), + SCE_KERNEL_ERROR_ILLEGAL_ELF_HEADER = ERROR_CODE(0x80025001), + SCE_KERNEL_ERROR_ILLEGAL_SELF_HEADER = ERROR_CODE(0x80025002), }; +enum SceLibKernelError0 : s32 +{ + SCE_KERNEL_ERROR_EXCPMGR_ERROR = ERROR_CODE(0x80027000), + SCE_KERNEL_ERROR_ILLEGAL_EXCPCODE = ERROR_CODE(0x80027001), + SCE_KERNEL_ERROR_ILLEGAL_EXCPHANDLER = ERROR_CODE(0x80027002), + SCE_KERNEL_ERROR_NOTFOUND_EXCPHANDLER = ERROR_CODE(0x80027003), + SCE_KERNEL_ERROR_CANNOT_RELEASE_EXCPHANDLER = ERROR_CODE(0x80027004), + SCE_KERNEL_ERROR_INTRMGR_ERROR = ERROR_CODE(0x80027100), + SCE_KERNEL_ERROR_ILLEGAL_CONTEXT = ERROR_CODE(0x80027101), + SCE_KERNEL_ERROR_ILLEGAL_INTRCODE = ERROR_CODE(0x80027102), + SCE_KERNEL_ERROR_ILLEGAL_INTRPARAM = ERROR_CODE(0x80027103), + SCE_KERNEL_ERROR_ILLEGAL_INTRPRIORITY = ERROR_CODE(0x80027104), + SCE_KERNEL_ERROR_ILLEGAL_TARGET_CPU = ERROR_CODE(0x80027105), + SCE_KERNEL_ERROR_ILLEGAL_INTRFILTER = ERROR_CODE(0x80027106), + SCE_KERNEL_ERROR_ILLEGAL_INTRTYPE = ERROR_CODE(0x80027107), + SCE_KERNEL_ERROR_ILLEGAL_HANDLER = ERROR_CODE(0x80027108), + SCE_KERNEL_ERROR_FOUND_HANDLER = ERROR_CODE(0x80027109), + SCE_KERNEL_ERROR_NOTFOUND_HANDLER = ERROR_CODE(0x8002710A), + SCE_KERNEL_ERROR_NO_MEMORY = ERROR_CODE(0x8002710B), + SCE_KERNEL_ERROR_DMACMGR_ERROR = ERROR_CODE(0x80027200), + SCE_KERNEL_ERROR_ALREADY_QUEUED = ERROR_CODE(0x80027201), + SCE_KERNEL_ERROR_NOT_QUEUED = ERROR_CODE(0x80027202), + SCE_KERNEL_ERROR_NOT_SETUP = ERROR_CODE(0x80027203), + SCE_KERNEL_ERROR_ON_TRANSFERRING = ERROR_CODE(0x80027204), + SCE_KERNEL_ERROR_NOT_INITIALIZED = ERROR_CODE(0x80027205), + SCE_KERNEL_ERROR_TRANSFERRED = ERROR_CODE(0x80027206), + SCE_KERNEL_ERROR_NOT_UNDER_CONTROL = ERROR_CODE(0x80027207), + SCE_KERNEL_ERROR_SYSTIMER_ERROR = ERROR_CODE(0x80027300), + SCE_KERNEL_ERROR_NO_FREE_TIMER = ERROR_CODE(0x80027301), + SCE_KERNEL_ERROR_TIMER_NOT_ALLOCATED = ERROR_CODE(0x80027302), + SCE_KERNEL_ERROR_TIMER_COUNTING = ERROR_CODE(0x80027303), + SCE_KERNEL_ERROR_TIMER_STOPPED = ERROR_CODE(0x80027304), + SCE_KERNEL_ERROR_THREADMGR_ERROR = ERROR_CODE(0x80028000), + SCE_KERNEL_ERROR_DORMANT = ERROR_CODE(0x80028001), + SCE_KERNEL_ERROR_NOT_DORMANT = ERROR_CODE(0x80028002), + SCE_KERNEL_ERROR_UNKNOWN_THID = ERROR_CODE(0x80028003), + SCE_KERNEL_ERROR_CAN_NOT_WAIT = ERROR_CODE(0x80028004), + SCE_KERNEL_ERROR_ILLEGAL_THID = ERROR_CODE(0x80028005), + SCE_KERNEL_ERROR_THREAD_TERMINATED = ERROR_CODE(0x80028006), + SCE_KERNEL_ERROR_DELETED = ERROR_CODE(0x80028007), + SCE_KERNEL_ERROR_WAIT_TIMEOUT = ERROR_CODE(0x80028008), + SCE_KERNEL_ERROR_NOTIFY_CALLBACK = ERROR_CODE(0x80028009), + SCE_KERNEL_ERROR_WAIT_DELETE = ERROR_CODE(0x8002800A), + SCE_KERNEL_ERROR_ILLEGAL_ATTR = ERROR_CODE(0x8002800B), + SCE_KERNEL_ERROR_EVF_MULTI = ERROR_CODE(0x8002800C), + SCE_KERNEL_ERROR_WAIT_CANCEL = ERROR_CODE(0x8002800D), + SCE_KERNEL_ERROR_EVF_COND = ERROR_CODE(0x8002800E), + SCE_KERNEL_ERROR_ILLEGAL_COUNT = ERROR_CODE(0x8002800F), + SCE_KERNEL_ERROR_ILLEGAL_PRIORITY = ERROR_CODE(0x80028010), + SCE_KERNEL_ERROR_MUTEX_RECURSIVE = ERROR_CODE(0x80028011), + SCE_KERNEL_ERROR_MUTEX_LOCK_OVF = ERROR_CODE(0x80028012), + SCE_KERNEL_ERROR_MUTEX_NOT_OWNED = ERROR_CODE(0x80028013), + SCE_KERNEL_ERROR_MUTEX_UNLOCK_UDF = ERROR_CODE(0x80028014), + SCE_KERNEL_ERROR_MUTEX_FAILED_TO_OWN = ERROR_CODE(0x80028015), + SCE_KERNEL_ERROR_FAST_MUTEX_RECURSIVE = ERROR_CODE(0x80028016), + SCE_KERNEL_ERROR_FAST_MUTEX_LOCK_OVF = ERROR_CODE(0x80028017), + SCE_KERNEL_ERROR_FAST_MUTEX_FAILED_TO_OWN = ERROR_CODE(0x80028018), + SCE_KERNEL_ERROR_FAST_MUTEX_NOT_OWNED = ERROR_CODE(0x80028019), + SCE_KERNEL_ERROR_FAST_MUTEX_OWNED = ERROR_CODE(0x8002801A), + SCE_KERNEL_ERROR_ALARM_CAN_NOT_CANCEL = ERROR_CODE(0x8002801B), + SCE_KERNEL_ERROR_INVALID_OBJECT_TYPE = ERROR_CODE(0x8002801C), + SCE_KERNEL_ERROR_KERNEL_TLS_FULL = ERROR_CODE(0x8002801D), + SCE_KERNEL_ERROR_ILLEGAL_KERNEL_TLS_INDEX = ERROR_CODE(0x8002801E), + SCE_KERNEL_ERROR_KERNEL_TLS_BUSY = ERROR_CODE(0x8002801F), + SCE_KERNEL_ERROR_DIFFERENT_UID_CLASS = ERROR_CODE(0x80028020), + SCE_KERNEL_ERROR_UNKNOWN_UID = ERROR_CODE(0x80028021), + SCE_KERNEL_ERROR_SEMA_ZERO = ERROR_CODE(0x80028022), + SCE_KERNEL_ERROR_SEMA_OVF = ERROR_CODE(0x80028023), + SCE_KERNEL_ERROR_PMON_NOT_THREAD_MODE = ERROR_CODE(0x80028024), + SCE_KERNEL_ERROR_PMON_NOT_CPU_MODE = ERROR_CODE(0x80028025), + SCE_KERNEL_ERROR_ALREADY_REGISTERED = ERROR_CODE(0x80028026), + SCE_KERNEL_ERROR_INVALID_THREAD_ID = ERROR_CODE(0x80028027), + SCE_KERNEL_ERROR_ALREADY_DEBUG_SUSPENDED = ERROR_CODE(0x80028028), + SCE_KERNEL_ERROR_NOT_DEBUG_SUSPENDED = ERROR_CODE(0x80028029), + SCE_KERNEL_ERROR_CAN_NOT_USE_VFP = ERROR_CODE(0x8002802A), + SCE_KERNEL_ERROR_RUNNING = ERROR_CODE(0x8002802B), + SCE_KERNEL_ERROR_EVENT_COND = ERROR_CODE(0x8002802C), + SCE_KERNEL_ERROR_MSG_PIPE_FULL = ERROR_CODE(0x8002802D), + SCE_KERNEL_ERROR_MSG_PIPE_EMPTY = ERROR_CODE(0x8002802E), + SCE_KERNEL_ERROR_ALREADY_SENT = ERROR_CODE(0x8002802F), + SCE_KERNEL_ERROR_CAN_NOT_SUSPEND = ERROR_CODE(0x80028030), + SCE_KERNEL_ERROR_FAST_MUTEX_ALREADY_INITIALIZED = ERROR_CODE(0x80028031), + SCE_KERNEL_ERROR_FAST_MUTEX_NOT_INITIALIZED = ERROR_CODE(0x80028032), + SCE_KERNEL_ERROR_THREAD_STOPPED = ERROR_CODE(0x80028033), + SCE_KERNEL_ERROR_THREAD_SUSPENDED = ERROR_CODE(0x80028034), + SCE_KERNEL_ERROR_NOT_SUSPENDED = ERROR_CODE(0x80028035), + SCE_KERNEL_ERROR_WAIT_DELETE_MUTEX = ERROR_CODE(0x80028036), + SCE_KERNEL_ERROR_WAIT_CANCEL_MUTEX = ERROR_CODE(0x80028037), + SCE_KERNEL_ERROR_WAIT_DELETE_COND = ERROR_CODE(0x80028038), + SCE_KERNEL_ERROR_WAIT_CANCEL_COND = ERROR_CODE(0x80028039), + SCE_KERNEL_ERROR_LW_MUTEX_NOT_OWNED = ERROR_CODE(0x8002803A), + SCE_KERNEL_ERROR_LW_MUTEX_LOCK_OVF = ERROR_CODE(0x8002803B), + SCE_KERNEL_ERROR_LW_MUTEX_UNLOCK_UDF = ERROR_CODE(0x8002803C), + SCE_KERNEL_ERROR_LW_MUTEX_RECURSIVE = ERROR_CODE(0x8002803D), + SCE_KERNEL_ERROR_LW_MUTEX_FAILED_TO_OWN = ERROR_CODE(0x8002803E), + SCE_KERNEL_ERROR_WAIT_DELETE_LW_MUTEX = ERROR_CODE(0x8002803F), + SCE_KERNEL_ERROR_ILLEGAL_STACK_SIZE = ERROR_CODE(0x80028040), + SCE_KERNEL_ERROR_RW_LOCK_RECURSIVE = ERROR_CODE(0x80028041), + SCE_KERNEL_ERROR_RW_LOCK_LOCK_OVF = ERROR_CODE(0x80028042), + SCE_KERNEL_ERROR_RW_LOCK_NOT_OWNED = ERROR_CODE(0x80028043), + SCE_KERNEL_ERROR_RW_LOCK_UNLOCK_UDF = ERROR_CODE(0x80028044), + SCE_KERNEL_ERROR_RW_LOCK_FAILED_TO_LOCK = ERROR_CODE(0x80028045), + SCE_KERNEL_ERROR_RW_LOCK_FAILED_TO_UNLOCK = ERROR_CODE(0x80028046), +}; + +enum SceLibKernelError1 : s32 +{ + SCE_KERNEL_ERROR_PROCESSMGR_ERROR = ERROR_CODE(0x80029000), + SCE_KERNEL_ERROR_INVALID_PID = ERROR_CODE(0x80029001), + SCE_KERNEL_ERROR_INVALID_PROCESS_TYPE = ERROR_CODE(0x80029002), + SCE_KERNEL_ERROR_PLS_FULL = ERROR_CODE(0x80029003), + SCE_KERNEL_ERROR_INVALID_PROCESS_STATUS = ERROR_CODE(0x80029004), + SCE_KERNEL_ERROR_INVALID_BUDGET_ID = ERROR_CODE(0x80029005), + SCE_KERNEL_ERROR_INVALID_BUDGET_SIZE = ERROR_CODE(0x80029006), + SCE_KERNEL_ERROR_CP14_DISABLED = ERROR_CODE(0x80029007), + SCE_KERNEL_ERROR_EXCEEDED_MAX_PROCESSES = ERROR_CODE(0x80029008), + SCE_KERNEL_ERROR_PROCESS_REMAINING = ERROR_CODE(0x80029009), + SCE_KERNEL_ERROR_IOFILEMGR_ERROR = ERROR_CODE(0x8002A000), + SCE_KERNEL_ERROR_IO_NAME_TOO_LONG = ERROR_CODE(0x8002A001), + SCE_KERNEL_ERROR_IO_REG_DEV = ERROR_CODE(0x8002A002), + SCE_KERNEL_ERROR_IO_ALIAS_USED = ERROR_CODE(0x8002A003), + SCE_KERNEL_ERROR_IO_DEL_DEV = ERROR_CODE(0x8002A004), + SCE_KERNEL_ERROR_IO_WOULD_BLOCK = ERROR_CODE(0x8002A005), + SCE_KERNEL_ERROR_MODULEMGR_START_FAILED = ERROR_CODE(0x8002D000), + SCE_KERNEL_ERROR_MODULEMGR_STOP_FAIL = ERROR_CODE(0x8002D001), + SCE_KERNEL_ERROR_MODULEMGR_IN_USE = ERROR_CODE(0x8002D002), + SCE_KERNEL_ERROR_MODULEMGR_NO_LIB = ERROR_CODE(0x8002D003), + SCE_KERNEL_ERROR_MODULEMGR_SYSCALL_REG = ERROR_CODE(0x8002D004), + SCE_KERNEL_ERROR_MODULEMGR_NOMEM_LIB = ERROR_CODE(0x8002D005), + SCE_KERNEL_ERROR_MODULEMGR_NOMEM_STUB = ERROR_CODE(0x8002D006), + SCE_KERNEL_ERROR_MODULEMGR_NOMEM_SELF = ERROR_CODE(0x8002D007), + SCE_KERNEL_ERROR_MODULEMGR_NOMEM = ERROR_CODE(0x8002D008), + SCE_KERNEL_ERROR_MODULEMGR_INVALID_LIB = ERROR_CODE(0x8002D009), + SCE_KERNEL_ERROR_MODULEMGR_INVALID_STUB = ERROR_CODE(0x8002D00A), + SCE_KERNEL_ERROR_MODULEMGR_NO_FUNC_NID = ERROR_CODE(0x8002D00B), + SCE_KERNEL_ERROR_MODULEMGR_NO_VAR_NID = ERROR_CODE(0x8002D00C), + SCE_KERNEL_ERROR_MODULEMGR_INVALID_TYPE = ERROR_CODE(0x8002D00D), + SCE_KERNEL_ERROR_MODULEMGR_NO_MOD_ENTRY = ERROR_CODE(0x8002D00E), + SCE_KERNEL_ERROR_MODULEMGR_INVALID_PROC_PARAM = ERROR_CODE(0x8002D00F), + SCE_KERNEL_ERROR_MODULEMGR_NO_MODOBJ = ERROR_CODE(0x8002D010), + SCE_KERNEL_ERROR_MODULEMGR_NO_MOD = ERROR_CODE(0x8002D011), + SCE_KERNEL_ERROR_MODULEMGR_NO_PROCESS = ERROR_CODE(0x8002D012), + SCE_KERNEL_ERROR_MODULEMGR_OLD_LIB = ERROR_CODE(0x8002D013), + SCE_KERNEL_ERROR_MODULEMGR_STARTED = ERROR_CODE(0x8002D014), + SCE_KERNEL_ERROR_MODULEMGR_NOT_STARTED = ERROR_CODE(0x8002D015), + SCE_KERNEL_ERROR_MODULEMGR_NOT_STOPPED = ERROR_CODE(0x8002D016), + SCE_KERNEL_ERROR_MODULEMGR_INVALID_PROCESS_UID = ERROR_CODE(0x8002D017), + SCE_KERNEL_ERROR_MODULEMGR_CANNOT_EXPORT_LIB_TO_SHARED = ERROR_CODE(0x8002D018), + SCE_KERNEL_ERROR_MODULEMGR_INVALID_REL_INFO = ERROR_CODE(0x8002D019), + SCE_KERNEL_ERROR_MODULEMGR_INVALID_REF_INFO = ERROR_CODE(0x8002D01A), + SCE_KERNEL_ERROR_MODULEMGR_ELINK = ERROR_CODE(0x8002D01B), + SCE_KERNEL_ERROR_MODULEMGR_NOENT = ERROR_CODE(0x8002D01C), + SCE_KERNEL_ERROR_MODULEMGR_BUSY = ERROR_CODE(0x8002D01D), + SCE_KERNEL_ERROR_MODULEMGR_NOEXEC = ERROR_CODE(0x8002D01E), + SCE_KERNEL_ERROR_MODULEMGR_NAMETOOLONG = ERROR_CODE(0x8002D01F), + SCE_KERNEL_ERROR_LIBRARYDB_NOENT = ERROR_CODE(0x8002D080), + SCE_KERNEL_ERROR_LIBRARYDB_NO_LIB = ERROR_CODE(0x8002D081), + SCE_KERNEL_ERROR_LIBRARYDB_NO_MOD = ERROR_CODE(0x8002D082), + SCE_KERNEL_ERROR_AUTHFAIL = ERROR_CODE(0x8002F000), + SCE_KERNEL_ERROR_NO_AUTH = ERROR_CODE(0x8002F001), +}; + +template<> +inline const char* arm_error_code::print(SceLibKernelError error) +{ + switch (error) + { + STR_CASE(SCE_KERNEL_ERROR_ERROR); + STR_CASE(SCE_KERNEL_ERROR_NOT_IMPLEMENTED); + STR_CASE(SCE_KERNEL_ERROR_INVALID_ARGUMENT); + STR_CASE(SCE_KERNEL_ERROR_INVALID_ARGUMENT_SIZE); + STR_CASE(SCE_KERNEL_ERROR_INVALID_FLAGS); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_SIZE); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_ADDR); + STR_CASE(SCE_KERNEL_ERROR_UNSUP); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_MODE); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_ALIGNMENT); + STR_CASE(SCE_KERNEL_ERROR_NOSYS); + STR_CASE(SCE_KERNEL_ERROR_DEBUG_ERROR); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_DIPSW_NUMBER); + STR_CASE(SCE_KERNEL_ERROR_CPU_ERROR); + STR_CASE(SCE_KERNEL_ERROR_MMU_ILLEGAL_L1_TYPE); + STR_CASE(SCE_KERNEL_ERROR_MMU_L2_INDEX_OVERFLOW); + STR_CASE(SCE_KERNEL_ERROR_MMU_L2_SIZE_OVERFLOW); + STR_CASE(SCE_KERNEL_ERROR_INVALID_CPU_AFFINITY); + STR_CASE(SCE_KERNEL_ERROR_INVALID_MEMORY_ACCESS); + STR_CASE(SCE_KERNEL_ERROR_INVALID_MEMORY_ACCESS_PERMISSION); + STR_CASE(SCE_KERNEL_ERROR_VA2PA_FAULT); + STR_CASE(SCE_KERNEL_ERROR_VA2PA_MAPPED); + STR_CASE(SCE_KERNEL_ERROR_VALIDATION_CHECK_FAILED); + STR_CASE(SCE_KERNEL_ERROR_SYSMEM_ERROR); + STR_CASE(SCE_KERNEL_ERROR_INVALID_PROCESS_CONTEXT); + STR_CASE(SCE_KERNEL_ERROR_UID_NAME_TOO_LONG); + STR_CASE(SCE_KERNEL_ERROR_VARANGE_IS_NOT_PHYSICAL_CONTINUOUS); + STR_CASE(SCE_KERNEL_ERROR_PHYADDR_ERROR); + STR_CASE(SCE_KERNEL_ERROR_NO_PHYADDR); + STR_CASE(SCE_KERNEL_ERROR_PHYADDR_USED); + STR_CASE(SCE_KERNEL_ERROR_PHYADDR_NOT_USED); + STR_CASE(SCE_KERNEL_ERROR_NO_IOADDR); + STR_CASE(SCE_KERNEL_ERROR_PHYMEM_ERROR); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_PHYPAGE_STATUS); + STR_CASE(SCE_KERNEL_ERROR_NO_FREE_PHYSICAL_PAGE); + STR_CASE(SCE_KERNEL_ERROR_NO_FREE_PHYSICAL_PAGE_UNIT); + STR_CASE(SCE_KERNEL_ERROR_PHYMEMPART_NOT_EMPTY); + STR_CASE(SCE_KERNEL_ERROR_NO_PHYMEMPART_LPDDR2); + STR_CASE(SCE_KERNEL_ERROR_NO_PHYMEMPART_CDRAM); + STR_CASE(SCE_KERNEL_ERROR_FIXEDHEAP_ERROR); + STR_CASE(SCE_KERNEL_ERROR_FIXEDHEAP_ILLEGAL_SIZE); + STR_CASE(SCE_KERNEL_ERROR_FIXEDHEAP_ILLEGAL_INDEX); + STR_CASE(SCE_KERNEL_ERROR_FIXEDHEAP_INDEX_OVERFLOW); + STR_CASE(SCE_KERNEL_ERROR_FIXEDHEAP_NO_CHUNK); + STR_CASE(SCE_KERNEL_ERROR_UID_ERROR); + STR_CASE(SCE_KERNEL_ERROR_INVALID_UID); + STR_CASE(SCE_KERNEL_ERROR_SYSMEM_UID_INVALID_ARGUMENT); + STR_CASE(SCE_KERNEL_ERROR_SYSMEM_INVALID_UID_RANGE); + STR_CASE(SCE_KERNEL_ERROR_SYSMEM_NO_VALID_UID); + STR_CASE(SCE_KERNEL_ERROR_SYSMEM_CANNOT_ALLOCATE_UIDENTRY); + STR_CASE(SCE_KERNEL_ERROR_NOT_PROCESS_UID); + STR_CASE(SCE_KERNEL_ERROR_NOT_KERNEL_UID); + STR_CASE(SCE_KERNEL_ERROR_INVALID_UID_CLASS); + STR_CASE(SCE_KERNEL_ERROR_INVALID_UID_SUBCLASS); + STR_CASE(SCE_KERNEL_ERROR_UID_CANNOT_FIND_BY_NAME); + STR_CASE(SCE_KERNEL_ERROR_VIRPAGE_ERROR); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_VIRPAGE_TYPE); + STR_CASE(SCE_KERNEL_ERROR_BLOCK_ERROR); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_BLOCK_ID); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_BLOCK_TYPE); + STR_CASE(SCE_KERNEL_ERROR_BLOCK_IN_USE); + STR_CASE(SCE_KERNEL_ERROR_PARTITION_ERROR); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_PARTITION_ID); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_PARTITION_INDEX); + STR_CASE(SCE_KERNEL_ERROR_NO_L2PAGETABLE); + STR_CASE(SCE_KERNEL_ERROR_HEAPLIB_ERROR); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_HEAP_ID); + STR_CASE(SCE_KERNEL_ERROR_OUT_OF_RANG); + STR_CASE(SCE_KERNEL_ERROR_HEAPLIB_NOMEM); + STR_CASE(SCE_KERNEL_ERROR_SYSMEM_ADDRESS_SPACE_ERROR); + STR_CASE(SCE_KERNEL_ERROR_INVALID_ADDRESS_SPACE_ID); + STR_CASE(SCE_KERNEL_ERROR_INVALID_PARTITION_INDEX); + STR_CASE(SCE_KERNEL_ERROR_ADDRESS_SPACE_CANNOT_FIND_PARTITION_BY_ADDR); + STR_CASE(SCE_KERNEL_ERROR_SYSMEM_MEMBLOCK_ERROR); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_MEMBLOCK_TYPE); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_MEMBLOCK_REMAP_TYPE); + STR_CASE(SCE_KERNEL_ERROR_NOT_PHY_CONT_MEMBLOCK); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_MEMBLOCK_CODE); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_MEMBLOCK_SIZE); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_USERMAP_SIZE); + STR_CASE(SCE_KERNEL_ERROR_MEMBLOCK_TYPE_FOR_KERNEL_PROCESS); + STR_CASE(SCE_KERNEL_ERROR_PROCESS_CANNOT_REMAP_MEMBLOCK); + STR_CASE(SCE_KERNEL_ERROR_SYSMEM_PHYMEMLOW_ERROR); + STR_CASE(SCE_KERNEL_ERROR_CANNOT_ALLOC_PHYMEMLOW); + STR_CASE(SCE_KERNEL_ERROR_UNKNOWN_PHYMEMLOW_TYPE); + STR_CASE(SCE_KERNEL_ERROR_SYSMEM_BITHEAP_ERROR); + STR_CASE(SCE_KERNEL_ERROR_CANNOT_ALLOC_BITHEAP); + STR_CASE(SCE_KERNEL_ERROR_LOADCORE_ERROR); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_ELF_HEADER); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_SELF_HEADER); + } + + return nullptr; +} + +template<> +inline const char* arm_error_code::print(SceLibKernelError0 error) +{ + switch (error) + { + STR_CASE(SCE_KERNEL_ERROR_EXCPMGR_ERROR); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_EXCPCODE); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_EXCPHANDLER); + STR_CASE(SCE_KERNEL_ERROR_NOTFOUND_EXCPHANDLER); + STR_CASE(SCE_KERNEL_ERROR_CANNOT_RELEASE_EXCPHANDLER); + STR_CASE(SCE_KERNEL_ERROR_INTRMGR_ERROR); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_CONTEXT); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_INTRCODE); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_INTRPARAM); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_INTRPRIORITY); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_TARGET_CPU); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_INTRFILTER); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_INTRTYPE); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_HANDLER); + STR_CASE(SCE_KERNEL_ERROR_FOUND_HANDLER); + STR_CASE(SCE_KERNEL_ERROR_NOTFOUND_HANDLER); + STR_CASE(SCE_KERNEL_ERROR_NO_MEMORY); + STR_CASE(SCE_KERNEL_ERROR_DMACMGR_ERROR); + STR_CASE(SCE_KERNEL_ERROR_ALREADY_QUEUED); + STR_CASE(SCE_KERNEL_ERROR_NOT_QUEUED); + STR_CASE(SCE_KERNEL_ERROR_NOT_SETUP); + STR_CASE(SCE_KERNEL_ERROR_ON_TRANSFERRING); + STR_CASE(SCE_KERNEL_ERROR_NOT_INITIALIZED); + STR_CASE(SCE_KERNEL_ERROR_TRANSFERRED); + STR_CASE(SCE_KERNEL_ERROR_NOT_UNDER_CONTROL); + STR_CASE(SCE_KERNEL_ERROR_SYSTIMER_ERROR); + STR_CASE(SCE_KERNEL_ERROR_NO_FREE_TIMER); + STR_CASE(SCE_KERNEL_ERROR_TIMER_NOT_ALLOCATED); + STR_CASE(SCE_KERNEL_ERROR_TIMER_COUNTING); + STR_CASE(SCE_KERNEL_ERROR_TIMER_STOPPED); + STR_CASE(SCE_KERNEL_ERROR_THREADMGR_ERROR); + STR_CASE(SCE_KERNEL_ERROR_DORMANT); + STR_CASE(SCE_KERNEL_ERROR_NOT_DORMANT); + STR_CASE(SCE_KERNEL_ERROR_UNKNOWN_THID); + STR_CASE(SCE_KERNEL_ERROR_CAN_NOT_WAIT); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_THID); + STR_CASE(SCE_KERNEL_ERROR_THREAD_TERMINATED); + STR_CASE(SCE_KERNEL_ERROR_DELETED); + STR_CASE(SCE_KERNEL_ERROR_WAIT_TIMEOUT); + STR_CASE(SCE_KERNEL_ERROR_NOTIFY_CALLBACK); + STR_CASE(SCE_KERNEL_ERROR_WAIT_DELETE); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_ATTR); + STR_CASE(SCE_KERNEL_ERROR_EVF_MULTI); + STR_CASE(SCE_KERNEL_ERROR_WAIT_CANCEL); + STR_CASE(SCE_KERNEL_ERROR_EVF_COND); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_COUNT); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_PRIORITY); + STR_CASE(SCE_KERNEL_ERROR_MUTEX_RECURSIVE); + STR_CASE(SCE_KERNEL_ERROR_MUTEX_LOCK_OVF); + STR_CASE(SCE_KERNEL_ERROR_MUTEX_NOT_OWNED); + STR_CASE(SCE_KERNEL_ERROR_MUTEX_UNLOCK_UDF); + STR_CASE(SCE_KERNEL_ERROR_MUTEX_FAILED_TO_OWN); + STR_CASE(SCE_KERNEL_ERROR_FAST_MUTEX_RECURSIVE); + STR_CASE(SCE_KERNEL_ERROR_FAST_MUTEX_LOCK_OVF); + STR_CASE(SCE_KERNEL_ERROR_FAST_MUTEX_FAILED_TO_OWN); + STR_CASE(SCE_KERNEL_ERROR_FAST_MUTEX_NOT_OWNED); + STR_CASE(SCE_KERNEL_ERROR_FAST_MUTEX_OWNED); + STR_CASE(SCE_KERNEL_ERROR_ALARM_CAN_NOT_CANCEL); + STR_CASE(SCE_KERNEL_ERROR_INVALID_OBJECT_TYPE); + STR_CASE(SCE_KERNEL_ERROR_KERNEL_TLS_FULL); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_KERNEL_TLS_INDEX); + STR_CASE(SCE_KERNEL_ERROR_KERNEL_TLS_BUSY); + STR_CASE(SCE_KERNEL_ERROR_DIFFERENT_UID_CLASS); + STR_CASE(SCE_KERNEL_ERROR_UNKNOWN_UID); + STR_CASE(SCE_KERNEL_ERROR_SEMA_ZERO); + STR_CASE(SCE_KERNEL_ERROR_SEMA_OVF); + STR_CASE(SCE_KERNEL_ERROR_PMON_NOT_THREAD_MODE); + STR_CASE(SCE_KERNEL_ERROR_PMON_NOT_CPU_MODE); + STR_CASE(SCE_KERNEL_ERROR_ALREADY_REGISTERED); + STR_CASE(SCE_KERNEL_ERROR_INVALID_THREAD_ID); + STR_CASE(SCE_KERNEL_ERROR_ALREADY_DEBUG_SUSPENDED); + STR_CASE(SCE_KERNEL_ERROR_NOT_DEBUG_SUSPENDED); + STR_CASE(SCE_KERNEL_ERROR_CAN_NOT_USE_VFP); + STR_CASE(SCE_KERNEL_ERROR_RUNNING); + STR_CASE(SCE_KERNEL_ERROR_EVENT_COND); + STR_CASE(SCE_KERNEL_ERROR_MSG_PIPE_FULL); + STR_CASE(SCE_KERNEL_ERROR_MSG_PIPE_EMPTY); + STR_CASE(SCE_KERNEL_ERROR_ALREADY_SENT); + STR_CASE(SCE_KERNEL_ERROR_CAN_NOT_SUSPEND); + STR_CASE(SCE_KERNEL_ERROR_FAST_MUTEX_ALREADY_INITIALIZED); + STR_CASE(SCE_KERNEL_ERROR_FAST_MUTEX_NOT_INITIALIZED); + STR_CASE(SCE_KERNEL_ERROR_THREAD_STOPPED); + STR_CASE(SCE_KERNEL_ERROR_THREAD_SUSPENDED); + STR_CASE(SCE_KERNEL_ERROR_NOT_SUSPENDED); + STR_CASE(SCE_KERNEL_ERROR_WAIT_DELETE_MUTEX); + STR_CASE(SCE_KERNEL_ERROR_WAIT_CANCEL_MUTEX); + STR_CASE(SCE_KERNEL_ERROR_WAIT_DELETE_COND); + STR_CASE(SCE_KERNEL_ERROR_WAIT_CANCEL_COND); + STR_CASE(SCE_KERNEL_ERROR_LW_MUTEX_NOT_OWNED); + STR_CASE(SCE_KERNEL_ERROR_LW_MUTEX_LOCK_OVF); + STR_CASE(SCE_KERNEL_ERROR_LW_MUTEX_UNLOCK_UDF); + STR_CASE(SCE_KERNEL_ERROR_LW_MUTEX_RECURSIVE); + STR_CASE(SCE_KERNEL_ERROR_LW_MUTEX_FAILED_TO_OWN); + STR_CASE(SCE_KERNEL_ERROR_WAIT_DELETE_LW_MUTEX); + STR_CASE(SCE_KERNEL_ERROR_ILLEGAL_STACK_SIZE); + STR_CASE(SCE_KERNEL_ERROR_RW_LOCK_RECURSIVE); + STR_CASE(SCE_KERNEL_ERROR_RW_LOCK_LOCK_OVF); + STR_CASE(SCE_KERNEL_ERROR_RW_LOCK_NOT_OWNED); + STR_CASE(SCE_KERNEL_ERROR_RW_LOCK_UNLOCK_UDF); + STR_CASE(SCE_KERNEL_ERROR_RW_LOCK_FAILED_TO_LOCK); + STR_CASE(SCE_KERNEL_ERROR_RW_LOCK_FAILED_TO_UNLOCK); + } + + return nullptr; +} + +template<> +inline const char* arm_error_code::print(SceLibKernelError1 error) +{ + switch (error) + { + STR_CASE(SCE_KERNEL_ERROR_PROCESSMGR_ERROR); + STR_CASE(SCE_KERNEL_ERROR_INVALID_PID); + STR_CASE(SCE_KERNEL_ERROR_INVALID_PROCESS_TYPE); + STR_CASE(SCE_KERNEL_ERROR_PLS_FULL); + STR_CASE(SCE_KERNEL_ERROR_INVALID_PROCESS_STATUS); + STR_CASE(SCE_KERNEL_ERROR_INVALID_BUDGET_ID); + STR_CASE(SCE_KERNEL_ERROR_INVALID_BUDGET_SIZE); + STR_CASE(SCE_KERNEL_ERROR_CP14_DISABLED); + STR_CASE(SCE_KERNEL_ERROR_EXCEEDED_MAX_PROCESSES); + STR_CASE(SCE_KERNEL_ERROR_PROCESS_REMAINING); + STR_CASE(SCE_KERNEL_ERROR_IOFILEMGR_ERROR); + STR_CASE(SCE_KERNEL_ERROR_IO_NAME_TOO_LONG); + STR_CASE(SCE_KERNEL_ERROR_IO_REG_DEV); + STR_CASE(SCE_KERNEL_ERROR_IO_ALIAS_USED); + STR_CASE(SCE_KERNEL_ERROR_IO_DEL_DEV); + STR_CASE(SCE_KERNEL_ERROR_IO_WOULD_BLOCK); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_START_FAILED); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_STOP_FAIL); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_IN_USE); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_NO_LIB); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_SYSCALL_REG); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_NOMEM_LIB); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_NOMEM_STUB); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_NOMEM_SELF); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_NOMEM); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_INVALID_LIB); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_INVALID_STUB); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_NO_FUNC_NID); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_NO_VAR_NID); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_INVALID_TYPE); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_NO_MOD_ENTRY); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_INVALID_PROC_PARAM); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_NO_MODOBJ); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_NO_MOD); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_NO_PROCESS); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_OLD_LIB); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_STARTED); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_NOT_STARTED); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_NOT_STOPPED); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_INVALID_PROCESS_UID); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_CANNOT_EXPORT_LIB_TO_SHARED); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_INVALID_REL_INFO); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_INVALID_REF_INFO); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_ELINK); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_NOENT); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_BUSY); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_NOEXEC); + STR_CASE(SCE_KERNEL_ERROR_MODULEMGR_NAMETOOLONG); + STR_CASE(SCE_KERNEL_ERROR_LIBRARYDB_NOENT); + STR_CASE(SCE_KERNEL_ERROR_LIBRARYDB_NO_LIB); + STR_CASE(SCE_KERNEL_ERROR_LIBRARYDB_NO_MOD); + STR_CASE(SCE_KERNEL_ERROR_AUTHFAIL); + STR_CASE(SCE_KERNEL_ERROR_NO_AUTH); + } + + return nullptr; +} + enum psv_object_class_t : u32 { SCE_KERNEL_UID_CLASS_PROCESS = 0, @@ -458,7 +740,7 @@ struct psv_event_flag_t std::mutex mutex; - sleep_queue_t sq; + sleep_queue sq; psv_event_flag_t(const char* name, u32 attr, u32 pattern) : name(name) @@ -479,7 +761,8 @@ struct psv_event_flag_t { static_cast(*thread).GPR[0] = SCE_KERNEL_ERROR_WAIT_DELETE; static_cast(*thread).GPR[1] = pattern; - thread->signal(); + thread->state += cpu_state::signal; + thread->cv.notify_one(); } } }; @@ -741,8 +1024,6 @@ struct SceIoDirent }; // Module -extern psv_log_base sceLibKernel; - // Aux inline bool ipc_ref_try_dec(u32& ref) diff --git a/rpcs3/Emu/ARMv7/Modules/sceXml.cpp b/rpcs3/Emu/ARMv7/Modules/sceLibXml.cpp similarity index 97% rename from rpcs3/Emu/ARMv7/Modules/sceXml.cpp rename to rpcs3/Emu/ARMv7/Modules/sceLibXml.cpp index f07d94665b..789a45e8d7 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceXml.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceLibXml.cpp @@ -1,18 +1,15 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" -#include "sceXml.h" +#include "sceLibXml.h" -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceXml, #name, name) +LOG_CHANNEL(sceLibXml); -psv_log_base sceXml("SceXml", []() +#define REG_FUNC(nid, name) REG_FNID(SceLibXml, nid, name) + +DECLARE(arm_module_manager::SceLibXml)("SceLibXml", []() { - sceXml.on_load = nullptr; - sceXml.on_unload = nullptr; - sceXml.on_stop = nullptr; - sceXml.on_error = nullptr; - //REG_FUNC(0x57400A1A, _ZN3sce3Xml10SimpleDataC1EPKcj); //REG_FUNC(0x7E582075, _ZN3sce3Xml10SimpleDataC1Ev); //REG_FUNC(0x4CF0656B, _ZN3sce3Xml10SimpleDataC2EPKcj); diff --git a/rpcs3/Emu/ARMv7/Modules/sceLibXml.h b/rpcs3/Emu/ARMv7/Modules/sceLibXml.h new file mode 100644 index 0000000000..6f70f09bee --- /dev/null +++ b/rpcs3/Emu/ARMv7/Modules/sceLibXml.h @@ -0,0 +1 @@ +#pragma once diff --git a/rpcs3/Emu/ARMv7/Modules/sceLibc.cpp b/rpcs3/Emu/ARMv7/Modules/sceLibc.cpp index d3a3f08c47..0e23fc0e3e 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceLibc.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceLibc.cpp @@ -1,18 +1,21 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "Emu/ARMv7/ARMv7Thread.h" #include "Emu/ARMv7/ARMv7Callback.h" #include "sceLibc.h" +LOG_CHANNEL(sceLibc); + +// TODO vm::ptr g_dso; std::vector> g_atexit; std::mutex g_atexit_mutex; -std::string armv7_fmt(ARMv7Context& context, vm::cptr fmt, u32 g_count, u32 f_count, u32 v_count) +std::string arm_fmt(ARMv7Thread& cpu, vm::cptr fmt, u32 g_count) { std::string result; @@ -40,7 +43,7 @@ std::string armv7_fmt(ARMv7Context& context, vm::cptr fmt, u32 g_count, u3 if (*fmt == '*') { fmt++; - return context.get_next_gpr_arg(g_count, f_count, v_count); + return cpu.get_next_gpr_arg(g_count); } while (*fmt - '0' < 10) @@ -64,7 +67,7 @@ std::string armv7_fmt(ARMv7Context& context, vm::cptr fmt, u32 g_count, u3 if (*++fmt == '*') { fmt++; - return context.get_next_gpr_arg(g_count, f_count, v_count); + return cpu.get_next_gpr_arg(g_count); } while (*fmt - '0' < 10) @@ -88,7 +91,7 @@ std::string armv7_fmt(ARMv7Context& context, vm::cptr fmt, u32 g_count, u3 case 'i': { // signed decimal - const s64 value = context.get_next_gpr_arg(g_count, f_count, v_count); + const s64 value = cpu.get_next_gpr_arg(g_count); if (plus_sign || minus_sign || space_sign || number_sign || zero_padding || width || prec) break; @@ -99,7 +102,7 @@ std::string armv7_fmt(ARMv7Context& context, vm::cptr fmt, u32 g_count, u3 case 'X': { // hexadecimal - const u64 value = context.get_next_gpr_arg(g_count, f_count, v_count); + const u64 value = cpu.get_next_gpr_arg(g_count); if (plus_sign || minus_sign || space_sign || prec) break; @@ -108,7 +111,7 @@ std::string armv7_fmt(ARMv7Context& context, vm::cptr fmt, u32 g_count, u3 result += cf == 'x' ? "0x" : "0X"; } - const std::string& hex = cf == 'x' ? fmt::to_hex(value) : fmt::toupper(fmt::to_hex(value)); + const std::string& hex = cf == 'x' ? fmt::to_hex(value) : fmt::to_upper(fmt::to_hex(value)); if (hex.length() >= width) { @@ -127,7 +130,7 @@ std::string armv7_fmt(ARMv7Context& context, vm::cptr fmt, u32 g_count, u3 case 's': { // string - const vm::cptr string{ context.get_next_gpr_arg(g_count, f_count, v_count), vm::addr }; + const vm::cptr string{ cpu.get_next_gpr_arg(g_count), vm::addr }; if (plus_sign || minus_sign || space_sign || number_sign || zero_padding || width || prec) break; @@ -154,9 +157,9 @@ namespace sce_libc_func std::lock_guard lock(g_atexit_mutex); - g_atexit.insert(g_atexit.begin(), [func, arg, dso](ARMv7Thread& context) + g_atexit.insert(g_atexit.begin(), [func, arg, dso](ARMv7Thread& cpu) { - func(context, arg); + func(cpu, arg); }); } @@ -166,13 +169,13 @@ namespace sce_libc_func std::lock_guard lock(g_atexit_mutex); - g_atexit.insert(g_atexit.begin(), [func, arg, dso](ARMv7Thread& context) + g_atexit.insert(g_atexit.begin(), [func, arg, dso](ARMv7Thread& cpu) { - func(context, arg); + func(cpu, arg); }); } - void exit(ARMv7Thread& context) + void exit(ARMv7Thread& cpu) { sceLibc.warning("exit()"); @@ -182,7 +185,7 @@ namespace sce_libc_func for (auto& func : decltype(g_atexit)(std::move(g_atexit))) { - func(context); + func(cpu); } sceLibc.success("Process finished"); @@ -196,27 +199,27 @@ namespace sce_libc_func { CHECK_EMU_STATUS; - std::this_thread::sleep_for(std::chrono::milliseconds(1)); + std::this_thread::sleep_for(1ms); } } - void printf(ARMv7Thread& context, vm::cptr fmt, armv7_va_args_t va_args) + void printf(ARMv7Thread& cpu, vm::cptr fmt, arm_va_args_t va_args) { sceLibc.warning("printf(fmt=*0x%x)", fmt); sceLibc.trace("*** *fmt = '%s'", fmt.get_ptr()); - const std::string& result = armv7_fmt(context, fmt, va_args.g_count, va_args.f_count, va_args.v_count); + const std::string& result = arm_fmt(cpu, fmt, va_args.count); sceLibc.trace("*** -> '%s'", result); _log::g_tty_file.log(result); } - void sprintf(ARMv7Thread& context, vm::ptr str, vm::cptr fmt, armv7_va_args_t va_args) + void sprintf(ARMv7Thread& cpu, vm::ptr str, vm::cptr fmt, arm_va_args_t va_args) { sceLibc.warning("sprintf(str=*0x%x, fmt=*0x%x)", str, fmt); sceLibc.trace("*** *fmt = '%s'", fmt.get_ptr()); - const std::string& result = armv7_fmt(context, fmt, va_args.g_count, va_args.f_count, va_args.v_count); + const std::string& result = arm_fmt(cpu, fmt, va_args.count); sceLibc.trace("*** -> '%s'", result); ::memcpy(str.get_ptr(), result.c_str(), result.size() + 1); @@ -225,8 +228,9 @@ namespace sce_libc_func void __cxa_set_dso_handle_main(vm::ptr dso) { sceLibc.warning("__cxa_set_dso_handle_main(dso=*0x%x)", dso); - + g_dso = dso; + g_atexit.clear(); } void memcpy(vm::ptr dst, vm::cptr src, u32 size) @@ -252,18 +256,10 @@ namespace sce_libc_func } } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceLibc, #name, sce_libc_func::name) +#define REG_FUNC(nid, name) REG_FNID(SceLibc, nid, sce_libc_func::name) -psv_log_base sceLibc("SceLibc", []() +DECLARE(arm_module_manager::SceLibc)("SceLibc", []() { - g_dso = vm::null; - g_atexit.clear(); - - sceLibc.on_load = nullptr; - sceLibc.on_unload = nullptr; - sceLibc.on_stop = nullptr; - sceLibc.on_error = nullptr; - REG_FUNC(0xE4531F85, _Assert); //REG_FUNC(0xE71C5CDE, _Stoul); //REG_FUNC(0x7A5CA6A3, _Stoulx); diff --git a/rpcs3/Emu/ARMv7/Modules/sceLibc.h b/rpcs3/Emu/ARMv7/Modules/sceLibc.h index 2766711aea..05cc11c1b4 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceLibc.h +++ b/rpcs3/Emu/ARMv7/Modules/sceLibc.h @@ -1,5 +1,3 @@ #pragma once using atexit_func_t = void(vm::ptr); - -extern psv_log_base sceLibc; diff --git a/rpcs3/Emu/ARMv7/Modules/sceLibm.cpp b/rpcs3/Emu/ARMv7/Modules/sceLibm.cpp index 6bf914f617..cdadc4e103 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceLibm.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceLibm.cpp @@ -1,23 +1,20 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceLibm.h" +LOG_CHANNEL(sceLibm); + namespace sce_libm_func { } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceLibm, #name, sce_libm_func::name) +#define REG_FUNC(nid, name) REG_FNID(SceLibm, nid, sce_libm_func::name) -psv_log_base sceLibm("SceLibm", []() +DECLARE(arm_module_manager::SceLibm)("SceLibm", []() { - sceLibm.on_load = nullptr; - sceLibm.on_unload = nullptr; - sceLibm.on_stop = nullptr; - sceLibm.on_error = nullptr; - //REG_FUNC(0xC73FE76D, _Exp); //REG_FUNC(0xFF4EAE04, _FExp); //REG_FUNC(0xB363D7D4, _LExp); diff --git a/rpcs3/Emu/ARMv7/Modules/sceLibm.h b/rpcs3/Emu/ARMv7/Modules/sceLibm.h index 1b0a58e4f6..6f70f09bee 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceLibm.h +++ b/rpcs3/Emu/ARMv7/Modules/sceLibm.h @@ -1,3 +1 @@ #pragma once - -extern psv_log_base sceLibm; diff --git a/rpcs3/Emu/ARMv7/Modules/sceLibstdcxx.cpp b/rpcs3/Emu/ARMv7/Modules/sceLibstdcxx.cpp index 82dd811e25..53fd57dcec 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceLibstdcxx.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceLibstdcxx.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceLibstdcxx.h" +LOG_CHANNEL(sceLibstdcxx); + namespace sce_libstdcxx_func { void __aeabi_unwind_cpp_pr0() @@ -22,16 +24,12 @@ namespace sce_libstdcxx_func } } -// Attention: find and set correct original mangled name in third parameter, for example: REG_FUNC(0xAE71DC3, operator_new_nothrow, "_ZnwjRKSt9nothrow_t"); -#define REG_FUNC(nid, name, orig_name) reg_psv_func(nid, &sceLibstdcxx, orig_name, sce_libstdcxx_func::name) +// TODO: find and set correct original mangled name. Currently ignored. +// Example of correct usage: REG_FUNC(0xAE71DC3, operator_new_nothrow, "_ZnwjRKSt9nothrow_t"); +#define REG_FUNC(nid, name, orig_name) REG_FNID(SceLibstdcxx, nid, sce_libstdcxx_func::name) -psv_log_base sceLibstdcxx("SceLibstdcxx", []() +DECLARE(arm_module_manager::SceLibstdcxx)("SceLibstdcxx", []() { - sceLibstdcxx.on_load = nullptr; - sceLibstdcxx.on_unload = nullptr; - sceLibstdcxx.on_stop = nullptr; - sceLibstdcxx.on_error = nullptr; - //REG_FUNC(0x52B0C625, std::bad_typeid::what() const); //REG_FUNC(0x64D7D074, std::bad_typeid::_Doraise() const); //REG_FUNC(0x15FB88E2, std::logic_error::what() const); diff --git a/rpcs3/Emu/ARMv7/Modules/sceLibstdcxx.h b/rpcs3/Emu/ARMv7/Modules/sceLibstdcxx.h index 5ddc0e48f4..6f70f09bee 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceLibstdcxx.h +++ b/rpcs3/Emu/ARMv7/Modules/sceLibstdcxx.h @@ -1,3 +1 @@ #pragma once - -extern psv_log_base sceLibstdcxx; diff --git a/rpcs3/Emu/ARMv7/Modules/sceLiveArea.cpp b/rpcs3/Emu/ARMv7/Modules/sceLiveArea.cpp index 05ef8948e6..f93fe7479e 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceLiveArea.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceLiveArea.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceLiveArea.h" +LOG_CHANNEL(sceLiveArea); + s32 sceLiveAreaResourceReplaceAll(vm::cptr dirpath) { throw EXCEPTION(""); @@ -14,15 +16,10 @@ s32 sceLiveAreaResourceGetStatus() throw EXCEPTION(""); } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceLiveArea, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceLiveArea, nid, name) -psv_log_base sceLiveArea("SceLiveArea", []() +DECLARE(arm_module_manager::SceLiveArea)("SceLiveArea", []() { - sceLiveArea.on_load = nullptr; - sceLiveArea.on_unload = nullptr; - sceLiveArea.on_stop = nullptr; - sceLiveArea.on_error = nullptr; - REG_FUNC(0xA4B506F9, sceLiveAreaResourceReplaceAll); REG_FUNC(0x54A395FB, sceLiveAreaResourceGetStatus); }); diff --git a/rpcs3/Emu/ARMv7/Modules/sceLiveArea.h b/rpcs3/Emu/ARMv7/Modules/sceLiveArea.h index fab4f795c2..6f70f09bee 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceLiveArea.h +++ b/rpcs3/Emu/ARMv7/Modules/sceLiveArea.h @@ -1,3 +1 @@ #pragma once - -extern psv_log_base sceLiveArea; diff --git a/rpcs3/Emu/ARMv7/Modules/sceLocation.cpp b/rpcs3/Emu/ARMv7/Modules/sceLocation.cpp index 007a4e742e..c180e99c52 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceLocation.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceLocation.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceLocation.h" +LOG_CHANNEL(sceLocation); + s32 sceLocationOpen(vm::ptr handle, SceLocationLocationMethod lmethod, SceLocationHeadingMethod hmethod) { throw EXCEPTION(""); @@ -90,15 +92,10 @@ s32 sceLocationSetGpsEmulationFile(vm::ptr filename) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceLocation, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceLibLocation, nid, name) -psv_log_base sceLocation("SceLibLocation", []() +DECLARE(arm_module_manager::SceLocation)("SceLibLocation", []() { - sceLocation.on_load = nullptr; - sceLocation.on_unload = nullptr; - sceLocation.on_stop = nullptr; - sceLocation.on_error = nullptr; - REG_FUNC(0xDD271661, sceLocationOpen); REG_FUNC(0x14FE76E8, sceLocationClose); REG_FUNC(0xB1F55065, sceLocationReopen); diff --git a/rpcs3/Emu/ARMv7/Modules/sceLocation.h b/rpcs3/Emu/ARMv7/Modules/sceLocation.h index 95d809797c..f6eccc0fac 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceLocation.h +++ b/rpcs3/Emu/ARMv7/Modules/sceLocation.h @@ -79,5 +79,3 @@ struct SceLocationPermissionInfo SceLocationPermissionStatus mainstatus; SceLocationPermissionApplicationStatus applicationstatus; }; - -extern psv_log_base sceLocation; diff --git a/rpcs3/Emu/ARMv7/Modules/sceMd5.cpp b/rpcs3/Emu/ARMv7/Modules/sceMd5.cpp index 8b8172ebf8..e7f1412a5e 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceMd5.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceMd5.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceMd5.h" +LOG_CHANNEL(sceMd5); + s32 sceMd5Digest(vm::cptr plain, u32 len, vm::ptr digest) { throw EXCEPTION(""); @@ -24,15 +26,10 @@ s32 sceMd5BlockResult(vm::ptr pContext, vm::ptr digest) throw EXCEPTION(""); } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceMd5, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceMd5, nid, name) -psv_log_base sceMd5("SceMd5", []() +DECLARE(arm_module_manager::SceMd5)("SceMd5", []() { - sceMd5.on_load = nullptr; - sceMd5.on_unload = nullptr; - sceMd5.on_stop = nullptr; - sceMd5.on_error = nullptr; - REG_FUNC(0xB845BCCB, sceMd5Digest); REG_FUNC(0x4D6436F9, sceMd5BlockInit); REG_FUNC(0x094A4902, sceMd5BlockUpdate); diff --git a/rpcs3/Emu/ARMv7/Modules/sceMd5.h b/rpcs3/Emu/ARMv7/Modules/sceMd5.h index 27b1ba9879..14d1d630ef 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceMd5.h +++ b/rpcs3/Emu/ARMv7/Modules/sceMd5.h @@ -10,5 +10,3 @@ struct SceMd5Context u8 buf[64]; u8 result[64]; }; - -extern psv_log_base sceMd5; diff --git a/rpcs3/Emu/ARMv7/Modules/sceMotion.cpp b/rpcs3/Emu/ARMv7/Modules/sceMotion.cpp index 2b11a2c932..10d1729ecd 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceMotion.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceMotion.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceMotion.h" +LOG_CHANNEL(sceMotion); + s32 sceMotionGetState(vm::ptr motionState) { throw EXCEPTION(""); @@ -84,15 +86,10 @@ s32 sceMotionStopSampling() throw EXCEPTION(""); } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceMotion, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceMotion, nid, name) -psv_log_base sceMotion("SceMotion", []() +DECLARE(arm_module_manager::SceMotion)("SceMotion", []() { - sceMotion.on_load = nullptr; - sceMotion.on_unload = nullptr; - sceMotion.on_stop = nullptr; - sceMotion.on_error = nullptr; - REG_FUNC(0xBDB32767, sceMotionGetState); REG_FUNC(0x47D679EA, sceMotionGetSensorState); REG_FUNC(0xC1652201, sceMotionGetTiltCorrection); diff --git a/rpcs3/Emu/ARMv7/Modules/sceMotion.h b/rpcs3/Emu/ARMv7/Modules/sceMotion.h index 7f1b986758..102108b336 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceMotion.h +++ b/rpcs3/Emu/ARMv7/Modules/sceMotion.h @@ -26,5 +26,3 @@ struct SceMotionSensorState le_t hostTimestamp; u8 reserve3[8]; }; - -extern psv_log_base sceMotion; diff --git a/rpcs3/Emu/ARMv7/Modules/sceMt19937.cpp b/rpcs3/Emu/ARMv7/Modules/sceMt19937.cpp index 885b9c9088..5acabc9c25 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceMt19937.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceMt19937.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceMt19937.h" +LOG_CHANNEL(sceMt19937); + s32 sceMt19937Init(vm::ptr pCtx, u32 seed) { throw EXCEPTION(""); @@ -15,15 +17,10 @@ u32 sceMt19937UInt(vm::ptr pCtx) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceMt19937, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceMt19937, nid, name) -psv_log_base sceMt19937("SceMt19937", []() +DECLARE(arm_module_manager::SceMt19937)("SceMt19937", []() { - sceMt19937.on_load = nullptr; - sceMt19937.on_unload = nullptr; - sceMt19937.on_stop = nullptr; - sceMt19937.on_error = nullptr; - REG_FUNC(0xEE5BA27C, sceMt19937Init); REG_FUNC(0x29E43BB5, sceMt19937UInt); }); diff --git a/rpcs3/Emu/ARMv7/Modules/sceMt19937.h b/rpcs3/Emu/ARMv7/Modules/sceMt19937.h index b647a670a8..65981e30bc 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceMt19937.h +++ b/rpcs3/Emu/ARMv7/Modules/sceMt19937.h @@ -5,5 +5,3 @@ struct SceMt19937Context le_t count; le_t state[624]; }; - -extern psv_log_base sceMt19937; diff --git a/rpcs3/Emu/ARMv7/Modules/sceNet.cpp b/rpcs3/Emu/ARMv7/Modules/sceNet.cpp index e873854dae..1775cb22a4 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceNet.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceNet.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceNet.h" +LOG_CHANNEL(sceNet); + s32 sceNetSetDnsInfo(vm::ptr info, s32 flags) { throw EXCEPTION(""); @@ -295,15 +297,10 @@ s32 sceNetGetStatisticsInfo(vm::ptr info, s32 flags) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceNet, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceNet, nid, name) -psv_log_base sceNet("SceNet", []() +DECLARE(arm_module_manager::SceNet)("SceNet", []() { - sceNet.on_load = nullptr; - sceNet.on_unload = nullptr; - sceNet.on_stop = nullptr; - sceNet.on_error = nullptr; - REG_FUNC(0xD62EF218, sceNetSetDnsInfo); REG_FUNC(0xFEC1166D, sceNetClearDnsCache); REG_FUNC(0xAFF9FA4D, sceNetDumpCreate); diff --git a/rpcs3/Emu/ARMv7/Modules/sceNet.h b/rpcs3/Emu/ARMv7/Modules/sceNet.h index 816f31541a..8173c492f5 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceNet.h +++ b/rpcs3/Emu/ARMv7/Modules/sceNet.h @@ -178,5 +178,3 @@ struct SceNetStatisticsInfo le_t libnet_mem_free_size; le_t libnet_mem_free_min; }; - -extern psv_log_base sceNet; diff --git a/rpcs3/Emu/ARMv7/Modules/sceNetCtl.cpp b/rpcs3/Emu/ARMv7/Modules/sceNetCtl.cpp index 46f3880b59..6a19caba05 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceNetCtl.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceNetCtl.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceNetCtl.h" +LOG_CHANNEL(sceNetCtl); + s32 sceNetCtlInit() { throw EXCEPTION(""); @@ -84,15 +86,10 @@ s32 sceNetCtlAdhocGetInAddr(vm::ptr inaddr) throw EXCEPTION(""); } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceNetCtl, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceNetCtl, nid, name) -psv_log_base sceNetCtl("SceNetCtl", []() +DECLARE(arm_module_manager::SceNetCtl)("SceNetCtl", []() { - sceNetCtl.on_load = nullptr; - sceNetCtl.on_unload = nullptr; - sceNetCtl.on_stop = nullptr; - sceNetCtl.on_error = nullptr; - REG_FUNC(0x495CA1DB, sceNetCtlInit); REG_FUNC(0xCD188648, sceNetCtlTerm); REG_FUNC(0xDFFC3ED4, sceNetCtlCheckCallback); diff --git a/rpcs3/Emu/ARMv7/Modules/sceNetCtl.h b/rpcs3/Emu/ARMv7/Modules/sceNetCtl.h index 212ed9bd4b..219486777c 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceNetCtl.h +++ b/rpcs3/Emu/ARMv7/Modules/sceNetCtl.h @@ -43,5 +43,3 @@ struct SceNetCtlAdhocPeerInfo }; using SceNetCtlCallback = void(s32 event_type, vm::ptr arg); - -extern psv_log_base sceNetCtl; diff --git a/rpcs3/Emu/ARMv7/Modules/sceNgs.cpp b/rpcs3/Emu/ARMv7/Modules/sceNgs.cpp index 6f38a0aff6..7b8005c8f0 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceNgs.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceNgs.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceNgs.h" +LOG_CHANNEL(sceNgs); + s32 sceNgsSystemGetRequiredMemorySize(vm::cptr pSynthParams, vm::ptr pnSize) { throw EXCEPTION(""); @@ -320,15 +322,10 @@ s32 sceSulphaNgsTrace(vm::cptr message) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceNgs, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceNgs, nid, name) -psv_log_base sceNgs("SceNgs", []() +DECLARE(arm_module_manager::SceNgs)("SceNgs", []() { - sceNgs.on_load = nullptr; - sceNgs.on_unload = nullptr; - sceNgs.on_stop = nullptr; - sceNgs.on_error = nullptr; - REG_FUNC(0x6CE8B36F, sceNgsSystemGetRequiredMemorySize); REG_FUNC(0xED14CF4A, sceNgsSystemInit); REG_FUNC(0x684F080C, sceNgsSystemUpdate); diff --git a/rpcs3/Emu/ARMv7/Modules/sceNgs.h b/rpcs3/Emu/ARMv7/Modules/sceNgs.h index ce2d70751a..3c0c34a9f6 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceNgs.h +++ b/rpcs3/Emu/ARMv7/Modules/sceNgs.h @@ -102,5 +102,3 @@ struct SceSulphaNgsConfig le_t maxNamedObjects; le_t maxTraceBufferBytes; }; - -extern psv_log_base sceNgs; diff --git a/rpcs3/Emu/ARMv7/Modules/sceNpBasic.cpp b/rpcs3/Emu/ARMv7/Modules/sceNpBasic.cpp index a081254608..c09a8002c4 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceNpBasic.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceNpBasic.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceNpBasic.h" +LOG_CHANNEL(sceNpBasic); + s32 sceNpBasicInit(vm::ptr opt) { throw EXCEPTION(""); @@ -94,15 +96,10 @@ s32 sceNpBasicGetPlaySessionLog(SceNpBasicPlaySessionLogType type, u32 index, vm throw EXCEPTION(""); } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceNpBasic, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceNpBasic, nid, name) -psv_log_base sceNpBasic("SceNpBasic", []() +DECLARE(arm_module_manager::SceNpBasic)("SceNpBasic", []() { - sceNpBasic.on_load = nullptr; - sceNpBasic.on_unload = nullptr; - sceNpBasic.on_stop = nullptr; - sceNpBasic.on_error = nullptr; - REG_FUNC(0xEFB91A99, sceNpBasicInit); REG_FUNC(0x389BCB3B, sceNpBasicTerm); REG_FUNC(0x26E6E048, sceNpBasicRegisterHandler); diff --git a/rpcs3/Emu/ARMv7/Modules/sceNpBasic.h b/rpcs3/Emu/ARMv7/Modules/sceNpBasic.h index 02c6f4b19e..4079e6c26e 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceNpBasic.h +++ b/rpcs3/Emu/ARMv7/Modules/sceNpBasic.h @@ -113,5 +113,3 @@ enum SceNpBasicPlaySessionLogType : s32 SCE_NP_BASIC_PLAY_SESSION_LOG_TYPE_BY_NP_COMM_ID = 1, SCE_NP_BASIC_PLAY_SESSION_LOG_TYPE_MAX = 2 }; - -extern psv_log_base sceNpBasic; diff --git a/rpcs3/Emu/ARMv7/Modules/sceNpCommon.cpp b/rpcs3/Emu/ARMv7/Modules/sceNpCommon.cpp index 477cab5523..f052347148 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceNpCommon.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceNpCommon.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceNpCommon.h" +LOG_CHANNEL(sceNpCommon); + s32 sceNpAuthInit() { throw EXCEPTION(""); @@ -59,15 +61,10 @@ s32 sceNpCmpNpIdInOrder(vm::cptr npid1, vm::cptr npid2, vm::pt throw EXCEPTION(""); } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceNpCommon, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceNpCommon, nid, name) -psv_log_base sceNpCommon("SceNpCommon", []() +DECLARE(arm_module_manager::SceNpCommon)("SceNpCommon", []() { - sceNpCommon.on_load = nullptr; - sceNpCommon.on_unload = nullptr; - sceNpCommon.on_stop = nullptr; - sceNpCommon.on_error = nullptr; - REG_FUNC(0x441D8B4E, sceNpAuthInit); REG_FUNC(0x6093B689, sceNpAuthTerm); REG_FUNC(0xED42079F, sceNpAuthCreateStartRequest); diff --git a/rpcs3/Emu/ARMv7/Modules/sceNpCommon.h b/rpcs3/Emu/ARMv7/Modules/sceNpCommon.h index 31c2ff9937..f1395ae5dc 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceNpCommon.h +++ b/rpcs3/Emu/ARMv7/Modules/sceNpCommon.h @@ -147,5 +147,3 @@ struct SceNpEntitlement le_t consumedCount; char padding[4]; }; - -extern psv_log_base sceNpCommon; diff --git a/rpcs3/Emu/ARMv7/Modules/sceNpManager.cpp b/rpcs3/Emu/ARMv7/Modules/sceNpManager.cpp index b2dcb72816..e964eaccd2 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceNpManager.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceNpManager.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceNpManager.h" +LOG_CHANNEL(sceNpManager); + s32 sceNpInit(vm::cptr commConf, vm::ptr opt) { throw EXCEPTION(""); @@ -54,15 +56,10 @@ s32 sceNpManagerGetChatRestrictionFlag(vm::ptr isRestricted) throw EXCEPTION(""); } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceNpManager, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceNpManager, nid, name) -psv_log_base sceNpManager("SceNpManager", []() +DECLARE(arm_module_manager::SceNpManager)("SceNpManager", []() { - sceNpManager.on_load = nullptr; - sceNpManager.on_unload = nullptr; - sceNpManager.on_stop = nullptr; - sceNpManager.on_error = nullptr; - REG_FUNC(0x04D9F484, sceNpInit); REG_FUNC(0x19E40AE1, sceNpTerm); REG_FUNC(0x3C94B4B4, sceNpManagerGetNpId); diff --git a/rpcs3/Emu/ARMv7/Modules/sceNpManager.h b/rpcs3/Emu/ARMv7/Modules/sceNpManager.h index 5753bf421d..6feb11b954 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceNpManager.h +++ b/rpcs3/Emu/ARMv7/Modules/sceNpManager.h @@ -8,5 +8,3 @@ struct SceNpOptParam }; using SceNpServiceStateCallback = void(SceNpServiceState state, vm::ptr userdata); - -extern psv_log_base sceNpManager; diff --git a/rpcs3/Emu/ARMv7/Modules/sceNpMatching.cpp b/rpcs3/Emu/ARMv7/Modules/sceNpMatching.cpp index d267f98bb4..0d19c7d717 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceNpMatching.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceNpMatching.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceNpMatching.h" +LOG_CHANNEL(sceNpMatching); + // Functions s32 sceNpMatching2Init(u32 poolSize, s32 threadPriority, s32 cpuAffinityMask, u32 threadStackSize) @@ -224,15 +226,10 @@ s32 sceNpMatching2SignalingGetPeerNetInfoResult( throw EXCEPTION(""); } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceNpMatching, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceNpMatching2, nid, name) -psv_log_base sceNpMatching("SceNpMatching2", []() +DECLARE(arm_module_manager::SceNpMatching)("SceNpMatching2", []() { - sceNpMatching.on_load = nullptr; - sceNpMatching.on_unload = nullptr; - sceNpMatching.on_stop = nullptr; - sceNpMatching.on_error = nullptr; - REG_FUNC(0xEBB1FE74, sceNpMatching2Init); REG_FUNC(0x0124641C, sceNpMatching2Term); REG_FUNC(0xADF578E1, sceNpMatching2CreateContext); diff --git a/rpcs3/Emu/ARMv7/Modules/sceNpMatching.h b/rpcs3/Emu/ARMv7/Modules/sceNpMatching.h index e438c38655..4385720830 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceNpMatching.h +++ b/rpcs3/Emu/ARMv7/Modules/sceNpMatching.h @@ -985,5 +985,3 @@ struct SceNpMatching2SignalingNetInfo SceNetInAddr mappedAddr; le_t natStatus; }; - -extern psv_log_base sceNpMatching; diff --git a/rpcs3/Emu/ARMv7/Modules/sceNpScore.cpp b/rpcs3/Emu/ARMv7/Modules/sceNpScore.cpp index ba7f686505..c9557fdc41 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceNpScore.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceNpScore.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceNpScore.h" +LOG_CHANNEL(sceNpScore); + s32 sceNpScoreInit(s32 threadPriority, s32 cpuAffinityMask, vm::ptr option) { throw EXCEPTION(""); @@ -276,15 +278,10 @@ s32 sceNpScoreSanitizeCommentAsync(s32 reqId, vm::cptr comment, vm::ptr pcId; u8 pad[4]; }; - -extern psv_log_base sceNpScore; diff --git a/rpcs3/Emu/ARMv7/Modules/sceNpUtility.cpp b/rpcs3/Emu/ARMv7/Modules/sceNpUtility.cpp index 1c76fffba6..561bd9d7a2 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceNpUtility.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceNpUtility.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceNpUtility.h" +LOG_CHANNEL(sceNpUtility); + s32 sceNpLookupInit(s32 usesAsync, s32 threadPriority, s32 cpuAffinityMask, vm::ptr option) { throw EXCEPTION(""); @@ -126,15 +128,10 @@ s32 sceNpBandwidthTestAbort() throw EXCEPTION(""); } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceNpUtility, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceNpUtility, nid, name) -psv_log_base sceNpUtility("SceNpUtility", []() +DECLARE(arm_module_manager::SceNpUtility)("SceNpUtility", []() { - sceNpUtility.on_load = nullptr; - sceNpUtility.on_unload = nullptr; - sceNpUtility.on_stop = nullptr; - sceNpUtility.on_error = nullptr; - REG_FUNC(0x9246A673, sceNpLookupInit); REG_FUNC(0x0158B61B, sceNpLookupTerm); REG_FUNC(0x5110E17E, sceNpLookupCreateTitleCtx); diff --git a/rpcs3/Emu/ARMv7/Modules/sceNpUtility.h b/rpcs3/Emu/ARMv7/Modules/sceNpUtility.h index dd2adec373..a66a429a5b 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceNpUtility.h +++ b/rpcs3/Emu/ARMv7/Modules/sceNpUtility.h @@ -9,5 +9,3 @@ struct SceNpBandwidthTestResult le_t result; char padding[4]; }; - -extern psv_log_base sceNpUtility; diff --git a/rpcs3/Emu/ARMv7/Modules/scePerf.cpp b/rpcs3/Emu/ARMv7/Modules/scePerf.cpp index 844c1e79bf..bb04f5b6ad 100644 --- a/rpcs3/Emu/ARMv7/Modules/scePerf.cpp +++ b/rpcs3/Emu/ARMv7/Modules/scePerf.cpp @@ -1,33 +1,29 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "scePerf.h" +LOG_CHANNEL(scePerf); + extern u64 get_system_time(); -s32 scePerfArmPmonReset(ARMv7Thread& context, s32 threadId) +arm_error_code scePerfArmPmonReset(ARMv7Thread& cpu, s32 threadId) { scePerf.warning("scePerfArmPmonReset(threadId=0x%x)", threadId); - if (threadId != SCE_PERF_ARM_PMON_THREAD_ID_SELF) - { - throw EXCEPTION("Unexpected thread"); - } + ASSERT(threadId == SCE_PERF_ARM_PMON_THREAD_ID_SELF); - context.counters = {}; + cpu.counters = {}; return SCE_OK; } -s32 scePerfArmPmonSelectEvent(ARMv7Thread& context, s32 threadId, u32 counter, u8 eventCode) +arm_error_code scePerfArmPmonSelectEvent(ARMv7Thread& cpu, s32 threadId, u32 counter, u8 eventCode) { scePerf.warning("scePerfArmPmonSelectEvent(threadId=0x%x, counter=0x%x, eventCode=0x%x)", threadId, counter, eventCode); - if (threadId != SCE_PERF_ARM_PMON_THREAD_ID_SELF) - { - throw EXCEPTION("Unexpected thread"); - } + ASSERT(threadId == SCE_PERF_ARM_PMON_THREAD_ID_SELF); if (counter >= 6) { @@ -66,44 +62,35 @@ s32 scePerfArmPmonSelectEvent(ARMv7Thread& context, s32 threadId, u32 counter, u } } - context.counters[counter].event = eventCode; - context.counters[counter].value = value; + cpu.counters[counter].event = eventCode; + cpu.counters[counter].value = value; return SCE_OK; } -s32 scePerfArmPmonStart(ARMv7Thread& context, s32 threadId) +arm_error_code scePerfArmPmonStart(ARMv7Thread& cpu, s32 threadId) { scePerf.warning("scePerfArmPmonStart(threadId=0x%x)", threadId); - if (threadId != SCE_PERF_ARM_PMON_THREAD_ID_SELF) - { - throw EXCEPTION("Unexpected thread"); - } + ASSERT(threadId == SCE_PERF_ARM_PMON_THREAD_ID_SELF); return SCE_OK; } -s32 scePerfArmPmonStop(ARMv7Thread& context, s32 threadId) +arm_error_code scePerfArmPmonStop(ARMv7Thread& cpu, s32 threadId) { scePerf.warning("scePerfArmPmonStop(threadId=0x%x)"); - if (threadId != SCE_PERF_ARM_PMON_THREAD_ID_SELF) - { - throw EXCEPTION("Unexpected thread"); - } + ASSERT(threadId == SCE_PERF_ARM_PMON_THREAD_ID_SELF); return SCE_OK; } -s32 scePerfArmPmonGetCounterValue(ARMv7Thread& context, s32 threadId, u32 counter, vm::ptr pValue) +arm_error_code scePerfArmPmonGetCounterValue(ARMv7Thread& cpu, s32 threadId, u32 counter, vm::ptr pValue) { scePerf.warning("scePerfArmPmonGetCounterValue(threadId=0x%x, counter=%d, pValue=*0x%x)", threadId, counter, pValue); - if (threadId != SCE_PERF_ARM_PMON_THREAD_ID_SELF) - { - throw EXCEPTION("Unexpected thread"); - } + ASSERT(threadId == SCE_PERF_ARM_PMON_THREAD_ID_SELF); if (counter >= 6 && counter != SCE_PERF_ARM_PMON_CYCLE_COUNTER) { @@ -112,7 +99,7 @@ s32 scePerfArmPmonGetCounterValue(ARMv7Thread& context, s32 threadId, u32 counte if (counter < 6) { - *pValue = context.counters[counter].value; + *pValue = cpu.counters[counter].value; } else { @@ -122,7 +109,7 @@ s32 scePerfArmPmonGetCounterValue(ARMv7Thread& context, s32 threadId, u32 counte return SCE_OK; } -s32 scePerfArmPmonSoftwareIncrement(ARMv7Thread& context, u32 mask) +arm_error_code scePerfArmPmonSoftwareIncrement(ARMv7Thread& cpu, u32 mask) { scePerf.warning("scePerfArmPmonSoftwareIncrement(mask=0x%x)", mask); @@ -135,7 +122,7 @@ s32 scePerfArmPmonSoftwareIncrement(ARMv7Thread& context, u32 mask) { if (mask & 1) { - context.counters[i].value++; + cpu.counters[i].value++; } } @@ -176,15 +163,10 @@ s32 sceRazorCpuSync() throw EXCEPTION(""); } -#define REG_FUNC(nid, name) reg_psv_func(nid, &scePerf, #name, name) +#define REG_FUNC(nid, name) REG_FNID(ScePerf, nid, name) -psv_log_base scePerf("ScePerf", []() +DECLARE(arm_module_manager::ScePerf)("ScePerf", []() { - scePerf.on_load = nullptr; - scePerf.on_unload = nullptr; - scePerf.on_stop = nullptr; - //scePerf.on_error = nullptr; // keep default error handler - REG_FUNC(0x35151735, scePerfArmPmonReset); REG_FUNC(0x63CBEA8B, scePerfArmPmonSelectEvent); REG_FUNC(0xC9D969D5, scePerfArmPmonStart); diff --git a/rpcs3/Emu/ARMv7/Modules/scePerf.h b/rpcs3/Emu/ARMv7/Modules/scePerf.h index cf8b27c891..81d4833320 100644 --- a/rpcs3/Emu/ARMv7/Modules/scePerf.h +++ b/rpcs3/Emu/ARMv7/Modules/scePerf.h @@ -1,11 +1,24 @@ #pragma once -enum +#include "Emu/ARMv7/ErrorCodes.h" + +enum ScePerfError : s32 { // Error Codes - SCE_PERF_ERROR_INVALID_ARGUMENT = 0x80580000, + SCE_PERF_ERROR_INVALID_ARGUMENT = ERROR_CODE(0x80580000), }; +template<> +inline const char* arm_error_code::print(ScePerfError error) +{ + switch (error) + { + STR_CASE(SCE_PERF_ERROR_INVALID_ARGUMENT); + } + + return nullptr; +} + enum : s32 { // Thread IDs @@ -89,5 +102,3 @@ enum : u8 SCE_PERF_ARM_PMON_PLE_FIFO_OVERFLOW = 0xA4, SCE_PERF_ARM_PMON_PLE_REQ_PROGRAMMED = 0xA5, }; - -extern psv_log_base scePerf; diff --git a/rpcs3/Emu/ARMv7/Modules/scePgf.cpp b/rpcs3/Emu/ARMv7/Modules/scePgf.cpp index ec4fb307bf..550c08def8 100644 --- a/rpcs3/Emu/ARMv7/Modules/scePgf.cpp +++ b/rpcs3/Emu/ARMv7/Modules/scePgf.cpp @@ -1,18 +1,15 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "scePgf.h" -#define REG_FUNC(nid, name) reg_psv_func(nid, &scePgf, #name, name) +LOG_CHANNEL(scePgf); -psv_log_base scePgf("ScePgf", []() +#define REG_FUNC(nid, name) REG_FNID(ScePgf, nid, name) + +DECLARE(arm_module_manager::ScePgf)("ScePgf", []() { - scePgf.on_load = nullptr; - scePgf.on_unload = nullptr; - scePgf.on_stop = nullptr; - scePgf.on_error = nullptr; - //REG_FUNC(0x1055ABA3, sceFontNewLib); //REG_FUNC(0x07EE1733, sceFontDoneLib); //REG_FUNC(0xDE47674C, sceFontSetResolution); diff --git a/rpcs3/Emu/ARMv7/Modules/scePgf.h b/rpcs3/Emu/ARMv7/Modules/scePgf.h index 0b299c6785..6f70f09bee 100644 --- a/rpcs3/Emu/ARMv7/Modules/scePgf.h +++ b/rpcs3/Emu/ARMv7/Modules/scePgf.h @@ -1,3 +1 @@ #pragma once - -extern psv_log_base scePgf; diff --git a/rpcs3/Emu/ARMv7/Modules/scePhotoExport.cpp b/rpcs3/Emu/ARMv7/Modules/scePhotoExport.cpp index a3bb019b95..d2caa21947 100644 --- a/rpcs3/Emu/ARMv7/Modules/scePhotoExport.cpp +++ b/rpcs3/Emu/ARMv7/Modules/scePhotoExport.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "scePhotoExport.h" +LOG_CHANNEL(scePhotoExport); + s32 scePhotoExportFromData( vm::cptr photodata, s32 photodataSize, @@ -29,15 +31,10 @@ s32 scePhotoExportFromFile( throw EXCEPTION(""); } -#define REG_FUNC(nid, name) reg_psv_func(nid, &scePhotoExport, #name, name) +#define REG_FUNC(nid, name) REG_FNID(libScePhotoExport, nid, name) -psv_log_base scePhotoExport("ScePhotoExport", []() +DECLARE(arm_module_manager::ScePhotoExport)("libScePhotoExport", []() { - scePhotoExport.on_load = nullptr; - scePhotoExport.on_unload = nullptr; - scePhotoExport.on_stop = nullptr; - scePhotoExport.on_error = nullptr; - REG_FUNC(0x70512321, scePhotoExportFromData); REG_FUNC(0x84FD9FC5, scePhotoExportFromFile); }); diff --git a/rpcs3/Emu/ARMv7/Modules/scePhotoExport.h b/rpcs3/Emu/ARMv7/Modules/scePhotoExport.h index 23b25755b8..bff84f9810 100644 --- a/rpcs3/Emu/ARMv7/Modules/scePhotoExport.h +++ b/rpcs3/Emu/ARMv7/Modules/scePhotoExport.h @@ -10,5 +10,3 @@ struct ScePhotoExportParam }; using ScePhotoExportCancelFunc = s32(vm::ptr); - -extern psv_log_base scePhotoExport; diff --git a/rpcs3/Emu/ARMv7/Modules/sceRazorCapture.cpp b/rpcs3/Emu/ARMv7/Modules/sceRazorCapture.cpp index 9107db2660..5fa33f4102 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceRazorCapture.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceRazorCapture.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceRazorCapture.h" +LOG_CHANNEL(sceRazorCapture); + void sceRazorCaptureSetTrigger(u32 frameIndex, vm::cptr captureFilename) { throw EXCEPTION(""); @@ -19,15 +21,10 @@ b8 sceRazorCaptureIsInProgress() throw EXCEPTION(""); } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceRazorCapture, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceRazorCapture, nid, name) -psv_log_base sceRazorCapture("SceRazorCapture", []() +DECLARE(arm_module_manager::SceRazorCapture)("SceRazorCapture", []() { - sceRazorCapture.on_load = nullptr; - sceRazorCapture.on_unload = nullptr; - sceRazorCapture.on_stop = nullptr; - sceRazorCapture.on_error = nullptr; - REG_FUNC(0x911E0AA0, sceRazorCaptureIsInProgress); REG_FUNC(0xE916B538, sceRazorCaptureSetTrigger); REG_FUNC(0x3D4B7E68, sceRazorCaptureSetTriggerNextFrame); diff --git a/rpcs3/Emu/ARMv7/Modules/sceRazorCapture.h b/rpcs3/Emu/ARMv7/Modules/sceRazorCapture.h index 25a64f6465..6f70f09bee 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceRazorCapture.h +++ b/rpcs3/Emu/ARMv7/Modules/sceRazorCapture.h @@ -1,3 +1 @@ #pragma once - -extern psv_log_base sceRazorCapture; diff --git a/rpcs3/Emu/ARMv7/Modules/sceRtc.cpp b/rpcs3/Emu/ARMv7/Modules/sceRtc.cpp index 2464327af3..b0c8836dc6 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceRtc.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceRtc.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceRtc.h" +LOG_CHANNEL(sceRtc); + u32 sceRtcGetTickResolution() { throw EXCEPTION(""); @@ -190,15 +192,10 @@ s32 sceRtcParseRFC3339(vm::ptr pUtc, vm::cptr pszDateTime) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceRtc, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceRtcUser, nid, name) -psv_log_base sceRtc("SceRtc", []() +DECLARE(arm_module_manager::SceRtc)("SceRtcUser", []() { - sceRtc.on_load = nullptr; - sceRtc.on_unload = nullptr; - sceRtc.on_stop = nullptr; - sceRtc.on_error = nullptr; - REG_FUNC(0x23F79274, sceRtcGetCurrentTick); REG_FUNC(0xCDDD25FE, sceRtcGetCurrentNetworkTick); REG_FUNC(0x70FDE8F1, sceRtcGetCurrentClock); diff --git a/rpcs3/Emu/ARMv7/Modules/sceRtc.h b/rpcs3/Emu/ARMv7/Modules/sceRtc.h index 2c60084b05..6f70f09bee 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceRtc.h +++ b/rpcs3/Emu/ARMv7/Modules/sceRtc.h @@ -1,3 +1 @@ #pragma once - -extern psv_log_base sceRtc; diff --git a/rpcs3/Emu/ARMv7/Modules/sceSas.cpp b/rpcs3/Emu/ARMv7/Modules/sceSas.cpp index 40ee51bfaf..52088d1e00 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceSas.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceSas.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceSas.h" +LOG_CHANNEL(sceSas); + s32 sceSasGetNeededMemorySize(vm::cptr config, vm::ptr outSize) { throw EXCEPTION(""); @@ -150,15 +152,10 @@ s32 sceSasSetEffectParam(u32 delayTime, u32 feedback) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceSas, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceSas, nid, name) -psv_log_base sceSas("SceSas", []() +DECLARE(arm_module_manager::SceSas)("SceSas", []() { - sceSas.on_load = nullptr; - sceSas.on_unload = nullptr; - sceSas.on_stop = nullptr; - sceSas.on_error = nullptr; - //REG_FUNC(0xA2209C58, sceAsSetRegisterReportHandler); //REG_FUNC(0xBB635544, sceAsSetUnregisterReportHandler); //REG_FUNC(0xF578F0EF, sceAsGetSystemNeededMemory); diff --git a/rpcs3/Emu/ARMv7/Modules/sceSas.h b/rpcs3/Emu/ARMv7/Modules/sceSas.h index d60bd26155..6f70f09bee 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceSas.h +++ b/rpcs3/Emu/ARMv7/Modules/sceSas.h @@ -1,3 +1 @@ #pragma once - -extern psv_log_base sceSas; diff --git a/rpcs3/Emu/ARMv7/Modules/sceScreenShot.cpp b/rpcs3/Emu/ARMv7/Modules/sceScreenShot.cpp index 62e4c88e00..a1d4385b02 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceScreenShot.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceScreenShot.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceScreenShot.h" +LOG_CHANNEL(sceScreenShot); + s32 sceScreenShotSetParam(vm::cptr param) { throw EXCEPTION(""); @@ -25,15 +27,10 @@ s32 sceScreenShotEnable() } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceScreenShot, #name, name) +#define REG_FUNC(nid, name) REG_FNID(libSceScreenShot, nid, name) -psv_log_base sceScreenShot("SceScreenShot", []() +DECLARE(arm_module_manager::SceScreenShot)("libSceScreenShot", []() { - sceScreenShot.on_load = nullptr; - sceScreenShot.on_unload = nullptr; - sceScreenShot.on_stop = nullptr; - sceScreenShot.on_error = nullptr; - REG_FUNC(0x05DB59C7, sceScreenShotSetParam); REG_FUNC(0x7061665B, sceScreenShotSetOverlayImage); REG_FUNC(0x50AE9FF9, sceScreenShotDisable); diff --git a/rpcs3/Emu/ARMv7/Modules/sceScreenShot.h b/rpcs3/Emu/ARMv7/Modules/sceScreenShot.h index 9aab6bef39..98d79a5b27 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceScreenShot.h +++ b/rpcs3/Emu/ARMv7/Modules/sceScreenShot.h @@ -7,5 +7,3 @@ struct SceScreenShotParam vm::lcptr gameComment; vm::lptr reserved; }; - -extern psv_log_base sceScreenShot; diff --git a/rpcs3/Emu/ARMv7/Modules/sceSfmt.cpp b/rpcs3/Emu/ARMv7/Modules/sceSfmt.cpp index 57931d32be..601c7d02de 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceSfmt.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceSfmt.cpp @@ -1,18 +1,13 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" -extern psv_log_base sceSfmt; +LOG_CHANNEL(sceSfmt); -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceSfmt, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceSfmt, nid, name) -psv_log_base sceSfmt("SceSfmt", []() +DECLARE(arm_module_manager::SceSfmt)("SceSfmt", []() { - sceSfmt.on_load = nullptr; - sceSfmt.on_unload = nullptr; - sceSfmt.on_stop = nullptr; - sceSfmt.on_error = nullptr; - //REG_FUNC(0x8FF464C9, sceSfmt11213InitGenRand); //REG_FUNC(0xBAF5F058, sceSfmt11213InitByArray); //REG_FUNC(0xFB281CD7, sceSfmt11213GenRand32); diff --git a/rpcs3/Emu/ARMv7/Modules/sceSha.cpp b/rpcs3/Emu/ARMv7/Modules/sceSha.cpp index 2fb134841e..a5322de9f6 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceSha.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceSha.cpp @@ -1,18 +1,13 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" -extern psv_log_base sceSha; +LOG_CHANNEL(sceSha); -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceSha, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceSha, nid, name) -psv_log_base sceSha("SceSha", []() +DECLARE(arm_module_manager::SceSha)("SceSha", []() { - sceSha.on_load = nullptr; - sceSha.on_unload = nullptr; - sceSha.on_stop = nullptr; - sceSha.on_error = nullptr; - //REG_FUNC(0xD19A9AA8, sceSha0Digest); //REG_FUNC(0xBCF6DB3A, sceSha0BlockInit); //REG_FUNC(0x37EF2AFC, sceSha0BlockUpdate); diff --git a/rpcs3/Emu/ARMv7/Modules/sceSqlite.cpp b/rpcs3/Emu/ARMv7/Modules/sceSqlite.cpp index 2acaffae9d..8d50081196 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceSqlite.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceSqlite.cpp @@ -1,18 +1,15 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceSqlite.h" -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceSqlite, #name, name) +LOG_CHANNEL(sceSqlite); -psv_log_base sceSqlite("SceSqlite", []() +#define REG_FUNC(nid, name) REG_FNID(SceSqlite, nid, name) + +DECLARE(arm_module_manager::SceSqlite)("SceSqlite", []() { - sceSqlite.on_load = nullptr; - sceSqlite.on_unload = nullptr; - sceSqlite.on_stop = nullptr; - sceSqlite.on_error = nullptr; - //REG_FUNC(0x26E46324, sqlite3_libversion); //REG_FUNC(0x4CCB58A2, sqlite3_sourceid); //REG_FUNC(0x5982F404, sqlite3_libversion_number); diff --git a/rpcs3/Emu/ARMv7/Modules/sceSqlite.h b/rpcs3/Emu/ARMv7/Modules/sceSqlite.h index be4fc046b7..6f70f09bee 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceSqlite.h +++ b/rpcs3/Emu/ARMv7/Modules/sceSqlite.h @@ -1,3 +1 @@ #pragma once - -extern psv_log_base sceSqlite; diff --git a/rpcs3/Emu/ARMv7/Modules/sceSsl.cpp b/rpcs3/Emu/ARMv7/Modules/sceSsl.cpp index 75e72e4717..1a9979517f 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceSsl.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceSsl.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceSsl.h" +LOG_CHANNEL(sceSsl); + s32 sceSslInit(u32 poolSize) { throw EXCEPTION(""); @@ -60,15 +62,10 @@ s32 sceSslFreeSslCertName(vm::ptr certName) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceSsl, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceSsl, nid, name) -psv_log_base sceSsl("SceSsl", []() +DECLARE(arm_module_manager::SceSsl)("SceSsl", []() { - sceSsl.on_load = nullptr; - sceSsl.on_unload = nullptr; - sceSsl.on_stop = nullptr; - sceSsl.on_error = nullptr; - REG_FUNC(0x3C733316, sceSslInit); REG_FUNC(0x03CE6E3A, sceSslTerm); REG_FUNC(0xBD203262, sceSslGetMemoryPoolStats); diff --git a/rpcs3/Emu/ARMv7/Modules/sceSsl.h b/rpcs3/Emu/ARMv7/Modules/sceSsl.h index 4d9f7a9bb3..ef70e48946 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceSsl.h +++ b/rpcs3/Emu/ARMv7/Modules/sceSsl.h @@ -10,5 +10,3 @@ struct SceSslMemoryPoolStats le_t currentInuseSize; le_t reserved; }; - -extern psv_log_base sceSsl; diff --git a/rpcs3/Emu/ARMv7/Modules/sceSulpha.cpp b/rpcs3/Emu/ARMv7/Modules/sceSulpha.cpp index eabbe2c065..3210e04906 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceSulpha.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceSulpha.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceSulpha.h" +LOG_CHANNEL(sceSulpha); + s32 sceSulphaNetworkInit() { throw EXCEPTION(""); @@ -70,15 +72,10 @@ s32 sceSulphaAgentsUnregister(vm::cptr handles, u32 agentCount) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceSulpha, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceSulpha, nid, name) -psv_log_base sceSulpha("SceSulpha", []() +DECLARE(arm_module_manager::SceSulpha)("SceSulpha", []() { - sceSulpha.on_load = nullptr; - sceSulpha.on_unload = nullptr; - sceSulpha.on_stop = nullptr; - sceSulpha.on_error = nullptr; - REG_FUNC(0xB4668AEA, sceSulphaNetworkInit); REG_FUNC(0x0FC71B72, sceSulphaNetworkShutdown); REG_FUNC(0xA6A05C50, sceSulphaGetDefaultConfig); diff --git a/rpcs3/Emu/ARMv7/Modules/sceSulpha.h b/rpcs3/Emu/ARMv7/Modules/sceSulpha.h index e373c37e8e..a513d22bfd 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceSulpha.h +++ b/rpcs3/Emu/ARMv7/Modules/sceSulpha.h @@ -12,5 +12,3 @@ struct SceSulphaConfig struct SceSulphaAgentsRegister; using SceSulphaHandle = void; - -extern psv_log_base sceSulpha; diff --git a/rpcs3/Emu/ARMv7/Modules/sceSysmodule.cpp b/rpcs3/Emu/ARMv7/Modules/sceSysmodule.cpp index 7637ba5aa8..6906f2cf3a 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceSysmodule.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceSysmodule.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceSysmodule.h" +LOG_CHANNEL(sceSysmodule); + s32 sceSysmoduleLoadModule(u16 id) { sceSysmodule.warning("sceSysmoduleLoadModule(id=0x%04x) -> SCE_OK", id); @@ -25,15 +27,10 @@ s32 sceSysmoduleIsLoaded(u16 id) return SCE_OK; // module is loaded } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceSysmodule, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceSysmodule, nid, name) -psv_log_base sceSysmodule("SceSysmodule", []() +DECLARE(arm_module_manager::SceSysmodule)("SceSysmodule", []() { - sceSysmodule.on_load = nullptr; - sceSysmodule.on_unload = nullptr; - sceSysmodule.on_stop = nullptr; - sceSysmodule.on_error = nullptr; - REG_FUNC(0x79A0160A, sceSysmoduleLoadModule); REG_FUNC(0x31D87805, sceSysmoduleUnloadModule); REG_FUNC(0x53099B7A, sceSysmoduleIsLoaded); diff --git a/rpcs3/Emu/ARMv7/Modules/sceSysmodule.h b/rpcs3/Emu/ARMv7/Modules/sceSysmodule.h index 0153c8725d..6f70f09bee 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceSysmodule.h +++ b/rpcs3/Emu/ARMv7/Modules/sceSysmodule.h @@ -1,3 +1 @@ #pragma once - -extern psv_log_base sceSysmodule; diff --git a/rpcs3/Emu/ARMv7/Modules/sceSystemGesture.cpp b/rpcs3/Emu/ARMv7/Modules/sceSystemGesture.cpp index f9e9c0f318..6d6dedf763 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceSystemGesture.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceSystemGesture.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceSystemGesture.h" +LOG_CHANNEL(sceSystemGesture); + s32 sceSystemGestureInitializePrimitiveTouchRecognizer(vm::ptr parameter) { throw EXCEPTION(""); @@ -90,15 +92,10 @@ s32 sceSystemGestureGetTouchEventByEventID(vm::cptr pPanelInfo) { throw EXCEPTION(""); @@ -30,15 +32,10 @@ s32 sceTouchGetSamplingState(u32 port, vm::ptr pState) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceTouch, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceTouch, nid, name) -psv_log_base sceTouch("SceTouch", []() +DECLARE(arm_module_manager::SceTouch)("SceTouch", []() { - sceTouch.on_load = nullptr; - sceTouch.on_unload = nullptr; - sceTouch.on_stop = nullptr; - sceTouch.on_error = nullptr; - REG_FUNC(0x169A1D58, sceTouchRead); REG_FUNC(0xFF082DF0, sceTouchPeek); REG_FUNC(0x1B9C5D14, sceTouchSetSamplingState); diff --git a/rpcs3/Emu/ARMv7/Modules/sceTouch.h b/rpcs3/Emu/ARMv7/Modules/sceTouch.h index 021f6a86c6..0905fad0b0 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceTouch.h +++ b/rpcs3/Emu/ARMv7/Modules/sceTouch.h @@ -32,5 +32,3 @@ struct SceTouchData le_t reportNum; SceTouchReport report[8]; }; - -extern psv_log_base sceTouch; diff --git a/rpcs3/Emu/ARMv7/Modules/sceUlt.cpp b/rpcs3/Emu/ARMv7/Modules/sceUlt.cpp index 4b47e74181..445cf18212 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceUlt.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceUlt.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceUlt.h" +LOG_CHANNEL(sceUlt); + // Functions s32 _sceUltWaitingQueueResourcePoolOptParamInitialize(vm::ptr optParam, u32 buildVersion) @@ -384,15 +386,10 @@ s32 sceUltUlthreadGetSelf(vm::pptr ulthread) throw EXCEPTION(""); } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceUlt, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceUlt, nid, name) -psv_log_base sceUlt("SceUlt", []() +DECLARE(arm_module_manager::SceUlt)("SceUlt", []() { - sceUlt.on_load = nullptr; - sceUlt.on_unload = nullptr; - sceUlt.on_stop = nullptr; - sceUlt.on_error = nullptr; - REG_FUNC(0xEF094E35, _sceUltWaitingQueueResourcePoolOptParamInitialize); REG_FUNC(0x644DA029, sceUltWaitingQueueResourcePoolGetWorkAreaSize); REG_FUNC(0x62F9493E, _sceUltWaitingQueueResourcePoolCreate); diff --git a/rpcs3/Emu/ARMv7/Modules/sceUlt.h b/rpcs3/Emu/ARMv7/Modules/sceUlt.h index 42e741f2a7..0518badd7d 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceUlt.h +++ b/rpcs3/Emu/ARMv7/Modules/sceUlt.h @@ -154,5 +154,3 @@ struct SceUltUlthread CHECK_SIZE(SceUltUlthread, 256); using SceUltUlthreadEntry = s32(u32 arg); - -extern psv_log_base sceUlt; diff --git a/rpcs3/Emu/ARMv7/Modules/sceVideodec.cpp b/rpcs3/Emu/ARMv7/Modules/sceVideodec.cpp index 190645df00..9c57870236 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceVideodec.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceVideodec.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceVideodec.h" +LOG_CHANNEL(sceVideodec); + s32 sceVideodecInitLibrary(u32 codecType, vm::cptr pInitInfo) { throw EXCEPTION(""); @@ -50,15 +52,10 @@ s32 sceAvcdecDecodeFlush(vm::ptr pCtrl) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceVideodec, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceVideodecUser, nid, name) -psv_log_base sceVideodec("SceVideodec", []() +DECLARE(arm_module_manager::SceVideodec)("SceVideodecUser", []() { - sceVideodec.on_load = nullptr; - sceVideodec.on_unload = nullptr; - sceVideodec.on_stop = nullptr; - sceVideodec.on_error = nullptr; - REG_FUNC(0xF1AF65A3, sceVideodecInitLibrary); REG_FUNC(0x3A5F4924, sceVideodecTermLibrary); REG_FUNC(0x97E95EDB, sceAvcdecQueryDecoderMemSize); diff --git a/rpcs3/Emu/ARMv7/Modules/sceVideodec.h b/rpcs3/Emu/ARMv7/Modules/sceVideodec.h index 825d4fc1b3..0ea43e1eea 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceVideodec.h +++ b/rpcs3/Emu/ARMv7/Modules/sceVideodec.h @@ -122,5 +122,3 @@ struct SceAvcdecArrayPicture le_t numOfElm; vm::lpptr pPicture; }; - -extern psv_log_base sceVideodec; diff --git a/rpcs3/Emu/ARMv7/Modules/sceVoice.cpp b/rpcs3/Emu/ARMv7/Modules/sceVoice.cpp index a76177503e..b0c1d53bca 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceVoice.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceVoice.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceVoice.h" +LOG_CHANNEL(sceVoice); + s32 sceVoiceInit(vm::ptr pArg, SceVoiceVersion version) { throw EXCEPTION(""); @@ -130,15 +132,10 @@ s32 sceVoiceGetResourceInfo(vm::ptr pInfo) } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceVoice, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceVoice, nid, name) -psv_log_base sceVoice("SceVoice", []() +DECLARE(arm_module_manager::SceVoice)("SceVoice", []() { - sceVoice.on_load = nullptr; - sceVoice.on_unload = nullptr; - sceVoice.on_stop = nullptr; - sceVoice.on_error = nullptr; - REG_FUNC(0xD02C00B4, sceVoiceGetBitRate); REG_FUNC(0xC913F7E9, sceVoiceGetMuteFlag); REG_FUNC(0x875CC80D, sceVoiceGetVolume); diff --git a/rpcs3/Emu/ARMv7/Modules/sceVoice.h b/rpcs3/Emu/ARMv7/Modules/sceVoice.h index a7986df9a6..4006e05f17 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceVoice.h +++ b/rpcs3/Emu/ARMv7/Modules/sceVoice.h @@ -128,5 +128,3 @@ struct SceVoiceStartParam le_t container; u8 reserved[28]; }; - -extern psv_log_base sceVoice; diff --git a/rpcs3/Emu/ARMv7/Modules/sceVoiceQoS.cpp b/rpcs3/Emu/ARMv7/Modules/sceVoiceQoS.cpp index 0adead3bfc..b584945713 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceVoiceQoS.cpp +++ b/rpcs3/Emu/ARMv7/Modules/sceVoiceQoS.cpp @@ -1,9 +1,11 @@ #include "stdafx.h" #include "Emu/System.h" -#include "Emu/ARMv7/PSVFuncList.h" +#include "Emu/ARMv7/ARMv7Module.h" #include "sceVoiceQoS.h" +LOG_CHANNEL(sceVoiceQoS); + s32 sceVoiceQoSInit() { throw EXCEPTION(""); @@ -90,15 +92,10 @@ s32 sceVoiceQoSReadPacket(s32 connectionId, vm::ptr pData, vm::ptr pS } -#define REG_FUNC(nid, name) reg_psv_func(nid, &sceVoiceQoS, #name, name) +#define REG_FUNC(nid, name) REG_FNID(SceVoiceQoS, nid, name) -psv_log_base sceVoiceQoS("SceVoiceQos", []() +DECLARE(arm_module_manager::SceVoiceQoS)("SceVoiceQoS", []() { - sceVoiceQoS.on_load = nullptr; - sceVoiceQoS.on_unload = nullptr; - sceVoiceQoS.on_stop = nullptr; - sceVoiceQoS.on_error = nullptr; - REG_FUNC(0x4B5FFF1C, sceVoiceQoSInit); REG_FUNC(0xFB0B747B, sceVoiceQoSEnd); REG_FUNC(0xAAB54BE4, sceVoiceQoSCreateLocalEndpoint); diff --git a/rpcs3/Emu/ARMv7/Modules/sceVoiceQoS.h b/rpcs3/Emu/ARMv7/Modules/sceVoiceQoS.h index c66b56b366..4dbb38f0c3 100644 --- a/rpcs3/Emu/ARMv7/Modules/sceVoiceQoS.h +++ b/rpcs3/Emu/ARMv7/Modules/sceVoiceQoS.h @@ -17,5 +17,3 @@ enum SceVoiceQoSStatusId : s32 SCE_VOICE_QOS_IN_FRAME_RECEIVED_RATIO, SCE_VOICE_QOS_HEARTBEAT_FLAG }; - -extern psv_log_base sceVoiceQoS; diff --git a/rpcs3/Emu/ARMv7/Modules/sceXml.h b/rpcs3/Emu/ARMv7/Modules/sceXml.h deleted file mode 100644 index ea5d63ed71..0000000000 --- a/rpcs3/Emu/ARMv7/Modules/sceXml.h +++ /dev/null @@ -1,3 +0,0 @@ -#pragma once - -extern psv_log_base sceXml; diff --git a/rpcs3/Emu/ARMv7/PSVFuncList.cpp b/rpcs3/Emu/ARMv7/PSVFuncList.cpp deleted file mode 100644 index d293d066b1..0000000000 --- a/rpcs3/Emu/ARMv7/PSVFuncList.cpp +++ /dev/null @@ -1,256 +0,0 @@ -#include "stdafx.h" -#include "Emu/System.h" -#include "ARMv7Thread.h" -#include "PSVFuncList.h" - -psv_log_base::psv_log_base(const std::string& name, init_func_t init) - : _log::channel(name) - , m_init(init) -{ - on_error = [this](s32 code, psv_func* func) - { - if (code < 0) - { - error("%s() failed: 0x%08X", func->name, code); - Emu.Pause(); - } - }; -} - -std::vector g_psv_func_list; -std::vector g_psv_modules; - -u32 add_psv_func(psv_func data) -{ - for (auto& f : g_psv_func_list) - { - assert(f.nid != data.nid || (&f - g_psv_func_list.data()) < SFI_MAX); - } - - g_psv_func_list.push_back(data); - return (u32)(g_psv_func_list.size() - 1); -} - -psv_func* get_psv_func_by_nid(u32 nid, u32* out_index) -{ - for (auto& f : g_psv_func_list) - { - if (f.nid == nid && &f - g_psv_func_list.data()) - { - const u32 index = (u32)(&f - g_psv_func_list.data()); - - if (index < SFI_MAX) - { - continue; - } - - if (out_index) - { - *out_index = index; - } - - return &f; - } - } - - return nullptr; -} - -psv_func* get_psv_func_by_index(u32 index) -{ - if (index >= g_psv_func_list.size()) - { - return nullptr; - } - - return &g_psv_func_list[index]; -} - -void execute_psv_func_by_index(ARMv7Thread& context, u32 index) -{ - if (auto func = get_psv_func_by_index(index)) - { - const u32 old_func = context.hle_func; - context.hle_func = func->nid; - - if (func->func) - { - func->func(context); - } - else - { - throw EXCEPTION("Unimplemented function"); - } - - // rough error code processing - if (context.GPR[0] && func->module && func->module->on_error) - { - func->module->on_error(context.GPR[0], func); - } - - context.hle_func = old_func; - } - else - { - throw EXCEPTION("Invalid function index"); - } -} - -extern psv_log_base sceAppMgr; -extern psv_log_base sceAppUtil; -extern psv_log_base sceAudio; -extern psv_log_base sceAudiodec; -extern psv_log_base sceAudioenc; -extern psv_log_base sceAudioIn; -extern psv_log_base sceCamera; -extern psv_log_base sceCodecEngine; -extern psv_log_base sceCommonDialog; -extern psv_log_base sceCtrl; -extern psv_log_base sceDbg; -extern psv_log_base sceDeci4p; -extern psv_log_base sceDeflt; -extern psv_log_base sceDisplay; -extern psv_log_base sceFiber; -extern psv_log_base sceFios; -extern psv_log_base sceFpu; -extern psv_log_base sceGxm; -extern psv_log_base sceHttp; -extern psv_log_base sceIme; -extern psv_log_base sceJpeg; -extern psv_log_base sceJpegEnc; -extern psv_log_base sceLibc; -extern psv_log_base sceLibKernel; -extern psv_log_base sceLibm; -extern psv_log_base sceLibstdcxx; -extern psv_log_base sceLiveArea; -extern psv_log_base sceLocation; -extern psv_log_base sceMd5; -extern psv_log_base sceMotion; -extern psv_log_base sceMt19937; -extern psv_log_base sceNet; -extern psv_log_base sceNetCtl; -extern psv_log_base sceNgs; -extern psv_log_base sceNpBasic; -extern psv_log_base sceNpCommon; -extern psv_log_base sceNpManager; -extern psv_log_base sceNpMatching; -extern psv_log_base sceNpScore; -extern psv_log_base sceNpUtility; -extern psv_log_base scePerf; -extern psv_log_base scePgf; -extern psv_log_base scePhotoExport; -extern psv_log_base sceRazorCapture; -extern psv_log_base sceRtc; -extern psv_log_base sceSas; -extern psv_log_base sceScreenShot; -extern psv_log_base sceSfmt; -extern psv_log_base sceSha; -extern psv_log_base sceSqlite; -extern psv_log_base sceSsl; -extern psv_log_base sceSulpha; -extern psv_log_base sceSysmodule; -extern psv_log_base sceSystemGesture; -extern psv_log_base sceTouch; -extern psv_log_base sceUlt; -extern psv_log_base sceVideodec; -extern psv_log_base sceVoice; -extern psv_log_base sceVoiceQoS; -extern psv_log_base sceXml; - -void initialize_psv_modules() -{ - assert(!g_psv_func_list.size() && !g_psv_modules.size()); - - // fill module list - g_psv_modules.push_back(&sceAppMgr); - g_psv_modules.push_back(&sceAppUtil); - g_psv_modules.push_back(&sceAudio); - g_psv_modules.push_back(&sceAudiodec); - g_psv_modules.push_back(&sceAudioenc); - g_psv_modules.push_back(&sceAudioIn); - g_psv_modules.push_back(&sceCamera); - g_psv_modules.push_back(&sceCodecEngine); - g_psv_modules.push_back(&sceCommonDialog); - g_psv_modules.push_back(&sceCtrl); - g_psv_modules.push_back(&sceDbg); - g_psv_modules.push_back(&sceDeci4p); - g_psv_modules.push_back(&sceDeflt); - g_psv_modules.push_back(&sceDisplay); - g_psv_modules.push_back(&sceFiber); - g_psv_modules.push_back(&sceFios); - g_psv_modules.push_back(&sceFpu); - g_psv_modules.push_back(&sceGxm); - g_psv_modules.push_back(&sceHttp); - g_psv_modules.push_back(&sceIme); - g_psv_modules.push_back(&sceJpeg); - g_psv_modules.push_back(&sceJpegEnc); - g_psv_modules.push_back(&sceLibc); - g_psv_modules.push_back(&sceLibKernel); - g_psv_modules.push_back(&sceLibm); - g_psv_modules.push_back(&sceLibstdcxx); - g_psv_modules.push_back(&sceLiveArea); - g_psv_modules.push_back(&sceLocation); - g_psv_modules.push_back(&sceMd5); - g_psv_modules.push_back(&sceMotion); - g_psv_modules.push_back(&sceMt19937); - g_psv_modules.push_back(&sceNet); - g_psv_modules.push_back(&sceNetCtl); - g_psv_modules.push_back(&sceNgs); - g_psv_modules.push_back(&sceNpBasic); - g_psv_modules.push_back(&sceNpCommon); - g_psv_modules.push_back(&sceNpManager); - g_psv_modules.push_back(&sceNpMatching); - g_psv_modules.push_back(&sceNpScore); - g_psv_modules.push_back(&sceNpUtility); - g_psv_modules.push_back(&scePerf); - g_psv_modules.push_back(&scePgf); - g_psv_modules.push_back(&scePhotoExport); - g_psv_modules.push_back(&sceRazorCapture); - g_psv_modules.push_back(&sceRtc); - g_psv_modules.push_back(&sceSas); - g_psv_modules.push_back(&sceScreenShot); - g_psv_modules.push_back(&sceSfmt); - g_psv_modules.push_back(&sceSha); - g_psv_modules.push_back(&sceSqlite); - g_psv_modules.push_back(&sceSsl); - g_psv_modules.push_back(&sceSulpha); - g_psv_modules.push_back(&sceSysmodule); - g_psv_modules.push_back(&sceSystemGesture); - g_psv_modules.push_back(&sceTouch); - g_psv_modules.push_back(&sceUlt); - g_psv_modules.push_back(&sceVideodec); - g_psv_modules.push_back(&sceVoice); - g_psv_modules.push_back(&sceVoiceQoS); - g_psv_modules.push_back(&sceXml); - - // setup special functions (without NIDs) - g_psv_func_list.resize(SFI_MAX); - - psv_func& hle_return = g_psv_func_list[SFI_HLE_RETURN]; - hle_return.nid = 0; - hle_return.name = "HLE_RETURN"; - hle_return.func = [](ARMv7Thread& context) - { - context.fast_stop(); - }; - - // load functions - for (auto module : g_psv_modules) - { - module->Init(); - } -} - -void finalize_psv_modules() -{ - for (auto module : g_psv_modules) - { - if (module->on_stop) - { - module->on_stop(); - } - } - - g_psv_func_list.clear(); - g_psv_modules.clear(); -} diff --git a/rpcs3/Emu/ARMv7/PSVFuncList.h b/rpcs3/Emu/ARMv7/PSVFuncList.h deleted file mode 100644 index f9a4977953..0000000000 --- a/rpcs3/Emu/ARMv7/PSVFuncList.h +++ /dev/null @@ -1,676 +0,0 @@ -#pragma once - -#include "Emu/Memory/Memory.h" -#include "ARMv7Thread.h" - -namespace vm { using namespace psv; } - -// PSV module class -class psv_log_base : public _log::channel -{ - using init_func_t = void(*)(); - - init_func_t m_init; - -public: - std::function on_load; - std::function on_unload; - std::function on_stop; - std::function on_error; - -public: - psv_log_base(const std::string& name, init_func_t init); - - void Init() - { - on_load = nullptr; - on_unload = nullptr; - on_stop = nullptr; - on_error = nullptr; - - m_init(); - } -}; - -using armv7_func_caller = void(*)(ARMv7Thread&); - -struct armv7_va_args_t -{ - u32 g_count; - u32 f_count; - u32 v_count; -}; - -// Utilities for binding ARMv7Context to C++ function arguments received by HLE functions or sent to callbacks -namespace psv_func_detail -{ - enum arg_class : u32 - { - ARG_GENERAL, - ARG_FLOAT, - ARG_VECTOR, - ARG_STACK, - ARG_CONTEXT, - ARG_VARIADIC, - ARG_UNKNOWN, - }; - - static const auto FIXED_STACK_FRAME_SIZE = 0x80; // described in CB_FUNC.h - - template - struct bind_arg - { - static_assert(type == ARG_GENERAL, "Unknown function argument type"); - static_assert(!std::is_pointer::value, "Invalid function argument type (pointer)"); - static_assert(!std::is_reference::value, "Invalid function argument type (reference)"); - static_assert(sizeof(T) <= 4, "Invalid function argument type for ARG_GENERAL"); - - force_inline static T get_arg(ARMv7Thread& context) - { - return cast_from_armv7_gpr(context.GPR[g_count - 1]); - } - - force_inline static void put_arg(ARMv7Thread& context, const T& arg) - { - context.GPR[g_count - 1] = cast_to_armv7_gpr(arg); - } - }; - - template - struct bind_arg - { - // first u64 argument is passed in r0-r1, second one is passed in r2-r3 (if g_count = 3) - static_assert(g_count == 2 || g_count == 4, "Wrong u64 argument position"); - - force_inline static u64 get_arg(ARMv7Thread& context) - { - return context.GPR_D[(g_count - 1) >> 1]; - } - - force_inline static void put_arg(ARMv7Thread& context, u64 arg) - { - context.GPR_D[(g_count - 1) >> 1] = arg; - } - }; - - template - struct bind_arg - { - static_assert(g_count == 2 || g_count == 4, "Wrong s64 argument position"); - - force_inline static s64 get_arg(ARMv7Thread& context) - { - return context.GPR_D[(g_count - 1) >> 1]; - } - - force_inline static void put_arg(ARMv7Thread& context, s64 arg) - { - context.GPR_D[(g_count - 1) >> 1] = arg; - } - }; - - template - struct bind_arg - { - static_assert(f_count <= 0, "TODO: Unsupported argument type (float)"); - static_assert(sizeof(T) <= 8, "Invalid function argument type for ARG_FLOAT"); - - force_inline static T get_arg(ARMv7Thread& context) - { - } - - force_inline static void put_arg(ARMv7Thread& context, const T& arg) - { - } - }; - - template - struct bind_arg - { - static_assert(v_count <= 0, "TODO: Unsupported argument type (vector)"); - static_assert(std::is_same, v128>::value, "Invalid function argument type for ARG_VECTOR"); - - force_inline static T get_arg(ARMv7Thread& context) - { - } - - force_inline static void put_arg(ARMv7Thread& context, const T& arg) - { - } - }; - - template - struct bind_arg - { - static_assert(f_count <= 0, "TODO: Unsupported stack argument type (float)"); - static_assert(v_count <= 0, "TODO: Unsupported stack argument type (vector)"); - static_assert(sizeof(T) <= 4, "Invalid function argument type for ARG_STACK"); - - force_inline static T get_arg(ARMv7Thread& context) - { - // TODO: check - return cast_from_armv7_gpr(vm::read32(context.SP + sizeof(u32) * (g_count - 5))); - } - - force_inline static void put_arg(ARMv7Thread& context, const T& arg) - { - // TODO: check - const int stack_pos = (g_count - 5) * 4 - FIXED_STACK_FRAME_SIZE; - static_assert(stack_pos < 0, "TODO: Increase fixed stack frame size (arg count limit broken)"); - - vm::write32(context.SP + stack_pos, cast_to_armv7_gpr(arg)); - } - }; - - template - struct bind_arg - { - force_inline static u64 get_arg(ARMv7Thread& context) - { - // TODO: check - return vm::read64(context.SP + sizeof(u32) * (g_count - 6)); - } - - force_inline static void put_arg(ARMv7Thread& context, u64 arg) - { - // TODO: check - const int stack_pos = (g_count - 6) * 4 - FIXED_STACK_FRAME_SIZE; - static_assert(stack_pos < -4, "TODO: Increase fixed stack frame size (arg count limit broken)"); - - vm::write64(context.SP + stack_pos, arg); - } - }; - - template - struct bind_arg - { - force_inline static s64 get_arg(ARMv7Thread& context) - { - // TODO: check - return vm::read64(context.SP + sizeof(u32) * (g_count - 6)); - } - - force_inline static void put_arg(ARMv7Thread& context, s64 arg) - { - // TODO: check - const int stack_pos = (g_count - 6) * 4 - FIXED_STACK_FRAME_SIZE; - static_assert(stack_pos < -4, "TODO: Increase fixed stack frame size (arg count limit broken)"); - - vm::write64(context.SP + stack_pos, arg); - } - }; - - template - struct bind_arg - { - static_assert(std::is_same::value, "Invalid function argument type for ARG_CONTEXT"); - - force_inline static ARMv7Thread& get_arg(ARMv7Thread& context) - { - return context; - } - - force_inline static void put_arg(ARMv7Thread& context, ARMv7Thread& arg) - { - } - }; - - template - struct bind_arg - { - static_assert(std::is_same, armv7_va_args_t>::value, "Invalid function argument type for ARG_VARIADIC"); - - force_inline static armv7_va_args_t get_arg(ARMv7Thread& context) - { - return{ g_count, f_count, v_count }; - } - }; - - template - struct bind_result - { - static_assert(type != ARG_FLOAT, "TODO: Unsupported funcion result type (float)"); - static_assert(type != ARG_VECTOR, "TODO: Unsupported funcion result type (vector)"); - static_assert(type == ARG_GENERAL, "Wrong use of bind_result template"); - static_assert(sizeof(T) <= 4, "Invalid function result type for ARG_GENERAL"); - - force_inline static T get_result(ARMv7Thread& context) - { - return cast_from_armv7_gpr(context.GPR[0]); - } - - force_inline static void put_result(ARMv7Thread& context, const T& result) - { - context.GPR[0] = cast_to_armv7_gpr(result); - } - }; - - template<> - struct bind_result - { - force_inline static u64 get_result(ARMv7Thread& context) - { - return context.GPR_D[0]; - } - - force_inline static void put_result(ARMv7Thread& context, u64 result) - { - context.GPR_D[0] = result; - } - }; - - template<> - struct bind_result - { - force_inline static s64 get_result(ARMv7Thread& context) - { - return context.GPR_D[0]; - } - - force_inline static void put_result(ARMv7Thread& context, s64 result) - { - context.GPR_D[0] = result; - } - }; - - //template - //struct bind_result - //{ - // static_assert(sizeof(T) <= 8, "Invalid function result type for ARG_FLOAT"); - - // static force_inline void put_result(ARMv7Thread& context, const T& result) - // { - // } - //}; - - //template - //struct bind_result - //{ - // static_assert(std::is_same, v128>::value, "Invalid function result type for ARG_VECTOR"); - - // static force_inline void put_result(ARMv7Thread& context, const T& result) - // { - // } - //}; - - template - struct result_type - { - static_assert(!std::is_pointer::value, "Invalid function result type (pointer)"); - static_assert(!std::is_reference::value, "Invalid function result type (reference)"); - static const bool is_float = std::is_floating_point::value; - static const bool is_vector = std::is_same, v128>::value; - static const arg_class value = is_float ? ARG_FLOAT : (is_vector ? ARG_VECTOR : ARG_GENERAL); - }; - - template - struct arg_type - { - // TODO: check calculations - static const bool is_float = std::is_floating_point::value; - static const bool is_vector = std::is_same, v128>::value; - static const bool is_context = std::is_same::value; - static const bool is_variadic = std::is_same, armv7_va_args_t>::value; - static const bool is_general = !is_float && !is_vector && !is_context && !is_variadic; - - static const u32 g_align = ALIGN_32(T) > 4 ? ALIGN_32(T) >> 2 : 1; - static const u32 g_value = is_general ? ((g_count + (g_align - 1)) & ~(g_align - 1)) + (g_align) : g_count; - static const u32 f_value = f_count + is_float; - static const u32 v_value = v_count + is_vector; - - static const arg_class value = - is_general ? (g_value > 4 ? ARG_STACK : ARG_GENERAL) : - is_float ? (f_value > 9000 ? ARG_STACK : ARG_FLOAT) : - is_vector ? (v_value > 9000 ? ARG_STACK : ARG_VECTOR) : - is_context ? ARG_CONTEXT : - is_variadic ? ARG_VARIADIC : - ARG_UNKNOWN; - }; - - // wrapper for variadic argument info list, each value contains packed argument type and counts of GENERAL, FLOAT and VECTOR arguments - template struct arg_info_pack_t; - - template struct arg_info_pack_t - { - static const u32 last_value = arg_info_pack_t::last_value; - }; - - template struct arg_info_pack_t - { - static const u32 last_value = First; - }; - - template<> struct arg_info_pack_t<> - { - static const u32 last_value = 0; - }; - - // argument type + g/f/v_count unpacker - template struct bind_arg_packed - { - force_inline static T get_arg(ARMv7Thread& context) - { - return bind_arg(type_pack & 0xff), (type_pack >> 8) & 0xff, (type_pack >> 16) & 0xff, (type_pack >> 24)>::get_arg(context); - } - }; - - template - force_inline RT call(ARMv7Thread& context, RT(*func)(Args...), arg_info_pack_t info) - { - // do the actual function call when all arguments are prepared (simultaneous unpacking of Args... and Info...) - return func(bind_arg_packed::get_arg(context)...); - } - - template - force_inline RT call(ARMv7Thread& context, RT(*func)(Args...), arg_info_pack_t info) - { - // unpack previous type counts (0/0/0 for the first time) - const u32 g_count = (info.last_value >> 8) & 0xff; - const u32 f_count = (info.last_value >> 16) & 0xff; - const u32 v_count = (info.last_value >> 24); - - using type = arg_type; - const arg_class t = type::value; - const u32 g = type::g_value; - const u32 f = type::f_value; - const u32 v = type::v_value; - - return call(context, func, arg_info_pack_t{}); - } - - template - force_inline static bool put_func_args(ARMv7Thread& context) - { - // terminator - return false; - } - - template - force_inline static bool put_func_args(ARMv7Thread& context, T1 arg, T... args) - { - using type = arg_type; - const arg_class t = type::value; - const u32 g = type::g_value; - const u32 f = type::f_value; - const u32 v = type::v_value; - - bind_arg::put_arg(context, arg); - - // return true if stack was used - return put_func_args(context, args...) || (t == ARG_STACK); - } - - template - struct func_binder; - - template - struct func_binder - { - using func_t = void(*)(T...); - - static void do_call(ARMv7Thread& context, func_t func) - { - call(context, func, arg_info_pack_t<>{}); - } - }; - - template - struct func_binder - { - using func_t = RT(*)(T...); - - static void do_call(ARMv7Thread& context, func_t func) - { - bind_result::value>::put_result(context, call(context, func, arg_info_pack_t<>{})); - } - }; - - template - struct func_caller - { - force_inline static RT call(ARMv7Thread& context, u32 addr, T... args) - { - func_caller::call(context, addr, args...); - - return bind_result::value>::get_result(context); - } - }; - - template - struct func_caller - { - force_inline static void call(ARMv7Thread& context, u32 addr, T... args) - { - if (put_func_args<0, 0, 0, T...>(context, args...)) - { - context.SP -= FIXED_STACK_FRAME_SIZE; - context.fast_call(addr); - context.SP += FIXED_STACK_FRAME_SIZE; - } - else - { - context.fast_call(addr); - } - } - }; -} - -// Basic information about the HLE function -struct psv_func -{ - u32 nid; // Unique function ID (should be generated individually for each elf loaded) - u32 flags; - const char* name; // Function name for information - armv7_func_caller func; // Function caller - psv_log_base* module; // Module for information - - psv_func() - { - } - - psv_func(u32 nid, u32 flags, psv_log_base* module, const char* name, armv7_func_caller func) - : nid(nid) - , flags(flags) - , name(name) - , func(func) - , module(module) - { - } -}; - -enum psv_special_function_index : u16 -{ - SFI_HLE_RETURN, - - SFI_MAX -}; - -// Do not call directly -u32 add_psv_func(psv_func data); -// Do not call directly -template force_inline void call_psv_func(ARMv7Thread& context, RT(*func)(T...)) -{ - psv_func_detail::func_binder::do_call(context, func); -} - -#define reg_psv_func(nid, module, name, func) add_psv_func(psv_func(nid, 0, module, name, [](ARMv7Thread& context){ call_psv_func(context, func); })) - -// Find registered HLE function by NID -psv_func* get_psv_func_by_nid(u32 nid, u32* out_index = nullptr); -// Find registered HLE function by its index -psv_func* get_psv_func_by_index(u32 index); -// Execute registered HLE function by its index -void execute_psv_func_by_index(ARMv7Thread& context, u32 index); -// Register all HLE functions -void initialize_psv_modules(); -// Unregister all HLE functions -void finalize_psv_modules(); - -// General definitions - -enum psv_error_codes -{ - SCE_OK = 0, - - SCE_ERROR_ERRNO_EPERM = 0x80010001, - SCE_ERROR_ERRNO_ENOENT = 0x80010002, - SCE_ERROR_ERRNO_ESRCH = 0x80010003, - SCE_ERROR_ERRNO_EINTR = 0x80010004, - SCE_ERROR_ERRNO_EIO = 0x80010005, - SCE_ERROR_ERRNO_ENXIO = 0x80010006, - SCE_ERROR_ERRNO_E2BIG = 0x80010007, - SCE_ERROR_ERRNO_ENOEXEC = 0x80010008, - SCE_ERROR_ERRNO_EBADF = 0x80010009, - SCE_ERROR_ERRNO_ECHILD = 0x8001000A, - SCE_ERROR_ERRNO_EAGAIN = 0x8001000B, - SCE_ERROR_ERRNO_ENOMEM = 0x8001000C, - SCE_ERROR_ERRNO_EACCES = 0x8001000D, - SCE_ERROR_ERRNO_EFAULT = 0x8001000E, - SCE_ERROR_ERRNO_ENOTBLK = 0x8001000F, - SCE_ERROR_ERRNO_EBUSY = 0x80010010, - SCE_ERROR_ERRNO_EEXIST = 0x80010011, - SCE_ERROR_ERRNO_EXDEV = 0x80010012, - SCE_ERROR_ERRNO_ENODEV = 0x80010013, - SCE_ERROR_ERRNO_ENOTDIR = 0x80010014, - SCE_ERROR_ERRNO_EISDIR = 0x80010015, - SCE_ERROR_ERRNO_EINVAL = 0x80010016, - SCE_ERROR_ERRNO_ENFILE = 0x80010017, - SCE_ERROR_ERRNO_EMFILE = 0x80010018, - SCE_ERROR_ERRNO_ENOTTY = 0x80010019, - SCE_ERROR_ERRNO_ETXTBSY = 0x8001001A, - SCE_ERROR_ERRNO_EFBIG = 0x8001001B, - SCE_ERROR_ERRNO_ENOSPC = 0x8001001C, - SCE_ERROR_ERRNO_ESPIPE = 0x8001001D, - SCE_ERROR_ERRNO_EROFS = 0x8001001E, - SCE_ERROR_ERRNO_EMLINK = 0x8001001F, - SCE_ERROR_ERRNO_EPIPE = 0x80010020, - SCE_ERROR_ERRNO_EDOM = 0x80010021, - SCE_ERROR_ERRNO_ERANGE = 0x80010022, - SCE_ERROR_ERRNO_ENOMSG = 0x80010023, - SCE_ERROR_ERRNO_EIDRM = 0x80010024, - SCE_ERROR_ERRNO_ECHRNG = 0x80010025, - SCE_ERROR_ERRNO_EL2NSYNC = 0x80010026, - SCE_ERROR_ERRNO_EL3HLT = 0x80010027, - SCE_ERROR_ERRNO_EL3RST = 0x80010028, - SCE_ERROR_ERRNO_ELNRNG = 0x80010029, - SCE_ERROR_ERRNO_EUNATCH = 0x8001002A, - SCE_ERROR_ERRNO_ENOCSI = 0x8001002B, - SCE_ERROR_ERRNO_EL2HLT = 0x8001002C, - SCE_ERROR_ERRNO_EDEADLK = 0x8001002D, - SCE_ERROR_ERRNO_ENOLCK = 0x8001002E, - SCE_ERROR_ERRNO_EFORMAT = 0x8001002F, - SCE_ERROR_ERRNO_EUNSUP = 0x80010030, - SCE_ERROR_ERRNO_EBADE = 0x80010032, - SCE_ERROR_ERRNO_EBADR = 0x80010033, - SCE_ERROR_ERRNO_EXFULL = 0x80010034, - SCE_ERROR_ERRNO_ENOANO = 0x80010035, - SCE_ERROR_ERRNO_EBADRQC = 0x80010036, - SCE_ERROR_ERRNO_EBADSLT = 0x80010037, - SCE_ERROR_ERRNO_EDEADLOCK = 0x80010038, - SCE_ERROR_ERRNO_EBFONT = 0x80010039, - SCE_ERROR_ERRNO_ENOSTR = 0x8001003C, - SCE_ERROR_ERRNO_ENODATA = 0x8001003D, - SCE_ERROR_ERRNO_ETIME = 0x8001003E, - SCE_ERROR_ERRNO_ENOSR = 0x8001003F, - SCE_ERROR_ERRNO_ENONET = 0x80010040, - SCE_ERROR_ERRNO_ENOPKG = 0x80010041, - SCE_ERROR_ERRNO_EREMOTE = 0x80010042, - SCE_ERROR_ERRNO_ENOLINK = 0x80010043, - SCE_ERROR_ERRNO_EADV = 0x80010044, - SCE_ERROR_ERRNO_ESRMNT = 0x80010045, - SCE_ERROR_ERRNO_ECOMM = 0x80010046, - SCE_ERROR_ERRNO_EPROTO = 0x80010047, - SCE_ERROR_ERRNO_EMULTIHOP = 0x8001004A, - SCE_ERROR_ERRNO_ELBIN = 0x8001004B, - SCE_ERROR_ERRNO_EDOTDOT = 0x8001004C, - SCE_ERROR_ERRNO_EBADMSG = 0x8001004D, - SCE_ERROR_ERRNO_EFTYPE = 0x8001004F, - SCE_ERROR_ERRNO_ENOTUNIQ = 0x80010050, - SCE_ERROR_ERRNO_EBADFD = 0x80010051, - SCE_ERROR_ERRNO_EREMCHG = 0x80010052, - SCE_ERROR_ERRNO_ELIBACC = 0x80010053, - SCE_ERROR_ERRNO_ELIBBAD = 0x80010054, - SCE_ERROR_ERRNO_ELIBSCN = 0x80010055, - SCE_ERROR_ERRNO_ELIBMAX = 0x80010056, - SCE_ERROR_ERRNO_ELIBEXEC = 0x80010057, - SCE_ERROR_ERRNO_ENOSYS = 0x80010058, - SCE_ERROR_ERRNO_ENMFILE = 0x80010059, - SCE_ERROR_ERRNO_ENOTEMPTY = 0x8001005A, - SCE_ERROR_ERRNO_ENAMETOOLONG = 0x8001005B, - SCE_ERROR_ERRNO_ELOOP = 0x8001005C, - SCE_ERROR_ERRNO_EOPNOTSUPP = 0x8001005F, - SCE_ERROR_ERRNO_EPFNOSUPPORT = 0x80010060, - SCE_ERROR_ERRNO_ECONNRESET = 0x80010068, - SCE_ERROR_ERRNO_ENOBUFS = 0x80010069, - SCE_ERROR_ERRNO_EAFNOSUPPORT = 0x8001006A, - SCE_ERROR_ERRNO_EPROTOTYPE = 0x8001006B, - SCE_ERROR_ERRNO_ENOTSOCK = 0x8001006C, - SCE_ERROR_ERRNO_ENOPROTOOPT = 0x8001006D, - SCE_ERROR_ERRNO_ESHUTDOWN = 0x8001006E, - SCE_ERROR_ERRNO_ECONNREFUSED = 0x8001006F, - SCE_ERROR_ERRNO_EADDRINUSE = 0x80010070, - SCE_ERROR_ERRNO_ECONNABORTED = 0x80010071, - SCE_ERROR_ERRNO_ENETUNREACH = 0x80010072, - SCE_ERROR_ERRNO_ENETDOWN = 0x80010073, - SCE_ERROR_ERRNO_ETIMEDOUT = 0x80010074, - SCE_ERROR_ERRNO_EHOSTDOWN = 0x80010075, - SCE_ERROR_ERRNO_EHOSTUNREACH = 0x80010076, - SCE_ERROR_ERRNO_EINPROGRESS = 0x80010077, - SCE_ERROR_ERRNO_EALREADY = 0x80010078, - SCE_ERROR_ERRNO_EDESTADDRREQ = 0x80010079, - SCE_ERROR_ERRNO_EMSGSIZE = 0x8001007A, - SCE_ERROR_ERRNO_EPROTONOSUPPORT = 0x8001007B, - SCE_ERROR_ERRNO_ESOCKTNOSUPPORT = 0x8001007C, - SCE_ERROR_ERRNO_EADDRNOTAVAIL = 0x8001007D, - SCE_ERROR_ERRNO_ENETRESET = 0x8001007E, - SCE_ERROR_ERRNO_EISCONN = 0x8001007F, - SCE_ERROR_ERRNO_ENOTCONN = 0x80010080, - SCE_ERROR_ERRNO_ETOOMANYREFS = 0x80010081, - SCE_ERROR_ERRNO_EPROCLIM = 0x80010082, - SCE_ERROR_ERRNO_EUSERS = 0x80010083, - SCE_ERROR_ERRNO_EDQUOT = 0x80010084, - SCE_ERROR_ERRNO_ESTALE = 0x80010085, - SCE_ERROR_ERRNO_ENOTSUP = 0x80010086, - SCE_ERROR_ERRNO_ENOMEDIUM = 0x80010087, - SCE_ERROR_ERRNO_ENOSHARE = 0x80010088, - SCE_ERROR_ERRNO_ECASECLASH = 0x80010089, - SCE_ERROR_ERRNO_EILSEQ = 0x8001008A, - SCE_ERROR_ERRNO_EOVERFLOW = 0x8001008B, - SCE_ERROR_ERRNO_ECANCELED = 0x8001008C, - SCE_ERROR_ERRNO_ENOTRECOVERABLE = 0x8001008D, - SCE_ERROR_ERRNO_EOWNERDEAD = 0x8001008E, -}; - -struct SceDateTime -{ - le_t year; - le_t month; - le_t day; - le_t hour; - le_t minute; - le_t second; - le_t microsecond; -}; - -struct SceFVector3 -{ - le_t x, y, z; -}; - -struct SceFQuaternion -{ - le_t x, y, z, w; -}; - -union SceUMatrix4 -{ - struct - { - le_t f[4][4]; - }; - - struct - { - le_t i[4][4]; - }; -}; diff --git a/rpcs3/Emu/ARMv7/PSVObjectList.h b/rpcs3/Emu/ARMv7/PSVObjectList.h deleted file mode 100644 index 97e98ffd75..0000000000 --- a/rpcs3/Emu/ARMv7/PSVObjectList.h +++ /dev/null @@ -1,124 +0,0 @@ -#pragma once - -union psv_uid_t -{ - // true UID format is partially unknown - s32 uid; - - struct - { - u32 oddness : 1; // always 1 for UIDs (to not mess it up with addresses) - u32 number : 15; // ID from 0 to 2^15-1 - u32 type : 15; // UID class (psv_object_class_t) - u32 sign : 1; // UIDs are positive, error codes are negative - }; - - static psv_uid_t make(s32 uid) - { - psv_uid_t result; - result.uid = uid; - return result; - } -}; - -template -class psv_object_list_t // Class for managing object data -{ - std::array, 0x8000> m_data; - std::atomic m_hint; // guessing next free position - std::mutex m_mutex; - -public: - psv_object_list_t() - : m_hint(0) - { - } - - // check if UID is potentially valid (will return true even if the object doesn't exist) - static inline bool check(s32 uid) - { - const psv_uid_t id = psv_uid_t::make(uid); - - // check sign bit, uid class and ensure that value is odd - return !id.sign && id.type == uid_class && id.oddness == 1; - } - - // share object with UID specified - std::shared_ptr get(s32 uid) - { - if (!check(uid)) - { - return nullptr; - } - - std::lock_guard lock(m_mutex); - - return m_data[psv_uid_t::make(uid).number]; - } - - std::shared_ptr operator [](s32 uid) - { - return this->get(uid); - } - - // create new object and generate UID for it, or do nothing and return zero (if limit reached) - template s32 create(Args&&... args) - { - std::lock_guard lock(m_mutex); - - for (u32 i = 0, j = m_hint; i < m_data.size(); i++, j = (j + 1) % m_data.size()) - { - // find an empty position and copy the pointer - if (!m_data[j]) - { - m_data[j] = std::make_shared(args...); // construct object with specified arguments - - m_hint = (j + 1) % m_data.size(); // guess next position - - psv_uid_t id = psv_uid_t::make(1); // make UID - id.type = uid_class; - id.number = j; - - return id.uid; // return UID - } - } - - return 0; - } - - // remove object with specified UID - bool remove(s32 uid) - { - if (!check(uid)) - { - return false; - } - - std::lock_guard lock(m_mutex); - - const u32 pos = psv_uid_t::make(uid).number; - - m_hint = std::min(pos, m_hint); - - if (!m_data[pos]) - { - return false; - } - - m_data[pos].reset(); - return true; - } - - // remove all objects - void clear() - { - std::lock_guard lock(m_mutex); - - for (auto& v : m_data) - { - v.reset(); - } - - m_hint = 0; - } -};