mirror of https://github.com/RPCS3/rpcs3.git
mfc: Fix support for list transfer stall bit with partial support for out of order execution - Also give Sync commands a size so they are properly detected by queue checks
This commit is contained in:
Jake
kd-11
parent
8b476b5bfa
commit
34e01ba3d8
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@ -142,107 +142,142 @@ void mfc_thread::cpu_task()
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if (queue_size)
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{
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auto& cmd = spu.mfc_queue[0];
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if ((cmd.cmd & ~(MFC_BARRIER_MASK | MFC_FENCE_MASK)) == MFC_PUTQLLUC_CMD)
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u32 fence_mask = 0; // Using this instead of stall_mask to avoid a possible race condition
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u32 barrier_mask = 0;
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bool first = true;
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for (u32 i = 0; i < spu.mfc_queue.size(); i++, first = false)
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{
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auto& data = vm::ps3::_ref<decltype(spu.rdata)>(cmd.eal);
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const auto to_write = spu._ref<decltype(spu.rdata)>(cmd.lsa & 0x3ffff);
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auto& cmd = spu.mfc_queue[i];
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cmd.size = 0;
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no_updates = 0;
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// this check all revolves around a potential 'stalled list' in the queue as its the one thing that can cause out of order mfc list execution currently
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// a list with barrier hard blocks that tag until it's been dealt with
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// and a new command that has a fence cant be executed until the stalled list has been dealt with
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if ((cmd.size != 0) && ((barrier_mask & (1u << cmd.tag)) || ((cmd.cmd & MFC_FENCE_MASK) && ((1 << cmd.tag) & fence_mask))))
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continue;
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vm::reservation_acquire(cmd.eal, 128);
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// Store unconditionally
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if (s_use_rtm && utils::transaction_enter())
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if ((cmd.cmd & ~(MFC_BARRIER_MASK | MFC_FENCE_MASK)) == MFC_PUTQLLUC_CMD)
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{
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if (!vm::reader_lock{vm::try_to_lock})
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{
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_xabort(0);
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}
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auto& data = vm::ps3::_ref<decltype(spu.rdata)>(cmd.eal);
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const auto to_write = spu._ref<decltype(spu.rdata)>(cmd.lsa & 0x3ffff);
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data = to_write;
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vm::reservation_update(cmd.eal, 128);
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vm::notify(cmd.eal, 128);
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_xend();
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}
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else
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{
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vm::writer_lock lock(0);
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data = to_write;
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vm::reservation_update(cmd.eal, 128);
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vm::notify(cmd.eal, 128);
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}
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}
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else if (cmd.cmd & MFC_LIST_MASK)
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{
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struct list_element
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{
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be_t<u16> sb; // Stall-and-Notify bit (0x8000)
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be_t<u16> ts; // List Transfer Size
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be_t<u32> ea; // External Address Low
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};
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if (cmd.size && (spu.ch_stall_mask & (1u << cmd.tag)) == 0)
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{
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cmd.lsa &= 0x3fff0;
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const list_element item = spu._ref<list_element>(cmd.eal & 0x3fff8);
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const u32 size = item.ts;
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const u32 addr = item.ea;
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if (size)
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{
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spu_mfc_cmd transfer;
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transfer.eal = addr;
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transfer.eah = 0;
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transfer.lsa = cmd.lsa | (addr & 0xf);
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transfer.tag = cmd.tag;
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transfer.cmd = MFC(cmd.cmd & ~MFC_LIST_MASK);
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transfer.size = size;
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spu.do_dma_transfer(transfer);
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cmd.lsa += std::max<u32>(size, 16);
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}
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cmd.eal += 8;
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cmd.size -= 8;
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cmd.size = 0;
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no_updates = 0;
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if (item.sb & 0x8000)
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vm::reservation_acquire(cmd.eal, 128);
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// Store unconditionally
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if (s_use_rtm && utils::transaction_enter())
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{
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spu.ch_stall_stat.push_or(spu, 1 << cmd.tag);
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const u32 evt = spu.ch_event_stat.fetch_or(SPU_EVENT_SN);
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if (evt & SPU_EVENT_WAITING)
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if (!vm::reader_lock{ vm::try_to_lock })
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{
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spu.notify();
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}
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else if (evt & SPU_EVENT_INTR_ENABLED)
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{
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spu.state += cpu_flag::suspend;
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_xabort(0);
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}
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data = to_write;
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vm::reservation_update(cmd.eal, 128);
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vm::notify(cmd.eal, 128);
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_xend();
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}
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else
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{
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vm::writer_lock lock(0);
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data = to_write;
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vm::reservation_update(cmd.eal, 128);
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vm::notify(cmd.eal, 128);
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}
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}
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}
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else if (LIKELY(cmd.size))
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{
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spu.do_dma_transfer(cmd);
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cmd.size = 0;
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}
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else if (UNLIKELY((cmd.cmd & ~0xc) == MFC_BARRIER_CMD))
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{
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// TODO (MFC_BARRIER_CMD, MFC_EIEIO_CMD, MFC_SYNC_CMD)
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_mm_mfence();
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}
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else if (cmd.cmd & MFC_LIST_MASK)
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{
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struct list_element
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{
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be_t<u16> sb; // Stall-and-Notify bit (0x8000)
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be_t<u16> ts; // List Transfer Size
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be_t<u32> ea; // External Address Low
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};
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if (!cmd.size)
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{
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spu.mfc_queue.end_pop();
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no_updates = 0;
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if (cmd.size && (spu.ch_stall_mask & (1u << cmd.tag)) == 0)
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{
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cmd.lsa &= 0x3fff0;
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// try to get the whole list done in one go
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while (cmd.size != 0)
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{
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const list_element item = spu._ref<list_element>(cmd.eal & 0x3fff8);
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const u32 size = item.ts;
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const u32 addr = item.ea;
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if (size)
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{
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spu_mfc_cmd transfer;
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transfer.eal = addr;
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transfer.eah = 0;
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transfer.lsa = cmd.lsa | (addr & 0xf);
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transfer.tag = cmd.tag;
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transfer.cmd = MFC(cmd.cmd & ~MFC_LIST_MASK);
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transfer.size = size;
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spu.do_dma_transfer(transfer);
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cmd.lsa += std::max<u32>(size, 16);
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}
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cmd.eal += 8;
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cmd.size -= 8;
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no_updates = 0;
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// dont stall for last 'item' in list
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if ((item.sb & 0x8000) && (cmd.size != 0))
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{
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spu.ch_stall_mask |= (1 << cmd.tag);
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spu.ch_stall_stat.push_or(spu, 1 << cmd.tag);
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const u32 evt = spu.ch_event_stat.fetch_or(SPU_EVENT_SN);
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if (evt & SPU_EVENT_WAITING)
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{
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spu.notify();
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}
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break;
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}
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}
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}
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if (cmd.size != 0 && (cmd.cmd & MFC_BARRIER_MASK))
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barrier_mask |= (1 << cmd.tag);
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else if (cmd.size != 0)
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fence_mask |= (1 << cmd.tag);
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}
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else if (UNLIKELY((cmd.cmd & ~0xc) == MFC_BARRIER_CMD))
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{
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// Raw barrier commands / sync commands are tag agnostic and hard sync the mfc list
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// Need to gaurentee everything ahead of it has processed before this
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if (first)
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cmd.size = 0;
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else
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break;
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}
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else if (LIKELY(cmd.size))
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{
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spu.do_dma_transfer(cmd);
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cmd.size = 0;
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}
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if (!cmd.size && first)
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{
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spu.mfc_queue.end_pop();
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no_updates = 0;
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break;
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}
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else if (!cmd.size && i == 1)
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{
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// nasty hack, shoving stalled list down one
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// this *works* from the idea that the only thing that could have been passed over in position 0 is a stalled list
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// todo: this can still create a situation where we say the mfc queue is full when its actually not, which will cause a rough deadlock between spu and mfc
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// which will causes a situation where the spu is waiting for the queue to open up but hasnt signaled the stall yet
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spu.mfc_queue[1] = spu.mfc_queue[0];
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spu.mfc_queue.end_pop();
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no_updates = 0;
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break;
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}
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}
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}
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@ -252,26 +287,21 @@ void mfc_thread::cpu_task()
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{
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// Mask incomplete transfers
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u32 completed = spu.ch_tag_mask;
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for (u32 i = 0; i < spu.mfc_queue.size(); i++)
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{
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const auto& _cmd = spu.mfc_queue[i];
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if (_cmd.size)
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for (u32 i = 0; i < spu.mfc_queue.size(); i++)
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{
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if (spu.ch_tag_upd == 1)
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{
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const auto& _cmd = spu.mfc_queue[i];
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if (_cmd.size)
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completed &= ~(1u << _cmd.tag);
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}
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else
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{
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completed = 0;
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break;
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}
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}
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}
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if (completed && spu.ch_tag_upd.exchange(0))
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if (completed && spu.ch_tag_upd.compare_and_swap_test(1, 0))
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{
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spu.ch_tag_stat.push(spu, completed);
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no_updates = 0;
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}
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else if (completed && spu.ch_tag_mask == completed && spu.ch_tag_upd.compare_and_swap_test(2, 0))
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{
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spu.ch_tag_stat.push(spu, completed);
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no_updates = 0;
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@ -280,7 +310,6 @@ void mfc_thread::cpu_task()
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test_state();
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}
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if (no_updates++)
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{
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if (no_updates >= 3)
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@ -815,7 +815,7 @@ void SPUThread::process_mfc_cmd()
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case MFC_GETLB_CMD:
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case MFC_GETLF_CMD:
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{
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if (ch_mfc_cmd.size <= max_imm_dma_size && mfc_queue.size() == 0 && (ch_stall_mask & (1u << ch_mfc_cmd.tag)) == 0)
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if (ch_mfc_cmd.size <= max_imm_dma_size && mfc_queue.size() == 0)
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{
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vm::reader_lock lock(vm::try_to_lock);
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@ -890,7 +890,7 @@ void SPUThread::process_mfc_cmd()
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case MFC_EIEIO_CMD:
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case MFC_SYNC_CMD:
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{
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ch_mfc_cmd.size = 0;
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ch_mfc_cmd.size = 1;
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if (mfc_queue.size() == 0)
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{
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@ -283,7 +283,7 @@ struct cfg_root : cfg::node
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cfg::_bool bind_spu_cores{this, "Bind SPU threads to secondary cores"};
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cfg::_bool lower_spu_priority{this, "Lower SPU thread priority"};
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cfg::_bool spu_debug{this, "SPU Debug"};
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cfg::_int<32, 16384> max_spu_immediate_write_size{this, "Maximum immediate DMA write size", 16384}; // Maximum size that an SPU thread can write directly without posting to MFC
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cfg::_int<0, 16384> max_spu_immediate_write_size{this, "Maximum immediate DMA write size", 16384}; // Maximum size that an SPU thread can write directly without posting to MFC
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cfg::_int<0, 6> preferred_spu_threads{this, "Preferred SPU Threads", 0}; //Numnber of hardware threads dedicated to heavy simultaneous spu tasks
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cfg::_int<0, 16> spu_delay_penalty{this, "SPU delay penalty", 3}; //Number of milliseconds to block a thread if a virtual 'core' isn't free
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cfg::_bool spu_loop_detection{this, "SPU loop detection", true}; //Try to detect wait loops and trigger thread yield
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