mirror of https://github.com/RPCS3/rpcs3.git
rsx: Scrap the prebuffered queue approach
- Basically starting over - The cost of making command copies into the queue has a measurable impact
This commit is contained in:
kd-11
kd-11
parent
9deecd506a
commit
2e32777375
File diff suppressed because it is too large
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@ -29,6 +29,7 @@ namespace rsx
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NOP = 0,
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FIFO_EMPTY = 0xDEADF1F0,
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FIFO_BUSY = 0xBABEF1F0,
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FIFO_ERROR = 0xDEADBEEF,
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FIFO_PACKET_BEGIN = 0xF1F0,
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FIFO_DISABLED_COMMAND = 0xF1F4,
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FIFO_DRAW_BARRIER = 0xF1F8,
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@ -42,193 +43,30 @@ namespace rsx
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u32 reserved;
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};
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struct fifo_buffer_info_t
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{
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u32 start_loc;
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u32 length;
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u32 num_draw_calls;
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u32 reserved;
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};
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struct branch_target_info_t
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{
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u32 branch_target;
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u32 branch_origin;
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s64 weight;
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u64 checksum_16;
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u64 reserved;
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};
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struct optimization_pass
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{
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virtual void optimize(const fifo_buffer_info_t& info, simple_array<register_pair>& commands, const u32* registers) = 0;
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};
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struct flattening_pass : public optimization_pass
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class FIFO_control
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{
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private:
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enum register_props : u8
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{
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skippable = 1,
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ignorable = 2
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none = 0,
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skip_on_match = 1,
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always_ignore = 2
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};
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std::array<u8, 0x10000 / 4> m_register_properties;
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public:
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flattening_pass();
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void optimize(const fifo_buffer_info_t& info, simple_array<register_pair>& commands, const u32* registers) override;
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};
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struct reordering_pass : public optimization_pass
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{
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private:
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struct instruction_buffer_t
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{
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std::unordered_map<u32, u32> m_storage;
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simple_array<u32> m_insertion_order;
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instruction_buffer_t()
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{
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m_insertion_order.reserve(64);
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}
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void add_cmd(u32 reg, u32 value)
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{
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const auto is_new = std::get<1>(m_storage.insert_or_assign(reg, value));
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if (!is_new)
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{
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for (auto &loc : m_insertion_order)
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{
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if (loc == reg)
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{
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loc |= 0x80000000;
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break;
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}
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}
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}
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m_insertion_order.push_back(reg);
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}
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void clear()
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{
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m_storage.clear();
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m_insertion_order.clear();
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}
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void swap(instruction_buffer_t& other)
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{
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m_storage.swap(other.m_storage);
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m_insertion_order.swap(other.m_insertion_order);
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}
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auto size() const
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{
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return m_storage.size();
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}
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inline std::pair<u32, u32> get(int index) const
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{
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const auto key = m_insertion_order[index];
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if (key & 0x80000000)
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{
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// Disabled by a later write to the same register
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// TODO: Track command type registers and avoid this
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return { FIFO_DISABLED_COMMAND, 0 };
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}
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const auto value = m_storage.at(key);
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return { key, value };
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}
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bool operator == (const instruction_buffer_t& other) const
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{
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if (size() == other.size())
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{
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for (const auto &e : other.m_storage)
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{
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const auto found = m_storage.find(e.first);
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if (found == m_storage.end())
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return false;
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if (found->second != e.second)
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return false;
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}
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return true;
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}
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return false;
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}
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};
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struct draw_call
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{
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instruction_buffer_t prologue;
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std::vector<register_pair> draws;
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bool write_prologue;
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u32 primitive_type;
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const register_pair* start_pos;
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bool matches(const instruction_buffer_t setup, u32 prim) const
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{
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if (prim != primitive_type)
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return false;
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return prologue == setup;
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}
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};
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instruction_buffer_t registers_changed;
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std::vector<draw_call> bins;
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std::unordered_multimap<u32, fifo_buffer_info_t> m_results_prediction_table;
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public:
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void optimize(const fifo_buffer_info_t& info, simple_array<register_pair>& commands, const u32* registers) override;
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};
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class FIFO_control
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{
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RsxDmaControl* m_ctrl = nullptr;
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u32 m_internal_get = 0;
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std::shared_ptr<thread_base> m_prefetcher_thread;
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u32 m_prefetch_get = 0;
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atomic_t<bool> m_prefetcher_busy{ false };
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atomic_t<bool> m_fifo_busy{ false };
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fifo_buffer_info_t m_prefetcher_info;
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bool m_prefetcher_speculating;
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std::vector<std::unique_ptr<optimization_pass>> m_optimization_passes;
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simple_array<register_pair> m_queue;
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simple_array<register_pair> m_prefetched_queue;
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atomic_t<u32> m_command_index{ 0 };
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shared_mutex m_prefetch_mutex; // Guards prefetch queue
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shared_mutex m_queue_mutex; // Guards primary queue
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atomic_t<u64> m_ctrl_tag{ 0 }; // 'Guards' control registers
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register_pair empty_cmd { FIFO_EMPTY };
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register_pair busy_cmd { FIFO_BUSY };
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u32 m_memwatch_addr = 0;
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u32 m_memwatch_cmp = 0;
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fifo_buffer_info_t m_fifo_info;
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std::unordered_multimap<u32, branch_target_info_t> m_branch_prediction_table;
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u32 m_command_reg = 0;
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u32 m_command_inc = 0;
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u32 m_remaining_commands = 0;
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u32 m_args_ptr = 0;
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void read_ahead(fifo_buffer_info_t& info, simple_array<register_pair>& commands, u32& get_pointer);
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void optimize(const fifo_buffer_info_t& info, simple_array<register_pair>& commands);
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void clear_buffer();
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u32 get_likely_target(u32 source);
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void report_branch_miss(u32 source, u32 target, u32 actual);
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void report_branch_hit(u32 source, u32 target);
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bool test_prefetcher_correctness(u32 actual_target);
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std::array<u8, 0x10000 / 4> m_register_properties;
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bool has_deferred_draw = false;
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public:
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FIFO_control(rsx::thread* pctrl);
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@ -237,12 +75,9 @@ namespace rsx
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void set_get(u32 get, bool spinning = false);
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void set_put(u32 put);
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const register_pair& read();
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inline const register_pair& read_unsafe();
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void register_optimization_pass(optimization_pass* pass);
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void finalize();
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void read(register_pair& data);
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inline void read_unsafe(register_pair& data);
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inline bool has_next() const;
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public:
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static bool is_blocking_cmd(u32 cmd);
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@ -554,10 +554,6 @@ namespace rsx
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fifo_ctrl = std::make_unique<::rsx::FIFO::FIFO_control>(this);
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fifo_ctrl->register_optimization_pass(new FIFO::flattening_pass());
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//fifo_ctrl->register_optimization_pass(new FIFO::reordering_pass()); // R&C2 - Not working if flattening is also enabled!!!
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//fifo_ctrl->register_optimization_pass(new FIFO::flattening_pass());
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last_flip_time = get_system_time() - 1000000;
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named_thread vblank_thread("VBlank Thread", [this]()
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@ -682,11 +678,6 @@ namespace rsx
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m_decompiler_thread->join();
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m_decompiler_thread.reset();
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}
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if (fifo_ctrl)
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{
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fifo_ctrl->finalize();
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}
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}
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std::string thread::get_name() const
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@ -456,6 +456,10 @@ namespace rsx
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rsx::method_registers.current_draw_clause.compile();
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rsxthr->end();
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}
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else
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{
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rsxthr->in_begin_end = false;
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}
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}
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vm::addr_t get_report_data_impl(u32 offset)
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@ -2229,8 +2233,11 @@ namespace rsx
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{
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u32 result = 0;
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for (const auto &barrier : draw_command_barriers[current_range_index])
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for (const auto &barrier : draw_command_barriers)
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{
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if (barrier.draw_id != current_range_index)
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continue;
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switch (barrier.type)
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{
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case primitive_restart_barrier:
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@ -43,6 +43,7 @@ namespace rsx
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struct barrier_t
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{
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u32 draw_id;
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u64 timestamp;
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u32 address;
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@ -74,7 +75,7 @@ namespace rsx
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simple_array<draw_range_t> draw_command_ranges;
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// Stores rasterization barriers for primitive types sensitive to adjacency
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std::vector<std::set<barrier_t>> draw_command_barriers;
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simple_array<barrier_t> draw_command_barriers;
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// Counter used to parse the commands in order
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u32 current_range_index;
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@ -87,28 +88,27 @@ namespace rsx
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void append_draw_command(const draw_range_t& range)
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{
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draw_command_ranges.push_back(range);
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draw_command_barriers.push_back({});
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}
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// Insert a new draw command within the others
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void insert_draw_command(int index, const draw_range_t& range)
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{
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auto range_It = draw_command_ranges.begin();
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auto barrier_It = draw_command_barriers.begin();
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// Because deque::insert fails with initializer list on MSVC
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const std::set<barrier_t> new_barrier;
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while (index--)
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{
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++range_It;
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++barrier_It;
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}
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draw_command_ranges.insert(range_It, range);
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draw_command_barriers.insert(barrier_It, new_barrier);
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verify(HERE), draw_command_ranges.size() == draw_command_barriers.size();
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// Update all barrier draw ids after this one
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for (auto &barrier : draw_command_barriers)
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{
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if (barrier.draw_id >= index)
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{
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barrier.draw_id++;
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}
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}
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}
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public:
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@ -125,6 +125,26 @@ namespace rsx
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{
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verify(HERE), !draw_command_ranges.empty();
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auto _do_barrier_insert = [this](barrier_t&& val)
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{
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if (draw_command_barriers.empty() || draw_command_barriers.back() < val)
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{
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draw_command_barriers.push_back(val);
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return;
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}
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for (auto it = draw_command_barriers.begin(); it != draw_command_barriers.end(); it++)
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{
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if (*it < val)
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{
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continue;
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}
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draw_command_barriers.insert(it, val);
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break;
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}
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};
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if (type == primitive_restart_barrier)
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{
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// Rasterization flow barrier
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@ -132,7 +152,7 @@ namespace rsx
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const auto address = last.first + last.count;
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const auto command_index = draw_command_ranges.size() - 1;
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draw_command_barriers[command_index].insert({ 0, address, arg, 0, type });
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_do_barrier_insert({ command_index, 0, address, arg, 0, type });
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}
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else
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{
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@ -140,7 +160,7 @@ namespace rsx
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append_draw_command({});
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const auto command_index = draw_command_ranges.size() - 1;
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draw_command_barriers[command_index].insert({ get_system_time(), -1u, arg, 0, type });
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_do_barrier_insert({ command_index, get_system_time(), -1u, arg, 0, type });
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last_execution_barrier_index = command_index;
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}
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}
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@ -243,8 +263,11 @@ namespace rsx
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}
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verify(HERE), current_range_index != -1u;
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for (const auto &barrier : draw_command_barriers[current_range_index])
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for (const auto &barrier : draw_command_barriers)
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{
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if (barrier.draw_id != current_range_index)
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continue;
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if (barrier.type == primitive_restart_barrier)
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return false;
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}
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@ -342,8 +365,11 @@ namespace rsx
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u32 previous_barrier = range.first;
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u32 vertex_counter = 0;
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for (const auto &barrier : draw_command_barriers[current_range_index])
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for (const auto &barrier : draw_command_barriers)
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{
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if (barrier.draw_id != current_range_index)
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continue;
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if (barrier.type != primitive_restart_barrier)
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continue;
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